coreboot-gerrit November 2020

coreboot-gerrit@coreboot.org

1 participants
3241 discussions

Change in coreboot[master]: device: Allow configuring bus mastering for PCI bridges conditionally
by Felix Singer (Code Review) 09 Nov '20

09 Nov '20

Hello build bot (Jenkins), Nico Huber, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45150 to look at the new patch set (#6). Change subject: device: Allow configuring bus mastering for PCI bridges conditionally ...................................................................... device: Allow configuring bus mastering for PCI bridges conditionally Change-Id: Ic7cacce28f473dda76ca203016dbb8e00149a990 Signed-off-by: Felix Singer <felix.singer(a)secunet.com> --- M src/device/Kconfig M src/device/pci_device.c 2 files changed, 13 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/45150/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/45150 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7cacce28f473dda76ca203016dbb8e00149a990 Gerrit-Change-Number: 45150 Gerrit-PatchSet: 6 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/google/zork: Add finalize GPIO routine
by Martin Roth (Code Review) 09 Nov '20

09 Nov '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47310 ) Change subject: mb/google/zork: Add finalize GPIO routine ...................................................................... mb/google/zork: Add finalize GPIO routine The fingerprint GPIOs need to be brought out of reset at the end of coreboot's boot sequence. This routine allows that to happen. BUG=b:171837716 TEST=Boot, verify fingerprint works BRANCH=Zork Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: I11d14de44caa370f06b8da1277c8d88a7b3437bb Change-Id: Iee178cc98259b490424c600c2ea6e55a2095670e --- M src/mainboard/google/zork/mainboard.c M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c M src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/zork/variants/berknip/gpio.c M src/mainboard/google/zork/variants/morphius/gpio.c 6 files changed, 62 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/47310/1 diff --git a/src/mainboard/google/zork/mainboard.c b/src/mainboard/google/zork/mainboard.c index 9503d37..15957af 100644 --- a/src/mainboard/google/zork/mainboard.c +++ b/src/mainboard/google/zork/mainboard.c @@ -247,12 +247,13 @@ gnvs = acpi_get_gnvs(); - if (gnvs) { gnvs->tmps = CTL_TDP_SENSOR_ID; gnvs->tcrt = CRITICAL_TEMPERATURE; gnvs->tpsv = PASSIVE_TEMPERATURE; } + + finalize_gpios(); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c index e538aef..d5f8ed4 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c @@ -291,6 +291,10 @@ wifi_power_reset_configure_pre_v3(); } +const __weak void finalize_gpios(void) +{ +} + const __weak struct soc_amd_gpio *variant_poweron_gpio_table(size_t *size, int slp_typ) { *size = 0; diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c index 74e7ed2..bf27622 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c @@ -297,6 +297,11 @@ wifi_power_reset_configure_pre_v3(); } + +__weak void finalize_gpios(void) +{ +} + static const struct soc_amd_gpio gpio_fingerprint_poweron_table[] = { /* FPMCU_RST_L */ PAD_GPO(GPIO_11, LOW), diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h index 61c8b3c..643fe39 100644 --- a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h @@ -39,6 +39,9 @@ /* Determine whether to init fingerprint sensor or not */ int variant_init_fingerprint(void); +/* Program any required GPIOs at the finalize phase */ +void finalize_gpios(void); + /* Modify devictree settings during ramstage. */ void variant_devtree_update(void); /* Update audio configuration in devicetree during ramstage. */ diff --git a/src/mainboard/google/zork/variants/berknip/gpio.c b/src/mainboard/google/zork/variants/berknip/gpio.c index ae2d02a..a4d5a64 100644 --- a/src/mainboard/google/zork/variants/berknip/gpio.c +++ b/src/mainboard/google/zork/variants/berknip/gpio.c @@ -3,6 +3,7 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> #include <boardid.h> +#include <delay.h> #include <gpio.h> #include <soc/gpio.h> #include <ec/google/chromeec/ec.h> @@ -52,6 +53,29 @@ PAD_NC(GPIO_5), }; +void finalize_gpios(void) +{ + uint32_t board_version; + + if (variant_init_fingerprint()) { + + if (google_chromeec_cbi_get_board_version(&board_version)) + board_version = 1; + + /* Berknip board versions prior to v4 need an extra delay here */ + if (board_version <= 3) { + mdelay(550); + } + /* + * Enable the FPMCU by enabling EN_PWR_FP, then bringing it out + * of reset by setting FPMCU_RST_L high 3ms later. + */ + gpio_set(GPIO_32, 1); + mdelay(3); + gpio_set(GPIO_11, 1); + } +} + const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) { uint32_t board_version; diff --git a/src/mainboard/google/zork/variants/morphius/gpio.c b/src/mainboard/google/zork/variants/morphius/gpio.c index 9b36e37..14211b2 100644 --- a/src/mainboard/google/zork/variants/morphius/gpio.c +++ b/src/mainboard/google/zork/variants/morphius/gpio.c @@ -3,6 +3,7 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> #include <boardid.h> +#include <delay.h> #include <gpio.h> #include <soc/gpio.h> #include <ec/google/chromeec/ec.h> @@ -86,3 +87,26 @@ *size = 0; return NULL; } + +/* Assume all SKUS have a fingerprint sensor */ + +void finalize_gpios(void) +{ + uint32_t board_version; + + if (google_chromeec_cbi_get_board_version(&board_version)) + board_version = 1; + + /* Morphius board versions prior to v5 need an extra delay here */ + if (board_version <= 4) { + mdelay(550); + } + /* + * Enable the FPMCU by enabling EN_PWR_FP, then bringing it out + * of reset by setting FPMCU_RST_L high 3ms later. + */ + gpio_set(GPIO_32, 1); + mdelay(3); + gpio_set(GPIO_11, 1); +} + -- To view, visit https://review.coreboot.org/c/coreboot/+/47310 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee178cc98259b490424c600c2ea6e55a2095670e Gerrit-Change-Number: 47310 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

3 9

Change in coreboot[master]: mb/google/dedede/var/drawcia: Probe and enable DPTF configuration
by Tim Wawrzynczak (Code Review) 09 Nov '20

09 Nov '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47010 ) Change subject: mb/google/dedede/var/drawcia: Probe and enable DPTF configuration ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/c/coreboot/+/47010/5/src/mainboard/google/deded… File src/mainboard/google/dedede/variants/drawcia/overridetree.cb: https://review.coreboot.org/c/coreboot/+/47010/5/src/mainboard/google/deded… PS5, Line 139: # Default DPTF Policy for all drawcia boards if not overridden : register "options.tsr[0].desc" = ""Memory"" : register "options.tsr[1].desc" = ""Ambient"" : register "options.tsr[2].desc" = ""Charger"" : register "options.tsr[3].desc" = ""5V regulator"" > Tim, I did not get your comment, please elaborate. […] In short, the answer is no, right now you can't just define the sensor description entries only once, unless they come from some override. You could add something like this in the baseboard devicetree: ``` chip drivers/intel/dptf registers "options.tsr[0].desc" = ""Memory"" ... device generic 0 off end registers "options.tsr[0].desc" = ""Memory"" ... device generic 1 off end ``` and then any variants will automatically pick up those entries -- To view, visit https://review.coreboot.org/c/coreboot/+/47010 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf166a2e36fa5775e2dea7c1adcae843cc143d32 Gerrit-Change-Number: 47010 Gerrit-PatchSet: 5 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 09 Nov 2020 22:12:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/skylake: Enable PCH thermal depending on devicetree
by Michael Niewöhner (Code Review) 09 Nov '20

09 Nov '20

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47116 ) Change subject: soc/intel/skylake: Enable PCH thermal depending on devicetree ...................................................................... soc/intel/skylake: Enable PCH thermal depending on devicetree Hook up PCH thermal subsystem configuration to devicetree. Change-Id: I84bac2cec079370370ecf1e5e4742e6704921d40 Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47116 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/mainboard/protectli/vault_kbl/ramstage.c M src/soc/intel/skylake/chip.c 2 files changed, 2 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved Michael Niewöhner: Looks good to me, approved diff --git a/src/mainboard/protectli/vault_kbl/ramstage.c b/src/mainboard/protectli/vault_kbl/ramstage.c index 962702f..9518b1d 100644 --- a/src/mainboard/protectli/vault_kbl/ramstage.c +++ b/src/mainboard/protectli/vault_kbl/ramstage.c @@ -13,7 +13,6 @@ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); params->TurboMode = 1; - params->PchThermalDeviceEnable = 0; params->PchPort61hEnable = 1; params->CdClock = 3; } diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 89eaef5..1e13428 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -295,6 +295,8 @@ dev = pcidev_path_on_root(SA_DEVFN_TS); params->Device4Enable = dev && dev->enabled; + dev = pcidev_path_on_root(PCH_DEVFN_THERMAL); + params->PchThermalDeviceEnable = dev && dev->enabled; params->EnableTcoTimer = !config->PmTimerDisabled; tconfig->PchLockDownGlobalSmi = config->LockDownConfigGlobalSmi; -- To view, visit https://review.coreboot.org/c/coreboot/+/47116 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I84bac2cec079370370ecf1e5e4742e6704921d40 Gerrit-Change-Number: 47116 Gerrit-PatchSet: 5 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: soc/intel/skylake: Enable PCH thermal depending on devicetree
by Michael Niewöhner (Code Review) 09 Nov '20

09 Nov '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47116 ) Change subject: soc/intel/skylake: Enable PCH thermal depending on devicetree ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/47116 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I84bac2cec079370370ecf1e5e4742e6704921d40 Gerrit-Change-Number: 47116 Gerrit-PatchSet: 4 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 09 Nov 2020 21:34:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/skylake: Enable PCH thermal depending on devicetree
by Felix Singer (Code Review) 09 Nov '20

09 Nov '20

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47116 ) Change subject: soc/intel/skylake: Enable PCH thermal depending on devicetree ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/47116 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I84bac2cec079370370ecf1e5e4742e6704921d40 Gerrit-Change-Number: 47116 Gerrit-PatchSet: 4 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 09 Nov 2020 21:31:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/ocp/deltalake: Configure GPIO for DVT
by Angel Pons (Code Review) 09 Nov '20

09 Nov '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47229 ) Change subject: mb/ocp/deltalake: Configure GPIO for DVT ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/47229/3//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/47229/3//COMMIT_MSG@11 PS3, Line 11: Add a config to switch between EVT and DVT. > Jingle, what's the best way to differentiate between EVT, DVT and PVT? In case of DeltaLake, does CP […] On desktop/laptop boards, one would usually have some PCH GPIOs connected to external pull up/down resistors to encode an ID on the board itself. Not sure if servers also do this. -- To view, visit https://review.coreboot.org/c/coreboot/+/47229 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9837a22bc231a4cb919de316ff6f6ee88411ab8 Gerrit-Change-Number: 47229 Gerrit-PatchSet: 3 Gerrit-Owner: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Bryant Ou <bryant.ou.q(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Comment-Date: Mon, 09 Nov 2020 18:39:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jonathan Zhang <jonzhang(a)fb.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/ocp/deltalake: Configure GPIO for DVT
by Jonathan Zhang (Code Review) 09 Nov '20

09 Nov '20

Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47229 ) Change subject: mb/ocp/deltalake: Configure GPIO for DVT ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/47229/3//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/47229/3//COMMIT_MSG@11 PS3, Line 11: Add a config to switch between EVT and DVT. > I would prefer to determine at runtime whether a board is EVT or DVT. […] Jingle, what's the best way to differentiate between EVT, DVT and PVT? In case of DeltaLake, does CPUID change between DVT and PVT? If it does, CPUID can be used. Otherwise the best way is to use IPMI response from BMC, and default to DVT if there is issue with BMC communication? This would involve boot time differentiation instead of build time. -- To view, visit https://review.coreboot.org/c/coreboot/+/47229 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9837a22bc231a4cb919de316ff6f6ee88411ab8 Gerrit-Change-Number: 47229 Gerrit-PatchSet: 3 Gerrit-Owner: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Bryant Ou <bryant.ou.q(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Comment-Date: Mon, 09 Nov 2020 18:33:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: vc/intel/FSP2_0/CPX-SP: add FSPM DIMM watermark option
by Jonathan Zhang (Code Review) 09 Nov '20

09 Nov '20

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46480 ) Change subject: vc/intel/FSP2_0/CPX-SP: add FSPM DIMM watermark option ...................................................................... vc/intel/FSP2_0/CPX-SP: add FSPM DIMM watermark option FSPM MemRefreshWatermark option support is present in FB's CPX-SP FSP binary, but not in Intel's CPX-SP FSP binary. Add a Kconfig HAVE_FSPM_DIMM_WATERMARK_OPTION to indicate whether the FSP binary supports such option. When such option is set, if corresponding VPD variable is set, use it to control the behavior. Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Change-Id: I7592dfc8836f457d64f1976cba3b59f8251c7abe --- M src/mainboard/ocp/deltalake/Kconfig M src/mainboard/ocp/deltalake/romstage.c M src/mainboard/ocp/deltalake/vpd.h M src/soc/intel/xeon_sp/cpx/Kconfig M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h 5 files changed, 88 insertions(+), 50 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/46480/1 diff --git a/src/mainboard/ocp/deltalake/Kconfig b/src/mainboard/ocp/deltalake/Kconfig index ff5599c..0777ad3 100644 --- a/src/mainboard/ocp/deltalake/Kconfig +++ b/src/mainboard/ocp/deltalake/Kconfig @@ -4,6 +4,7 @@ def_bool y select BOARD_ROMSIZE_KB_65536 select HAVE_ACPI_TABLES + select HAVE_FSPM_DIMM_WATERMARK_OPTION select MAINBOARD_USES_FSP2_0 select SOC_INTEL_COOPERLAKE_SP select SUPERIO_ASPEED_AST2400 diff --git a/src/mainboard/ocp/deltalake/romstage.c b/src/mainboard/ocp/deltalake/romstage.c index 71a26c8..3cb514b 100644 --- a/src/mainboard/ocp/deltalake/romstage.c +++ b/src/mainboard/ocp/deltalake/romstage.c @@ -59,6 +59,25 @@ "DciEn to %d\n", FSP_DCI, FSP_DCI_DEFAULT); mupd->FspmConfig.PchDciEn = FSP_DCI_DEFAULT; } + + /* Set MemRefreshWaterMark */ + if (CONFIG(HAVE_FSPM_DIMM_WATERMARK_OPTION)) { + if (vpd_gets(FSPM_MEMREFRESHWATERMARK, val_str, VPD_LEN, VPD_RW_THEN_RO)) { + val = (uint8_t)atol(val_str); + if (val > 2) { + printk(BIOS_DEBUG, "Invalid MemRefreshWatermark value from VPD: " + "%d\n", val); + val = FSPM_MEMREFRESHWATERMARK_DEFAULT; + } + printk(BIOS_DEBUG, "Setting MemRefershWatermark %d from VPD\n", val); + mupd->FspmConfig.MemRefreshWaterMark = val; + } else { + printk(BIOS_INFO, "Not able to get VPD %s, default set " + "MemRefreshWatermark to %d\n", FSPM_MEMREFRESHWATERMARK, + FSPM_MEMREFRESHWATERMARK_DEFAULT); + mupd->FspmConfig.MemRefreshWaterMark = FSPM_MEMREFRESHWATERMARK_DEFAULT; + } + } } /* Update bifurcation settings according to different Configs */ diff --git a/src/mainboard/ocp/deltalake/vpd.h b/src/mainboard/ocp/deltalake/vpd.h index ae2099d..2db9851 100644 --- a/src/mainboard/ocp/deltalake/vpd.h +++ b/src/mainboard/ocp/deltalake/vpd.h @@ -32,4 +32,8 @@ #define FSP_DCI "fsp_dci_enable" /* 1 or 0: enable or disable DCI */ #define FSP_DCI_DEFAULT 0 /* Default value when the VPD variable is not found */ +/* FSPM MemRefreshWatermark: 0:Auto (default), 1: high, 2: low */ +#define FSPM_MEMREFRESHWATERMARK "fspm_mem_refresh_watermark" +#define FSPM_MEMREFRESHWATERMARK_DEFAULT 1 /* Default value when the VPD variable is not found */ + #endif diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig index 975afc9..1d69889 100644 --- a/src/soc/intel/xeon_sp/cpx/Kconfig +++ b/src/soc/intel/xeon_sp/cpx/Kconfig @@ -91,4 +91,7 @@ int default 512 +config HAVE_FSPM_DIMM_WATERMARK_OPTION + def_bool n + endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h index 37ff1bd..89922ef 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h @@ -495,237 +495,248 @@ **/ UINT8 serialDebugMsgLvl; -/** Offset 0x00C4 - IIO ConfigIOU0 +#if CONFIG_HAVE_FSPM_DIMM_WATERMARK_OPTION +/** Offset 0x00C4 - Usage type for Memory Refresh Watermark + Select Memory Refresh Watermark, 0: Auto (default), 1: High, 2: Low +**/ + UINT8 MemRefreshWaterMark; +#endif + +/** Offset 0x00C5 - IIO ConfigIOU0 ConfigIOU[MAX_SOCKET][0]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO **/ UINT8 IioConfigIOU0[8]; -/** Offset 0x00CC - IIO ConfigIOU1 +/** Offset 0x00CD - IIO ConfigIOU1 ConfigIOU[MAX_SOCKET][1]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO **/ UINT8 IioConfigIOU1[8]; -/** Offset 0x00D4 - IIO ConfigIOU2 +/** Offset 0x00D5 - IIO ConfigIOU2 ConfigIOU[MAX_SOCKET][2]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO **/ UINT8 IioConfigIOU2[8]; -/** Offset 0x00DC - IIO ConfigIOU3 +/** Offset 0x00DD - IIO ConfigIOU3 ConfigIOU[MAX_SOCKET][3]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO **/ UINT8 IioConfigIOU3[8]; -/** Offset 0x00E4 - IIO ConfigIOU4 +/** Offset 0x00E5 - IIO ConfigIOU4 ConfigIOU[MAX_SOCKET][4]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO **/ UINT8 IioConfigIOU4[8]; -/** Offset 0x00EC - Usage type for IIO PCIE Config Table Ptr +/** Offset 0x00ED +**/ + UINT8 UnusedUpdSpace2[3]; + +/** Offset 0x00F0 - Usage type for IIO PCIE Config Table Ptr IIO PCIE Config Table Ptr **/ UINT32 IioPcieConfigTablePtr; -/** Offset 0x00F0 - Usage type for IIO PCIE Config Table Number +/** Offset 0x00F4 - Usage type for IIO PCIE Config Table Number IIO PCIE Config Table Number **/ UINT32 IioPcieConfigTableNumber; -/** Offset 0x00F4 - Usage type for IIO PCIE Root Port Enable or Disable +/** Offset 0x00F8 - Usage type for IIO PCIE Root Port Enable or Disable IIO PCH rootport, if port is enabled, the value is 0x01, if the port is disabled, the value is 0x00 **/ UINT8 IIOPcieRootPortEnable; -/** Offset 0x00F5 - Usage type for IIO DeEmphasis +/** Offset 0x00F9 - Usage type for IIO DeEmphasis IIO DeEmphasis **/ UINT8 DeEmphasis; -/** Offset 0x00F6 - Usage type for IIO PCIE Root Port link speed +/** Offset 0x00FA - Usage type for IIO PCIE Root Port link speed IIO root port link speed **/ UINT8 IIOPciePortLinkSpeed; -/** Offset 0x00F7 - Usage type for IIO PCIE Root Port Max Payload +/** Offset 0x00FB - Usage type for IIO PCIE Root Port Max Payload IIO Root Port Max Payload **/ UINT8 IIOPcieMaxPayload; -/** Offset 0x00F8 - Usage type for IIO DfxDnTxPreset +/** Offset 0x00FC - Usage type for IIO DfxDnTxPreset IIO DfxDnTxPreset **/ UINT8 DfxDnTxPreset; -/** Offset 0x00F9 - Usage type for IIO DfxRxPreset +/** Offset 0x00FD - Usage type for IIO DfxRxPreset IIO DfxRxPreset **/ UINT8 DfxRxPreset; -/** Offset 0x00FA - Usage type for IIO DfxUpTxPreset +/** Offset 0x00FE - Usage type for IIO DfxUpTxPreset IIO DfxUpTxPreset **/ UINT8 DfxUpTxPreset; -/** Offset 0x00FB - Usage type for IIO PcieCommonClock +/** Offset 0x00FF - Usage type for IIO PcieCommonClock IIO PcieCommonClock **/ UINT8 PcieCommonClock; -/** Offset 0x00FC - Usage type for IIO NtbPpd +/** Offset 0x0100 - Usage type for IIO NtbPpd IIO NtbPpd **/ UINT8 NtbPpd; -/** Offset 0x00FD - Usage type for IIO NtbBarSizeOverride +/** Offset 0x0101 - Usage type for IIO NtbBarSizeOverride IIO NtbBarSizeOverride **/ UINT8 NtbBarSizeOverride; -/** Offset 0x00FE - Usage type for IIO NtbSplitBar +/** Offset 0x0102 - Usage type for IIO NtbSplitBar IIO NtbSplitBar **/ UINT8 NtbSplitBar; -/** Offset 0x00FF - Usage type for IIO NtbBarSizeImBar1 +/** Offset 0x0103 - Usage type for IIO NtbBarSizeImBar1 IIO NtbBarSizeImBar1 **/ UINT8 NtbBarSizeImBar1; -/** Offset 0x0100 - Usage type for IIO NtbBarSizeImBar2 +/** Offset 0x0104 - Usage type for IIO NtbBarSizeImBar2 IIO PNtbBarSizeImBar2 **/ UINT8 NtbBarSizeImBar2; -/** Offset 0x0101 - Usage type for IIO NtbBarSizeImBar2_0 +/** Offset 0x0105 - Usage type for IIO NtbBarSizeImBar2_0 IIO PNtbBarSizeImBar2_0 **/ UINT8 NtbBarSizeImBar2_0; -/** Offset 0x0102 - Usage type for IIO NtbBarSizeImBar2_1 +/** Offset 0x0106 - Usage type for IIO NtbBarSizeImBar2_1 IIO NtbBarSizeImBar2_1 **/ UINT8 NtbBarSizeImBar2_1; -/** Offset 0x0103 - Usage type for IIO NtbBarSizeEmBarSZ1 +/** Offset 0x0107 - Usage type for IIO NtbBarSizeEmBarSZ1 IIO NtbBarSizeEmBarSZ1 **/ UINT8 NtbBarSizeEmBarSZ1; -/** Offset 0x0104 - Usage type for IIO NtbBarSizeEmBarSZ2 +/** Offset 0x0108 - Usage type for IIO NtbBarSizeEmBarSZ2 IIO NtbBarSizeEmBarSZ2 **/ UINT8 NtbBarSizeEmBarSZ2; -/** Offset 0x0105 - Usage type for IIO NtbBarSizeEmBarSZ2_0 +/** Offset 0x0109 - Usage type for IIO NtbBarSizeEmBarSZ2_0 IIO NtbBarSizeEmBarSZ2_0 **/ UINT8 NtbBarSizeEmBarSZ2_0; -/** Offset 0x0106 - Usage type for IIO NtbBarSizeEmBarSZ2_1 +/** Offset 0x010A - Usage type for IIO NtbBarSizeEmBarSZ2_1 IIO NtbBarSizeEmBarSZ2_1 **/ UINT8 NtbBarSizeEmBarSZ2_1; -/** Offset 0x0107 - Usage type for IIO NtbXlinkCtlOverride +/** Offset 0x010B - Usage type for IIO NtbXlinkCtlOverride IIO NtbXlinkCtlOverride **/ UINT8 NtbXlinkCtlOverride; -/** Offset 0x0108 - Usage type for IIO VT-D Function +/** Offset 0x010C - Usage type for IIO VT-D Function IIO VT-D Function, if supported, the value is 0x01, if not supported, the value is 0x00 **/ UINT8 VtdSupport; -/** Offset 0x0109 - Usage type for IIO Pcie Port Hide +/** Offset 0x010D - Usage type for IIO Pcie Port Hide Hide or visible for IIO Pcie Port, 1 : Hide, 0 : Visible **/ UINT8 PEXPHIDE; -/** Offset 0x010A - Usage type for IIO Pcie Port Menu Hide +/** Offset 0x010E - Usage type for IIO Pcie Port Menu Hide Hide or visible for IIO Pcie Port Menu, 1 : Hide, 0 : Visible **/ UINT8 HidePEXPMenu; -/** Offset 0x010B - PchSirqMode +/** Offset 0x010F - PchSirqMode Enable or Disable PchSirqMode **/ UINT8 PchSirqMode; -/** Offset 0x010C - PchAdrEn +/** Offset 0x0110 - PchAdrEn Enable or Disable PchAdr **/ UINT8 PchAdrEn; -/** Offset 0x010D - ThermalDeviceEnable +/** Offset 0x0111 - ThermalDeviceEnable Enable or Disable ThermalDeviceEnable with PCI or ACPI mode **/ UINT8 ThermalDeviceEnable; -/** Offset 0x010E - } TYPE:{Combo +/** Offset 0x0112 - } TYPE:{Combo Root port swapping based on device connection status : TRUE or FALSE TRUE : 0x01, FALSE : 0x00 **/ UINT8 PchPcieRootPortFunctionSwap; -/** Offset 0x010F - PCH PCIE PLL Ssc +/** Offset 0x0113 - PCH PCIE PLL Ssc Valid spread range : 0x00-0x14 (A value of 0 is SSC of 0.0%. A value of 20 is SSC of 2.0%), Auto : 0xFE(Set to hardware default), Disable : 0xFF **/ UINT8 PchPciePllSsc; -/** Offset 0x0110 - Usage type for PCH PCIE Root Port Index +/** Offset 0x0114 - Usage type for PCH PCIE Root Port Index Index assigned to every PCH PCIE Root Port **/ UINT8 PchPciePortIndex[20]; -/** Offset 0x0124 - Usage type for PCH PCIE Root Port Enable or Disable +/** Offset 0x0128 - Usage type for PCH PCIE Root Port Enable or Disable 0-19: PCH rootport, if port is enabled, the value is 0x01, if the port is disabled, the value is 0x00 **/ UINT8 PchPcieForceEnable[20]; -/** Offset 0x0138 - Usage type for PCH PCIE Root Port Link Speed +/** Offset 0x013C - Usage type for PCH PCIE Root Port Link Speed 0-19: PCH rootport, 0x00 : Pcie Auto Speed, 0x01 : Pcie Gen1 Speed, 0x02 : Pcie Gen2 Speed, 0x03 : Pcie Gen3 Speed **/ UINT8 PchPciePortLinkSpeed[20]; -/** Offset 0x014C - PchDciEn +/** Offset 0x0150 - PchDciEn Enable or Disable Pch DciEn **/ UINT8 PchDciEn; -/** Offset 0x014D - MeUmaEnable +/** Offset 0x0151 - MeUmaEnable Enable or disable ME UMA feature **/ UINT8 MeUmaEnable; -/** Offset 0x014E - SerialIoUartDebugEnable +/** Offset 0x0152 - SerialIoUartDebugEnable Enable SerialIo Uart debug library in FSP. 0:Disable, 1:Enable **/ UINT8 SerialIoUartDebugEnable; -/** Offset 0x014F +/** Offset 0x0153 **/ - UINT8 UnusedUpdSpace2; + UINT8 UnusedUpdSpace3; -/** Offset 0x0150 - ISA Serial Base selection +/** Offset 0x0154 - ISA Serial Base selection Select ISA Serial Base address could be initialized by boot loader. Default is 0x3F8 0x3F8, 0x2F8 **/ UINT16 SerialIoUartDebugIoBase; -/** Offset 0x0152 +/** Offset 0x0156 **/ - UINT8 UnusedUpdSpace3[2]; + UINT8 UnusedUpdSpace4[2]; -/** Offset 0x0154 +/** Offset 0x0158 **/ UINT8 ReservedMemoryInitUpd[16]; } FSPM_CONFIG; @@ -746,11 +757,11 @@ **/ FSPM_CONFIG FspmConfig; -/** Offset 0x0164 +/** Offset 0x0168 **/ - UINT8 UnusedUpdSpace4[2]; + UINT8 UnusedUpdSpace5[6]; -/** Offset 0x0166 +/** Offset 0x016E **/ UINT16 UpdTerminator; } FSPM_UPD; -- To view, visit https://review.coreboot.org/c/coreboot/+/46480 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7592dfc8836f457d64f1976cba3b59f8251c7abe Gerrit-Change-Number: 46480 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: newchange

5 11

Change in coreboot[master]: vc/intel/FSP2_0/CPX-SP: update FSP to ww43 release
by Jonathan Zhang (Code Review) 09 Nov '20

09 Nov '20

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46609 ) Change subject: vc/intel/FSP2_0/CPX-SP: update FSP to ww43 release ...................................................................... vc/intel/FSP2_0/CPX-SP: update FSP to ww43 release Intel CPX-SP FSP ww43 release added default values explanation to FSP-M header file. Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Change-Id: Icc75f39f8f7a6d47690464dd4e5194f6e2ba12a8 --- M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h 1 file changed, 165 insertions(+), 159 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/46609/1 diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h index 34aa6c1..2a169af 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h @@ -151,223 +151,231 @@ UINT8 CustomerRevision[32]; /** Offset 0x0060 - Bus Ratio - Indicates the ratio of Bus/MMIOL/IO resource to be allocated for each CPU's IIO + Indicates the ratio of Bus/MMIOL/IO resource to be allocated for each CPU's IIO. + Default 0x1 **/ UINT8 BusRatio[8]; /** Offset 0x0068 - D2K Credit Config - Set the D2K Credit Config + Set the D2K Credit Config. 1: Min,2: Med (Default), 3: Max. 1:Min, 2:Med, 3:Max **/ UINT8 D2KCreditConfig; /** Offset 0x0069 - Snoop Throttle Config - Set the Snoop Throttle Config - 0:DIS, 1:Min, 2:Med, 3:Max + Set the Snoop Throttle Config. 0: Disable(Default), 1: Min, 2: Med, 3: Max + 0:Disable, 1:Min, 2:Med, 3:Max **/ UINT8 SnoopThrottleConfig; /** Offset 0x006A - Snoop Throttle Config - Set the Snoop All Core Config - 0:DIS, 1:EN, 2:Auto + Set the Snoop All Core Config. 0: Disable(Default), 1: Enable, 2: Auto + 0:Disable, 1:Enable, 2:Auto **/ UINT8 SnoopAllCores; -/** Offset 0x006B - Legacy VGA Soc - Socket that claims the legacy VGA range +/** Offset 0x006B - Legacy VGA Socket + Socket that claims the legacy VGA range. Default: Socket 0 **/ UINT8 LegacyVgaSoc; /** Offset 0x006C - Legacy VGA Stack - Stack that claims the legacy VGA range + Stack that claims the legacy VGA range. Default: Stack 0 **/ UINT8 LegacyVgaStack; /** Offset 0x006D - Pcie P2P Performance Mode - Determine if to enable PCIe P2P Performance Mode + Enable: Enable PCIe P2P Performance Mode, Disable(Default): Disable PCIe + P2P Performance Mode $EN_DIS **/ UINT8 P2pRelaxedOrdering; /** Offset 0x006E - Debug Print Level - Set Debug Print Level + Debug Print Level Bitmask. 0: Disable, 1: Fatal, 2: Warning, 4: Summary, 8: Detail, + 0xF: All(Default) 1:Fatal, 2:Warning, 4:Summary, 8:Detail, 0x0F:All **/ UINT8 DebugPrintLevel; /** Offset 0x006F - SNC - Enable or Disable SNC + Enable(Default) or Disable SNC $EN_DIS **/ UINT8 SncEn; /** Offset 0x0070 - UMA Clustering - Set UMA Clusters + Set number of enabled UMA Clusters. 0: Disable(Default), 2: Two Clusters, + 4: Four Clusters 0:Disable, 2:Two Clusters, 4:Four Clusters **/ UINT8 UmaClustering; /** Offset 0x0071 - IODC Mode - IODC Setup Option + IODC Mode. 0: Disable, 1: Auto(Default), 2: Push, 3: AllocFlow 4: NonAlloc, 5: WCILF 0:Disable, 1:Auto, 2:Push, 3:AllocFlow 4:NonAlloc, 5:WCILF **/ UINT8 IoDcMode; /** Offset 0x0072 - Degrade Precedence - Setup Degrade Precedence + Degrade Precedence. 0: Topology(Default), 1: Feature 0:Topology, 1:Feature **/ UINT8 DegradePrecedence; /** Offset 0x0073 - Degrade 4 Socket Preference - Setup Degrade 4 Socket Preference + Degrade 4 Socket Preference. 0: Fully Connect(Default), 1: Dual Link Ring 0:Fully Connect, 1:Dual Link Ring **/ UINT8 Degrade4SPreference; /** Offset 0x0074 - Directory Mode - Enable or Disable Directory Mode + Enable(Default) or Disable Directory Mode $EN_DIS **/ UINT8 DirectoryModeEn; /** Offset 0x0075 - XPT Prefetch Enable - Enable or Disable XPT Prefetch + XPT Prefetch. 0: Disable, 1: Enable, 2: Auto(Default) **/ UINT8 XptPrefetchEn; /** Offset 0x0076 - KTI Prefetch Enable - Enable or Disable KTI Prefetch + Enable(Default) or Disable KTI Prefetch $EN_DIS **/ UINT8 KtiPrefetchEn; /** Offset 0x0077 - XPT Remote Prefetch Enable - Enable or Disable XPT Remote Prefetch Enable + Enable or Disable(Default) XPT Remote Prefetch $EN_DIS **/ UINT8 XptRemotePrefetchEn; /** Offset 0x0078 - KTI FPGA - Enable or Disable KTI FPGA - $EN_DIS + Enable or Disable KTI FPGA, Default: 0x1 (Enable) **/ UINT8 KtiFpgaEnable[8]; /** Offset 0x0080 - DDRT QoS Mode - Setup DDRT QoS + DDRT QoS. 0: Mode 0(Default), 1: Mode 1, 2: Mode 2 **/ UINT8 DdrtQosMode; /** Offset 0x0081 - KTI Link Speed Mode - Choose KTI Link Speed Mode + KTI Link Speed Mode. 0: Slow, 1: Full(Default) **/ UINT8 KtiLinkSpeedMode; /** Offset 0x0082 - KTI Link Speed - Setup KTI Link Speed + KTI Link Speed. 0: 128GT, 1: 144GT, 2: 160GT, 3: Max KTI Link Speed(Default), + 4: Frequency Per Link **/ UINT8 KtiLinkSpeed; /** Offset 0x0083 - KTI Link L0p - Enable or Disable KTI Link L0p + KTI Link L0p. 0: Disable, 1: Enable, 2: Auto(Default) **/ UINT8 KtiLinkL0pEn; /** Offset 0x0084 - KTI Link L1 - Enable or Disable KTI Link L1 + KTI Link L1. 0: Disable, 1: Enable, 2: Auto(Default) **/ UINT8 KtiLinkL1En; /** Offset 0x0085 - KTI Failover - Enable or Disable KTI Failover + KTI Failover. 0: Disable, 1: Enable, 2: Auto(Default) **/ UINT8 KtiFailoverEn; /** Offset 0x0086 - KTI LB Enable - Enable or Disable KTI LB + Enable or Disable(Default) KTI LB $EN_DIS **/ UINT8 KtiLbEn; /** Offset 0x0087 - KTI CRC Mode - Select KTI CRC Mode + KTI CRC Mode. 0: 16bit, 1: 32bit, 2: Auto(Default) 0:16bit, 1:32bit, 2:Auto **/ UINT8 KtiCrcMode; /** Offset 0x0088 - KTI CPU Socket Hotplug - Enable or Disable KTI CPU Socket Hotplug + Enable or Disable(Default) KTI CPU Socket Hotplug $EN_DIS **/ UINT8 KtiCpuSktHotPlugEn; /** Offset 0x0089 - KTI CPU Socket HotPlug Topology - Select KTI CPU Socket HotPlug Topology + KTI CPU Socket HotPlug Topology. 0: 4 Socket(Default), 1: 8 Socket 0:4Socket, 1:8Socket **/ UINT8 KtiCpuSktHotPlugTopology; /** Offset 0x008A - KTI SKU Mismatch Check - Enable or Disable KTI SKU Mismatch Check + Enable(Default) or Disable KTI SKU Mismatch Check $EN_DIS **/ UINT8 KtiSkuMismatchCheck; /** Offset 0x008B - IRQ Threshold - Select IRQ Threshold + IRQ Threshold. 0: Disable, 1: Auto(Default), 2: Low, 3: Medium, 4: High 0:Disable, 1:Auto, 2:Low, 3:Medium, 4:High **/ UINT8 IrqThreshold; -/** Offset 0x008C - IRQ Threshold - Enable or Disable +/** Offset 0x008C - TOR threshold - Loctorem threshold normal + TOR threshold - Loctorem threshold normal. 0: Disable, 1: Auto(Default), + 2: Low, 3: Medium, 4: High 0:Disable, 1:Auto, 2:Low, 3:Medium, 4:High **/ UINT8 TorThresLoctoremNorm; /** Offset 0x008D - TOR threshold - Loctorem threshold empty - Select TOR threshold - Loctorem threshold empty + TOR threshold - Loctorem threshold empty. 0: Disable, 1: Auto(Default), + 2: Low, 3: Medium, 4: High 0:Disable, 1:Auto, 2:Low, 3:Medium, 4:High **/ UINT8 TorThresLoctoremEmpty; /** Offset 0x008E - MBA BW Calibration - MBA BW Calibration setting + MBA BW Calibration setting. 0: Linear, 1: Biased, 2: Legacy, 3: Auto(Default) 0:Linear, 1:Biased, 2:Legacy, 3:Auto **/ UINT8 MbeBwCal; /** Offset 0x008F - TSC Sync in Sockets - Enable or Disable TSC Sync in Sockets + TSC Sync in Sockets. 0: Disable, 1: Enable, 2: Auto(Default) **/ UINT8 TscSyncEn; /** Offset 0x0090 - HA A to S directory optimization - Enable or Disable HA A to S directory optimization + HA A to S directory optimization. 0: Disable, 1: Enable, 2: Auto(Default) **/ UINT8 StaleAtoSOptEn; /** Offset 0x0091 - LLC Deadline Allocation - Enable or Disable LLC Deadline Allocation + Enable(Default) or Disable LLC Deadline Allocation $EN_DIS **/ UINT8 LLCDeadLineAlloc; /** Offset 0x0092 - Split Lock - Enable or Disable Split Lock + Split Lock. 0: Disable(Default), 1: Enable, 2: Auto **/ UINT8 SplitLock; /** Offset 0x0093 - MMCFG Base Address - Setup MMCFG Base Address - 0:1G, 1:1.5G, 2:1.75G, 3:2G, 4:2.25G, 5:3G, 6:Auto + MMCFG Base Address. 0: 1GB, 1: 1.5GB, 2: 1.75GB, 3: 2GB, 4: 2.25GB, 5: 3GB, 6: + Auto(Default) + 0:1GB, 1:1.5GB, 2:1.75GB, 3:2GB, 4:2.25GB, 5:3GB, 6:Auto **/ UINT8 mmCfgBase; /** Offset 0x0094 - MMCFG Size - Select MMCFG Size - 0:64M, 1:128M, 2:256M, 3:512M, 4:1G, 5:2G, 6: Auto + Select MMCFG Size. 0: 64MB, 1: 128MB, 2: 256MB, 3: 512MB, 4: 1GB, 5: 2GB, 6: + Auto(Default) + 0:64MB, 1:128MB, 2:256MB, 3:512MB, 4:1GB, 5:2GB, 6: Auto **/ UINT8 mmCfgSize; @@ -376,36 +384,36 @@ UINT8 UnusedUpdSpace0[3]; /** Offset 0x0098 - MMIO High Base Address - MMIO High Base Address, a hex number for Bit[51:32] + MMIO High Base Address, a hex number for Bit[51:32]. Default: 0x6 (Gives 0x200) **/ UINT32 mmiohBase; /** Offset 0x009C - CPU Physical Address Limit - CPU Physical Address Limit + Enable(Default) or Disable CPU Physical Address Limit 0:Disable, 1:Enable **/ UINT8 CpuPaLimit; /** Offset 0x009D - High Gap - Enable or Disable High Gap + Enable or Disable(Default) High Gap $EN_DIS **/ UINT8 highGap; /** Offset 0x009E - MMIO High Size MMIO High Size, Number of 1GB contiguous regions to be assigned for MMIOH space - per CPU. Range 1-1024 + per CPU. Range 1-1024, Default: 3 **/ UINT16 mmiohSize; -/** Offset 0x00A0 - } TYPE:{Combo - Enable or Disable +/** Offset 0x00A0 - ISOC + Enable(Default) or Disable ISOC $EN_DIS **/ UINT8 isocEn; /** Offset 0x00A1 - DCA - Enable or Disable DCA + Enable or Disable(Default) DCA $EN_DIS **/ UINT8 dcaEn; @@ -414,121 +422,115 @@ **/ UINT8 UnusedUpdSpace1[2]; -/** Offset 0x00A4 - } TYPE:{Combo - Enable or Disable - $EN_DIS +/** Offset 0x00A4 - BoardTypeBitmask + Board Type Bitmask. Default: 0x1 **/ UINT32 BoardTypeBitmask; -/** Offset 0x00A8 - } TYPE:{Combo - Enable or Disable - $EN_DIS +/** Offset 0x00A8 - AllLanesPtr + Pointer to array of ALL_LANES_EPARAM_LINK_INFO **/ UINT32 AllLanesPtr; -/** Offset 0x00AC - } TYPE:{Combo - Enable or Disable - $EN_DIS +/** Offset 0x00AC - PerLanePtr + Pointer to array of PER_LANE_EPARAM_LINK_INFO **/ UINT32 PerLanePtr; -/** Offset 0x00B0 - } TYPE:{Combo - Enable or Disable - $EN_DIS +/** Offset 0x00B0 - AllLanesSizeOfTable + Number of elements in AllLanesPtr array. **/ UINT32 AllLanesSizeOfTable; -/** Offset 0x00B4 - } TYPE:{Combo - Enable or Disable - $EN_DIS +/** Offset 0x00B4 - PerLaneSizeOfTable + Number of elements in PerLanePtr array. **/ UINT32 PerLaneSizeOfTable; -/** Offset 0x00B8 - } TYPE:{Combo - Enable or Disable - $EN_DIS +/** Offset 0x00B8 - WaitTimeForPSBP + Number of milliseconds to wait for remote CPUs to initialize. Default: 30 sec **/ UINT32 WaitTimeForPSBP; -/** Offset 0x00BC - } TYPE:{Combo - Enable or Disable +/** Offset 0x00BC - IsKtiNvramDataReady + IsKtiNvramDataReady. Default: Disable $EN_DIS **/ UINT8 IsKtiNvramDataReady; -/** Offset 0x00BD - } TYPE:{Combo - Enable or Disable - $EN_DIS +/** Offset 0x00BD - BoardId + Board ID **/ UINT8 BoardId; -/** Offset 0x00BE - } TYPE:{Combo - Enable or Disable +/** Offset 0x00BE - WaSerializationEn + Enable(Default) or Disable BIOS serialization WA $EN_DIS **/ UINT8 WaSerializationEn; -/** Offset 0x00BF - } TYPE:{Combo - Enable or Disable +/** Offset 0x00BF - KtiInEnableMktme + Enable(Default) or Disable MkTme status decides D2Kti feature state $EN_DIS **/ UINT8 KtiInEnableMktme; -/** Offset 0x00C0 - Usage type for Processor VmxEnable Function - Processor VmxEnable Function, if enabled, the value is 0x01, if disabled, the value is 0x00 +/** Offset 0x00C0 - Processor VmxEnable Function + Enable(Default) or Disable Processor VmxEnable Function $EN_DIS **/ UINT8 VmxEnable; -/** Offset 0x00C1 - Usage type for Processor X2apic Function - Processor X2apic Function, if enabled, the value is 0x01, if disabled, the value is 0x00 +/** Offset 0x00C1 - Processor X2apic Function + Enable(Default) or Disable Processor X2apic Function + $EN_DIS **/ UINT8 X2apic; -/** Offset 0x00C2 - Usage type for DDR frequency limit - Processor X2apic Function, if enabled, the value is 0x01, if disabled, the value is 0x00 +/** Offset 0x00C2 - DDR frequency limit + Enable(Default) or Disable Processor X2apic Function **/ UINT8 DdrFreqLimit; -/** Offset 0x00C3 - Usage type for Memory Serial Debug Message Level - Processor X2apic Function, if enabled, the value is 0x01, if disabled, the value is 0x00 +/** Offset 0x00C3 - Memory Serial Debug Message Level + Enable(Default) or Disable Processor X2apic Function **/ UINT8 serialDebugMsgLvl; #if CONFIG(HAVE_FSPM_DIMM_WATERMARK_OPTION) /** Offset 0x00C4 - Usage type for Memory Refresh Watermark - Select Memory Refresh Watermark, 0: Auto (default), 1: High, 2: Low + Select Memory Refresh Watermark, 0: Auto, 1: High(Default), 2: Low **/ UINT8 MemRefreshWaterMark; #endif /** Offset 0x00C5 - IIO ConfigIOU0 ConfigIOU[MAX_SOCKET][0]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, - 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO + 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO(Default) **/ UINT8 IioConfigIOU0[8]; /** Offset 0x00CD - IIO ConfigIOU1 ConfigIOU[MAX_SOCKET][1]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, - 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO + 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO(Default) **/ UINT8 IioConfigIOU1[8]; /** Offset 0x00D5 - IIO ConfigIOU2 ConfigIOU[MAX_SOCKET][2]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, - 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO + 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO(Default) **/ UINT8 IioConfigIOU2[8]; /** Offset 0x00DD - IIO ConfigIOU3 ConfigIOU[MAX_SOCKET][3]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, - 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO + 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO(Default) **/ UINT8 IioConfigIOU3[8]; /** Offset 0x00E5 - IIO ConfigIOU4 ConfigIOU[MAX_SOCKET][4]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, - 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO + 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO(Default) **/ UINT8 IioConfigIOU4[8]; @@ -536,178 +538,182 @@ **/ UINT8 UnusedUpdSpace2[3]; -/** Offset 0x00F0 - Usage type for IIO PCIE Config Table Ptr - IIO PCIE Config Table Ptr +/** Offset 0x00F0 - IIO PCIE Config Table Ptr + Pointer to array of UPD_IIO_PCIE_PORT_CONFIG **/ UINT32 IioPcieConfigTablePtr; -/** Offset 0x00F4 - Usage type for IIO PCIE Config Table Number - IIO PCIE Config Table Number +/** Offset 0x00F4 - IIO PCIE Config Table Number + Number of elements in IioPcieConfigTablePtr array. **/ UINT32 IioPcieConfigTableNumber; -/** Offset 0x00F8 - Usage type for IIO PCIE Root Port Enable or Disable - IIO PCH rootport, if port is enabled, the value is 0x01, if the port is disabled, - the value is 0x00 +/** Offset 0x00F8 - IIO PCIE Root Port Enable + Enable(Default) or Disable IIO PCH rootport **/ UINT8 IIOPcieRootPortEnable; -/** Offset 0x00F9 - Usage type for IIO DeEmphasis - IIO DeEmphasis +/** Offset 0x00F9 - IIO DeEmphasis + IIO DeEmphasis. Default: 0x1 **/ UINT8 DeEmphasis; -/** Offset 0x00FA - Usage type for IIO PCIE Root Port link speed - IIO root port link speed +/** Offset 0x00FA - IIO PCIe Root Port Link Speed + IIO PCIe Root Port Link Speed. 0: Auto(Default), 1: Gen1, 2: Gen2, 3: Gen3, 4: Gen4 + 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3, 4:Gen4 **/ UINT8 IIOPciePortLinkSpeed; -/** Offset 0x00FB - Usage type for IIO PCIE Root Port Max Payload - IIO Root Port Max Payload +/** Offset 0x00FB - IIO PCIe Root Port Max Payload + IIO PCIe Root Port Max Payload. 0: 128B, 1: 256B, 2: 512B, 7: Auto(Default) + 0:128B, 1: 256B, 2:512B, 7:Auto **/ UINT8 IIOPcieMaxPayload; -/** Offset 0x00FC - Usage type for IIO DfxDnTxPreset - IIO DfxDnTxPreset +/** Offset 0x00FC - IIO DfxDnTxPreset + IIO Downstream Transmitter Preset. Default: Auto(0xFF), otherwise preset 0-10 **/ UINT8 DfxDnTxPreset; -/** Offset 0x00FD - Usage type for IIO DfxRxPreset - IIO DfxRxPreset +/** Offset 0x00FD - IIO DfxRxPreset + IIO Downstream Reciever Preset. Default: Auto(0xFF), otherwise preset 0-10 **/ UINT8 DfxRxPreset; -/** Offset 0x00FE - Usage type for IIO DfxUpTxPreset - IIO DfxUpTxPreset +/** Offset 0x00FE - IIO DfxUpTxPreset + IIO Upstream Transmitter Preset. Default: Auto(0xFF), otherwise preset 0-10 **/ UINT8 DfxUpTxPreset; -/** Offset 0x00FF - Usage type for IIO PcieCommonClock - IIO PcieCommonClock +/** Offset 0x00FF - IIO PCIe Common Clock + IIO PCIe Common Clock. 0: Disable, 1: Enable(Default), 2: Auto **/ UINT8 PcieCommonClock; -/** Offset 0x0100 - Usage type for IIO NtbPpd - IIO NtbPpd +/** Offset 0x0100 - IIO Non-Transparent Port Definition + IIO Non-Transparent Port Definition. 0: Transparent(Default), 1: Non-Transparent + Bridge, 2: Non-Transparent Root Port **/ UINT8 NtbPpd; -/** Offset 0x0101 - Usage type for IIO NtbBarSizeOverride - IIO NtbBarSizeOverride +/** Offset 0x0101 - IIO Non-Transparent Bridge BAR Size Override + Enable or Disable(Default) IIO Non-Transparent Bridge BAR Size Override. **/ UINT8 NtbBarSizeOverride; -/** Offset 0x0102 - Usage type for IIO NtbSplitBar - IIO NtbSplitBar +/** Offset 0x0102 - IIO Non-Transparent Bridge Split BAR Mode + Enable or Disable(Default) IIO Non-Transparent Bridge Split BAR Mode **/ UINT8 NtbSplitBar; -/** Offset 0x0103 - Usage type for IIO NtbBarSizeImBar1 - IIO NtbBarSizeImBar1 +/** Offset 0x0103 - IIO NtbBarSizeImBar1 + IIO NtbBarSizeImBar1. Default: 0x16 **/ UINT8 NtbBarSizeImBar1; -/** Offset 0x0104 - Usage type for IIO NtbBarSizeImBar2 - IIO PNtbBarSizeImBar2 +/** Offset 0x0104 - IIO NtbBarSizeImBar2 + IIO PNtbBarSizeImBar2. Default: 0x16 **/ UINT8 NtbBarSizeImBar2; -/** Offset 0x0105 - Usage type for IIO NtbBarSizeImBar2_0 - IIO PNtbBarSizeImBar2_0 +/** Offset 0x0105 - IIO NtbBarSizeImBar2_0 + IIO PNtbBarSizeImBar2_0. Default: 0x0C **/ UINT8 NtbBarSizeImBar2_0; -/** Offset 0x0106 - Usage type for IIO NtbBarSizeImBar2_1 - IIO NtbBarSizeImBar2_1 +/** Offset 0x0106 - IIO NtbBarSizeImBar2_1 + IIO NtbBarSizeImBar2_1. Default: 0x0C **/ UINT8 NtbBarSizeImBar2_1; -/** Offset 0x0107 - Usage type for IIO NtbBarSizeEmBarSZ1 - IIO NtbBarSizeEmBarSZ1 +/** Offset 0x0107 - IIO NtbBarSizeEmBarSZ1 + IIO NtbBarSizeEmBarSZ1. . Default: 0x16 **/ UINT8 NtbBarSizeEmBarSZ1; -/** Offset 0x0108 - Usage type for IIO NtbBarSizeEmBarSZ2 - IIO NtbBarSizeEmBarSZ2 +/** Offset 0x0108 - IIO NtbBarSizeEmBarSZ2 + IIO NtbBarSizeEmBarSZ2. . Default: 0x16 **/ UINT8 NtbBarSizeEmBarSZ2; -/** Offset 0x0109 - Usage type for IIO NtbBarSizeEmBarSZ2_0 - IIO NtbBarSizeEmBarSZ2_0 +/** Offset 0x0109 - IIO NtbBarSizeEmBarSZ2_0 + IIO NtbBarSizeEmBarSZ2_0. . Default: 0x0C **/ UINT8 NtbBarSizeEmBarSZ2_0; -/** Offset 0x010A - Usage type for IIO NtbBarSizeEmBarSZ2_1 - IIO NtbBarSizeEmBarSZ2_1 +/** Offset 0x010A - IIO NtbBarSizeEmBarSZ2_1 + IIO NtbBarSizeEmBarSZ2_1. . Default: 0x0C **/ UINT8 NtbBarSizeEmBarSZ2_1; -/** Offset 0x010B - Usage type for IIO NtbXlinkCtlOverride - IIO NtbXlinkCtlOverride +/** Offset 0x010B - IIO Non-Transparent Cross Link Override + IIO Non-Transparent Cross Link Override. 1:Operate as RP, 2:Operate as NTB-NTB (NT + Port), 3:Operate as NTB-> DSP (NTB EP)(Default) **/ UINT8 NtbXlinkCtlOverride; -/** Offset 0x010C - Usage type for IIO VT-D Function - IIO VT-D Function, if supported, the value is 0x01, if not supported, the value is 0x00 +/** Offset 0x010C - VT-d Support + Enable or Disable(Default) VT-d Support **/ UINT8 VtdSupport; -/** Offset 0x010D - Usage type for IIO Pcie Port Hide +/** Offset 0x010D - IIO PCIe Port Hide Hide or visible for IIO Pcie Port, 1 : Hide, 0 : Visible **/ UINT8 PEXPHIDE; -/** Offset 0x010E - Usage type for IIO Pcie Port Menu Hide - Hide or visible for IIO Pcie Port Menu, 1 : Hide, 0 : Visible +/** Offset 0x010E - IIO Pcie Port Menu Hide + Hide or visible for IIO PCIe Port Menu, 1 : Hide, 0 : Visible **/ UINT8 HidePEXPMenu; /** Offset 0x010F - PchSirqMode - Enable or Disable PchSirqMode + PchSirqMode. 0: Quiet Mode(Default) 1: Continuous Mode **/ UINT8 PchSirqMode; /** Offset 0x0110 - PchAdrEn - Enable or Disable PchAdr + PchAdr 0:PLATFORM POR, 1:FORCE ENABLE(Default), 2:FORCE DISABLE **/ UINT8 PchAdrEn; /** Offset 0x0111 - ThermalDeviceEnable - Enable or Disable ThermalDeviceEnable with PCI or ACPI mode + Thermal Device Mode. 0: Disable, 1: Enabled in PCI mode, 2: Enabled in ACPI + mode(Default) **/ UINT8 ThermalDeviceEnable; -/** Offset 0x0112 - } TYPE:{Combo - Root port swapping based on device connection status : TRUE or FALSE +/** Offset 0x0112 - PchPcieRootPortFunctionSwap + Root port swapping based on device connection status : TRUE(Default) or FALSE TRUE : 0x01, FALSE : 0x00 **/ UINT8 PchPcieRootPortFunctionSwap; /** Offset 0x0113 - PCH PCIE PLL Ssc Valid spread range : 0x00-0x14 (A value of 0 is SSC of 0.0%. A value of 20 is SSC - of 2.0%), Auto : 0xFE(Set to hardware default), Disable : 0xFF + of 2.0%), Auto : 0xFE(Set to hardware default), Disable(Default) : 0xFF **/ UINT8 PchPciePllSsc; -/** Offset 0x0114 - Usage type for PCH PCIE Root Port Index +/** Offset 0x0114 - PCH PCIE Root Port Index Index assigned to every PCH PCIE Root Port **/ UINT8 PchPciePortIndex[20]; -/** Offset 0x0128 - Usage type for PCH PCIE Root Port Enable or Disable - 0-19: PCH rootport, if port is enabled, the value is 0x01, if the port is disabled, - the value is 0x00 +/** Offset 0x0128 - PCH PCIE Root Port Enable or Disable + 0-19: PCH rootport, if port is enabled(Default), the value is 0x01, if the port + is disabled, the value is 0x00 **/ UINT8 PchPcieForceEnable[20]; -/** Offset 0x013C - Usage type for PCH PCIE Root Port Link Speed - 0-19: PCH rootport, 0x00 : Pcie Auto Speed, 0x01 : Pcie Gen1 Speed, 0x02 : Pcie - Gen2 Speed, 0x03 : Pcie Gen3 Speed +/** Offset 0x013C - PCH PCIE Root Port Link Speed + 0-19: PCH rootport, 0x00 : Pcie Auto Speed(Default), 0x01 : Pcie Gen1 Speed, 0x02 + : Pcie Gen2 Speed, 0x03 : Pcie Gen3 Speed **/ UINT8 PchPciePortLinkSpeed[20]; /** Offset 0x0150 - PchDciEn - Enable or Disable Pch DciEn + Enable or Disable(Default) PCH DCI **/ UINT8 PchDciEn; @@ -717,7 +723,7 @@ UINT8 MeUmaEnable; /** Offset 0x0152 - SerialIoUartDebugEnable - Enable SerialIo Uart debug library in FSP. + Enable(Default) or Disable SerialIo Uart debug library in FSP. 0:Disable, 1:Enable **/ UINT8 SerialIoUartDebugEnable; -- To view, visit https://review.coreboot.org/c/coreboot/+/46609 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc75f39f8f7a6d47690464dd4e5194f6e2ba12a8 Gerrit-Change-Number: 46609 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: newchange

1 1

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2020