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Change in coreboot[master]: Implementation of crashlog for intel TGL
by Patrick Georgi (Code Review) 10 Nov '20

10 Nov '20

Patrick Georgi has removed Martin Roth from this change. ( https://review.coreboot.org/c/coreboot/+/46965 ) Change subject: Implementation of crashlog for intel TGL ...................................................................... Removed reviewer Martin Roth. -- To view, visit https://review.coreboot.org/c/coreboot/+/46965 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e084dfb9e50832c4baae969eb87b6d9b0f0401e Gerrit-Change-Number: 46965 Gerrit-PatchSet: 2 Gerrit-Owner: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Nikunj Dadhania <nikunj.dadhania(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Francois Toguo Fotso <francois.toguo.fotso(a)intel.corp-partner.google.com> Gerrit-MessageType: deleteReviewer

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Change in coreboot[master]: Implementation of crashlog for intel TGL
by Francois Toguo Fotso (Code Review) 10 Nov '20

10 Nov '20

Francois Toguo Fotso has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46965 ) Change subject: Implementation of crashlog for intel TGL ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/46965 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e084dfb9e50832c4baae969eb87b6d9b0f0401e Gerrit-Change-Number: 46965 Gerrit-PatchSet: 2 Gerrit-Owner: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Francois Toguo Fotso <francois.toguo.fotso(a)intel.corp-partner.google.com> Gerrit-CC: Nikunj Dadhania <nikunj.dadhania(a)intel.com> Gerrit-Comment-Date: Tue, 10 Nov 2020 09:21:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Log PM event from an internal device
by Karthik Ramasubramanian (Code Review) 10 Nov '20

10 Nov '20

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47227 ) Change subject: soc/intel/tigerlake: Log PM event from an internal device ...................................................................... soc/intel/tigerlake: Log PM event from an internal device Add support to check for the Power Management (PM) Status bit for various internal devices like USB, CNVi etc. and log them into the event log for debugging purposes. BUG=b:172279037 BRANCH=volteer Change-Id: Ib3d0bf33d780444f8240f749a3319212c985950d Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/Makefile.inc M src/soc/intel/tigerlake/elog.c A src/soc/intel/tigerlake/xhci.c 4 files changed, 100 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/47227/1 diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index ed35bd6..c0fb764 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -55,6 +55,7 @@ select SOC_INTEL_COMMON_BLOCK_USB4 select SOC_INTEL_COMMON_BLOCK_USB4_PCIE select SOC_INTEL_COMMON_BLOCK_USB4_XHCI + select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG select SOC_INTEL_COMMON_FSP_RESET select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_RESET diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc index a25d0a4..3103d60 100644 --- a/src/soc/intel/tigerlake/Makefile.inc +++ b/src/soc/intel/tigerlake/Makefile.inc @@ -44,6 +44,7 @@ ramstage-y += soundwire.c ramstage-y += systemagent.c ramstage-y += me.c +ramstage-y += xhci.c smm-y += gpio.c smm-y += p2sb.c @@ -51,6 +52,7 @@ smm-y += smihandler.c smm-y += uart.c smm-y += elog.c +smm-y += xhci.c verstage-y += gpio.c diff --git a/src/soc/intel/tigerlake/elog.c b/src/soc/intel/tigerlake/elog.c index 84f0a7e..8e2db86 100644 --- a/src/soc/intel/tigerlake/elog.c +++ b/src/soc/intel/tigerlake/elog.c @@ -2,12 +2,26 @@ #include <bootstate.h> #include <console/console.h> +#include <device/pci_ops.h> #include <stdint.h> #include <elog.h> #include <intelblocks/pmclib.h> +#include <intelblocks/xhci.h> #include <soc/pci_devs.h> #include <soc/pm.h> +#define PME_STS_BIT (1 << 15) + +struct pme_status_info { +#ifdef __SIMPLE_DEVICE__ + pci_devfn_t dev; +#else + struct device *dev; +#endif + uint8_t reg_offset; + uint32_t elog_event; +}; + static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) { int i; @@ -20,6 +34,67 @@ } } +static void pch_log_add_elog_event(const struct pme_status_info *info) +{ + /* + * If wake source is XHCI, check for detailed wake source events on + * USB2/3 ports. + */ + if ((info->dev == PCH_DEV_XHCI) && + pch_xhci_update_wake_event(soc_get_xhci_usb_info())) + return; + + elog_add_event_wake(info->elog_event, 0); +} + +static void pch_log_pme_internal_wake_source(void) +{ + size_t i; +#ifdef __SIMPLE_DEVICE__ + pci_devfn_t dev; +#else + struct device *dev; +#endif + uint16_t val; + bool dev_found = false; + + struct pme_status_info pme_status_info[] = { + { PCH_DEV_HDA, 0x54, ELOG_WAKE_SOURCE_PME_HDA }, + { PCH_DEV_GBE, 0xcc, ELOG_WAKE_SOURCE_PME_GBE }, + { PCH_DEV_SATA, 0x74, ELOG_WAKE_SOURCE_PME_SATA }, + { PCH_DEV_CSE, 0x54, ELOG_WAKE_SOURCE_PME_CSE }, + { PCH_DEV_XHCI, 0x74, ELOG_WAKE_SOURCE_PME_XHCI }, + { PCH_DEV_USBOTG, 0x84, ELOG_WAKE_SOURCE_PME_XDCI }, + { PCH_DEV_CNVI_WIFI, 0xcc, ELOG_WAKE_SOURCE_PME_WIFI }, + }; + + for (i = 0; i < ARRAY_SIZE(pme_status_info); i++) { + dev = pme_status_info[i].dev; + if (!dev) + continue; + + val = pci_read_config16(dev, pme_status_info[i].reg_offset); + if ((val == 0xFFFF) || !(val & PME_STS_BIT)) + continue; + + pch_log_add_elog_event(&pme_status_info[i]); + dev_found = true; + } + + /* + * If device is still not found, but the wake source is internal PME, + * try probing XHCI ports to see if any of the USB2/3 ports indicate + * that it was the wake source. This path would be taken in case of GSMI + * logging with S0ix where the pci_pm_resume_noirq runs and clears the + * PME_STS_BIT in controller register. + */ + if (!dev_found) + dev_found = pch_xhci_update_wake_event(soc_get_xhci_usb_info()); + + if (!dev_found) + elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0); +} + static void pch_log_wake_source(struct chipset_power_state *ps) { /* Power Button */ @@ -38,9 +113,9 @@ if (ps->gpe0_sts[GPE_STD] & PME_STS) elog_add_event_wake(ELOG_WAKE_SOURCE_PME, 0); - /* Internal PME (TODO: determine wake device) */ + /* Internal PME */ if (ps->gpe0_sts[GPE_STD] & PME_B0_STS) - elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0); + pch_log_pme_internal_wake_source(); /* SMBUS Wake */ if (ps->gpe0_sts[GPE_STD] & SMB_WAK_STS) diff --git a/src/soc/intel/tigerlake/xhci.c b/src/soc/intel/tigerlake/xhci.c new file mode 100644 index 0000000..18bb129 --- /dev/null +++ b/src/soc/intel/tigerlake/xhci.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <intelblocks/xhci.h> + +#define XHCI_USB2_PORT_STATUS_REG 0x480 +#define XHCI_USB3_PORT_STATUS_REG 0x520 +#define XHCI_USB2_PORT_NUM 10 +#define XHCI_USB3_PORT_NUM 4 + +static const struct xhci_usb_info usb_info = { + .usb2_port_status_reg = XHCI_USB2_PORT_STATUS_REG, + .num_usb2_ports = XHCI_USB2_PORT_NUM, + .usb3_port_status_reg = XHCI_USB3_PORT_STATUS_REG, + .num_usb3_ports = XHCI_USB3_PORT_NUM, +}; + +const struct xhci_usb_info *soc_get_xhci_usb_info(void) +{ + return &usb_info; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/47227 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib3d0bf33d780444f8240f749a3319212c985950d Gerrit-Change-Number: 47227 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/jasperlake: Log PM event from an internal device
by Karthik Ramasubramanian (Code Review) 10 Nov '20

10 Nov '20

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47226 ) Change subject: soc/intel/jasperlake: Log PM event from an internal device ...................................................................... soc/intel/jasperlake: Log PM event from an internal device Add support to check for the Power Management (PM) Status bit for various internal devices like USB, CNVi etc. and log them into the event log for debugging purposes. BUG=b:172279037 TEST=Build and boot to OS in Drawlat. Ensure that the wake up event is logged into the event log for one of the internal devices eg. USB bluetooth. 17 | 2020-11-04 16:57:49 | S0ix Enter 18 | 2020-11-04 16:57:56 | S0ix Exit 19 | 2020-11-04 16:57:56 | Wake Source | PME - XHCI (USB 2.0 port) | 8 20 | 2020-11-04 16:57:56 | Wake Source | GPE # | 109 21 | 2020-11-04 16:59:00 | S0ix Enter 22 | 2020-11-04 16:59:06 | S0ix Exit 23 | 2020-11-04 16:59:06 | Wake Source | PME - XHCI (USB 2.0 port) | 8 24 | 2020-11-04 16:59:06 | Wake Source | GPE # | 109 Change-Id: I9f43675b698bf310f6b98b5e775d1259607abbcd Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/soc/intel/jasperlake/Kconfig M src/soc/intel/jasperlake/Makefile.inc M src/soc/intel/jasperlake/elog.c A src/soc/intel/jasperlake/xhci.c 4 files changed, 100 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/47226/1 diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index e84add0..294f19f8 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -52,6 +52,7 @@ select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP + select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG select SOC_INTEL_COMMON_FSP_RESET select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_RESET diff --git a/src/soc/intel/jasperlake/Makefile.inc b/src/soc/intel/jasperlake/Makefile.inc index 209d8a2..677b5f3 100644 --- a/src/soc/intel/jasperlake/Makefile.inc +++ b/src/soc/intel/jasperlake/Makefile.inc @@ -44,6 +44,7 @@ ramstage-y += systemagent.c ramstage-y += sd.c ramstage-y += me.c +ramstage-y += xhci.c smm-y += gpio.c smm-y += p2sb.c @@ -52,6 +53,7 @@ smm-y += smihandler.c smm-y += uart.c smm-y += elog.c +smm-y += xhci.c verstage-y += gpio.c diff --git a/src/soc/intel/jasperlake/elog.c b/src/soc/intel/jasperlake/elog.c index 235dc6e..62ea5d3 100644 --- a/src/soc/intel/jasperlake/elog.c +++ b/src/soc/intel/jasperlake/elog.c @@ -2,12 +2,26 @@ #include <bootstate.h> #include <console/console.h> +#include <device/pci_ops.h> #include <stdint.h> #include <elog.h> #include <intelblocks/pmclib.h> +#include <intelblocks/xhci.h> #include <soc/pci_devs.h> #include <soc/pm.h> +#define PME_STS_BIT (1 << 15) + +struct pme_status_info { +#ifdef __SIMPLE_DEVICE__ + pci_devfn_t dev; +#else + struct device *dev; +#endif + uint8_t reg_offset; + uint32_t elog_event; +}; + static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) { int i; @@ -20,6 +34,67 @@ } } +static void pch_log_add_elog_event(const struct pme_status_info *info) +{ + /* + * If wake source is XHCI, check for detailed wake source events on + * USB2/3 ports. + */ + if ((info->dev == PCH_DEV_XHCI) && + pch_xhci_update_wake_event(soc_get_xhci_usb_info())) + return; + + elog_add_event_wake(info->elog_event, 0); +} + +static void pch_log_pme_internal_wake_source(void) +{ + size_t i; +#ifdef __SIMPLE_DEVICE__ + pci_devfn_t dev; +#else + struct device *dev; +#endif + uint16_t val; + bool dev_found = false; + + struct pme_status_info pme_status_info[] = { + { PCH_DEV_HDA, 0x54, ELOG_WAKE_SOURCE_PME_HDA }, + { PCH_DEV_GBE, 0xcc, ELOG_WAKE_SOURCE_PME_GBE }, + { PCH_DEV_SATA, 0x74, ELOG_WAKE_SOURCE_PME_SATA }, + { PCH_DEV_CSE, 0x54, ELOG_WAKE_SOURCE_PME_CSE }, + { PCH_DEV_XHCI, 0x74, ELOG_WAKE_SOURCE_PME_XHCI }, + { PCH_DEV_USBOTG, 0x84, ELOG_WAKE_SOURCE_PME_XDCI }, + { PCH_DEV_CNVI_WIFI, 0xcc, ELOG_WAKE_SOURCE_PME_WIFI }, + }; + + for (i = 0; i < ARRAY_SIZE(pme_status_info); i++) { + dev = pme_status_info[i].dev; + if (!dev) + continue; + + val = pci_read_config16(dev, pme_status_info[i].reg_offset); + if ((val == 0xFFFF) || !(val & PME_STS_BIT)) + continue; + + pch_log_add_elog_event(&pme_status_info[i]); + dev_found = true; + } + + /* + * If device is still not found, but the wake source is internal PME, + * try probing XHCI ports to see if any of the USB2/3 ports indicate + * that it was the wake source. This path would be taken in case of GSMI + * logging with S0ix where the pci_pm_resume_noirq runs and clears the + * PME_STS_BIT in controller register. + */ + if (!dev_found) + dev_found = pch_xhci_update_wake_event(soc_get_xhci_usb_info()); + + if (!dev_found) + elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0); +} + static void pch_log_wake_source(struct chipset_power_state *ps) { /* Power Button */ @@ -38,9 +113,9 @@ if (ps->gpe0_sts[GPE_STD] & PME_STS) elog_add_event_wake(ELOG_WAKE_SOURCE_PME, 0); - /* Internal PME (TODO: determine wake device) */ + /* Internal PME */ if (ps->gpe0_sts[GPE_STD] & PME_B0_STS) - elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0); + pch_log_pme_internal_wake_source(); /* SMBUS Wake */ if (ps->gpe0_sts[GPE_STD] & SMB_WAK_STS) diff --git a/src/soc/intel/jasperlake/xhci.c b/src/soc/intel/jasperlake/xhci.c new file mode 100644 index 0000000..424751e --- /dev/null +++ b/src/soc/intel/jasperlake/xhci.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <intelblocks/xhci.h> + +#define XHCI_USB2_PORT_STATUS_REG 0x480 +#define XHCI_USB3_PORT_STATUS_REG 0x500 +#define XHCI_USB2_PORT_NUM 8 +#define XHCI_USB3_PORT_NUM 6 + +static const struct xhci_usb_info usb_info = { + .usb2_port_status_reg = XHCI_USB2_PORT_STATUS_REG, + .num_usb2_ports = XHCI_USB2_PORT_NUM, + .usb3_port_status_reg = XHCI_USB3_PORT_STATUS_REG, + .num_usb3_ports = XHCI_USB3_PORT_NUM, +}; + +const struct xhci_usb_info *soc_get_xhci_usb_info(void) +{ + return &usb_info; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/47226 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f43675b698bf310f6b98b5e775d1259607abbcd Gerrit-Change-Number: 47226 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: tests: Add lib/edid-test test case
by Name of user not set (Code Review) 10 Nov '20

10 Nov '20

Name of user not set #1003143 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46817 ) Change subject: tests: Add lib/edid-test test case ...................................................................... tests: Add lib/edid-test test case Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Change-Id: I796e660eebc4d2c3c32207bd3a6ee44aaffeb325 --- A tests/include/lib/edid-test.h M tests/lib/Makefile.inc A tests/lib/edid-test.c M tests/stubs/console.c 4 files changed, 1,373 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/46817/1 diff --git a/tests/include/lib/edid-test.h b/tests/include/lib/edid-test.h new file mode 100644 index 0000000..073905d --- /dev/null +++ b/tests/include/lib/edid-test.h @@ -0,0 +1,196 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdlib.h> +#include <commonlib/bsd/helpers.h> + + +struct edid_raw { + uint8_t header[8]; + + /* Display product identification */ + uint16_t manufacturer_id; + uint16_t product_code; + uint32_t serial_number; + uint8_t manufacture_week; + uint8_t manufacture_year; + + /* EDID version information */ + uint8_t edid_version; + uint8_t edid_revision; + + /* Basic display parameters */ + uint8_t video_input_type; + uint8_t horizontal_size; /* [cm] */ + uint8_t vertical_size; /* [cm] */ + uint8_t display_gamma; + uint8_t supported_features; + + /* Color space definition */ + uint8_t color_characteristics[10]; + + /* Timing information */ + uint8_t established_supported_timings[2]; + uint8_t manufacturers_reserved_timing; + uint8_t standard_timings_supported[16]; + uint8_t descriptor_block_1[18]; + uint8_t descriptor_block_2[18]; + uint8_t descriptor_block_3[18]; + uint8_t descriptor_block_4[18]; + + /* Number of optional 128-byte extension blocks */ + uint8_t extension_flag; + + uint8_t checksum; +} __packed; + +_Static_assert(sizeof(struct edid_raw) == 128); + +#define EDID_HEADER_RAW { 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00 } +#define EDID_HEADER_INVALID_RAW { 0, 0, 0, 0, 0, 0, 0, 0 } + +#define EDID_MANUFACTURER_ID 0xcb55 +#define EDID_MANUFACTURER_NAME "UNK" +#define EDID_PRODUCT_CODE 0x1234 +#define EDID_SERIAL_NUMBER 0x56789ABC +#define EDID_MANUFACTURE_WEEK 23u +#define EDID_MANUFACTURE_NO_WEEK 0u +#define EDID_MANUFACTURE_YEAR (2015u - 1990u) + +/* Video Input Definition for Analog Video Signal Interface */ +#define EDID_ANALOG_VSI (0u << 7) +#define EDID_SIGNAL_LEVEL_0 0u +#define EDID_SIGNAL_LEVEL_1 (1u << 5) +#define EDID_SIGNAL_LEVEL_2 (2u << 5) +#define EDID_SIGNAL_LEVEL_3 (3u << 5) +#define EDID_VIDEO_SETUP_BLANK_EQ_BLACK 0u +#define EDID_VIDEO_SETUP_BLANK_TO_BLACK (1u << 4) +#define EDID_SEPARATE_SYNC_H_AND_V(v) ((v != 0 ? 0x1 : 0x0) << 3) +#define EDID_COMPOSITE_SYNC_H(v) ((v != 0 ? 0x1 : 0x0) << 2) +#define EDID_COMPOSITE_SYNC_ON_GREEN(v) ((v != 0 ? 0x1 : 0x0) << 1) +#define EDID_SERRATION_VSYNC(v) (v != 0 ? 0x1 : 0x0) + +/* Video Input Definition for Digital Video Signal Interface */ +#define EDID_DIGITAL_VSI (1u << 7) +#define EDID_COLOR_BIT_DEPTH_UNDEFINED 0u +#define EDID_COLOR_BIT_DEPTH_6B (1u << 4) +#define EDID_COLOR_BIT_DEPTH_8B (2u << 4) +#define EDID_COLOR_BIT_DEPTH_10B (3u << 4) +#define EDID_COLOR_BIT_DEPTH_12B (4u << 4) +#define EDID_COLOR_BIT_DEPTH_14B (5u << 4) +#define EDID_COLOR_BIT_DEPTH_16B (6u << 4) +#define EDID_INTERFACE_UNDEFINED 0u +#define EDID_INTERFACE_DVI 1u +#define EDID_INTERFACE_HDMI_A 2u +#define EDID_INTERFACE_HDMI_B 3u +#define EDID_INTERFACE_MDDI 4u +#define EDID_INTERFACE_DP 5u + +/* BEGIN Supported features */ +#define EDID_STANDBY_MODE(v) ((v != 0 ? 0x1 : 0x0) << 7) +#define EDID_SUSPEND_MODE(v) ((v != 0 ? 0x1 : 0x0) << 6) +#define EDID_ACTIVE_OFF(v) ((v != 0 ? 0x1 : 0x0) << 5) +/* For analog interface */ +#define EDID_COLOR_TYPE_MONO 0u +#define EDID_COLOR_TYPE_RGB (1u << 3) +#define EDID_COLOR_TYPE_NON_RGB (2u << 3) +#define EDID_COLOR_TYPE_UNDEFINED (3u << 3) +/* For digital interface */ +#define EDID_COLOR_FORMAT_RGB444 0u +#define EDID_COLOR_FORMAT_RGB444_YCRCB444 (1u << 3) +#define EDID_COLOR_FORMAT_RGB444_YCRCB422 (2u << 3) +#define EDID_COLOR_FORMAT_RGB444_YCRCB422_YCRCB422 (3u << 3) + +#define EDID_SRGB_SUPPORTED(v) (((v) == 0 ? 0u : 1u) << 2) +#define EDID_PREFERRED_TIMING_EXTENDED_INFO (1u << 1) +#define EDID_PREFERRED_TIMING_NO_EXTENDED_INFO 0u +#define EDID_DISPLAY_FREQUENCY_CONTINUOUS 1u +#define EDID_DISPLAY_FREQUENCY_NON_CONTINUOUS 0u +/* END Supported features */ + +/* Red X 0.640 */ +#define EDID_COLOR_R_X 0x25 +/* Red Y 0.330 */ +#define EDID_COLOR_R_Y 0x152 +/* Green X 0.300 */ +#define EDID_COLOR_G_X 0x13a +/* Green Y 0.600 */ +#define EDID_COLOR_G_Y 0x267 +/* Blue X 0.150 */ +#define EDID_COLOR_B_X 0x9a +/* Blue Y 0.060 */ +#define EDID_COLOR_B_Y 0x3e +/* White X 0.3125 */ +#define EDID_COLOR_W_X 0xa +/* White Y 0.3291 */ +#define EDID_COLOR_W_Y 0x22a + +/* 1 and 0 bits of each color */ +#define EDID_COLOR_R_X10_Y10 (((EDID_COLOR_R_X & 0x3) << 2) | (EDID_COLOR_R_Y & 0x3)) +#define EDID_COLOR_G_X10_Y10 (((EDID_COLOR_G_X & 0x3) << 2) | (EDID_COLOR_G_Y & 0x3)) +#define EDID_COLOR_B_X10_Y10 (((EDID_COLOR_B_X & 0x3) << 2) | (EDID_COLOR_B_Y & 0x3)) +#define EDID_COLOR_W_X10_Y10 (((EDID_COLOR_W_X & 0x3) << 2) | (EDID_COLOR_W_Y & 0x3)) + +/* Concatenated 0 and 1 bits of each color. To be put + * as first and second byte of color characteristic. */ +#define EDID_COLOR_RG_XY ((EDID_COLOR_R_X10_Y10 << 4) | EDID_COLOR_G_X10_Y10) +#define EDID_COLOR_BW_XY ((EDID_COLOR_B_X10_Y10 << 4) | EDID_COLOR_W_X10_Y10) + +/* Bits 9 through 2 of each color */ +#define EDID_COLOR_R_X92 (EDID_COLOR_R_X >> 2) +#define EDID_COLOR_R_Y92 (EDID_COLOR_R_Y >> 2) +#define EDID_COLOR_G_X92 (EDID_COLOR_G_X >> 2) +#define EDID_COLOR_G_Y92 (EDID_COLOR_G_Y >> 2) +#define EDID_COLOR_B_X92 (EDID_COLOR_B_X >> 2) +#define EDID_COLOR_B_Y92 (EDID_COLOR_B_Y >> 2) +#define EDID_COLOR_W_X92 (EDID_COLOR_W_X >> 2) +#define EDID_COLOR_W_Y92 (EDID_COLOR_W_Y >> 2) + +#define EDID_ESTABLISHED_TIMINGS_1_800x600_60Hz 1u +#define EDID_ESTABLISHED_TIMINGS_1_800x600_56Hz (1u << 1) +#define EDID_ESTABLISHED_TIMINGS_1_640x480_75Hz (1u << 2) +#define EDID_ESTABLISHED_TIMINGS_1_640x480_72Hz (1u << 3) +#define EDID_ESTABLISHED_TIMINGS_1_640x480_67Hz (1u << 4) +#define EDID_ESTABLISHED_TIMINGS_1_640x480_60Hz (1u << 5) +#define EDID_ESTABLISHED_TIMINGS_1_720x400_88Hz (1u << 6) +#define EDID_ESTABLISHED_TIMINGS_1_720x400_70Hz (1u << 7) + +#define EDID_ESTABLISHED_TIMINGS_2_1280x1024_75Hz 1u +#define EDID_ESTABLISHED_TIMINGS_2_1024x768_75Hz (1u << 1) +#define EDID_ESTABLISHED_TIMINGS_2_1024x768_70Hz (1u << 2) +#define EDID_ESTABLISHED_TIMINGS_2_1024x768_60Hz (1u << 3) +#define EDID_ESTABLISHED_TIMINGS_2_1024x768_80HzI (1u << 4) +#define EDID_ESTABLISHED_TIMINGS_2_832x624_75Hz (1u << 5) +#define EDID_ESTABLISHED_TIMINGS_2_800x600_75Hz (1u << 6) +#define EDID_ESTABLISHED_TIMINGS_2_800x600_72Hz (1u << 7) + +#define EDID_MANUFACTURERS_TIMINGS_1152x870_75Hz (1u << 7) + +#define EDID_HORIZONTAL_ACCESSIBLE_PIXELS(px) (((px) / 8 - 31) & 0xFF) +#define EDID_ASPECT_RATIO_16_10 0u +#define EDID_ASPECT_RATIO_4_3 (1u << 6) +#define EDID_ASPECT_RATIO_5_4 (2u << 6) +#define EDID_ASPECT_RATIO_16_9 (3u << 6) +#define EDID_FIELD_REFRESH_RATE(hz) (((hz) - 60) & 0x1f) + +#define EDID_PIXEL_CLOCK(v) (((v) / 10000) & 0xFFFF) + +#define EDID_RAW_DEFAULT_PARAMS .header = EDID_HEADER_RAW, \ + .edid_version = 1, \ + .edid_revision = 4, \ + .manufacturer_id = EDID_MANUFACTURER_ID, \ + .product_code = EDID_PRODUCT_CODE, \ + .serial_number = EDID_SERIAL_NUMBER, \ + .manufacture_week = EDID_MANUFACTURE_NO_WEEK, \ + .manufacture_year = EDID_MANUFACTURE_YEAR, \ + .color_characteristics = { \ + EDID_COLOR_RG_XY, \ + EDID_COLOR_BW_XY, \ + EDID_COLOR_R_X92, \ + EDID_COLOR_R_Y92, \ + EDID_COLOR_G_X92, \ + EDID_COLOR_G_Y92, \ + EDID_COLOR_B_X92, \ + EDID_COLOR_B_Y92, \ + EDID_COLOR_W_X92, \ + EDID_COLOR_W_Y92, \ + } diff --git a/tests/lib/Makefile.inc b/tests/lib/Makefile.inc index 3062bca..e3b1bb8 100644 --- a/tests/lib/Makefile.inc +++ b/tests/lib/Makefile.inc @@ -4,6 +4,7 @@ tests-y += b64_decode-test tests-y += hexstrtobin-test tests-y += imd-test +tests-y += edid-test string-test-srcs += tests/lib/string-test.c string-test-srcs += src/lib/string.c @@ -17,4 +18,8 @@ imd-test-srcs += tests/lib/imd-test.c imd-test-srcs += tests/stubs/console.c -imd-test-srcs += src/lib/imd.c \ No newline at end of file +imd-test-srcs += src/lib/imd.c +edid-test-srcs += tests/lib/edid-test.c +edid-test-srcs += src/lib/edid.c +edid-test-srcs += tests/stubs/console.c + diff --git a/tests/lib/edid-test.c b/tests/lib/edid-test.c new file mode 100644 index 0000000..5f320d3 --- /dev/null +++ b/tests/lib/edid-test.c @@ -0,0 +1,1155 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdlib.h> +#include <tests/test.h> +#include <edid.h> +#include <assert.h> +#include <string.h> +#include <lib/edid-test.h> + + +static uint8_t get_raw_edid_checksum(const unsigned char *x) +{ + unsigned char sum = 0; + int i; + for (i = 0; i < 127; ++i) + sum += x[i]; + + return 256 - sum; +} + +static void edid_raw_calc_checksum(struct edid_raw *raw) +{ + raw->checksum = get_raw_edid_checksum((const unsigned char *)raw); +} + +static void test_decode_edid_no_edid(void **state) +{ + assert_int_equal(EDID_ABSENT, decode_edid(NULL, 0, NULL)); +} + +static void test_decode_edid_invalid_header(void **state) +{ + struct edid_raw raw = { + .header = EDID_HEADER_INVALID_RAW + }; + raw.checksum = get_raw_edid_checksum((const unsigned char *)&raw); + + assert_int_equal(EDID_ABSENT, decode_edid((unsigned char *)&raw, sizeof(raw), NULL)); +} + +static void test_decode_edid_frame_1(void **state) +{ + struct edid out; + struct edid_raw raw = { + EDID_RAW_DEFAULT_PARAMS, + .video_input_type = EDID_ANALOG_VSI + | EDID_SIGNAL_LEVEL_0 + | EDID_VIDEO_SETUP_BLANK_EQ_BLACK + | EDID_SEPARATE_SYNC_H_AND_V(1) + | EDID_COMPOSITE_SYNC_H(1) + | EDID_COMPOSITE_SYNC_ON_GREEN(1) + | EDID_SERRATION_VSYNC(1), + .horizontal_size = 43, /* [cm] */ + .vertical_size = 32, /* [cm] */ + .display_gamma = 120, /* 220% */ + .supported_features = EDID_STANDBY_MODE(0) + | EDID_SUSPEND_MODE(0) + | EDID_ACTIVE_OFF(1) + | EDID_COLOR_FORMAT_RGB444 + | EDID_SRGB_SUPPORTED(0) + | EDID_PREFERRED_TIMING_EXTENDED_INFO + | EDID_DISPLAY_FREQUENCY_CONTINUOUS, + .established_supported_timings = { + [0] = EDID_ESTABLISHED_TIMINGS_1_720x400_70Hz + | EDID_ESTABLISHED_TIMINGS_1_720x400_88Hz + | EDID_ESTABLISHED_TIMINGS_1_640x480_60Hz + | EDID_ESTABLISHED_TIMINGS_1_640x480_67Hz + | EDID_ESTABLISHED_TIMINGS_1_640x480_72Hz + | EDID_ESTABLISHED_TIMINGS_1_640x480_75Hz + | EDID_ESTABLISHED_TIMINGS_1_800x600_56Hz + | EDID_ESTABLISHED_TIMINGS_1_800x600_60Hz, + [1] = EDID_ESTABLISHED_TIMINGS_2_800x600_72Hz + | EDID_ESTABLISHED_TIMINGS_2_800x600_75Hz + | EDID_ESTABLISHED_TIMINGS_2_832x624_75Hz + | EDID_ESTABLISHED_TIMINGS_2_1024x768_80HzI + | EDID_ESTABLISHED_TIMINGS_2_1024x768_60Hz + | EDID_ESTABLISHED_TIMINGS_2_1024x768_70Hz + | EDID_ESTABLISHED_TIMINGS_2_1024x768_75Hz + | EDID_ESTABLISHED_TIMINGS_2_1280x1024_75Hz, + }, + .manufacturers_reserved_timing = EDID_MANUFACTURERS_TIMINGS_1152x870_75Hz, + .standard_timings_supported = { + [0] = EDID_HORIZONTAL_ACCESSIBLE_PIXELS(1600), + [1] = EDID_ASPECT_RATIO_4_3 | EDID_FIELD_REFRESH_RATE(85), + + [2] = EDID_HORIZONTAL_ACCESSIBLE_PIXELS(1600), + [3] = EDID_ASPECT_RATIO_4_3 | EDID_FIELD_REFRESH_RATE(75), + + [4] = EDID_HORIZONTAL_ACCESSIBLE_PIXELS(1600), + [5] = EDID_ASPECT_RATIO_4_3 | EDID_FIELD_REFRESH_RATE(70), + + [6] = EDID_HORIZONTAL_ACCESSIBLE_PIXELS(1600), + [7] = EDID_ASPECT_RATIO_4_3 | EDID_FIELD_REFRESH_RATE(65), + + [8] = EDID_HORIZONTAL_ACCESSIBLE_PIXELS(1280), + [9] = EDID_ASPECT_RATIO_5_4 | EDID_FIELD_REFRESH_RATE(85), + + [10] = EDID_HORIZONTAL_ACCESSIBLE_PIXELS(1280), + [11] = EDID_ASPECT_RATIO_5_4 | EDID_FIELD_REFRESH_RATE(60), + + [12] = EDID_HORIZONTAL_ACCESSIBLE_PIXELS(1024), + [13] = EDID_ASPECT_RATIO_4_3 | EDID_FIELD_REFRESH_RATE(85), + + [14] = EDID_HORIZONTAL_ACCESSIBLE_PIXELS(800), + [15] = EDID_ASPECT_RATIO_4_3 | EDID_FIELD_REFRESH_RATE(85), + }, + .descriptor_block_1 = { + [0] = EDID_PIXEL_CLOCK(162000000u) & 0xFF, + [1] = (EDID_PIXEL_CLOCK(162000000u) >> 8) & 0xFF, + + /* + * Horizontal Addressable Video is 1600px + * Horizontal Blanking is 560px + */ + [2] = 0x40, [3] = 0x30, [4] = 0x62, + + /* + * Vertical Addressable Video is 1200 lines + * Vertical Blanking is 50 lines + */ + [5] = 0xB0, [6] = 0x32, [7] = 0x40, + + [8] = 64u, /* Horizontal Front Porch in pixels */ + [9] = 192u, /* Horizontal Pulse Sync Width in pixels */ + [10] = 0x13, /* Vertical Front Porch is 1 line */ + [11] = 0x00, /* Vertical Sync Pulse Width is 3 lines */ + + /* + * Horizontal Addressable Image Size is 427mm + * Vertical Addressable Image Size is 320mm + */ + [12] = 0xAB, [13] = 0x40, [14] = 0x11, + + [15] = 0x00, /* Horizontal border size is 0px*/ + [16] = 0x00, /* Vertical Border Size is 0px */ + + /* + * Timing is Non-Interlaced Video, + * Stereo Video is not supported, + * Digital separate syncs are requires. + * */ + [17] = 0x1E, + }, + .descriptor_block_2 = { + /* Display Range Limits Block Tag */ + [0] = 0, [1] = 0, [2] = 0, [3] = 0xFD, + + [4] = 0, /* Horizontal and Vertical Rate Offsets are zero */ + [5] = 50u, /* Minimum Vertical Freq is 50Hz */ + [6] = 90u, /* Maximum Vertical Freq is 90Hz */ + + [7] = 30u, /* Minimum Horizontal Freq is 30kHz */ + [8] = 110u, /* Maximum Horizontal Freq is 110kHz */ + [9] = 23u, /* Maximum Pixel Clock Freq i 230MHz */ + [10] = 0x4, /* Begin CVT Support Info */ + [11] = 0x11, /* Compatible with CVT Version 1.1 */ + [12] = 0, /* Maimum Pixel Clock Freq remains at 230MHz */ + [13] = 200, /* Maximum Active Pixels per Pile is 1600 */ + [14] = 0x90, /* Supported aspect ratios: 4:3, 5:4 */ + + /* Preferred Aspect Ratio is 4:3, Standard CVT Blanking is supported */ + [15] = 0, + [16] = 0x50, /* H. & V. Stretch are supported and Shrinks are not */ + [17] = 60u, /* Preferred Refresh Rate is 60Hz */ + }, + .descriptor_block_3 = { + /* Established Timings III Block Tag */ + [0] = 0, [1] = 0, [2] = 0, [3] = 0xF7, [4] = 0, + + [5] = 10u, /* VESA DMT Standard Version #10 */ + /* + * 640x350@85Hz, + * 640x400@85Hz, + * 720x400@85Hz, + * 640x480@85Hz, + * 800x600@85Hz, + * 1024x768@85Hz, + * 1152x864@75Hz + */ + [6] = 0x7F, + + /* + * 1280x960@60Hz, + * 1280x960@85Hz, + * 1280x1024@60Hz, + * 1280x1024@85Hz + */ + [7] = 0x0F, + + /* + * 1400x1050@60Hz (Normal Blanking), + * 1400x1050@75Hz are supported. + */ + [8] = 0x03, + + /* + * 1400x1050@85Hz, + * 1600x1200@60Hz, + * 1600x1200@65Hz, + * 1600x1200@70Hz are supported. + */ + [9] = 0x87, + + /* + * 1600x1200@75Hz, + * 1600x1200@85Hz are supported. + */ + [10] = 0xC0, + + /* 1920 timings not supported */ + [11] = 0x0, + + [12 ... 17] = 0, + }, + .descriptor_block_4 = { + /* Display Product Name Block Tag */ + [0] = 0, [1] = 0, [2] = 0, [3] = 0xFC, [4] = 0, + + /* Product name */ + [5] = 'A', + [6] = 'B', + [7] = 'C', + [8] = ' ', + [9] = 'L', + [10] = 'C', + [11] = 'D', + [12] = '2', + [13] = '1', + [14] = '\n', + [15] = ' ', + [16] = ' ', + [17] = ' ', + }, + .extension_flag = 0x0, /* No extensions */ + }; + + edid_raw_calc_checksum(&raw); + + /* Only checking if frame is present. Don't care if is conformant. + * In real-life situations frames often are not 100% conformant, + * but are at least correct when it comes to key data fields. */ + assert_int_not_equal(EDID_ABSENT, + decode_edid((unsigned char *)&raw, + sizeof(struct edid_raw), + &out)); + + assert_int_equal(32, out.framebuffer_bits_per_pixel); + assert_int_equal(0, out.panel_bits_per_color); + assert_int_equal(0, out.panel_bits_per_pixel); + assert_int_equal(0, out.link_clock); + assert_int_equal(1600, out.x_resolution); + assert_int_equal(1200, out.y_resolution); + assert_int_equal(6400, out.bytes_per_line); + assert_int_equal(0, out.hdmi_monitor_detected); + assert_int_equal(0, strnlen(out.ascii_string, ARRAY_SIZE(out.ascii_string))); + assert_string_equal(out.manufacturer_name, EDID_MANUFACTURER_NAME); + + /* Mode */ + assert_null(out.mode.name); + assert_int_equal(162000, out.mode.pixel_clock); + assert_int_equal(1, out.mode.lvds_dual_channel); + assert_int_equal(0, out.mode.refresh); + assert_int_equal(1600, out.mode.ha); + assert_int_equal(560, out.mode.hbl); + assert_int_equal(64, out.mode.hso); + assert_int_equal(192, out.mode.hspw); + assert_int_equal(0, out.mode.hborder); + assert_int_equal(1200, out.mode.va); + assert_int_equal(50, out.mode.vbl); + assert_int_equal(1, out.mode.vso); + assert_int_equal(0, out.mode.vborder); + assert_int_equal(43, out.mode.phsync); + assert_int_equal(43, out.mode.pvsync); + assert_int_equal(0, out.mode.x_mm); + assert_int_equal(0, out.mode.y_mm); + + assert_int_equal(1, out.mode_is_supported[EDID_MODE_640x480_60Hz]); + assert_int_equal(0, out.mode_is_supported[EDID_MODE_720x480_60Hz]); + assert_int_equal(0, out.mode_is_supported[EDID_MODE_1280x720_60Hz]); + assert_int_equal(0, out.mode_is_supported[EDID_MODE_1920x1080_60Hz]); +} + +static void test_decode_edid_frame_2(void **state) +{ + struct edid out; + unsigned char raw_data[128 * 2]; /* Frame with one extension */ + struct edid_raw raw = { + EDID_RAW_DEFAULT_PARAMS, + .video_input_type = EDID_DIGITAL_VSI + | EDID_INTERFACE_HDMI_A + | EDID_COLOR_BIT_DEPTH_8B, + .horizontal_size = 16, /* Aspect ratio 16:9 in landscape */ + .vertical_size = 0, /* Landscape flag */ + .display_gamma = 120, /* 220% */ + .supported_features = EDID_STANDBY_MODE(0) + | EDID_SUSPEND_MODE(0) + | EDID_ACTIVE_OFF(0) + | EDID_COLOR_FORMAT_RGB444_YCRCB422_YCRCB422 + | EDID_SRGB_SUPPORTED(1) + | EDID_PREFERRED_TIMING_EXTENDED_INFO + | EDID_DISPLAY_FREQUENCY_NON_CONTINUOUS, + + .established_supported_timings = { + [0] = EDID_ESTABLISHED_TIMINGS_1_640x480_60Hz, + [1] = 0, + }, + .manufacturers_reserved_timing = 0, + .standard_timings_supported = { [0 ... 15] = 0, }, + .descriptor_block_1 = { + [0] = EDID_PIXEL_CLOCK(148500000u) & 0xFF, + [1] = (EDID_PIXEL_CLOCK(148500000u) >> 8) & 0xFF, + + /* Horizontal Addressable Video is 1920px + * Horizontal Blanking is 280px + */ + [2] = 0x80, [3] = 0x18, [4] = 0x71, + + /* Vertical Addressable Video is 1080 lines + * Vertical Blanking is 45 lines + */ + [5] = 0x38, [6] = 0x2D, [7] = 0x40, + + [8] = 88u, /* Horizontal Front Porch in pixels */ + [9] = 44u, /* Horizontal Pulse Sync Width in pixels */ + [10] = 4u, /* Vertical Front Porch is 4 lines */ + [11] = 5u, /* Vertical Sync Pulse Width is 5 lines */ + + /* Horizontal Addressable Image Size is 1039mm + * Vertical Addressable Image Size is 584mm + */ + [12] = 0x0F, [13] = 0x48, [14] = 0x42, + + [15] = 0x00, /* Horizontal border size is 0px*/ + [16] = 0x00, /* Vertical Border Size is 0px */ + + /* Timing is Non-Interlaced Video, + * Stereo Video is not supported, + * Digital separate and syncs are requires. + */ + [17] = 0x1E, + }, + .descriptor_block_2 = { + [0] = EDID_PIXEL_CLOCK(74250000u) & 0xFF, + [1] = (EDID_PIXEL_CLOCK(74250000u) >> 8) & 0xFF, + + /* Horizontal Addressable Video is 1920px + * Horizontal Blanking is 280px + */ + [2] = 0x80, [3] = 0x18, [4] = 0x71, + + /* Vertical Addressable Video is 540 lines + * Vertical Blanking is 22 lines + */ + [5] = 0x1C, [6] = 0x16, [7] = 0x20, + + [8] = 88u, /* Horizontal Front Porch in pixels */ + [9] = 44u, /* Horizontal Pulse Sync Width in pixels */ + [10] = 0x25, /* Vertical Front Porch is 2 lines */ + [11] = 0x00, /* Vertical Sync Pulse Width is 5 lines */ + + /* Horizontal Addressable Image Size is 1039mm + * Vertical Addressable Image Size is 584mm + */ + [12] = 0x0F, [13] = 0x48, [14] = 0x42, + + [15] = 0x00, /* Horizontal border size is 0px*/ + [16] = 0x00, /* Vertical Border Size is 0px */ + + /* Timing is Interlaced Video, + * Stereo Video is not supported, + * Digital separate and syncs are requires. + */ + [17] = 0x9E, + }, + .descriptor_block_3 = { + [0] = EDID_PIXEL_CLOCK(74250000u) & 0xFF, + [1] = (EDID_PIXEL_CLOCK(74250000u) >> 8) & 0xFF, + + /* Horizontal Addressable Video is 1280px + * Horizontal Blanking is 370px + */ + [2] = 0x00, [3] = 0x72, [4] = 0x51, + + /* Vertical Addressable Video is 720 lines + * Vertical Blanking is 30 lines + */ + [5] = 0xD0, [6] = 0x1E, [7] = 0x20, + + [8] = 110u, /* Horizontal Front Porch in pixels */ + [9] = 40u, /* Horizontal Pulse Sync Width in pixels */ + [10] = 0x55u, /* Vertical Front Porch is 5 lines */ + [11] = 0x00, /* Vertical Sync Pulse Width is 5 lines */ + + /* Horizontal Addressable Image Size is 1039mm + * Vertical Addressable Image Size is 584mm + */ + [12] = 0x0F, [13] = 0x48, [14] = 0x42, + + [15] = 0x00, /* Horizontal border size is 0px*/ + [16] = 0x00, /* Vertical Border Size is 0px */ + + /* Timing is Non-Interlaced Video, + * Stereo Video is not supported, + * Digital separate syncs are requires. + */ + [17] = 0x1E, + }, + .descriptor_block_4 = { + /* Display Product Name Block Tag */ + [0] = 0, [1] = 0, [2] = 0, [3] = 0xFC, [4] = 0, + + /* Product name */ + [5] = 'A', + [6] = 'B', + [7] = 'C', + [8] = ' ', + [9] = 'L', + [10] = 'C', + [11] = 'D', + [12] = '4', + [13] = '7', + [14] = 'w', + [15] = '\n', + [16] = ' ', + [17] = ' ', + }, + .extension_flag = 0x0, /* No extensions */ + }; + + edid_raw_calc_checksum(&raw); + + memcpy(raw_data, &raw, sizeof(raw)); + + unsigned char ext[128] = { + [0] = 0x02, /* CEA 861 Extension Block Tag Code */ + [1] = 0x03, /* CEA 861 Block Version */ + + [2] = 0x18, /* Detail Timing Descriptors start 0x18 bytes from here */ + + /* Underscan is not supported + * Basic Audio is supported + * YCbCr 4:4:4 & YCbCr 4:2:2 are supported + * Number of native formats: 2 + */ + [3] = 0x72, + + /* Video Data Block Tag Code is 2 + * Number of Short Video Descriptor Bytes i 7 + */ + [4] = 0x47, + + /* 1920x1080p 59.94/60 Hz 16 : 9 AR (CEA Format #16) + * is a supported Native Format. */ + [5] = 0x90, + + /* 1920x1080i 59.94/60 Hz 16 : 9 AR (CEA Format #5) + * is a supported Native Format. */ + [6] = 0x85, + + /* 1280x720p 59.94/60 Hz 16 : 9 AR (CEA Format #4) is a supported format. */ + [7] = 0x04, + + /* 720x480p 59.94/60 Hz 16 : 9 AR (CEA Format #3) is a supported format. */ + [8] = 0x03, + + /* 720x480p 59.94/60 Hz 4 : 3 AR (CEA Format #2) is a supported format. */ + [9] = 0x02, + + /* 720x480i 59.94/60 Hz 16 : 9 AR (CEA Format #7) is a supported format. */ + [10] = 0x07, + + /* 720x480i 59.94/60 Hz 4 : 3 AR (CEA Format #6) is a supported format. */ + [11] = 0x06, + + /* Audio Data Block Tag Code is 1. + * Number of Short Audio Descriptor Bytes is 3. + */ + [12] = 0x23, + + /* Audio Format Tag Code is 1 --- LPCM is supported. + * Maximum number of audio channels is 2 + */ + [13] = 0x09, + + /* Supported Sampling Frequencies include: 48kHz; 44.1kHz & 32kHz. */ + [14] = 0x07, + + /* Supported Sampling Bit Rates include: 24 bit; 20 bit & 16 bit. */ + [15] = 0x07, + + /* Speaker Allocation Block Tag Code is 4. + * Number of Speaker Allocation + * Descriptor Bytes is 3. + */ + [16] = 0x83, + + /* Speaker Allocation is Front-Left & Front-Right */ + [17] = 0x01, + + /* Reserved */ + [18 ... 19] = 0, + + /* Vendor Specific Data Block Tag Code is 3. + * Number of Vendor Specific Data Bytes is 5. + */ + [20] = 0x65, + + /* 24bit IEEE registration Identifier is 0x000C03 */ + [21] = 0x03, [22] = 0x0C, [23] = 0x00, + + /* Vendor Specific Data is 0x10000 */ + [24] = 0x01, [25] = 0x00, + + /* Descriptor Block 5 [18 Bytes] */ + + [26] = EDID_PIXEL_CLOCK(27027000u) & 0xFF, + [27] = (EDID_PIXEL_CLOCK(27027000u) >> 8) & 0xFF, + + /* Horizontal Addressable Video is 720px. + * Horizontal Blanking is 138 px. + */ + [28] = 0xD0, [29] = 0x8A, [30] = 0x20, + + /* Vertical Addressable Video is 480 lines. + * Vertical Blanking is 45 lines. + */ + [31] = 0xE0, [32] = 0x2D, [33] = 0x10, + + [34] = 16u, /* Horizontal Front Porch in pixels */ + [35] = 62u, /* Horizontal Sync Pulse Width in pixels */ + [36] = 0x96, /* Vertical Front Porch is 9 lines */ + [37] = 0x00, /* Vertical Sync Pulse Width is 6 lines */ + + /* Displayed Image Aspect Ratio is 16:9 */ + [38] = 16u, [39] = 9u, [40] = 0u, + + /* Horizontal and Vertical Border Size is 0 px */ + [41] = 0u, [42] = 0u, + + /* Timing is Interlaced Video + * Stereo Video is not supported + * Digital Separate Syncs are required + */ + [43] = 0x18, + + /* Descriptor Block 6 [18 Bytes] */ + + [44] = EDID_PIXEL_CLOCK(27027000u) & 0xFF, + [45] = (EDID_PIXEL_CLOCK(27027000u) >> 8) & 0xFF, + + /* Horizontal Addressable Video is 720px. + * Horizontal Blanking is 138 px. + */ + [46] = 0xD0, [47] = 0x8A, [48] = 0x20, + + /* Vertical Addressable Video is 480 lines. + * Vertical Blanking is 45 lines. + */ + [49] = 0xE0, [50] = 0x2D, [51] = 0x10, + + [52] = 16u, /* Horizontal Front Porch in pixels */ + [53] = 62u, /* Horizontal Sync Pulse Width in pixels */ + [54] = 0x96, /* Vertical Front Porch is 9 lines */ + [55] = 0x00, /* Vertical Sync Pulse Width is 6 lines */ + + /* Displayed Image Aspect Ratio is 4:3 */ + [56] = 4u, [57] = 3u, [58] = 0u, + + /* Horizontal and Vertical Border Size is 0 px */ + [59] = 0u, [60] = 0u, + + /* Timing is Interlaced Video + * Stereo Video is not supported + * Digital Separate Syncs are required + */ + [61] = 0x18, + + /* Descriptor Block 7 [18 Bytes] */ + + [62] = EDID_PIXEL_CLOCK(27027000u) & 0xFF, + [63] = (EDID_PIXEL_CLOCK(27027000u) >> 8) & 0xFF, + + /* Horizontal Addressable Video is 1440px. + * Horizontal Blanking is 276 px. + */ + [64] = 0xA0, [65] = 0x14, [66] = 0x51, + + /* Vertical Addressable Video is 240 lines. + * Vertical Blanking is 23 lines. + */ + [67] = 0xF0, [68] = 0x16, [69] = 0x00, + + [70] = 38u, /* Horizontal Front Porch in pixels */ + [71] = 124u, /* Horizontal Sync Pulse Width in pixels */ + [72] = 0x43, /* Vertical Front Porch is 9 lines */ + [73] = 0x00, /* Vertical Sync Pulse Width is 6 lines */ + + /* Displayed Image Aspect Ratio is 16:9 */ + [74] = 16u, [75] = 9u, [76] = 0u, + + /* Horizontal and Vertical Border Size is 0 px */ + [77] = 0u, [78] = 0u, + + /* Timing is Interlaced Video + * Stereo Video is not supported + * Digital Separate Syncs are required + */ + [79] = 0x98, + + /* Descriptor Block 8 [18 Bytes] */ + + [80] = EDID_PIXEL_CLOCK(27027000u) & 0xFF, + [81] = (EDID_PIXEL_CLOCK(27027000u) >> 8) & 0xFF, + + /* Horizontal Addressable Video is 1440px. + * Horizontal Blanking is 276 px. + */ + [82] = 0xA0, [83] = 0x14, [84] = 0x51, + + /* Vertical Addressable Video is 240 lines. + * Vertical Blanking is 23 lines. + */ + [85] = 0xF0, [86] = 0x16, [87] = 0x00, + + [88] = 38u, /* Horizontal Front Porch in pixels */ + [89] = 124u, /* Horizontal Sync Pulse Width in pixels */ + [90] = 0x43, /* Vertical Front Porch is 9 lines */ + [91] = 0x00, /* Vertical Sync Pulse Width is 6 lines */ + + /* Displayed Image Aspect Ratio is 4:3 */ + [92] = 4u, [93] = 3u, [94] = 0u, + + /* Horizontal and Vertical Border Size is 0 px */ + [95] = 0u, [96] = 0u, + + /* Timing is Interlaced Video + * Stereo Video is not supported + * Digital Separate Syncs are required + */ + [97] = 0x98, + + [99 ... 126] = 0 + }; + + ext[127] = get_raw_edid_checksum(ext); + + memcpy(raw_data + sizeof(raw), ext, sizeof(ext)); + + /* Only checking if frame is present. Don't care if is conformant. + * In real-life situations frames often are not 100% conformant, + * but are at least correct when it comes to key data fields. */ + assert_int_not_equal(EDID_ABSENT, decode_edid(raw_data, sizeof(raw_data), &out)); + + assert_int_equal(32, out.framebuffer_bits_per_pixel); + assert_int_equal(8, out.panel_bits_per_color); + assert_int_equal(24, out.panel_bits_per_pixel); + assert_int_equal(0, out.link_clock); + assert_int_equal(1920, out.x_resolution); + assert_int_equal(1080, out.y_resolution); + assert_int_equal(7680, out.bytes_per_line); + assert_int_equal(1, out.hdmi_monitor_detected); + assert_int_equal(0, strnlen(out.ascii_string, ARRAY_SIZE(out.ascii_string))); + assert_string_equal(out.manufacturer_name, EDID_MANUFACTURER_NAME); + + /* Mode */ + assert_null(out.mode.name); + assert_int_equal(148500, out.mode.pixel_clock); + assert_int_equal(1, out.mode.lvds_dual_channel); + assert_int_equal(0, out.mode.refresh); + assert_int_equal(1920, out.mode.ha); + assert_int_equal(280, out.mode.hbl); + assert_int_equal(88, out.mode.hso); + assert_int_equal(44, out.mode.hspw); + assert_int_equal(0, out.mode.hborder); + assert_int_equal(1080, out.mode.va); + assert_int_equal(45, out.mode.vbl); + assert_int_equal(16, out.mode.vso); + assert_int_equal(0, out.mode.vborder); + assert_int_equal(43, out.mode.phsync); + assert_int_equal(43, out.mode.pvsync); + assert_int_equal(0, out.mode.x_mm); + assert_int_equal(0, out.mode.y_mm); + + assert_int_equal(1, out.mode_is_supported[EDID_MODE_640x480_60Hz]); + assert_int_equal(0, out.mode_is_supported[EDID_MODE_720x480_60Hz]); + assert_int_equal(0, out.mode_is_supported[EDID_MODE_1280x720_60Hz]); + assert_int_equal(0, out.mode_is_supported[EDID_MODE_1920x1080_60Hz]); +} + +static void test_decode_edid_frame_3(void **state) +{ + struct edid out; + unsigned char raw_data[128 * 2]; /* Frame with one extension */ + struct edid_raw raw = { + EDID_RAW_DEFAULT_PARAMS, + .video_input_type = EDID_DIGITAL_VSI + | EDID_INTERFACE_HDMI_A + | EDID_COLOR_BIT_DEPTH_8B, + .horizontal_size = 121, /* Aspect ratio 16:9 in landscape */ + .vertical_size = 68, /* Landscape flag */ + .display_gamma = 120, /* 220% */ + .supported_features = EDID_STANDBY_MODE(0) + | EDID_SUSPEND_MODE(0) + | EDID_ACTIVE_OFF(0) + | EDID_COLOR_FORMAT_RGB444_YCRCB422_YCRCB422 + | EDID_SRGB_SUPPORTED(1) + | EDID_PREFERRED_TIMING_EXTENDED_INFO + | EDID_DISPLAY_FREQUENCY_NON_CONTINUOUS, + .established_supported_timings = { + [0] = EDID_ESTABLISHED_TIMINGS_1_800x600_60Hz + | EDID_ESTABLISHED_TIMINGS_1_800x600_56Hz + | EDID_ESTABLISHED_TIMINGS_1_640x480_75Hz + | EDID_ESTABLISHED_TIMINGS_1_640x480_72Hz + | EDID_ESTABLISHED_TIMINGS_1_640x480_67Hz + | EDID_ESTABLISHED_TIMINGS_1_640x480_60Hz + | EDID_ESTABLISHED_TIMINGS_1_720x400_88Hz + | EDID_ESTABLISHED_TIMINGS_1_720x400_70Hz, + [1] = EDID_ESTABLISHED_TIMINGS_2_1280x1024_75Hz + | EDID_ESTABLISHED_TIMINGS_2_1024x768_75Hz + | EDID_ESTABLISHED_TIMINGS_2_1024x768_70Hz + | EDID_ESTABLISHED_TIMINGS_2_1024x768_60Hz + | EDID_ESTABLISHED_TIMINGS_2_832x624_75Hz + | EDID_ESTABLISHED_TIMINGS_2_800x600_75Hz + | EDID_ESTABLISHED_TIMINGS_2_800x600_72Hz, + }, + .manufacturers_reserved_timing = EDID_MANUFACTURERS_TIMINGS_1152x870_75Hz, + .standard_timings_supported = { + [0] = EDID_HORIZONTAL_ACCESSIBLE_PIXELS(1280), + [1] = EDID_ASPECT_RATIO_5_4 | EDID_FIELD_REFRESH_RATE(85), + + [2] = EDID_HORIZONTAL_ACCESSIBLE_PIXELS(1280), + [3] = EDID_ASPECT_RATIO_5_4 | EDID_FIELD_REFRESH_RATE(60), + + [4] = EDID_HORIZONTAL_ACCESSIBLE_PIXELS(1280), + [5] = EDID_ASPECT_RATIO_4_3 | EDID_FIELD_REFRESH_RATE(85), + + [6] = EDID_HORIZONTAL_ACCESSIBLE_PIXELS(1280), + [7] = EDID_ASPECT_RATIO_4_3 | EDID_FIELD_REFRESH_RATE(60), + + [8] = EDID_HORIZONTAL_ACCESSIBLE_PIXELS(1024), + [9] = EDID_ASPECT_RATIO_4_3 | EDID_FIELD_REFRESH_RATE(85), + + [10] = EDID_HORIZONTAL_ACCESSIBLE_PIXELS(848), + [11] = EDID_ASPECT_RATIO_16_9 | EDID_FIELD_REFRESH_RATE(60), + + [12] = EDID_HORIZONTAL_ACCESSIBLE_PIXELS(800), + [13] = EDID_ASPECT_RATIO_4_3 | EDID_FIELD_REFRESH_RATE(60), + + [14] = EDID_HORIZONTAL_ACCESSIBLE_PIXELS(640), + [15] = EDID_ASPECT_RATIO_4_3 | EDID_FIELD_REFRESH_RATE(60), + }, + .descriptor_block_1 = { + [0] = EDID_PIXEL_CLOCK(85500000u) & 0xFF, + [1] = (EDID_PIXEL_CLOCK(85500000u) >> 8) & 0xFF, + + /* Horizontal Addressable Video is 1360px + * Horizontal Blanking is 432px + */ + [2] = 0x50, [3] = 0xB0, [4] = 0x51, + + /* Vertical Addressable Video is 768 lines + * Vertical Blanking is 27 lines + */ + [5] = 0x00, [6] = 0x1B, [7] = 0x30, + + [8] = 64u, /* Horizontal Front Porch in pixels */ + [9] = 112u, /* Horizontal Pulse Sync Width in pixels */ + [10] = 0x36, /* Vertical Front Porch is 3 lines */ + [11] = 0u, /* Vertical Sync Pulse Width is 6 lines */ + + /* Horizontal Addressable Image Size is 1214mm + * Vertical Addressable Image Size is 683mm + */ + [12] = 0xBE, [13] = 0xAB, [14] = 0x42, + + [15] = 0x00, /* Horizontal border size is 0px*/ + [16] = 0x00, /* Vertical Border Size is 0px */ + + /* Timing is Non-Interlaced Video, + * Stereo Video is not supported, + * Digital separate and syncs are requires. + */ + [17] = 0x1E, + }, + .descriptor_block_2 = { + [0] = EDID_PIXEL_CLOCK(74250000u) & 0xFF, + [1] = (EDID_PIXEL_CLOCK(74250000u) >> 8) & 0xFF, + + /* Horizontal Addressable Video is 1280px + * Horizontal Blanking is 370px + */ + [2] = 0x00, [3] = 0x72, [4] = 0x51, + + /* Vertical Addressable Video is 720 lines + * Vertical Blanking is 30 lines + */ + [5] = 0xD0, [6] = 0x1E, [7] = 0x20, + + [8] = 110u, /* Horizontal Front Porch in pixels */ + [9] = 40u, /* Horizontal Pulse Sync Width in pixels */ + [10] = 0x55, /* Vertical Front Porch is 5 lines */ + [11] = 0x00, /* Vertical Sync Pulse Width is 5 lines */ + + /* Horizontal Addressable Image Size is 1214mm + * Vertical Addressable Image Size is 683mm + */ + [12] = 0xBE, [13] = 0xAB, [14] = 0x42, + + [15] = 0x00, /* Horizontal border size is 0px*/ + [16] = 0x00, /* Vertical Border Size is 0px */ + + /* Timing is Non-Interlaced Video, + * Stereo Video is not supported, + * Digital separate and syncs are requires. + */ + [17] = 0x1E, + }, + .descriptor_block_3 = { + /* Established timings III Block Tag */ + [0 ... 2] = 0u, [3] = 0xF7, [4] = 0u, + + /* + * VESA DMT Standard Version #10 + */ + [5] = 10u, + + /* 640x350@85Hz, + * 640x400@85Hz, + * 720x400@85Hz, + * 640x480@85Hz, + * 800x600@85Hz, + * 1024x768@85Hz, + * 1152x864@75Hz are supported. + */ + [6] = 0x7F, + + /* 1280x960@60Hz, + * 1280x960@85Hz, + * 1280x1024@60Hz, + * 1280x1024@85Hz + */ + [7] = 0x0F, + + /* 1400x1050@60Hz (Normal Blanking), + * 1400x1050@75Hz are supported. + */ + [8] = 0x03, + + /* 1400x1050@85Hz, + * 1600x1200@60Hz, + * 1600x1200@65Hz, + * 1600x1200@70Hz are supported. + */ + [9] = 0x87, + + /* 1600x1200@75Hz, + * 1600x1200@85Hz are supported. + */ + [10] = 0xC0, + + /* 1920 PC Timings are not supported. */ + [11] = 0u, + + /* Reserved */ + [12 ... 17] = 0, + }, + .descriptor_block_4 = { + /* Display Product Name Block Tag */ + [0] = 0, [1] = 0, [2] = 0, [3] = 0xFC, [4] = 0, + + /* Product name */ + [5] = 'A', + [6] = 'B', + [7] = 'C', + [8] = ' ', + [9] = 'P', + [10] = 'L', + [11] = 'A', + [12] = '5', + [13] = '5', + [14] = '\n', + [15] = ' ', + [16] = ' ', + [17] = ' ', + }, + .extension_flag = 0x0, /* No extensions */ + }; + + edid_raw_calc_checksum(&raw); + + memcpy(raw_data, &raw, sizeof(raw)); + + unsigned char ext[128] = { + [0] = 0x02, /* CEA 861 Extension Block Tag Code */ + [1] = 0x03, /* CEA 861 Block Version */ + [2] = 0x17, /* Detail Timing Descriptors start 0x17 bytesfrom here */ + + /* Underscan is supported + * Basic Audio is supported + * YCbCr 4:4:4 & YCbCr 4:2:2 are supported + * Number of native formats: 0 + */ + [3] = 0xF0, + + /* Video Data Block Tag Code is 2 + * Number of Short Video Descriptor Bytes i 6 + */ + [4] = 0x46, + + /* 1920x1080i 59.94/60 Hz 16 : 9 AR (CEA Format #5) is a supported format. */ + [5] = 0x05, + + /* 1280x720p 59.94/60 Hz 16 : 9 AR (CEA Format #4) is a supported format. */ + [6] = 0x04, + + /* 720x480p 59.94/60 Hz 16 : 9 AR (CEA Format #3) is a supported format. */ + [7] = 0x03, + + /* 720x480p 59.94/60 Hz 4 : 3 AR (CEA Format #2) is a supported format. */ + [8] = 0x02, + + /* 720x480i 59.94/60 Hz 16 : 9 AR (CEA Format #7) is a supported format. */ + [9] = 0x07, + + /* 720x480i 59.94/60 Hz 4 : 3 AR (CEA Format #6) is a supported format. */ + [10] = 0x06, + + /* Audio Data Block Tag Code is 1. + * Number of Short Audio Descriptor Bytes is 3. + */ + [11] = 0x23, + + /* Audio Format Tag Code is 1 --- LPCM is supported. + * Maximum number of audio channels is 2 + */ + [12] = 0x09, + + /* Supported Sampling Frequencies include: 48kHz; 44.1kHz & 32kHz. */ + [13] = 0x07, + + /* Supported Sampling Bit Rates include: 24 bit; 20 bit & 16 bit. */ + [14] = 0x07, + + /* Speaker Allocation Block Tag Code is 4. + * Number of Speaker Allocation + * Descriptor Bytes is 3. + */ + [15] = 0x83, + + /* Speaker Allocation is Front-Left & Front-Right */ + [16] = 0x01, + + /* Reserved */ + [17 ... 18] = 0, + + /* Vendor Specific Data Block Tag Code is 3. + * Number of Vendor Specific Data Bytes is 5. + */ + [19] = 0x65, + + /* 24bit IEEE registration Identifier is 0x000C03 */ + [20] = 0x03, [21] = 0x0C, [22] = 0x00, + + /* Vendor Specific Data is 0x10000 */ + [23] = 0x01, [24] = 0x00, + + /* Descriptor Block 5 [18 Bytes] */ + + [25] = EDID_PIXEL_CLOCK(74250000u) & 0xFF, + [26] = (EDID_PIXEL_CLOCK(74250000u) >> 8) & 0xFF, + + /* Horizontal Addressable Video is 1920px. + * Horizontal Blanking is 280px. + */ + [27] = 0x80, [28] = 0x18, [29] = 0x71, + + /* Vertical Addressable Video is 540 lines. + * Vertical Blanking is 22 lines. + */ + [30] = 0x1C, [31] = 0x16, [32] = 0x20, + + [33] = 88u, /* Horizontal Front Porch in pixels */ + [34] = 44u, /* Horizontal Sync Pulse Width in pixels */ + [35] = 0x25, /* Vertical Front Porch is 2 lines */ + [36] = 0x00, /* Vertical Sync Pulse Width is 5 lines */ + + /* Image size: 1039mm x 584mm */ + [37] = 0x0F, [38] = 0x48, [39] = 0x42, + + /* Horizontal and Vertical Border Size is 0 px */ + [40] = 0u, [41] = 0u, + + /* Timing is Interlaced Video + * Stereo Video is not supported + * Digital Separate Syncs are required + */ + [42] = 0x9E, + + /* Descriptor Block 6 [18 Bytes] */ + + [43] = EDID_PIXEL_CLOCK(74250000u) & 0xFF, + [44] = (EDID_PIXEL_CLOCK(74250000u) >> 8) & 0xFF, + + /* Horizontal Addressable Video is 1280px. + * Horizontal Blanking is 370 px. + */ + [45] = 0x00, [46] = 0x72, [47] = 0x51, + + /* Vertical Addressable Video is 720 lines. + * Vertical Blanking is 30 lines. + */ + [48] = 0xD0, [49] = 0x1E, [50] = 0x20, + + [51] = 110u, /* Horizontal Front Porch in pixels */ + [52] = 40u, /* Horizontal Sync Pulse Width in pixels */ + [53] = 0x55, /* Vertical Front Porch is 5 lines */ + [54] = 0x00, /* Vertical Sync Pulse Width is 5 lines */ + + /* Image size: 1039mm x 584mm */ + [55] = 0x0F, [56] = 0x48, [57] = 0x42, + + /* Horizontal and Vertical Border Size is 0 px */ + [58] = 0u, [59] = 0u, + + /* Timing is Non-Interlaced Video + * Stereo Video is not supported + * Digital Separate Syncs are required + */ + [60] = 0x1E, + + /* Descriptor Block 7 [18 Bytes] */ + + [61] = EDID_PIXEL_CLOCK(27000000u) & 0xFF, + [62] = (EDID_PIXEL_CLOCK(27000000u) >> 8) & 0xFF, + + /* Horizontal Addressable Video is 1440px. + * Horizontal Blanking is 276 px. + */ + [63] = 0xA0, [64] = 0x14, [65] = 0x51, + + /* Vertical Addressable Video is 240 lines. + * Vertical Blanking is 23 lines. + */ + [66] = 0xF0, [67] = 0x16, [68] = 0x00, + + [69] = 38u, /* Horizontal Front Porch in pixels */ + [70] = 124u, /* Horizontal Sync Pulse Width in pixels */ + [71] = 0x43, /* Vertical Front Porch is 4 lines */ + [72] = 0x00, /* Vertical Sync Pulse Width is 3 lines */ + + /* Image size: 1039mm x 584mm */ + [73] = 0x0F, [74] = 0x48, [75] = 0x42, + + /* Horizontal and Vertical Border Size is 0 px */ + [76] = 0u, [77] = 0u, + + /* Timing is Interlaced Video + * Stereo Video is not supported + * Digital Separate Syncs are required + */ + [78] = 0x18, + + /* Descriptor Block 8 [18 Bytes] */ + + [79] = EDID_PIXEL_CLOCK(27027000u) & 0xFF, + [80] = (EDID_PIXEL_CLOCK(27027000u) >> 8) & 0xFF, + + /* Horizontal Addressable Video is 1440px. + * Horizontal Blanking is 276 px. + */ + [81] = 0xA0, [82] = 0x14, [83] = 0x51, + + /* Vertical Addressable Video is 240 lines. + * Vertical Blanking is 23 lines. + */ + [84] = 0xF0, [85] = 0x16, [86] = 0x00, + + [87] = 38u, /* Horizontal Front Porch in pixels */ + [88] = 124u, /* Horizontal Sync Pulse Width in pixels */ + [89] = 0x43, /* Vertical Front Porch is 4 lines */ + [90] = 0x00, /* Vertical Sync Pulse Width is 3 lines */ + + /* Image size: 1039mm x 584mm */ + [91] = 0x0F, [92] = 0x48, [93] = 0x42, + + /* Horizontal and Vertical Border Size is 0 px */ + [94] = 0u, [95] = 0u, + + /* Timing is Interlaced Video + * Stereo Video is not supported + * Digital Separate Syncs are required + */ + [96] = 0x98, + + [97 ... 126] = 0, + }; + + ext[127] = get_raw_edid_checksum(ext); + + memcpy(raw_data + sizeof(raw), ext, sizeof(ext)); + + /* Only checking if frame is present. Don't care if is conformant. + * In real-life situations frames often are not 100% conformant, + * but are at least correct when it comes to key data fields. */ + assert_int_not_equal(EDID_ABSENT, decode_edid(raw_data, sizeof(raw_data), &out)); + + assert_int_equal(32, out.framebuffer_bits_per_pixel); + assert_int_equal(8, out.panel_bits_per_color); + assert_int_equal(24, out.panel_bits_per_pixel); + assert_int_equal(0, out.link_clock); + assert_int_equal(1360, out.x_resolution); + assert_int_equal(768, out.y_resolution); + assert_int_equal(5440, out.bytes_per_line); + assert_int_equal(1, out.hdmi_monitor_detected); + assert_int_equal(0, strnlen(out.ascii_string, ARRAY_SIZE(out.ascii_string))); + assert_string_equal(out.manufacturer_name, EDID_MANUFACTURER_NAME); + + /* Mode */ + assert_null(out.mode.name); + assert_int_equal(85500, out.mode.pixel_clock); + assert_int_equal(0, out.mode.lvds_dual_channel); + assert_int_equal(0, out.mode.refresh); + assert_int_equal(1360, out.mode.ha); + assert_int_equal(432, out.mode.hbl); + assert_int_equal(64, out.mode.hso); + assert_int_equal(112, out.mode.hspw); + assert_int_equal(0, out.mode.hborder); + assert_int_equal(768, out.mode.va); + assert_int_equal(27, out.mode.vbl); + assert_int_equal(3, out.mode.vso); + assert_int_equal(0, out.mode.vborder); + assert_int_equal(43, out.mode.phsync); + assert_int_equal(43, out.mode.pvsync); + assert_int_equal(0, out.mode.x_mm); + assert_int_equal(0, out.mode.y_mm); + + assert_int_equal(1, out.mode_is_supported[EDID_MODE_640x480_60Hz]); + assert_int_equal(0, out.mode_is_supported[EDID_MODE_720x480_60Hz]); + assert_int_equal(0, out.mode_is_supported[EDID_MODE_1280x720_60Hz]); + assert_int_equal(0, out.mode_is_supported[EDID_MODE_1920x1080_60Hz]); +} + +int main(void) +{ + const struct CMUnitTest tests[] = { + cmocka_unit_test(test_decode_edid_no_edid), + cmocka_unit_test(test_decode_edid_invalid_header), + cmocka_unit_test(test_decode_edid_frame_1), + cmocka_unit_test(test_decode_edid_frame_2), + cmocka_unit_test(test_decode_edid_frame_3), + }; + + return cmocka_run_group_tests(tests, NULL, NULL); +} + diff --git a/tests/stubs/console.c b/tests/stubs/console.c index b6a7583..1baed18 100644 --- a/tests/stubs/console.c +++ b/tests/stubs/console.c @@ -1,13 +1,28 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <console/console.h> +#include <stdarg.h> +#include <stdio.h> int do_printk(int msg_level, const char *fmt, ...) { - return 0; + int res = 0; + va_list v; + va_start(v, fmt); + res = do_vprintk(msg_level, fmt, v); + va_end(v); + return res; } +extern int vprintf(const char *fmt, va_list ap); + int do_vprintk(int msg_level, const char *fmt, va_list args) { + return vprintf(fmt, args); + //return 0; +} + +int console_log_level(int msg_level) +{ return 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/46817 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I796e660eebc4d2c3c32207bd3a6ee44aaffeb325 Gerrit-Change-Number: 46817 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1003143 Gerrit-MessageType: newchange

3 8

Change in coreboot[master]: cpu/x86/mtrr.h: Rename CORE2 alternative SMRR registers
by Arthur Heymans (Code Review) 10 Nov '20

10 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46896 ) Change subject: cpu/x86/mtrr.h: Rename CORE2 alternative SMRR registers ...................................................................... cpu/x86/mtrr.h: Rename CORE2 alternative SMRR registers It is too easy to confuse those with IA32_SMRR_PHYS_x registers. Change-Id: Ice02ab6c0315a2be14ef110ede506262e3c0a4d5 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/smm/gen1/smmrelocate.c M src/include/cpu/x86/mtrr.h 2 files changed, 6 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/46896/1 diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c index ae2440d..36884a1 100644 --- a/src/cpu/intel/smm/gen1/smmrelocate.c +++ b/src/cpu/intel/smm/gen1/smmrelocate.c @@ -59,8 +59,8 @@ printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", relo_params->smrr_base.lo, relo_params->smrr_mask.lo); - wrmsr(MSR_SMRR_PHYS_BASE, relo_params->smrr_base); - wrmsr(MSR_SMRR_PHYS_MASK, relo_params->smrr_mask); + wrmsr(CORE2_SMRR_PHYS_BASE, relo_params->smrr_base); + wrmsr(CORE2_SMRR_PHYS_MASK, relo_params->smrr_mask); } static void fill_in_relocation_params(struct smm_relocation_params *params) diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 3bf8301c..a96f17f 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -31,9 +31,10 @@ #define IA32_SMRR_PHYS_MASK 0x1f3 #define SMRR_PHYS_MASK_LOCK (1 << 10) -/* Specific to model_6fx and model_1067x */ -#define MSR_SMRR_PHYS_BASE 0xa0 -#define MSR_SMRR_PHYS_MASK 0xa1 +/* Specific to model_6fx and model_1067x. + Those are named MSR_SMRR_PHYSBASE in the SDM. */ +#define CORE2_SMRR_PHYS_BASE 0xa0 +#define CORE2_SMRR_PHYS_MASK 0xa1 #define MTRR_PHYS_BASE(reg) (0x200 + 2 * (reg)) #define MTRR_PHYS_MASK(reg) (MTRR_PHYS_BASE(reg) + 1) -- To view, visit https://review.coreboot.org/c/coreboot/+/46896 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice02ab6c0315a2be14ef110ede506262e3c0a4d5 Gerrit-Change-Number: 46896 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: soc/intel/cbnt: Stitch in ACMs in the coreboot image
by Arthur Heymans (Code Review) 10 Nov '20

10 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46456 ) Change subject: soc/intel/cbnt: Stitch in ACMs in the coreboot image ...................................................................... soc/intel/cbnt: Stitch in ACMs in the coreboot image Actual support CbNT will be added later on. Change-Id: Icc35c5e6c74d002efee43cc05ecc8023e00631e0 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M Makefile.inc M src/cpu/intel/fit/Kconfig M src/security/intel/Kconfig M src/security/intel/Makefile.inc A src/security/intel/cbnt/Kconfig A src/security/intel/cbnt/Makefile.inc M src/security/intel/txt/Kconfig M src/security/intel/txt/Makefile.inc 8 files changed, 72 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/46456/1 diff --git a/Makefile.inc b/Makefile.inc index b5b81f0..29721b4 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -726,6 +726,16 @@ endif +ifeq ($(CONFIG_INTEL_CBNT_SUPPORT),y) + +CBNTIBB := --cbnt + +else + +CBNTIBB := + +endif # CONFIG_INTEL_CBNT_SUPPORT + ifeq ($(CONFIG_COMPRESS_BOOTBLOCK),y) $(objcbfs)/bootblock.lz4: $(objcbfs)/bootblock.elf $(objutil)/cbfstool/cbfs-compression-tool @@ -1057,6 +1067,7 @@ ifeq ($(CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK),y) TS_OPTIONS := -j $(CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE) endif + ifneq ($(CONFIG_UPDATE_IMAGE),y) $(obj)/coreboot.pre: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(CBFSTOOL) $(IFITTOOL) $$(cpu_ucode_cbfs_file) $(obj)/fmap.fmap $(obj)/fmap.desc $(CBFSTOOL) $@.tmp create -M $(obj)/fmap.fmap -r $(shell cat $(obj)/fmap.desc) @@ -1066,6 +1077,7 @@ -n bootblock \ -t bootblock \ $(TXTIBB) \ + $(CBNTIBB) \ -b -$(call file-size,$(objcbfs)/bootblock.bin) $(cbfs-autogen-attributes) \ $(TS_OPTIONS) else # ifeq ($(CONFIG_ARCH_X86),y) diff --git a/src/cpu/intel/fit/Kconfig b/src/cpu/intel/fit/Kconfig index fa10802..9ea867e 100644 --- a/src/cpu/intel/fit/Kconfig +++ b/src/cpu/intel/fit/Kconfig @@ -5,7 +5,7 @@ config CPU_INTEL_NUM_FIT_ENTRIES int - default 16 if INTEL_TXT + default 16 if INTEL_TXT || INTEL_CBNT_SUPPORT default 4 depends on CPU_INTEL_FIRMWARE_INTERFACE_TABLE help diff --git a/src/security/intel/Kconfig b/src/security/intel/Kconfig index 9cdd8a6..0609a45 100644 --- a/src/security/intel/Kconfig +++ b/src/security/intel/Kconfig @@ -2,3 +2,4 @@ source "src/security/intel/txt/Kconfig" source "src/security/intel/stm/Kconfig" +source "src/security/intel/cbnt/Kconfig" diff --git a/src/security/intel/Makefile.inc b/src/security/intel/Makefile.inc index e00802a..20aea27 100644 --- a/src/security/intel/Makefile.inc +++ b/src/security/intel/Makefile.inc @@ -1,2 +1,3 @@ subdirs-y += txt subdirs-y += stm +subdirs-y += cbnt diff --git a/src/security/intel/cbnt/Kconfig b/src/security/intel/cbnt/Kconfig new file mode 100644 index 0000000..568b7e5 --- /dev/null +++ b/src/security/intel/cbnt/Kconfig @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config INTEL_CBNT_SUPPORT + bool "Intel CBnT support" + default n + depends on CPU_INTEL_FIRMWARE_INTERFACE_TABLE + #depends on PLATFORM_HAS_DRAM_CLEAR + select INTEL_TXT_SUPPORT + help + Enables Intel Converged Bootguard and Trusted Execution Technology + Support. This will enable one to add a Key Manifest (KM) and a Boot + Policy Manifest (BPM) to the filesystem. It will also wrap a FIT around + the firmware and update appropriate entries. + +if INTEL_CBNT_SUPPORT + +config INTEL_CBNT_KEY_MANIFEST_BINARY + string "KM (Key Manifest) binary location" + help + Location of the Key Manifest (KM) + +config INTEL_CBNT_BOOT_POLICY_MANIFEST_BINARY + string "BPM (Boot Policy Manifest) binary location" + help + Location of the Boot Policy Manifest (BPM) + +endif # INTEL_CBNT_SUPPORT diff --git a/src/security/intel/cbnt/Makefile.inc b/src/security/intel/cbnt/Makefile.inc new file mode 100644 index 0000000..70c2353 --- /dev/null +++ b/src/security/intel/cbnt/Makefile.inc @@ -0,0 +1,25 @@ +ifeq ($(CONFIG_INTEL_CBNT_SUPPORT),y) + +ifneq ($(CONFIG_INTEL_CBNT_BOOT_POLICY_MANIFEST_BINARY),"") +cbfs-files-y += boot_policy_manifest.bin +boot_policy_manifest.bin-file := $(CONFIG_INTEL_CBNT_BOOT_POLICY_MANIFEST_BINARY) +boot_policy_manifest.bin-type := raw +boot_policy_manifest.bin-alignment := 0x10 + +INTERMEDIATE+=add_bpm_fit +add_bpm_fit: $(obj)/coreboot.pre $(IFITTOOL) + $(IFITTOOL) -r COREBOOT -a -n boot_policy_manifest.bin -t 12 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) -f $< +endif + +ifneq ($(CONFIG_INTEL_CBNT_KEY_MANIFEST_BINARY),"") +cbfs-files-y += key_manifest.bin +key_manifest.bin-file := $(CONFIG_INTEL_CBNT_KEY_MANIFEST_BINARY) +key_manifest.bin-type := raw +key_manifest.bin-alignment := 0x10 + +INTERMEDIATE+=add_km_fit +add_km_fit: $(obj)/coreboot.pre $(IFITTOOL) + $(IFITTOOL) -r COREBOOT -a -n key_manifest.bin -t 11 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) -f $< +endif + +endif # CONFIG_INTEL_CBNT_SUPPORT \ No newline at end of file diff --git a/src/security/intel/txt/Kconfig b/src/security/intel/txt/Kconfig index 70aa695..6ee8960 100644 --- a/src/security/intel/txt/Kconfig +++ b/src/security/intel/txt/Kconfig @@ -37,6 +37,7 @@ config INTEL_TXT_BIOSACM_ALIGNMENT hex + default 0x40000 if INTEL_CBNT_SUPPORT default 0x20000 # 128 KiB help Exceptions are Ivy and Sandy Bridge with 64 KiB and Purley with 256 KiB diff --git a/src/security/intel/txt/Makefile.inc b/src/security/intel/txt/Makefile.inc index 712ab58..ff0dcdf 100644 --- a/src/security/intel/txt/Makefile.inc +++ b/src/security/intel/txt/Makefile.inc @@ -29,6 +29,8 @@ $(IFITTOOL) -r COREBOOT -a -n $(CONFIG_INTEL_TXT_CBFS_BIOS_ACM) -t 2 \ -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) -f $< +# CbNT does not use FIT for IBB +ifneq ($(CONFIG_INTEL_CBNT_SUPPORT),y) # Initial BootBlock files ibb-files := $(foreach file,$(cbfs-files), \ $(if $(shell echo '$(call extract_nth,7,$(file))'|grep -- --ibb), \ @@ -41,6 +43,8 @@ $(foreach file, $(ibb-files), $(shell $(IFITTOOL) -f $< -a -n $(file) -t 7 \ -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) -r COREBOOT)) true +endif # INTEL_CBNT_SUPPORT + endif # CPU_INTEL_FIRMWARE_INTERFACE_TABLE endif # INTEL_TXT -- To view, visit https://review.coreboot.org/c/coreboot/+/46456 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc35c5e6c74d002efee43cc05ecc8023e00631e0 Gerrit-Change-Number: 46456 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 11

Change in coreboot[master]: mb/google/zork: Create Shuboz variant
by Kane Chen (Code Review) 10 Nov '20

10 Nov '20

Kane Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47152 ) Change subject: mb/google/zork: Create Shuboz variant ...................................................................... mb/google/zork: Create Shuboz variant Create the shuboz variant of the zork reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.2.0). BUG=b:none BRANCH=none TEST=emerge-zork coreboot Signed-off-by: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Change-Id: I3f62625f8cbde1c9adf8ab335edeb9e811e32679 --- M src/mainboard/google/zork/Kconfig M src/mainboard/google/zork/Kconfig.name A src/mainboard/google/zork/variants/shuboz/Makefile.inc A src/mainboard/google/zork/variants/shuboz/include/variant/acpi/audio.asl A src/mainboard/google/zork/variants/shuboz/include/variant/acpi/mainboard.asl A src/mainboard/google/zork/variants/shuboz/include/variant/acpi/thermal.asl A src/mainboard/google/zork/variants/shuboz/include/variant/ec.h A src/mainboard/google/zork/variants/shuboz/include/variant/gpio.h A src/mainboard/google/zork/variants/shuboz/include/variant/thermal.h A src/mainboard/google/zork/variants/shuboz/overridetree.cb A src/mainboard/google/zork/variants/shuboz/spd/Makefile.inc A src/mainboard/google/zork/variants/shuboz/spd/dram_id.generated.txt A src/mainboard/google/zork/variants/shuboz/spd/mem_parts_used.txt 13 files changed, 84 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/47152/1 diff --git a/src/mainboard/google/zork/Kconfig b/src/mainboard/google/zork/Kconfig index c4f6bf7..41e4989 100644 --- a/src/mainboard/google/zork/Kconfig +++ b/src/mainboard/google/zork/Kconfig @@ -71,6 +71,7 @@ default "vilboz" if BOARD_GOOGLE_VILBOZ default "woomax" if BOARD_GOOGLE_WOOMAX default "dirinboz" if BOARD_GOOGLE_DIRINBOZ + default "shuboz" if BOARD_GOOGLE_SHUBOZ config MAINBOARD_PART_NUMBER string @@ -82,6 +83,7 @@ default "Vilboz" if BOARD_GOOGLE_VILBOZ default "Woomax" if BOARD_GOOGLE_WOOMAX default "Dirinboz" if BOARD_GOOGLE_DIRINBOZ + default "Shuboz" if BOARD_GOOGLE_SHUBOZ config DEVICETREE string diff --git a/src/mainboard/google/zork/Kconfig.name b/src/mainboard/google/zork/Kconfig.name index 6f9a90c..8ed43f0 100644 --- a/src/mainboard/google/zork/Kconfig.name +++ b/src/mainboard/google/zork/Kconfig.name @@ -31,3 +31,7 @@ config BOARD_GOOGLE_DIRINBOZ bool "-> Dirinboz" select BOARD_GOOGLE_BASEBOARD_DALBOZ + +config BOARD_GOOGLE_SHUBOZ + bool "-> Shuboz" + select BOARD_GOOGLE_BASEBOARD_DALBOZ diff --git a/src/mainboard/google/zork/variants/shuboz/Makefile.inc b/src/mainboard/google/zork/variants/shuboz/Makefile.inc new file mode 100644 index 0000000..295acd2 --- /dev/null +++ b/src/mainboard/google/zork/variants/shuboz/Makefile.inc @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +subdirs-y += ./spd diff --git a/src/mainboard/google/zork/variants/shuboz/include/variant/acpi/audio.asl b/src/mainboard/google/zork/variants/shuboz/include/variant/acpi/audio.asl new file mode 100644 index 0000000..900e36f --- /dev/null +++ b/src/mainboard/google/zork/variants/shuboz/include/variant/acpi/audio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/acpi/audio.asl> diff --git a/src/mainboard/google/zork/variants/shuboz/include/variant/acpi/mainboard.asl b/src/mainboard/google/zork/variants/shuboz/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000..a1161ed --- /dev/null +++ b/src/mainboard/google/zork/variants/shuboz/include/variant/acpi/mainboard.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/acpi/mainboard.asl> diff --git a/src/mainboard/google/zork/variants/shuboz/include/variant/acpi/thermal.asl b/src/mainboard/google/zork/variants/shuboz/include/variant/acpi/thermal.asl new file mode 100644 index 0000000..7a793d8 --- /dev/null +++ b/src/mainboard/google/zork/variants/shuboz/include/variant/acpi/thermal.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/acpi/thermal.asl> diff --git a/src/mainboard/google/zork/variants/shuboz/include/variant/ec.h b/src/mainboard/google/zork/variants/shuboz/include/variant/ec.h new file mode 100644 index 0000000..9e61a44 --- /dev/null +++ b/src/mainboard/google/zork/variants/shuboz/include/variant/ec.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/ec.h> diff --git a/src/mainboard/google/zork/variants/shuboz/include/variant/gpio.h b/src/mainboard/google/zork/variants/shuboz/include/variant/gpio.h new file mode 100644 index 0000000..dfaeec3 --- /dev/null +++ b/src/mainboard/google/zork/variants/shuboz/include/variant/gpio.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> diff --git a/src/mainboard/google/zork/variants/shuboz/include/variant/thermal.h b/src/mainboard/google/zork/variants/shuboz/include/variant/thermal.h new file mode 100644 index 0000000..2af6479 --- /dev/null +++ b/src/mainboard/google/zork/variants/shuboz/include/variant/thermal.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/thermal.h> diff --git a/src/mainboard/google/zork/variants/shuboz/overridetree.cb b/src/mainboard/google/zork/variants/shuboz/overridetree.cb new file mode 100644 index 0000000..7645ba3 --- /dev/null +++ b/src/mainboard/google/zork/variants/shuboz/overridetree.cb @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +chip soc/amd/picasso + + # Start : OPN Performance Configuration + # See devhub #56670 Chapter 5 for documentation + # For the below fields, 0 indicates use SOC default + + # System config index + register "system_config" = "1" + + # Set STAPM confiuration. All of these fields must be set >0 to take affect + register "slow_ppt_limit" = "6000" #mw + register "fast_ppt_limit" = "9000" #mw + register "slow_ppt_time_constant" = "5" #second + register "stapm_time_constant" = "2500" #second + register "sustained_power_limit" = "4800" #mw + + # End : OPN Performance Configuration + + # I2C2 for touchscreen and trackpad + + register "i2c[2]" = "{ + .speed = I2C_SPEED_FAST, + }" + + # I2C3 for H1 + + register "i2c[3]" = "{ + .speed = I2C_SPEED_FAST, + .early_init = true, + }" + + # See AMD 55570-B1 Table 13: PCI Device ID Assignments. + device domain 0 on + subsystemid 0x1022 0x1510 inherit + end # domain + + device mmio 0xfedc4000 on # APU_I2C2_BASE + end # device + +end # chip soc/amd/picasso diff --git a/src/mainboard/google/zork/variants/shuboz/spd/Makefile.inc b/src/mainboard/google/zork/variants/shuboz/spd/Makefile.inc new file mode 100644 index 0000000..3edeb96 --- /dev/null +++ b/src/mainboard/google/zork/variants/shuboz/spd/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! +## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. + +SPD_SOURCES = ddr4-spd-empty.hex diff --git a/src/mainboard/google/zork/variants/shuboz/spd/dram_id.generated.txt b/src/mainboard/google/zork/variants/shuboz/spd/dram_id.generated.txt new file mode 100644 index 0000000..fa24790 --- /dev/null +++ b/src/mainboard/google/zork/variants/shuboz/spd/dram_id.generated.txt @@ -0,0 +1 @@ +DRAM Part Name ID to assign diff --git a/src/mainboard/google/zork/variants/shuboz/spd/mem_parts_used.txt b/src/mainboard/google/zork/variants/shuboz/spd/mem_parts_used.txt new file mode 100644 index 0000000..106a705 --- /dev/null +++ b/src/mainboard/google/zork/variants/shuboz/spd/mem_parts_used.txt @@ -0,0 +1,9 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Each part must also be listed in util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt. +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/ddr4. +# See util/spd_tools/ddr4/README.md for more details and instructions. + +# Part Name, Fixed ID (optional) -- To view, visit https://review.coreboot.org/c/coreboot/+/47152 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f62625f8cbde1c9adf8ab335edeb9e811e32679 Gerrit-Change-Number: 47152 Gerrit-PatchSet: 1 Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-MessageType: newchange

3 8

Change in coreboot[master]: mb/hp: Add HP EliteBook Folio 9480m
by Iru Cai (vimacs) (Code Review) 10 Nov '20

10 Nov '20

Hello Iru Cai, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45578 to review the following change. Change subject: mb/hp: Add HP EliteBook Folio 9480m ...................................................................... mb/hp: Add HP EliteBook Folio 9480m The code is based on autoport, with necessary modifications. This laptop uses SMSC MEC1322 embedded controller, but the EC interface is the same as the EliteBook laptops of previous generations that use KBC1126 EC. So it still uses ec/hp/kbc1126, but does not need EC firmware inserted into CBFS. Thanks to persmule for providing the laptop and pointing out how to program the system flash chip of it. Change-Id: I2328c43cbb1f488aa1d0ddd9116814d971e5d8ae Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- A Documentation/mainboard/hp/9480m.md A Documentation/mainboard/hp/9480m_flash.webp M Documentation/mainboard/index.md A src/mainboard/hp/folio_9480m/Kconfig A src/mainboard/hp/folio_9480m/Kconfig.name A src/mainboard/hp/folio_9480m/Makefile.inc A src/mainboard/hp/folio_9480m/acpi/ec.asl A src/mainboard/hp/folio_9480m/acpi/platform.asl A src/mainboard/hp/folio_9480m/acpi/superio.asl A src/mainboard/hp/folio_9480m/acpi_tables.c A src/mainboard/hp/folio_9480m/board_info.txt A src/mainboard/hp/folio_9480m/bootblock.c A src/mainboard/hp/folio_9480m/devicetree.cb A src/mainboard/hp/folio_9480m/dsdt.asl A src/mainboard/hp/folio_9480m/gma-mainboard.ads A src/mainboard/hp/folio_9480m/gpio.c A src/mainboard/hp/folio_9480m/hda_verb.c A src/mainboard/hp/folio_9480m/mainboard.c A src/mainboard/hp/folio_9480m/romstage.c 19 files changed, 575 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/45578/1 diff --git a/Documentation/mainboard/hp/9480m.md b/Documentation/mainboard/hp/9480m.md new file mode 100644 index 0000000..015d7b9 --- /dev/null +++ b/Documentation/mainboard/hp/9480m.md @@ -0,0 +1,140 @@ +# HP EliteBook Folio 9480m + +This page is about the notebook [HP EliteBook Folio 9480m]. + +## Release status + +HP EliteBook Folio 9480m was released in 2014 and is now end of life. +It can be bought from a secondhand market like Taobao or eBay. + +## Required proprietary blobs + +The following blobs are required to operate the hardware: + +1. EC firmware +2. Intel ME firmware +3. mrc.bin + +HP EliteBook Folio 9480m uses SMSC MEC1322 as its embedded controller. +The EC firmware is stored in the flash chip, but we don't need to touch it +or use it in the coreboot build process. + +Intel ME firmware is in the flash chip. It is not needed when building coreboot. + +The Haswell memory reference code binary is needed when building coreboot. +Please see [mrc.bin](../../northbridge/intel/haswell/mrc.bin). + +## Programming + +Before flashing, remove the battery and the hard drive cover according to the +[Maintenance and Service Guide] of this laptop. + +![Two flash chips of HP EliteBook Folio 9480m](9480m_flash.webp) + +HP EliteBook Folio 9480m has two flash chips, a 16MB system flash, and a 2MB +private flash. To install coreboot, we need to program both flash chips. +Read [HP Sure Start] for detailed information. + +To access the system flash. We need to connect the AC adapter to the machine, +then clip on the flash chip with an SOIC-8 clip. An [STM32-based flash programmer] +made with an STM32 develop board is tested to work. + +To access the private flash chip. You can use a ch341a based flash programmer and +flash the chip with the AC adapter disconnected. + +Before flashing coreboot, we need to do the following: + +1. Erase the private flash to disable the IFD protection +2. Modify the IFD to shrink the BIOS region, so that we'll not use or override + the protected bootblock and PEI region, as well as the EC firmware + +To erase the private flash chip, attach it with the flash programmer via the SOIC-8 clip, +then run: + + flashrom -p <programmer> --erase + +To modify the IFD, we need a new flash layout. The default coreboot configuration +sets the flash chip size to 12MB. We use the following flash layout in the modified IFD: + + 00000000:00000fff fd + 00600000:00bfffff bios + 00003000:005fffff me + 00001000:00002fff gbe + +Write the above layout in a file, and use ifdtool to modify the IFD of a flash image. +Suppose the above layout file is ``layout.txt`` and the origin content of the system flash +is in ``factory-sys.rom``, run: + + ifdtool -n layout.txt factory-sys.rom + +Then a flash image with a new IFD will be in ``factory-sys.rom.new``. + +Flash the IFD of the system flash: + + flashrom -p <programmer> --ifd -i fd -w factory-sys.rom.new + +Then flash the coreboot image: + + # first extend the 12M coreboot.rom to 16M + fallocate -l 16M build/coreboot.rom + flashrom -p <programmer> --ifd -i bios -w build/coreboot.rom + +## Debugging + +The board can be debugged with EHCI debug. The EHCI debug port is the USB port on the left. + +## Test status + +### Known issues + +- No audio output from speaker +- GRUB payload freezes just like previous EliteBook laptops + +### Untested + +- Ethernet +- Dock +- VGA +- TPM +- SD card reader +- Fingerprint reader +- Smart Card reader + +### Working + +- i5-4310U CPU with 4G+4G memory +- SATA and M.2 SATA disk +- WLAN +- WWAN +- USB +- Keyboard and touchpad +- DisplayPort +- Audio output from haedphone jack +- Webcam +- Arch Linux with Linux 5.8.9 +- Memory initialization with mrc.bin version 1.6.1 Build 2 +- Graphics initialization with libgfxinit +- Payload: SeaBIOS, Tianocore +- EC firmware + - KBC Revision 92.15 from OEM firmware version 01.33 + - KBC Revision 92.17 from OEM firmware version 01.50 +- Internal flashing under coreboot + +## Technology + +```eval_rst ++------------------+-----------------------------+ +| CPU | Intel Haswell-ULT | ++------------------+-----------------------------+ +| PCH | Intel Lynx Point Low Power | ++------------------+-----------------------------+ +| EC | SMSC MEC1322 | ++------------------+-----------------------------+ +| Coprocessor | Intel Management Engine | ++------------------+-----------------------------+ +``` + +[HP EliteBook Folio 9480m]: https://support.hp.com/us-en/product/hp-elitebook-folio-9480m-notebook-pc/7… +[Maintenance and Service Guide]: http://h10032.www1.hp.com/ctg/Manual/c05228980 +[STM32-based flash programmer]: https://github.com/dword1511/stm32-vserprog +[HP Sure Start]: hp_sure_start.md diff --git a/Documentation/mainboard/hp/9480m_flash.webp b/Documentation/mainboard/hp/9480m_flash.webp new file mode 100644 index 0000000..1abc306 --- /dev/null +++ b/Documentation/mainboard/hp/9480m_flash.webp Binary files differ diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 335eae2..bc3f0c6 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -64,6 +64,7 @@ - [HP Sure Start](hp/hp_sure_start.md) - [EliteBook 2560p](hp/2560p.md) - [EliteBook 8760w](hp/8760w.md) +- [EliteBook Folio 9480m](hp/9480m.md) ## Intel diff --git a/src/mainboard/hp/folio_9480m/Kconfig b/src/mainboard/hp/folio_9480m/Kconfig new file mode 100644 index 0000000..9200b82 --- /dev/null +++ b/src/mainboard/hp/folio_9480m/Kconfig @@ -0,0 +1,49 @@ +if BOARD_HP_FOLIO_9480M + +config BOARD_SPECIFIC_OPTIONS + def_bool y + # The board has a 16MB flash, but the end of the flash need + # to be reserved, so we use 12MB as default + select BOARD_ROMSIZE_KB_12288 + select EC_HP_KBC1126 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select INTEL_LYNXPOINT_LP + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM1 + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + select SYSTEM_TYPE_LAPTOP + +config MAINBOARD_DIR + string + default "hp/folio_9480m" + +config MAINBOARD_PART_NUMBER + string + default "HP EliteBook Folio 9480m" + +config VGA_BIOS_FILE + string + default "pci8086,0a16.rom" + +config VGA_BIOS_ID + string + default "8086,0a16" + +config USBDEBUG_HCD_INDEX + int + default 1 + +config EC_HP_KBC1126_ECFW_IN_CBFS + bool + default n + +config EC_HP_KBC1126_GPE + hex + default 0x6 + +endif diff --git a/src/mainboard/hp/folio_9480m/Kconfig.name b/src/mainboard/hp/folio_9480m/Kconfig.name new file mode 100644 index 0000000..67c671d --- /dev/null +++ b/src/mainboard/hp/folio_9480m/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_HP_FOLIO_9480M + bool "EliteBook Folio 9480m" diff --git a/src/mainboard/hp/folio_9480m/Makefile.inc b/src/mainboard/hp/folio_9480m/Makefile.inc new file mode 100644 index 0000000..fa23791 --- /dev/null +++ b/src/mainboard/hp/folio_9480m/Makefile.inc @@ -0,0 +1,3 @@ +bootblock-y += bootblock.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/hp/folio_9480m/acpi/ec.asl b/src/mainboard/hp/folio_9480m/acpi/ec.asl new file mode 100644 index 0000000..baa17a4 --- /dev/null +++ b/src/mainboard/hp/folio_9480m/acpi/ec.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <ec/hp/kbc1126/acpi/ec.asl> diff --git a/src/mainboard/hp/folio_9480m/acpi/platform.asl b/src/mainboard/hp/folio_9480m/acpi/platform.asl new file mode 100644 index 0000000..8023ae8 --- /dev/null +++ b/src/mainboard/hp/folio_9480m/acpi/platform.asl @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK,1) +{ + \_SB.PCI0.LPCB.EC0.ACPI = 1 + \_SB.PCI0.LPCB.EC0.SLPT = 0 + + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ + \_SB.PCI0.LPCB.EC0.SLPT = Arg0 +} diff --git a/src/mainboard/hp/folio_9480m/acpi/superio.asl b/src/mainboard/hp/folio_9480m/acpi/superio.asl new file mode 100644 index 0000000..55b1db5 --- /dev/null +++ b/src/mainboard/hp/folio_9480m/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/hp/folio_9480m/acpi_tables.c b/src/mainboard/hp/folio_9480m/acpi_tables.c new file mode 100644 index 0000000..00963e1 --- /dev/null +++ b/src/mainboard/hp/folio_9480m/acpi_tables.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi_gnvs.h> +#include <southbridge/intel/lynxpoint/nvs.h> + +void acpi_create_gnvs(struct global_nvs *gnvs) +{ + gnvs->lids = 1; + + /* Temperature at which OS will shutdown */ + gnvs->tcrt = 100; + /* Temperature at which OS will throttle CPU */ + gnvs->tpsv = 90; +} diff --git a/src/mainboard/hp/folio_9480m/board_info.txt b/src/mainboard/hp/folio_9480m/board_info.txt new file mode 100644 index 0000000..fdd0d60 --- /dev/null +++ b/src/mainboard/hp/folio_9480m/board_info.txt @@ -0,0 +1,7 @@ +Category: laptop +Board URL: https://support.hp.com/us-en/product/hp-elitebook-folio-9480m-notebook-pc/7… +ROM protocol: SPI +ROM package: SOIC-8 +ROM socketed: n +Flashrom support: y +Release year: 2014 diff --git a/src/mainboard/hp/folio_9480m/bootblock.c b/src/mainboard/hp/folio_9480m/bootblock.c new file mode 100644 index 0000000..ebc00fe --- /dev/null +++ b/src/mainboard/hp/folio_9480m/bootblock.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <ec/hp/kbc1126/ec.h> +#include <southbridge/intel/lynxpoint/pch.h> + +void mainboard_config_superio(void) +{ + kbc1126_enter_conf(); + kbc1126_mailbox_init(); + kbc1126_kbc_init(); + kbc1126_ec_init(); + kbc1126_pm1_init(); + kbc1126_exit_conf(); +} diff --git a/src/mainboard/hp/folio_9480m/devicetree.cb b/src/mainboard/hp/folio_9480m/devicetree.cb new file mode 100644 index 0000000..6653cf9 --- /dev/null +++ b/src/mainboard/hp/folio_9480m/devicetree.cb @@ -0,0 +1,86 @@ +chip northbridge/intel/haswell + register "dq_pins_interleaved" = "true" + register "ec_present" = "true" + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_panel_power_backlight_off_delay" = "1" + register "gpu_panel_power_backlight_on_delay" = "1" + register "gpu_panel_power_cycle_delay" = "6" + register "gpu_panel_power_down_delay" = "500" + register "gpu_panel_power_up_delay" = "2000" + register "gpu_pch_backlight_pwm_hz" = "200" + register "usb_xhci_on_resume" = "true" + device cpu_cluster 0 on + chip cpu/intel/haswell + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0 on end + device lapic 0xacac off end + end + end + device domain 0x0 on + subsystemid 0x103c 0x22da inherit + device pci 00.0 on end # Host bridge + device pci 02.0 on end # Internal graphics VGA controller + device pci 03.0 on end # Mini-HD audio + + chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH + register "docking_supported" = "0" + register "gen1_dec" = "0x007c0201" + register "gen2_dec" = "0x000c0101" + register "gen4_dec" = "0x000402e9" + register "sata_ahci" = "1" + register "sata_port0_gen3_dtle" = "0x6" + register "sata_port1_gen3_dtle" = "0x6" + # SATA(1), M.2(3) + register "sata_port_map" = "0xa" + device pci 13.0 off end # Intel Smart Sound DSP + device pci 14.0 on end # xHCI Controller + device pci 15.0 off end # Serial I/O DMA + device pci 15.1 off end # I2C0 + device pci 15.2 off end # I2C1 + device pci 15.3 off end # GSPI0 + device pci 15.4 off end # GSPI1 + device pci 15.5 off end # UART0 + device pci 15.6 off end # UART1 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 on end # Intel Gigabit Ethernet + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 on end # PCIe Port #2, Realtek Card Reader + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 on # PCIe Port #4, WLAN + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" + "M.2 2230" "SlotDataBusWidth1X" + end + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1f.0 on # LPC bridge + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + # This laptop uses MEC1322, but it has the same interface + # as the KBC1126 laptops + chip ec/hp/kbc1126 + register "ec_data_port" = "0x62" + register "ec_cmd_port" = "0x66" + register "ec_ctrl_reg" = "0x81" + register "ec_fan_ctrl_value" = "0x6b" + device pnp ff.1 off end + end + end + device pci 1f.2 on end # SATA Controller (AHCI) + device pci 1f.3 on end # SMBus + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/hp/folio_9480m/dsdt.asl b/src/mainboard/hp/folio_9480m/dsdt.asl new file mode 100644 index 0000000..eef373a --- /dev/null +++ b/src/mainboard/hp/folio_9480m/dsdt.asl @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI 2.0 and up */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/haswell/acpi/haswell.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/lynxpoint/acpi/pch.asl> + } +} diff --git a/src/mainboard/hp/folio_9480m/gma-mainboard.ads b/src/mainboard/hp/folio_9480m/gma-mainboard.ads new file mode 100644 index 0000000..8eea59a --- /dev/null +++ b/src/mainboard/hp/folio_9480m/gma-mainboard.ads @@ -0,0 +1,20 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + -- FIXME: check this + ports : constant Port_List := + (DP1, + DP2, + HDMI1, + HDMI2, + eDP, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/hp/folio_9480m/gpio.c b/src/mainboard/hp/folio_9480m/gpio.c new file mode 100644 index 0000000..3ad465a --- /dev/null +++ b/src/mainboard/hp/folio_9480m/gpio.c @@ -0,0 +1,105 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/lynxpoint/lp_gpio.h> + +const struct pch_lp_gpio_map mainboard_gpio_map[] = { + [0] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [1] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [2] = LP_GPIO_OUT_LOW, + [3] = LP_GPIO_OUT_HIGH, + [4] = LP_GPIO_OUT_HIGH, + [5] = LP_GPIO_OUT_HIGH, + [6] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [7] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [8] = LP_GPIO_OUT_HIGH, + [9] = LP_GPIO_OUT_HIGH, + [10] = LP_GPIO_OUT_HIGH, + [11] = LP_GPIO_OUT_HIGH, + [12] = LP_GPIO_NATIVE, + [13] = LP_GPIO_OUT_HIGH, + [14] = LP_GPIO_OUT_HIGH, + [15] = LP_GPIO_OUT_HIGH, + [16] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, .route = GPIO_ROUTE_SMI }, + [17] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [18] = LP_GPIO_OUT_HIGH, + [19] = LP_GPIO_NATIVE, + [20] = LP_GPIO_NATIVE, + [21] = LP_GPIO_NATIVE, + [22] = LP_GPIO_OUT_HIGH, + [23] = LP_GPIO_OUT_HIGH, + [24] = LP_GPIO_OUT_HIGH, + [25] = LP_GPIO_OUT_HIGH, + [26] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [27] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [28] = LP_GPIO_OUT_HIGH, + [29] = LP_GPIO_OUT_HIGH, + [30] = LP_GPIO_NATIVE, + [31] = LP_GPIO_NATIVE, + [32] = LP_GPIO_NATIVE, + [33] = LP_GPIO_NATIVE, + [34] = LP_GPIO_OUT_HIGH, + [35] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [36] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, .route = GPIO_ROUTE_SMI }, + [37] = LP_GPIO_NATIVE, + [38] = LP_GPIO_NATIVE, + [39] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL, + .route = GPIO_ROUTE_SMI }, + [40] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL, + .route = GPIO_ROUTE_SMI }, + [41] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [42] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [43] = LP_GPIO_OUT_HIGH, + [44] = LP_GPIO_OUT_LOW, + [45] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [46] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [47] = LP_GPIO_OUT_HIGH, + [48] = LP_GPIO_OUT_LOW, + [49] = LP_GPIO_OUT_HIGH, + [50] = LP_GPIO_OUT_HIGH, + [51] = LP_GPIO_OUT_HIGH, + [52] = LP_GPIO_OUT_HIGH, + [53] = LP_GPIO_OUT_HIGH, + [54] = LP_GPIO_OUT_LOW, + [55] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, + .pirq = GPIO_PIRQ_APIC_ROUTE }, + [56] = LP_GPIO_OUT_HIGH, + [57] = LP_GPIO_OUT_LOW, + [58] = LP_GPIO_OUT_HIGH, + [59] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [60] = LP_GPIO_OUT_HIGH, + [61] = LP_GPIO_OUT_LOW, + [62] = LP_GPIO_NATIVE, + [63] = LP_GPIO_NATIVE, + [64] = LP_GPIO_OUT_HIGH, + [65] = LP_GPIO_OUT_LOW, + [66] = LP_GPIO_OUT_HIGH, + [67] = LP_GPIO_OUT_HIGH, + [68] = LP_GPIO_OUT_HIGH, + [69] = LP_GPIO_OUT_HIGH, + [70] = LP_GPIO_OUT_LOW, + [71] = LP_GPIO_NATIVE, + [72] = LP_GPIO_NATIVE, + [73] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [74] = LP_GPIO_NATIVE, + [75] = LP_GPIO_NATIVE, + [76] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [77] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [78] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, .route = GPIO_ROUTE_SMI }, + [79] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [80] = LP_GPIO_OUT_LOW, + [81] = LP_GPIO_NATIVE, + [82] = LP_GPIO_OUT_HIGH, + [83] = LP_GPIO_OUT_HIGH, + [84] = LP_GPIO_OUT_HIGH, + [85] = LP_GPIO_OUT_HIGH, + [86] = LP_GPIO_OUT_HIGH, + [87] = LP_GPIO_OUT_HIGH, + [88] = LP_GPIO_OUT_HIGH, + [89] = LP_GPIO_OUT_HIGH, + [90] = LP_GPIO_OUT_HIGH, + [91] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [92] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [93] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [94] = LP_GPIO_OUT_HIGH, + LP_GPIO_END +}; diff --git a/src/mainboard/hp/folio_9480m/hda_verb.c b/src/mainboard/hp/folio_9480m/hda_verb.c new file mode 100644 index 0000000..fee9c3e --- /dev/null +++ b/src/mainboard/hp/folio_9480m/hda_verb.c @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0280, /* Codec Vendor / Device ID: Realtek */ + 0x103c22db, /* Subsystem ID */ + 13, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x103c22db), + AZALIA_PIN_CFG(0, 0x12, 0x90a60130), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x15, 0x0321101f), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x03a11020), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40738105), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/hp/folio_9480m/mainboard.c b/src/mainboard/hp/folio_9480m/mainboard.c new file mode 100644 index 0000000..98cc811 --- /dev/null +++ b/src/mainboard/hp/folio_9480m/mainboard.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> + +static void mainboard_enable(struct device *dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/hp/folio_9480m/romstage.c b/src/mainboard/hp/folio_9480m/romstage.c new file mode 100644 index 0000000..ca4046a --- /dev/null +++ b/src/mainboard/hp/folio_9480m/romstage.c @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdint.h> +#include <northbridge/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/raminit.h> +#include <southbridge/intel/lynxpoint/pch.h> + +void mainboard_config_rcba(void) +{ + RCBA16(D31IR) = DIR_ROUTE(PIRQF, PIRQD, PIRQC, PIRQA); + RCBA16(D29IR) = DIR_ROUTE(PIRQB, PIRQD, PIRQA, PIRQC); + RCBA16(D28IR) = DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA); + RCBA16(D27IR) = DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD); + RCBA16(D26IR) = DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD); + RCBA16(D25IR) = DIR_ROUTE(PIRQE, PIRQB, PIRQC, PIRQD); + RCBA16(D22IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); + RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); +} + +void mb_get_spd_map(uint8_t spd_map[4]) +{ + spd_map[0] = 0xa0; + spd_map[2] = 0xa4; +} + +void mainboard_fill_pei_data(struct pei_data *pei_data) +{ + struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = { + /* Length, Enable, OCn#, Location */ + { 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* left, EHCI debug */ + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* right */ + { 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE }, /* WLAN */ + { 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* SmartCard */ + { 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE }, /* WWAN */ + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* Webcam */ + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, + }; + struct usb3_port_setting usb3_ports[MAX_USB3_PORTS] = { + { 1, USB_OC_PIN_SKIP }, + { 1, USB_OC_PIN_SKIP }, /* left */ + { 1, USB_OC_PIN_SKIP }, /* right */ + { 0, USB_OC_PIN_SKIP }, + }; + memcpy(pei_data->usb2_ports, usb2_ports, sizeof(usb2_ports)); + memcpy(pei_data->usb3_ports, usb3_ports, sizeof(usb3_ports)); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/45578 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2328c43cbb1f488aa1d0ddd9116814d971e5d8ae Gerrit-Change-Number: 45578 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

5 30

Change in coreboot[master]: util/inteltool: add missing special function pads for CNL-H
by Stefan Reinauer (Code Review) 10 Nov '20

10 Nov '20

Stefan Reinauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45204 ) Change subject: util/inteltool: add missing special function pads for CNL-H ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/45204 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib83aeef9f4b6aa174e61ccbd87fb7b6450ed773b Gerrit-Change-Number: 45204 Gerrit-PatchSet: 7 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 10 Nov 2020 05:28:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit November 2020