coreboot-gerrit November 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/xeon_sp: Enable SMI handler
by Marc Jones (Code Review) 10 Nov '20

10 Nov '20

Marc Jones has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46231 ) Change subject: soc/intel/xeon_sp: Enable SMI handler ...................................................................... Patch Set 24: Code-Review+1 LGTM, but haven't been able to test it yet. -- To view, visit https://review.coreboot.org/c/coreboot/+/46231 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iabee5c72f0245ab988d477ac8df3d8d655a2a506 Gerrit-Change-Number: 46231 Gerrit-PatchSet: 24 Gerrit-Owner: Rocky Phagura Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 10 Nov 2020 17:21:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: Implementation of crashlog for intel TGL
by Angel Pons (Code Review) 10 Nov '20

10 Nov '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46965 ) Change subject: Implementation of crashlog for intel TGL ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/46965/2//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/46965/2//COMMIT_MSG@7 PS2, Line 7: crashlog I imagine this patch is still in a Work-In-Progress state, but it would be nice to explain what this crashlog is about. -- To view, visit https://review.coreboot.org/c/coreboot/+/46965 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e084dfb9e50832c4baae969eb87b6d9b0f0401e Gerrit-Change-Number: 46965 Gerrit-PatchSet: 2 Gerrit-Owner: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Nikunj Dadhania <nikunj.dadhania(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Francois Toguo Fotso <francois.toguo.fotso(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 10 Nov 2020 17:02:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer/delbin: Set GPP_B2 as GPIO
by Duncan Laurie (Code Review) 10 Nov '20

10 Nov '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47256 ) Change subject: mb/google/volteer/delbin: Set GPP_B2 as GPIO ...................................................................... mb/google/volteer/delbin: Set GPP_B2 as GPIO This pin controls the power of the attached M.2 storage device so it should be configured as a GPIO output and driven high at boot. BUG=b:160996445 TEST=test suspend/resume with RTD3 enabled Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Change-Id: Iaad1a92fed67882d7c937bf22360a3f93d17111d --- M src/mainboard/google/volteer/variants/delbin/gpio.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/47256/1 diff --git a/src/mainboard/google/volteer/variants/delbin/gpio.c b/src/mainboard/google/volteer/variants/delbin/gpio.c index 5748bb3..bebf38f 100644 --- a/src/mainboard/google/volteer/variants/delbin/gpio.c +++ b/src/mainboard/google/volteer/variants/delbin/gpio.c @@ -27,8 +27,8 @@ /* A23 : I2S1_SCLK ==> I2S1_SPKR_SCLK */ PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), - /* B2 : VRALERT# ==> NC */ - PAD_NC(GPP_B2, NONE), + /* B2 : VRALERT# ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_B2, 1, DEEP), /* B9 : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */ -- To view, visit https://review.coreboot.org/c/coreboot/+/47256 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaad1a92fed67882d7c937bf22360a3f93d17111d Gerrit-Change-Number: 47256 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer: Disable Precision Time Management for NVMe
by Duncan Laurie (Code Review) 10 Nov '20

10 Nov '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46857 ) Change subject: mb/google/volteer: Disable Precision Time Management for NVMe ...................................................................... mb/google/volteer: Disable Precision Time Management for NVMe In order for runtime D3 support on NVMe it has been found that Prevision Time Management needs to be disabled for the PCIe root port 9. BUG=b:16099644 TEST=test RTD3 on NVMe on reworked volteer and delbin device Change-Id: Ie77494214bee136a65b5a343da310b9b320ba5b4 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/46857/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 2a62505..f47e29a 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -83,6 +83,7 @@ register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[0]" = "8" register "PcieClkSrcClkReq[0]" = "0" + register "PciePtmDisable[8]" = "1" # Enable Optane PCIE 11 using clk 0 register "PcieRpEnable[10]" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/46857 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie77494214bee136a65b5a343da310b9b320ba5b4 Gerrit-Change-Number: 46857 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/block/cse: Modify heci_send_receive to support MCHI ...
by Krishna P Bhat D (Code Review) 10 Nov '20

10 Nov '20

Hello build bot (Jenkins), Furquan Shaikh, Maulik V Vaghela, Rizwan Qureshi, Aamir Bohra, Patrick Rudolph, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46881 to look at the new patch set (#5). Change subject: soc/intel/common/block/cse: Modify heci_send_receive to support MCHI address ...................................................................... soc/intel/common/block/cse: Modify heci_send_receive to support MCHI address Modify heci_send_receive function to add support to send and receive messages to MCHI Client address. BUG=b:169626786 BRANCH=None TEST=Verify send and receive reply HECI message on drawlat. Change-Id: Ice6f6bb0069080b9ac75a5323475c002e03eb751 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com> --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 14 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/46881/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/46881 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice6f6bb0069080b9ac75a5323475c002e03eb751 Gerrit-Change-Number: 46881 Gerrit-PatchSet: 5 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/block/cse: Modify heci_send_receive to support MCHI ...
by build bot (Jenkins) (Code Review) 10 Nov '20

10 Nov '20

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46881 ) Change subject: soc/intel/common/block/cse: Modify heci_send_receive to support MCHI address ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/46881/4/src/soc/intel/common/block… File src/soc/intel/common/block/cse/cse.c: https://review.coreboot.org/c/coreboot/+/46881/4/src/soc/intel/common/block… PS4, Line 545: else { else should follow close brace '}' -- To view, visit https://review.coreboot.org/c/coreboot/+/46881 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice6f6bb0069080b9ac75a5323475c002e03eb751 Gerrit-Change-Number: 46881 Gerrit-PatchSet: 4 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 10 Nov 2020 15:52:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/cse: Add functions to support setting DAM state
by Krishna P Bhat D (Code Review) 10 Nov '20

10 Nov '20

Hello build bot (Jenkins), Furquan Shaikh, Maulik V Vaghela, Rizwan Qureshi, Aamir Bohra, Patrick Rudolph, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46882 to look at the new patch set (#4). Change subject: soc/intel/common/block/cse: Add functions to support setting DAM state ...................................................................... soc/intel/common/block/cse: Add functions to support setting DAM state This patch adds the following helper functions, get_dam_state : To get DAM state. set_dam_state : To set DAM state. disable_dam : To disable DAM. To communicate with CSE, BIOS uses read_file_ex, set_file_ex and commit_file commands over MEI messages. After passing DAM setting to CSE, BIOS needs to initiate a global reset. BUG=b:169626786 BRANCH=None TEST=Build, boot drawlat and check DAM state, set DAM state. Change-Id: If42eb150577e9f76318e77ae31eb6f5844a4143d Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com> --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 64 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/46882/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/46882 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If42eb150577e9f76318e77ae31eb6f5844a4143d Gerrit-Change-Number: 46882 Gerrit-PatchSet: 4 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/block/cse: Add MCHI MCA group functions to cse lib
by Krishna P Bhat D (Code Review) 10 Nov '20

10 Nov '20

Hello build bot (Jenkins), Furquan Shaikh, Maulik V Vaghela, Rizwan Qureshi, Aamir Bohra, Patrick Rudolph, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46880 to look at the new patch set (#4). Change subject: soc/intel/common/block/cse: Add MCHI MCA group functions to cse lib ...................................................................... soc/intel/common/block/cse: Add MCHI MCA group functions to cse lib This patch adds the following, 1. MCHI MCA group command ID. 2. Read File Ex command Id and heci_read_file_ex helper function to read contents of a file. 3. Set File Ex command Id and heci_set_file_ex helper function to set file's data for write. 4. Commit Files command Id and heci_commit_files helper function to commit files previously set by set file command. BUG=b:169626786 BRANCH=None TEST=Build and boot drawcia. Change-Id: I1bdb83daffc291c618f3193b5b4e159c3eff188e Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com> --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 176 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/46880/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/46880 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1bdb83daffc291c618f3193b5b4e159c3eff188e Gerrit-Change-Number: 46880 Gerrit-PatchSet: 4 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/block/cse: Modify heci_send_receive to support MCHI ...
by Krishna P Bhat D (Code Review) 10 Nov '20

10 Nov '20

Hello build bot (Jenkins), Furquan Shaikh, Maulik V Vaghela, Rizwan Qureshi, Aamir Bohra, Patrick Rudolph, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46881 to look at the new patch set (#4). Change subject: soc/intel/common/block/cse: Modify heci_send_receive to support MCHI address ...................................................................... soc/intel/common/block/cse: Modify heci_send_receive to support MCHI address Modify heci_send_receive function to add support to send and receive messages to MCHI Client address. BUG=b:169626786 BRANCH=None TEST=Verify send and receive reply HECI message on drawlat. Change-Id: Ice6f6bb0069080b9ac75a5323475c002e03eb751 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com> --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 15 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/46881/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/46881 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice6f6bb0069080b9ac75a5323475c002e03eb751 Gerrit-Change-Number: 46881 Gerrit-PatchSet: 4 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/block/cse: Add functions to support setting DAM state
by build bot (Jenkins) (Code Review) 10 Nov '20

10 Nov '20

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46882 ) Change subject: soc/intel/common/block/cse: Add functions to support setting DAM state ...................................................................... Patch Set 3: (5 comments) https://review.coreboot.org/c/coreboot/+/46882/3/src/soc/intel/common/block… File src/soc/intel/common/block/cse/cse.c: https://review.coreboot.org/c/coreboot/+/46882/3/src/soc/intel/common/block… PS3, Line 956: if(heci_read_file_ex(MCA_DAM_FILE_ID, 0, &data_size, 0, dam_state) < 0){ space required before the open brace '{' https://review.coreboot.org/c/coreboot/+/46882/3/src/soc/intel/common/block… PS3, Line 956: if(heci_read_file_ex(MCA_DAM_FILE_ID, 0, &data_size, 0, dam_state) < 0){ space required before the open parenthesis '(' https://review.coreboot.org/c/coreboot/+/46882/3/src/soc/intel/common/block… PS3, Line 957: printk(BIOS_ERR, "Failed to get DAM state \n"); unnecessary whitespace before a quoted newline https://review.coreboot.org/c/coreboot/+/46882/3/src/soc/intel/common/block… PS3, Line 971: if(!status) space required before the open parenthesis '(' https://review.coreboot.org/c/coreboot/+/46882/3/src/soc/intel/common/block… PS3, Line 977: int disable_dam(void){ open brace '{' following function definitions go on the next line -- To view, visit https://review.coreboot.org/c/coreboot/+/46882 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If42eb150577e9f76318e77ae31eb6f5844a4143d Gerrit-Change-Number: 46882 Gerrit-PatchSet: 3 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 10 Nov 2020 15:42:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit November 2020