V Sowmya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47289 )
Change subject: mb/intel/adlrvp: Add PMC.MUX.CONx device configuration for adlrvp
......................................................................
mb/intel/adlrvp: Add PMC.MUX.CONx device configuration for adlrvp
This patch adds the PMC MUX and CONx devices for adlrvp. Device
specific method contains the port and orientation details used
to configure the mux.
BUG=:b:170607415
TEST=Built and booted adlrvp. Verified the PMC.MUX CONx objects
in SSDT tables.
Change-Id: I3b5bb73991feb99577c16fea00c381dd0f855769
Signed-off-by: V Sowmya <v.sowmya(a)intel.com>
---
M src/mainboard/intel/adlrvp/Kconfig
M src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb
2 files changed, 30 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/47289/1
diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig
index 97b4bf7..ee021fe 100644
--- a/src/mainboard/intel/adlrvp/Kconfig
+++ b/src/mainboard/intel/adlrvp/Kconfig
@@ -9,6 +9,7 @@
select DRIVERS_I2C_HID
select DRIVERS_I2C_GENERIC
select DRIVERS_INTEL_SOUNDWIRE
+ select DRIVERS_INTEL_PMC
select DRIVERS_USB_ACPI
select DRIVERS_SPI_ACPI
select SOC_INTEL_ALDERLAKE
diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb
index 44c324b..5e0ded5 100644
--- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb
+++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb
@@ -252,9 +252,36 @@
device pci 1e.1 off end # UART1
device pci 1e.2 on end # GSPI0
device pci 1e.3 off end # GSPI1
- device pci 1f.0 on end # eSPI
+ device pci 1f.0 on
+ chip ec/google/chromeec
+ device pnp 0c09.0 on end
+ use conn0 as mux_conn[0]
+ use conn1 as mux_conn[1]
+ end
+ end # eSPI
device pci 1f.1 on end # P2SB
- device pci 1f.2 hidden end # PMC
+ device pci 1f.2 hidden
+ # The pmc_mux chip driver is a placeholder for the
+ # PMC.MUX device in the ACPI hierarchy.
+ chip drivers/intel/pmc_mux
+ device generic 0 on
+ chip drivers/intel/pmc_mux/conn
+ register "usb2_port_number" = "1"
+ register "usb3_port_number" = "1"
+ # SBU is fixed, HSL follows CC
+ register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL"
+ device generic 0 alias conn0 on end
+ end
+ chip drivers/intel/pmc_mux/conn
+ register "usb2_port_number" = "2"
+ register "usb3_port_number" = "2"
+ # SBU is fixed, HSL follows CC
+ register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL"
+ device generic 1 alias conn1 on end
+ end
+ end
+ end
+ end # PMC
device pci 1f.3 on
chip drivers/intel/soundwire
device generic 0 on
--
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Gerrit-Change-Id: I3b5bb73991feb99577c16fea00c381dd0f855769
Gerrit-Change-Number: 47289
Gerrit-PatchSet: 1
Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com>
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Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47173 )
Change subject: soc/intel/xeon_sp: Don't add MC resource twice
......................................................................
soc/intel/xeon_sp: Don't add MC resource twice
Don't add the MC resources for each multiple sockets/CPUs. Only
do it for the boot CPU.
Change-Id: Ia336f604441ae8d30b8418300da7c34ab9907cae
Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com>
---
M src/soc/intel/xeon_sp/uncore.c
1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/47173/1
diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c
index 332b9a4..15a9f0f 100644
--- a/src/soc/intel/xeon_sp/uncore.c
+++ b/src/soc/intel/xeon_sp/uncore.c
@@ -155,6 +155,10 @@
struct resource *resource;
int index = *res_count;
+ /* Only add dram resources once. */
+ if (dev->bus->secondary != 0)
+ return;
+
fsp_find_reserved_memory(&fsp_mem);
/* Read in the MAP registers and report their values. */
--
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Gerrit-PatchSet: 1
Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
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Jingle Hsu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47163 )
Change subject: util/inteltool: Add support for Intel Lewisburg SKU C621A
......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/c/coreboot/+/47163/4//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/coreboot/+/47163/4//COMMIT_MSG@9
PS4, Line 9: for
> nit: on
Done
https://review.coreboot.org/c/coreboot/+/47163/4//COMMIT_MSG@11
PS4, Line 11: if
> nit: it
Done
--
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Gerrit-Change-Id: I58797914aa5816aedace094c179e832150ad5e2e
Gerrit-Change-Number: 47163
Gerrit-PatchSet: 4
Gerrit-Owner: Jingle Hsu <jingle_hsu(a)wiwynn.com>
Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com>
Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com>
Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com>
Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Gerrit-Comment-Date: Mon, 09 Nov 2020 09:59:36 +0000
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Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-MessageType: comment
Hello Jonathan Zhang, Johnny Lin, Stefan Reinauer, Angel Pons, Morgan Jang,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47163
to look at the new patch set (#5).
Change subject: util/inteltool: Add support for Intel Lewisburg SKU C621A
......................................................................
util/inteltool: Add support for Intel Lewisburg SKU C621A
Add support for dumping GPIOs on Intel Lewisburg SKU C621A.
Tested=On OCP Delta Lake DVT, verify it executes successfully.
Change-Id: I58797914aa5816aedace094c179e832150ad5e2e
Signed-off-by: Jingle Hsu <jingle_hsu(a)wiwynn.com>
---
M util/inteltool/inteltool.c
M util/inteltool/pcr.c
2 files changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/47163/5
--
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Gerrit-PatchSet: 5
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Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com>
Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com>
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47229 )
Change subject: mb/ocp/deltalake: Configure GPIO for DVT
......................................................................
Patch Set 3: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/47229/3//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/coreboot/+/47229/3//COMMIT_MSG@11
PS3, Line 11: Add a config to switch between EVT and DVT.
I would prefer to determine at runtime whether a board is EVT or DVT. Moreover, I believe most of the GPIOs don't change too much, so this could be simplified a lot. However, I don't have the schematics for Deltalake, so I can't check.
--
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Gerrit-PatchSet: 3
Gerrit-Owner: Jingle Hsu <jingle_hsu(a)wiwynn.com>
Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com>
Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com>
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Gerrit-Comment-Date: Mon, 09 Nov 2020 09:43:56 +0000
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47163 )
Change subject: util/inteltool: Add support for Intel Lewisburg SKU C621A
......................................................................
Patch Set 4: Code-Review+2
(2 comments)
https://review.coreboot.org/c/coreboot/+/47163/4//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/coreboot/+/47163/4//COMMIT_MSG@9
PS4, Line 9: for
nit: on
https://review.coreboot.org/c/coreboot/+/47163/4//COMMIT_MSG@11
PS4, Line 11: if
nit: it
--
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Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com>
Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com>
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Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
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