Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47173 )
Change subject: soc/intel/xeon_sp: Don't add MC resource twice
......................................................................
soc/intel/xeon_sp: Don't add MC resource twice
Don't add the MC resources for each multiple sockets/CPUs. Only
do it for the boot CPU.
Change-Id: Ia336f604441ae8d30b8418300da7c34ab9907cae
Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com>
---
M src/soc/intel/xeon_sp/uncore.c
1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/47173/1
diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c
index 332b9a4..15a9f0f 100644
--- a/src/soc/intel/xeon_sp/uncore.c
+++ b/src/soc/intel/xeon_sp/uncore.c
@@ -155,6 +155,10 @@
struct resource *resource;
int index = *res_count;
+ /* Only add dram resources once. */
+ if (dev->bus->secondary != 0)
+ return;
+
fsp_find_reserved_memory(&fsp_mem);
/* Read in the MAP registers and report their values. */
--
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Gerrit-Change-Id: Ia336f604441ae8d30b8418300da7c34ab9907cae
Gerrit-Change-Number: 47173
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Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com>
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Jingle Hsu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47163 )
Change subject: util/inteltool: Add support for Intel Lewisburg SKU C621A
......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/c/coreboot/+/47163/4//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/coreboot/+/47163/4//COMMIT_MSG@9
PS4, Line 9: for
> nit: on
Done
https://review.coreboot.org/c/coreboot/+/47163/4//COMMIT_MSG@11
PS4, Line 11: if
> nit: it
Done
--
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Gerrit-Owner: Jingle Hsu <jingle_hsu(a)wiwynn.com>
Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com>
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Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-MessageType: comment
Hello Jonathan Zhang, Johnny Lin, Stefan Reinauer, Angel Pons, Morgan Jang,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47163
to look at the new patch set (#5).
Change subject: util/inteltool: Add support for Intel Lewisburg SKU C621A
......................................................................
util/inteltool: Add support for Intel Lewisburg SKU C621A
Add support for dumping GPIOs on Intel Lewisburg SKU C621A.
Tested=On OCP Delta Lake DVT, verify it executes successfully.
Change-Id: I58797914aa5816aedace094c179e832150ad5e2e
Signed-off-by: Jingle Hsu <jingle_hsu(a)wiwynn.com>
---
M util/inteltool/inteltool.c
M util/inteltool/pcr.c
2 files changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/47163/5
--
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47229 )
Change subject: mb/ocp/deltalake: Configure GPIO for DVT
......................................................................
Patch Set 3: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/47229/3//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/coreboot/+/47229/3//COMMIT_MSG@11
PS3, Line 11: Add a config to switch between EVT and DVT.
I would prefer to determine at runtime whether a board is EVT or DVT. Moreover, I believe most of the GPIOs don't change too much, so this could be simplified a lot. However, I don't have the schematics for Deltalake, so I can't check.
--
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47163 )
Change subject: util/inteltool: Add support for Intel Lewisburg SKU C621A
......................................................................
Patch Set 4: Code-Review+2
(2 comments)
https://review.coreboot.org/c/coreboot/+/47163/4//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/coreboot/+/47163/4//COMMIT_MSG@9
PS4, Line 9: for
nit: on
https://review.coreboot.org/c/coreboot/+/47163/4//COMMIT_MSG@11
PS4, Line 11: if
nit: it
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Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47010 )
Change subject: mb/google/dedede/var/drawcia: Probe and enable DPTF configuration
......................................................................
Patch Set 5:
(2 comments)
https://review.coreboot.org/c/coreboot/+/47010/5/src/mainboard/google/deded…
File src/mainboard/google/dedede/variants/drawcia/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/47010/5/src/mainboard/google/deded…
PS5, Line 95: 65
> Thanks for this info.
How did we arrive to this 65 deg C value ?
We need to discuss with ODM on this new value 65 deg C. Does it meet skin spec as per on-going discussion on b:169691800 ?
https://review.coreboot.org/c/coreboot/+/47010/5/src/mainboard/google/deded…
PS5, Line 139: # Default DPTF Policy for all drawcia boards if not overridden
: register "options.tsr[0].desc" = ""Memory""
: register "options.tsr[1].desc" = ""Ambient""
: register "options.tsr[2].desc" = ""Charger""
: register "options.tsr[3].desc" = ""5V regulator""
> They are two separate devices so it's kind of tricky to share registers between them
Tim, I did not get your comment, please elaborate.
Here, in this patch the only new code change is TSR1 temperature trip value changed from 51 to 65 deg C. All other entries here are the same as previous existing ones, including sensor description entries.
So, I feel we might not need to add the same sensor description entries again here because these are common entries for the system which won't change. Thanks.
--
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Ken Lu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47358 )
Change subject: mb/google/volteer: Create drobit variant
......................................................................
Patch Set 2:
This CL is create for issue root cause investigation .
--
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