November 2020 - coreboot-gerrit

Change in coreboot[master]: mb/ocp/deltalake: Configure GPIO for DVT
by Angel Pons (Code Review) Nov. 9, 2020

Nov. 9, 2020

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47229 ) Change subject: mb/ocp/deltalake: Configure GPIO for DVT ...................................................................... Patch Set 3: Code-Review+1 (1 comment) https://review.coreboot.org/c/coreboot/+/47229/3//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/47229/3//COMMIT_MSG@11 PS3, Line 11: Add a config to switch between EVT and DVT. I would prefer to determine at runtime whether a board is EVT or DVT. Moreover, I believe most of the GPIOs don't change too much, so this could be simplified a lot. However, I don't have the schematics for Deltalake, so I can't check. -- To view, visit https://review.coreboot.org/c/coreboot/+/47229 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9837a22bc231a4cb919de316ff6f6ee88411ab8 Gerrit-Change-Number: 47229 Gerrit-PatchSet: 3 Gerrit-Owner: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Comment-Date: Mon, 09 Nov 2020 09:43:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: util/inteltool: Add support for Intel Lewisburg SKU C621A
by Angel Pons (Code Review) Nov. 9, 2020

Nov. 9, 2020

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47163 ) Change subject: util/inteltool: Add support for Intel Lewisburg SKU C621A ...................................................................... Patch Set 4: Code-Review+2 (2 comments) https://review.coreboot.org/c/coreboot/+/47163/4//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/47163/4//COMMIT_MSG@9 PS4, Line 9: for nit: on https://review.coreboot.org/c/coreboot/+/47163/4//COMMIT_MSG@11 PS4, Line 11: if nit: it -- To view, visit https://review.coreboot.org/c/coreboot/+/47163 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I58797914aa5816aedace094c179e832150ad5e2e Gerrit-Change-Number: 47163 Gerrit-PatchSet: 4 Gerrit-Owner: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Mon, 09 Nov 2020 09:40:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Replace if-else-if ladder with switch construct
by Angel Pons (Code Review) Nov. 9, 2020

Nov. 9, 2020

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47054 ) Change subject: mb/intel/adlrvp: Replace if-else-if ladder with switch construct ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/47054 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I268db8bc63aaf64d4a91c9a44ef5282154b20a53 Gerrit-Change-Number: 47054 Gerrit-PatchSet: 6 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 09 Nov 2020 09:07:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/drawcia: Probe and enable DPTF configuration
by Sumeet R Pawnikar (Code Review) Nov. 9, 2020

Nov. 9, 2020

Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47010 ) Change subject: mb/google/dedede/var/drawcia: Probe and enable DPTF configuration ...................................................................... Patch Set 5: (2 comments) https://review.coreboot.org/c/coreboot/+/47010/5/src/mainboard/google/deded… File src/mainboard/google/dedede/variants/drawcia/overridetree.cb: https://review.coreboot.org/c/coreboot/+/47010/5/src/mainboard/google/deded… PS5, Line 95: 65 > Thanks for this info. How did we arrive to this 65 deg C value ? We need to discuss with ODM on this new value 65 deg C. Does it meet skin spec as per on-going discussion on b:169691800 ? https://review.coreboot.org/c/coreboot/+/47010/5/src/mainboard/google/deded… PS5, Line 139: # Default DPTF Policy for all drawcia boards if not overridden : register "options.tsr[0].desc" = ""Memory"" : register "options.tsr[1].desc" = ""Ambient"" : register "options.tsr[2].desc" = ""Charger"" : register "options.tsr[3].desc" = ""5V regulator"" > They are two separate devices so it's kind of tricky to share registers between them Tim, I did not get your comment, please elaborate. Here, in this patch the only new code change is TSR1 temperature trip value changed from 51 to 65 deg C. All other entries here are the same as previous existing ones, including sensor description entries. So, I feel we might not need to add the same sensor description entries again here because these are common entries for the system which won't change. Thanks. -- To view, visit https://review.coreboot.org/c/coreboot/+/47010 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf166a2e36fa5775e2dea7c1adcae843cc143d32 Gerrit-Change-Number: 47010 Gerrit-PatchSet: 5 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 09 Nov 2020 08:35:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer: Create drobit variant
by Ken Lu (Code Review) Nov. 8, 2020

Nov. 8, 2020

Ken Lu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47358 ) Change subject: mb/google/volteer: Create drobit variant ...................................................................... Patch Set 2: This CL is create for issue root cause investigation . -- To view, visit https://review.coreboot.org/c/coreboot/+/47358 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib3dca73dea26c0d267d8e0e725d712f750810b06 Gerrit-Change-Number: 47358 Gerrit-PatchSet: 2 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Comment-Date: Mon, 09 Nov 2020 07:50:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/purism/librem_cml: Add baseboard and Librem Mini v2 board
by Matt DeVillier (Code Review) Nov. 8, 2020

Nov. 8, 2020

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46984 ) Change subject: mb/purism/librem_cml: Add baseboard and Librem Mini v2 board ...................................................................... mb/purism/librem_cml: Add baseboard and Librem Mini v2 board Add new Cometlake-U baseboard, and Librem Mini v2 variant. The Mini v2 is the same board as the v1, except for the SoC change from Whiskeylake-U to Cometlake-U. Documentation has been updated accordingly. Change-Id: I856bb914941211cfbec4fed871ba2a5a038e23c3 Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm> --- A Documentation/mainboard/purism/librem_mini_v2.md A src/mainboard/purism/librem_cml/Kconfig A src/mainboard/purism/librem_cml/Kconfig.name A src/mainboard/purism/librem_cml/Makefile.inc A src/mainboard/purism/librem_cml/acpi/mainboard.asl A src/mainboard/purism/librem_cml/board_info.txt A src/mainboard/purism/librem_cml/dsdt.asl A src/mainboard/purism/librem_cml/ramstage.c A src/mainboard/purism/librem_cml/romstage.c A src/mainboard/purism/librem_cml/variants/librem_mini/board_info.txt A src/mainboard/purism/librem_cml/variants/librem_mini/data.vbt A src/mainboard/purism/librem_cml/variants/librem_mini/devicetree.cb A src/mainboard/purism/librem_cml/variants/librem_mini/gpio.c A src/mainboard/purism/librem_cml/variants/librem_mini/hda_verb.c A src/mainboard/purism/librem_cml/variants/librem_mini/include/variant/gpio.h A src/mainboard/purism/librem_cml/variants/librem_mini/include/variant/variant.h A src/mainboard/purism/librem_cml/variants/librem_mini/variant.c 17 files changed, 1,352 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/46984/1 diff --git a/Documentation/mainboard/purism/librem_mini_v2.md b/Documentation/mainboard/purism/librem_mini_v2.md new file mode 100644 index 0000000..81ae9a5 --- /dev/null +++ b/Documentation/mainboard/purism/librem_mini_v2.md @@ -0,0 +1,123 @@ +# Purism Librem Mini v2 + +This page describes how to run coreboot on the [Purism Librem Mini v2]. + +```eval_rst ++------------------+--------------------------------------------------+ +| CPU | Intel Core i7-10510U | ++------------------+--------------------------------------------------+ +| PCH | Comet Point LP Premium (Cometlake-U) | ++------------------+--------------------------------------------------+ +| Super I/O, EC | ITE IT8528E | ++------------------+--------------------------------------------------+ +| Coprocessor | Intel Management Engine (CSME 14.x) | ++------------------+--------------------------------------------------+ +``` + +![](librem_mini.jpg) +![](librem_mini_flash.jpg) + +## Required proprietary blobs + +To build a minimal working coreboot image some blobs are required (assuming +only the BIOS region is being modified). + +```eval_rst ++-----------------+---------------------------------+---------------------+ +| Binary file | Apply | Required / Optional | ++=================+=================================+=====================+ +| FSP-M, FSP-S | Intel Firmware Support Package | Required | ++-----------------+---------------------------------+---------------------+ +| microcode | CPU microcode | Required | ++-----------------+---------------------------------+---------------------+ +| vgabios | VGA Option ROM | Optional | ++-----------------+---------------------------------+---------------------+ +``` + +FSP-M and FSP-S are obtained after splitting the Comet Lake FSP binary (done +automatically by the coreboot build system and included into the image) from +the `3rdparty/fsp` submodule. + +Microcode updates are automatically included into the coreboot image by the build +system from the `3rdparty/intel-microcode` submodule. Official Purism release +images may include newer microcode, which is instead pulled from Purism's +[purism-blobs] repository. + +VGA Option ROM is not required to boot, but if one needs graphics in pre-OS +stage, it should be included (if not using FSP/GOP display init). It can +be extracted via cbfstool from the existing board firmware or pulled from +the [purism-blobs] repository. + +## Intel Management Engine + +The Librem Mini v2 uses version 14.x of the Intel Management Engine (ME) / +Converged Security Engine (CSE). The ME/CSE is disabled using the High +Assurance Platform (HAP) bit, which puts the ME into a disabled state +after platform bring-up (BUP) and disables all PCI/HECI interfaces. +This can be verified via the coreboot cbmem utility: +`sudo ./cbmem -1 | grep 'ME:'` +provided coreboot has been modified to output the ME status even when +the PCI device is not visible/active (as it is in Purism's release builds). + +## Flashing coreboot + +### Internal programming + +The main SPI flash can be accessed using [flashrom]. The first build +supporting the chipset is flashrom v1.2-107-gb1f858f. Firmware an be +easily flashed with internal programmer (either BIOS region or full image). + +### External programming + +The system has an internal flash chip which is a 8 MiB soldered SOIC-8 chip, +and has a diode attached to the VCC line for in-system programming. +This chip is located on the bottom side of the board under the CPU heatsink, +in line with the front USB 2.0 ports. + +One has to remove all screws (in order): + + * 2 top cover screws + * 4 screws securing the mainboard to the chassis + * 4 screws securing the heatsink/fan assembly to the mainboard (under the SODIMMs) + +The m.2 SSD will need to be removed if the Wi-Fi antenna are connected to +an internal Wi-Fi/BT module. Use a SOIC-8 chip clip to program the chip. +Specifically, it's a Winbond W25Q128JV (3.3V) - [datasheet][W25Q128JV]. + +The EC firmware is stored on a separate SOIC-8 chip (a Winbond W25Q80DV), +but is not protected by a diode and therefore cannot be read/written to without +desoldering it from the mainboard. + +## Known issues + + * SeaBIOS can be finicky with detecting USB devices + * Mode switching with VGA option ROM display init can be slow and sometimes hang + * Some SATA devices on the 2.5" interface can have issues operating at 6Gbps, + despite the HSIO PHY settings being set optimally. These devices may show + errors in dmesg and drop down to 3Gbps, but should not fail to boot. + The same issue is present on the AMI vendor firmware. + +## Working + + * External displays via HDMI/DislpayPort with VGA option ROM or FSP/GOP init + (no libgfxinit support yet) + * SeaBIOS (1.14), Tianocore (CorebootPayloadpkg), Heads (Purism downstream) payloads + * Ethernet, m.2 2230 Wi-Fi + * System firmware updates via flashrom + * PCIe NVMe + * m.2 and SATA III + * Audio via front 3.5mm jack, HDMI, and DisplayPort + * SMBus (reading SPD from DIMMs) + * Initialization with CML FSP 2.0 + * S3 Suspend/Resume + * Booting PureOS 10.x, Debian 11.x, Qubes 4.1.0-alpha1, Linux Mint 20, Windows 10 2004 + +## Not working / untested + + * ITE IT8528E Super IO functions + + +[Purism Librem Mini v2]: https://puri.sm/products/librem-mini/ +[purism-blobs]: https://source.puri.sm/coreboot/purism-blobs +[W25Q128JV]: https://www.winbond.com/resource-files/w25q128jv%20revf%2003272018%20plus.p… +[flashrom]: https://flashrom.org/Flashrom diff --git a/src/mainboard/purism/librem_cml/Kconfig b/src/mainboard/purism/librem_cml/Kconfig new file mode 100644 index 0000000..0d70300 --- /dev/null +++ b/src/mainboard/purism/librem_cml/Kconfig @@ -0,0 +1,69 @@ +config BOARD_PURISM_BASEBOARD_LIBREM_CML + def_bool n + select BOARD_ROMSIZE_KB_16384 + select DRIVERS_GENERIC_CBFS_SERIAL + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select INTEL_LPSS_UART_FOR_CONSOLE + select NO_UART_ON_SUPERIO + select SOC_INTEL_COMETLAKE_1 + select SOC_INTEL_COMMON_BLOCK_HDA + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SPD_READ_BY_WORD + select USE_LEGACY_8254_TIMER + +if BOARD_PURISM_BASEBOARD_LIBREM_CML + +config MAINBOARD_DIR + string + default "purism/librem_cml" + +config MAINBOARD_FAMILY + string + default "Librem Mini" if BOARD_PURISM_LIBREM_MINI_V2 + +config MAINBOARD_PART_NUMBER + string + default "Librem Mini v2" if BOARD_PURISM_LIBREM_MINI_V2 + +config VARIANT_DIR + string + default "librem_mini" if BOARD_PURISM_LIBREM_MINI_V2 + +config DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + +config CBFS_SIZE + hex + default 0xA00000 + +config MAX_CPUS + int + default 8 + +config DIMM_MAX + int + default 2 + +config DIMM_SPD_SIZE + int + default 512 + +config VGA_BIOS_ID + string + default "8086,9b41" + +config PXE_ROM_ID + string + default "10ec,8168" + +config NO_POST + bool + default y + +config CONSOLE_SERIAL + bool + default n +endif diff --git a/src/mainboard/purism/librem_cml/Kconfig.name b/src/mainboard/purism/librem_cml/Kconfig.name new file mode 100644 index 0000000..726aee9 --- /dev/null +++ b/src/mainboard/purism/librem_cml/Kconfig.name @@ -0,0 +1,3 @@ +config BOARD_PURISM_LIBREM_MINI_V2 + bool "Librem Mini v2" + select BOARD_PURISM_BASEBOARD_LIBREM_CML diff --git a/src/mainboard/purism/librem_cml/Makefile.inc b/src/mainboard/purism/librem_cml/Makefile.inc new file mode 100644 index 0000000..8e3b5a6 --- /dev/null +++ b/src/mainboard/purism/librem_cml/Makefile.inc @@ -0,0 +1,9 @@ +## SPDX-License-Identifier: GPL-2.0-only + +romstage-y += variants/$(VARIANT_DIR)/variant.c + +ramstage-y += variants/$(VARIANT_DIR)/gpio.c +ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c +ramstage-y += ramstage.c + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/purism/librem_cml/acpi/mainboard.asl b/src/mainboard/purism/librem_cml/acpi/mainboard.asl new file mode 100644 index 0000000..999030d --- /dev/null +++ b/src/mainboard/purism/librem_cml/acpi/mainboard.asl @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope (\_SB.PCI0.LPCB) { + + Device (AC) + { + Name (_HID, "ACPI0003") + Name (_PCL, Package () { LPCB }) + Name (ACFG, One) + + Method (_PSR, 0, NotSerialized) + { + Return (ACFG) + } + } +} diff --git a/src/mainboard/purism/librem_cml/board_info.txt b/src/mainboard/purism/librem_cml/board_info.txt new file mode 100644 index 0000000..8283cee --- /dev/null +++ b/src/mainboard/purism/librem_cml/board_info.txt @@ -0,0 +1,8 @@ +Vendor name: Purism +Board name: Librem CometLake baseboard +Category: misc +Release year: 2020 +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/purism/librem_cml/dsdt.asl b/src/mainboard/purism/librem_cml/dsdt.asl new file mode 100644 index 0000000..6545a6e --- /dev/null +++ b/src/mainboard/purism/librem_cml/dsdt.asl @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + #include <soc/intel/common/block/acpi/acpi/platform.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + #include <cpu/intel/common/acpi/cpu.asl> + + Device (\_SB.PCI0) + { + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/cannonlake/acpi/southbridge.asl> + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> + + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/purism/librem_cml/ramstage.c b/src/mainboard/purism/librem_cml/ramstage.c new file mode 100644 index 0000000..56ed1b7 --- /dev/null +++ b/src/mainboard/purism/librem_cml/ramstage.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/ramstage.h> +#include <variant/gpio.h> + +void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + /* Configure pads prior to SiliconInit() in case there's any + * dependencies during hardware initialization. */ + size_t num_gpios; + const struct pad_config *gpio_table = variant_gpio_table(&num_gpios); + cnl_configure_pads(gpio_table, num_gpios); +} diff --git a/src/mainboard/purism/librem_cml/romstage.c b/src/mainboard/purism/librem_cml/romstage.c new file mode 100644 index 0000000..af8b473 --- /dev/null +++ b/src/mainboard/purism/librem_cml/romstage.c @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/cnl_memcfg_init.h> +#include <soc/romstage.h> +#include <variant/variant.h> + +static const struct cnl_mb_cfg memcfg = { + /* Parameters required to access SPD for CH0D0/CH0D1/CH1D0/CH1D1. */ + .spd[0] = { + .read_type = READ_SMBUS, + .spd_spec = {.spd_smbus_address = 0xa0}, + }, + .spd[1] = {.read_type = NOT_EXISTING}, + .spd[2] = { + .read_type = READ_SMBUS, + .spd_spec = {.spd_smbus_address = 0xa4}, + }, + .spd[3] = {.read_type = NOT_EXISTING}, + + /* + * Rcomp resistor values. These values represent the resistance in + * ohms of the three rcomp resistors attached to the DDR_COMP_0, + * DDR_COMP_1, and DDR_COMP_2 pins on the DRAM. + */ + .rcomp_resistor = { 121, 81, 100 }, + + /* + * Rcomp target values. These will typically be the following + * values for Cannon Lake : { 80, 40, 40, 40, 30 } + */ + .rcomp_targets = { 100, 40, 20, 20, 26 }, + + /* + * Indicates whether memory is interleaved. + * Set to 1 for an interleaved design, + * set to 0 for non-interleaved design. + */ + .dq_pins_interleaved = 1, + + /* + * VREF_CA configuration. + * Set to 0 VREF_CA goes to both CH_A and CH_B, + * set to 1 VREF_CA goes to CH_A and VREF_DQ_A goes to CH_B, + * set to 2 VREF_CA goes to CH_A and VREF_DQ_B goes to CH_B. + */ + .vref_ca_config = 2, + + /* Early Command Training */ + .ect = 0, +}; + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + FSP_M_CONFIG *mem_cfg = &memupd->FspmConfig; + cannonlake_memcfg_init(mem_cfg, &memcfg); + + variant_memory_init_params(mem_cfg); +} diff --git a/src/mainboard/purism/librem_cml/variants/librem_mini/board_info.txt b/src/mainboard/purism/librem_cml/variants/librem_mini/board_info.txt new file mode 100644 index 0000000..de22500 --- /dev/null +++ b/src/mainboard/purism/librem_cml/variants/librem_mini/board_info.txt @@ -0,0 +1,8 @@ +Vendor name: Purism +Board name: Librem Mini v2 +Category: desktop +Release year: 2020 +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/purism/librem_cml/variants/librem_mini/data.vbt b/src/mainboard/purism/librem_cml/variants/librem_mini/data.vbt new file mode 100644 index 0000000..b538209 --- /dev/null +++ b/src/mainboard/purism/librem_cml/variants/librem_mini/data.vbt Binary files differ diff --git a/src/mainboard/purism/librem_cml/variants/librem_mini/devicetree.cb b/src/mainboard/purism/librem_cml/variants/librem_mini/devicetree.cb new file mode 100644 index 0000000..5f49508 --- /dev/null +++ b/src/mainboard/purism/librem_cml/variants/librem_mini/devicetree.cb @@ -0,0 +1,170 @@ +chip soc/intel/cannonlake + # Lock Down + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + +# ACPI (soc/intel/cannonlake/acpi.c) + # PM Timer Disabled + register "PmTimerDisabled" = "1" + +# CPU (soc/intel/cannonlake/cpu.c) + # Power limit + register "power_limits_config" = "{ + .tdp_pl1_override = 25, + .tdp_pl2_override = 51, + }" + + # Enable Enhanced Intel SpeedStep + register "eist_enable" = "1" + +# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) + register "SaGv" = "SaGv_Enabled" + register "enable_c6dram" = "1" + +# FSP Silicon (soc/intel/cannonlake/fsp_params.c) + + # All SRCCLKREQ pins mapped directly + register "PcieClkSrcClkReq[0]" = "0" + register "PcieClkSrcClkReq[1]" = "1" + register "PcieClkSrcClkReq[2]" = "2" + register "PcieClkSrcClkReq[3]" = "3" + register "PcieClkSrcClkReq[4]" = "4" + register "PcieClkSrcClkReq[5]" = "5" + + # Set all SRCCLKREQ pins as free-use + register "PcieClkSrcUsage[0]" = "0x80" + register "PcieClkSrcUsage[1]" = "0x80" + register "PcieClkSrcUsage[2]" = "0x80" + register "PcieClkSrcUsage[3]" = "0x80" + register "PcieClkSrcUsage[4]" = "0x80" + register "PcieClkSrcUsage[5]" = "0x80" + + # Misc + register "satapwroptimize" = "1" + + # Power + register "PchPmSlpS3MinAssert" = "3" # 50ms + register "PchPmSlpS4MinAssert" = "1" # 1s + register "PchPmSlpSusMinAssert" = "2" # 500ms + register "PchPmSlpAMinAssert" = "4" # 2s + + # Thermal + register "tcc_offset" = "10" + +# PM Util (soc/intel/cannonlake/pmutil.c) + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + # sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG) + register "gpe0_dw0" = "PMC_GPP_C" + register "gpe0_dw1" = "PMC_GPP_D" + register "gpe0_dw2" = "PMC_GPP_E" + +# Actual device tree + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on # SA Thermal device + register "Device4Enable" = "1" + end + device pci 08.0 on end # Gaussian Mixture Model + device pci 12.0 on end # Thermal Subsystem + device pci 13.0 off end # Integrated Sensor Hub + device pci 14.0 on # USB xHCI + # USB2 + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port rear lower + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port rear upper + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port front right lower + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port front right upper + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port front left lower + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port front left upper + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port front + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Type-A ports front center (2) + # USB3 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port rear lower + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port rear upper + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port front lower + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port front upper + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C port front + end + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 on end # RAM memory + device pci 14.3 off end # CNVi wifi + device pci 14.5 off end # SDCard + device pci 15.0 off end # I2C #0 + device pci 15.1 off end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 off end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 16.5 off end # Management Engine Interface 4 + device pci 17.0 on # SATA + register "SataMode" = "Sata_AHCI" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[2]" = "1" + end + device pci 19.0 off end # I2C #4 + device pci 19.1 off end # I2C #5 + device pci 19.2 off end # UART #2 + device pci 1a.0 off end # eMMC + device pci 1c.0 off end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 on # PCI Express Port 8 + device pci 00.0 on end # x1 (WLAN) + register "PcieRpSlotImplemented[7]" = "1" + register "PcieRpEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "1" + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230" "SlotDataBusWidth1X" + chip drivers/wifi/generic + device pci 00.0 on end + end + end + device pci 1d.0 off end # PCI Express Port 9 + device pci 1d.1 on # PCI Express Port 10 + device pci 00.0 on end # x1 (LAN #2) + register "PcieRpSlotImplemented[9]" = "1" + register "PcieRpEnable[9]" = "1" + register "PcieRpLtrEnable[9]" = "0" + end + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.4 on # PCI Express Port 13 + device pci 00.0 on end # x4 M.2/M 2280 + register "PcieRpSlotImplemented[12]" = "1" + register "PcieRpEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "1" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X" + end + device pci 1d.5 off end # PCI Express Port 14 + device pci 1d.6 off end # PCI Express Port 15 + device pci 1d.7 off end # PCI Express Port 16 + device pci 1e.0 off end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1f.0 on end # LPC Interface + device pci 1f.1 off end # P2SB + device pci 1f.2 off end # Power Management Controller + device pci 1f.3 on # Intel HDA + register "PchHdaAudioLinkHda" = "1" + end + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/purism/librem_cml/variants/librem_mini/gpio.c b/src/mainboard/purism/librem_cml/variants/librem_mini/gpio.c new file mode 100644 index 0000000..001ef43 --- /dev/null +++ b/src/mainboard/purism/librem_cml/variants/librem_mini/gpio.c @@ -0,0 +1,783 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <variant/gpio.h> + +/* Pad configuration was generated automatically using intelp2m utility */ +static const struct pad_config gpio_table[] = { + + /* ------- GPIO Group GPP_A ------- */ + + /* GPP_A0 - RCIN# */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), + + /* GPP_A1 - LAD0 */ + /* DW0: 0x44000702, DW1: 0x00003c00 */ + PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), + + /* GPP_A2 - LAD1 */ + /* DW0: 0x44000702, DW1: 0x00003c00 */ + PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), + + /* GPP_A3 - LAD2 */ + /* DW0: 0x44000702, DW1: 0x00003c00 */ + PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), + + /* GPP_A4 - LAD3 */ + /* DW0: 0x44000702, DW1: 0x00003c00 */ + PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), + + /* GPP_A5 - LFRAME# */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), + + /* GPP_A6 - SERIRQ */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + + /* GPP_A7 - GPIO */ + /* DW0: 0x44000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_A7, 1, DEEP), + + /* GPP_A8 - CLKRUN# */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + + /* GPP_A9 - CLKOUT_LPC0 */ + /* DW0: 0x44000700, DW1: 0x00001000 */ + PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), + + /* GPP_A10 - CLKOUT_LPC1 */ + /* DW0: 0x44000700, DW1: 0x00001000 */ + PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1), + + /* GPP_A11 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_A11, 1, PLTRST), + + /* GPP_A12 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_A12, 1, PLTRST), + + /* GPP_A13 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_A13, 1, PLTRST), + + /* GPP_A14 - SUS_STAT# */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + + /* GPP_A15 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_A15, 1, PLTRST), + + /* GPP_A16 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00003000 */ + PAD_CFG_TERM_GPO(GPP_A16, 1, UP_20K, PLTRST), + + /* GPP_A17 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_A17, 1, PLTRST), + + /* GPP_A18 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00003000 */ + PAD_NC(GPP_A18, UP_20K), + + /* GPP_A19 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00003000 */ + PAD_NC(GPP_A19, UP_20K), + + /* GPP_A20 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00003000 */ + PAD_NC(GPP_A20, UP_20K), + + /* GPP_A21 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00003000 */ + PAD_NC(GPP_A21, UP_20K), + + /* GPP_A22 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00003000 */ + PAD_NC(GPP_A22, UP_20K), + + /* GPP_A23 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00003000 */ + PAD_NC(GPP_A23, UP_20K), + + /* ------- GPIO Group GPP_B ------- */ + + /* GPP_B0 - Reserved */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + + /* GPP_B1 - Reserved */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + + /* GPP_B2 - VRALERT# */ + /* DW0: 0x84000603, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_B2, NONE, PLTRST, NF1), + + /* GPP_B3 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_B3, 1, PLTRST), + + /* GPP_B4 - GPIO */ + /* DW0: 0x44000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), + + /* GPP_B5 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_B5, NONE), + + /* GPP_B6 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_B6, NONE), + + /* GPP_B7 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_B7, NONE), + + /* GPP_B8 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_B8, NONE), + + /* GPP_B9 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_B9, NONE), + + /* GPP_B10 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_B10, NONE), + + /* GPP_B11 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_B11, 1, PLTRST), + + /* GPP_B12 - SLP_S0# */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + + /* GPP_B13 - PLTRST# */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + + /* GPP_B14 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_B14, 1, PLTRST), + + /* GPP_B15 - GPIO */ + /* DW0: 0x80000201, DW1: 0x00003000 */ + PAD_CFG_TERM_GPO(GPP_B15, 1, UP_20K, PLTRST), + + /* GPP_B16 - GSPI0_CLK */ + /* DW0: 0x84000601, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_B16, NONE, PLTRST, NF1), + + /* GPP_B17 - GSPI0_MISO */ + /* DW0: 0x44000502, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + + /* GPP_B18 - GSPI0_MOSI */ + /* DW0: 0x84000601, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_B18, NONE, PLTRST, NF1), + + /* GPP_B19 - GSPI1_CS0# */ + /* DW0: 0x84000400, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_B19, NONE, PLTRST, NF1), + + /* GPP_B20 - GSPI1_CLK */ + /* DW0: 0x84000400, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_B20, NONE, PLTRST, NF1), + + /* GPP_B21 - GSPI1_MISO */ + /* DW0: 0x84000402, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_B21, NONE, PLTRST, NF1), + + /* GPP_B22 - GSPI1_MOSI */ + /* DW0: 0x84000400, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_B22, NONE, PLTRST, NF1), + + /* GPP_B23 - GPIO */ + /* DW0: 0x44000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_B23, 1, DEEP), + + /* ------- GPIO Group GPP_G ------- */ + + /* GPP_G0 - GPIO */ + /* DW0: 0x04000200, DW1: 0x00001000 */ + PAD_CFG_TERM_GPO(GPP_G0, 0, DN_20K, PWROK), + + /* GPP_G1 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_G1, NONE), + + /* GPP_G2 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_G2, NONE), + + /* GPP_G3 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_G3, NONE), + + /* GPP_G4 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_G4, NONE), + + /* GPP_G5 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00003000 */ + PAD_NC(GPP_G5, UP_20K), + + /* GPP_G6 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_G6, NONE), + + /* GPP_G7 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00001000 */ + PAD_NC(GPP_G7, DN_20K), + + /* ------- GPIO Group GPP_D ------- */ + + /* GPP_D0 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_D0, NONE), + + /* GPP_D1 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_D1, NONE), + + /* GPP_D2 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_D2, NONE), + + /* GPP_D3 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_D3, NONE), + + /* GPP_D4 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_D4, NONE), + + /* GPP_D5 - ISH_I2C0_SDA */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + + /* GPP_D6 - ISH_I2C0_SCL */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + + /* GPP_D7 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_D7, 1, PLTRST), + + /* GPP_D8 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_D8, 1, PLTRST), + + /* GPP_D9 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_D9, 1, PLTRST), + + /* GPP_D10 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_D10, 1, PLTRST), + + /* GPP_D11 - GPIO */ + /* DW0: 0x44000201, DW1: 0x00003000 */ + PAD_CFG_TERM_GPO(GPP_D11, 1, UP_20K, DEEP), + + /* GPP_D12 - GPIO */ + /* DW0: 0x42100102, DW1: 0x00003000 */ + PAD_CFG_GPI_APIC(GPP_D12, UP_20K, DEEP, EDGE_SINGLE, NONE), + + /* GPP_D13 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_D13, NONE), + + /* GPP_D14 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_D14, 1, PLTRST), + + /* GPP_D15 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_D15, 1, PLTRST), + + /* GPP_D16 - GPIO */ + /* DW0: 0x04000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_D16, 0, RSMRST), + + /* GPP_D17 - DMIC_CLK1 */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), + + /* GPP_D18 - DMIC_DATA1 */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), + + /* GPP_D19 - DMIC_CLK0 */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), + + /* GPP_D20 - DMIC_DATA0 */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), + + /* GPP_D21 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_D21, NONE), + + /* GPP_D22 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_D22, NONE), + + /* GPP_D23 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_D23, NONE), + + /* ------- GPIO Group GPP_F ------- */ + + /* GPP_F0 - GPIO */ + /* DW0: 0x00000301, DW1: 0x00000000 */ + PAD_NC(GPP_F0, NONE), + + /* GPP_F1 - GPIO */ + /* DW0: 0x04000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_F1, 0, RSMRST), + + /* GPP_F2 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00003000 */ + PAD_CFG_TERM_GPO(GPP_F2, 1, UP_20K, PLTRST), + + /* GPP_F3 - GPIO */ + /* DW0: 0x84000300, DW1: 0x00003000 */ + PAD_NC(GPP_F3, UP_20K), + + /* GPP_F4 - CNV_BRI_DT */ + /* DW0: 0x44000700, DW1: 0x00003000 */ + PAD_CFG_NF(GPP_F4, UP_20K, DEEP, NF1), + + /* GPP_F5 - CNV_BRI_RSP */ + /* DW0: 0x44000702, DW1: 0x00003000 */ + PAD_CFG_NF(GPP_F5, UP_20K, DEEP, NF1), + + /* GPP_F6 - CNV_RGI_DT */ + /* DW0: 0x44000700, DW1: 0x00003000 */ + PAD_CFG_NF(GPP_F6, UP_20K, DEEP, NF1), + + /* GPP_F7 - CNV_RGI_RSP */ + /* DW0: 0x44000702, DW1: 0x00003000 */ + PAD_CFG_NF(GPP_F7, UP_20K, DEEP, NF1), + + /* GPP_F8 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_F8, NONE), + + /* GPP_F9 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_F9, NONE), + + /* GPP_F10 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_F10, 1, PLTRST), + + /* GPP_F11 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_F11, NONE), + + /* GPP_F12 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_F12, NONE), + + /* GPP_F13 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_F13, NONE), + + /* GPP_F14 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_F14, NONE), + + /* GPP_F15 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_F15, NONE), + + /* GPP_F16 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_F16, NONE), + + /* GPP_F17 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_F17, NONE), + + /* GPP_F18 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_F18, NONE), + + /* GPP_F19 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_F19, NONE), + + /* GPP_F20 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_F20, NONE), + + /* GPP_F21 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_F21, NONE), + + /* GPP_F22 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_F22, NONE), + + /* GPP_F23 - A4WP_PRESENT */ + /* DW0: 0x44000700, DW1: 0x00001000 */ + PAD_CFG_NF(GPP_F23, DN_20K, DEEP, NF1), + + /* ------- GPIO Group GPP_H ------- */ + + /* GPP_H0 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00003000 */ + PAD_NC(GPP_H0, UP_20K), + + /* GPP_H1 - CNV_RF_RESET# */ + /* DW0: 0x44000f00, DW1: 0x00003000 */ + PAD_CFG_NF(GPP_H1, UP_20K, DEEP, NF3), + + /* GPP_H2 - MODEM_CLKREQ */ + /* DW0: 0x44000f00, DW1: 0x00003000 */ + PAD_CFG_NF(GPP_H2, UP_20K, DEEP, NF3), + + /* GPP_H3 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00003000 */ + PAD_NC(GPP_H3, UP_20K), + + /* GPP_H4 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_H4, NONE), + + /* GPP_H5 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_H5, NONE), + + /* GPP_H6 - I2C3_SDA */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + + /* GPP_H7 - I2C3_SCL */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + + /* GPP_H8 - I2C4_SDA */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), + + /* GPP_H9 - I2C4_SCL */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), + + /* GPP_H10 - I2C5_SDA */ + /* DW0: 0x84000603, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_H10, NONE, PLTRST, NF1), + + /* GPP_H11 - I2C5_SCL */ + /* DW0: 0x84000603, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_H11, NONE, PLTRST, NF1), + + /* GPP_H12 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_H12, 1, PLTRST), + + /* GPP_H13 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_H13, 1, PLTRST), + + /* GPP_H14 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_H14, 1, PLTRST), + + /* GPP_H15 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_H15, 1, PLTRST), + + /* GPP_H16 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_H16, NONE), + + /* GPP_H17 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_H17, 0, DEEP), + + /* GPP_H18 - CPU_C10_GATE# */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), + + /* GPP_H19 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_H19, 1, PLTRST), + + /* GPP_H20 - GPIO */ + /* DW0: 0x84000300, DW1: 0x00000000 */ + PAD_NC(GPP_H20, NONE), + + /* GPP_H21 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_H21, 0, DEEP), + + /* GPP_H22 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_H22, 1, PLTRST), + + /* GPP_H23 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_H23, 0, DEEP), + + /* ------- GPIO Group GPD ------- */ + + /* GPD0 - BATLOW# */ + /* DW0: 0x04000702, DW1: 0x00000000 */ + PAD_CFG_NF(GPD0, NONE, RSMRST, NF1), + + /* GPD1 - ACPRESENT */ + /* DW0: 0x04000702, DW1: 0x00003c00 */ + PAD_CFG_NF(GPD1, NATIVE, RSMRST, NF1), + + /* GPD2 - LAN_WAKE# */ + /* DW0: 0x04000702, DW1: 0x00003c00 */ + PAD_CFG_NF(GPD2, NATIVE, RSMRST, NF1), + + /* GPD3 - PRWBTN# */ + /* DW0: 0x04000702, DW1: 0x00003000 */ + PAD_CFG_NF(GPD3, UP_20K, RSMRST, NF1), + + /* GPD4 - SLP_S3# */ + /* DW0: 0x04000600, DW1: 0x00000000 */ + PAD_CFG_NF(GPD4, NONE, RSMRST, NF1), + + /* GPD5 - SLP_S4# */ + /* DW0: 0x04000600, DW1: 0x00000000 */ + PAD_CFG_NF(GPD5, NONE, RSMRST, NF1), + + /* GPD6 - SLP_A# */ + /* DW0: 0x04000600, DW1: 0x00000000 */ + PAD_CFG_NF(GPD6, NONE, RSMRST, NF1), + + /* GPD7 - GPIO */ + /* DW0: 0x04000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPD7, 0, RSMRST), + + /* GPD8 - SUSCLK */ + /* DW0: 0x04000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPD8, NONE, RSMRST, NF1), + + /* GPD9 - SLP_WLAN# */ + /* DW0: 0x04000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPD9, NONE, RSMRST, NF1), + + /* GPD10 - SLP_S5# */ + /* DW0: 0x04000600, DW1: 0x00000000 */ + PAD_CFG_NF(GPD10, NONE, RSMRST, NF1), + + /* GPD11 - LANPHYPC */ + /* DW0: 0x04000600, DW1: 0x00000000 */ + PAD_CFG_NF(GPD11, NONE, RSMRST, NF1), + + /* ------- GPIO Group GPP_C ------- */ + + /* GPP_C0 - SMBCLK */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + + /* GPP_C1 - SMBDATA */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + + /* GPP_C2 - GPIO */ + /* DW0: 0x44000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_C2, 1, DEEP), + + /* GPP_C3 - SML0CLK */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + + /* GPP_C4 - SML0DATA */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + + /* GPP_C5 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_C5, 1, PLTRST), + + /* GPP_C6 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_C6, NONE), + + /* GPP_C7 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_C7, NONE), + + /* GPP_C8 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_C8, 1, PLTRST), + + /* GPP_C9 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_C9, 1, PLTRST), + + /* GPP_C10 - GPIO */ + /* DW0: 0x84000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_C10, 0, PLTRST), + + /* GPP_C11 - GPIO */ + /* DW0: 0x40100103, DW1: 0x00000000 */ + PAD_CFG_GPI_APIC(GPP_C11, NONE, DEEP, LEVEL, NONE), + + /* GPP_C12 - UART1_RXD */ + /* DW0: 0x84000603, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_C12, NONE, PLTRST, NF1), + + /* GPP_C13 - UART1_TXD */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), + + /* GPP_C14 - UART1_RTS# */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), + + /* GPP_C15 - UART1_CTS# */ + /* DW0: 0x84000603, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_C15, NONE, PLTRST, NF1), + + /* GPP_C16 - I2C0_SDA */ + /* DW0: 0x84000402, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1), + + /* GPP_C17 - I2C0_SCL */ + /* DW0: 0x84000402, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1), + + /* GPP_C18 - I2C1_SDA */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + + /* GPP_C19 - I2C1_SCL */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + + /* GPP_C20 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_C20, NONE), + + /* GPP_C21 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_C21, NONE), + + /* GPP_C22 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_C22, 1, PLTRST), + + /* GPP_C23 - GPIO */ + /* DW0: 0x40100102, DW1: 0x00001000 */ + PAD_CFG_GPI_APIC(GPP_C23, DN_20K, DEEP, LEVEL, NONE), + + /* ------- GPIO Group GPP_E ------- */ + + /* GPP_E0 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_E0, NONE), + + /* GPP_E1 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_E1, NONE), + + /* GPP_E2 - SATAXPCIE2 */ + /* DW0: 0x84000502, DW1: 0x00003000 */ + PAD_CFG_NF(GPP_E2, UP_20K, PLTRST, NF1), + + /* GPP_E3 - GPIO */ + /* DW0: 0x82040102, DW1: 0x00000000 */ + PAD_CFG_GPI_SMI(GPP_E3, NONE, PLTRST, EDGE_SINGLE, NONE), + + /* GPP_E4 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_E4, 1, PLTRST), + + /* GPP_E5 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_E5, NONE), + + /* GPP_E6 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_E6, NONE), + + /* GPP_E7 - GPIO */ + /* DW0: 0x82000102, DW1: 0x00000000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_E7, NONE, PLTRST, EDGE_SINGLE, ACPI), + + /* GPP_E8 - SATALED# */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), + + /* GPP_E9 - RESERVED */ + /* DW0: 0x44001700, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF5), + + /* GPP_E10 - RESERVED */ + /* DW0: 0x44001700, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF5), + + /* GPP_E11 - USB2_OC2# */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), + + /* GPP_E12 - USB2_OC3# */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), + + /* GPP_E13 - DDPB_HPD0 */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), + + /* GPP_E14 - DDPC_HPD1 */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + + /* GPP_E15 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_E15, 1, PLTRST), + + /* GPP_E16 - GPIO */ + /* DW0: 0x80880102, DW1: 0x00003000 */ + PAD_CFG_GPI_SCI(GPP_E16, UP_20K, PLTRST, LEVEL, INVERT), + + /* GPP_E17 - EDP_HPD */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), + + /* GPP_E18 - DPPB_CTRLCLK */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), + + /* GPP_E19 - DPPB_CTRLDATA */ + /* DW0: 0x44000602, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), + + /* GPP_E20 - DPPC_CTRLCLK */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), + + /* GPP_E21 - DPPC_CTRLDATA */ + /* DW0: 0x44000602, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), + + /* GPP_E22 - DPPD_CTRLCLK */ + /* DW0: 0x84000603, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_E22, NONE, PLTRST, NF1), + + /* GPP_E23 - DPPD_CTRLDATA */ + /* DW0: 0x84000603, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_E23, NONE, PLTRST, NF1), +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} diff --git a/src/mainboard/purism/librem_cml/variants/librem_mini/hda_verb.c b/src/mainboard/purism/librem_cml/variants/librem_mini/hda_verb.c new file mode 100644 index 0000000..c3daf3c --- /dev/null +++ b/src/mainboard/purism/librem_cml/variants/librem_mini/hda_verb.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0269, /* Codec Vendor/Device ID: Realtek ALC293 */ + 0x10ec0000, /* Subsystem ID */ + 11, /* Number of entries */ + + AZALIA_SUBVENDOR(0, 0x10ec0000), + AZALIA_PIN_CFG(0, 0x12, 0x40000000), + AZALIA_PIN_CFG(0, 0x15, 0x01214010), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x01a19130), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40422201), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + + 0x8086280b, /* Codec Vendor/Device ID: Intel CannonPoint HDMI */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of entries */ + + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_PIN_CFG(2, 0x05, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560020), + AZALIA_PIN_CFG(2, 0x07, 0x18560030), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/purism/librem_cml/variants/librem_mini/include/variant/gpio.h b/src/mainboard/purism/librem_cml/variants/librem_mini/include/variant/gpio.h new file mode 100644 index 0000000..9094b04 --- /dev/null +++ b/src/mainboard/purism/librem_cml/variants/librem_mini/include/variant/gpio.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <soc/gpe.h> +#include <soc/gpio.h> + +const struct pad_config *variant_gpio_table(size_t *num); + +#endif diff --git a/src/mainboard/purism/librem_cml/variants/librem_mini/include/variant/variant.h b/src/mainboard/purism/librem_cml/variants/librem_mini/include/variant/variant.h new file mode 100644 index 0000000..ee104c8 --- /dev/null +++ b/src/mainboard/purism/librem_cml/variants/librem_mini/include/variant/variant.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_H +#define VARIANT_H + +#include <soc/romstage.h> + +void variant_memory_init_params(FSP_M_CONFIG *mem_cfg); + +#endif diff --git a/src/mainboard/purism/librem_cml/variants/librem_mini/variant.c b/src/mainboard/purism/librem_cml/variants/librem_mini/variant.c new file mode 100644 index 0000000..aaea8a4 --- /dev/null +++ b/src/mainboard/purism/librem_cml/variants/librem_mini/variant.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <variant/variant.h> + +void variant_memory_init_params(FSP_M_CONFIG *mem_cfg) +{ + /* Enable and set SATA HSIO adjustments for ports 0 and 2 */ + mem_cfg->PchSataHsioRxGen3EqBoostMagEnable[0] = 1; + mem_cfg->PchSataHsioRxGen3EqBoostMag[0] = 2; + mem_cfg->PchSataHsioRxGen3EqBoostMagEnable[2] = 1; + mem_cfg->PchSataHsioRxGen3EqBoostMag[2] = 1; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/46984 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I856bb914941211cfbec4fed871ba2a5a038e23c3 Gerrit-Change-Number: 46984 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/purism/librem_mini: Fix USB_OC mapping in devicetree
by Matt DeVillier (Code Review) Nov. 8, 2020

Nov. 8, 2020

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47222 ) Change subject: mb/purism/librem_mini: Fix USB_OC mapping in devicetree ...................................................................... mb/purism/librem_mini: Fix USB_OC mapping in devicetree Correct USB over-current mappings in devicetree now that the GPIO config has been fixed per schematics. Change-Id: I564630231933c7c17a2c0a2a403fdcca9189b92e Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm> --- M src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb 1 file changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/47222/1 diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb index 267e408..c13ba1b 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb @@ -146,16 +146,16 @@ end end end - register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front left upper - register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front left lower + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-A front left upper + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Type-A front left lower register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A rear upper - register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front right lower - register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front right upper + register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" # Type-A front right lower + register "usb2_ports[4]" = "USB2_PORT_MID(OC1)" # Type-A front right upper register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC3)" # Type-C rear register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # m.2-2230/Bluetooth register "usb2_ports[9]" = "USB2_PORT_MID(OC2)" # Type-A rear lower - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A front left upper - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A front left lower + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-A front left upper + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Type-A front left lower register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-C rear register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" # Type-A rear lower register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC2)" # Type-A rear upper -- To view, visit https://review.coreboot.org/c/coreboot/+/47222 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I564630231933c7c17a2c0a2a403fdcca9189b92e Gerrit-Change-Number: 47222 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/purism/librem_mini: drop PcieRpSlotImplemented from LAN PCIe
by Matt DeVillier (Code Review) Nov. 8, 2020

Nov. 8, 2020

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47252 ) Change subject: mb/purism/librem_mini: drop PcieRpSlotImplemented from LAN PCIe ...................................................................... mb/purism/librem_mini: drop PcieRpSlotImplemented from LAN PCIe The LAN NIC is onboard, not installed in a slot. Change-Id: I77ee7ee8c944b7942ca78d35cd881277c4030ab9 Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm> --- M src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/47252/1 diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb index 1a1c466..9b231a8 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb @@ -202,7 +202,6 @@ device pci 1d.0 off end # PCI Express Port 9 device pci 1d.1 on # PCI Express Port 10 device pci 00.0 on end # x1 (LAN) - register "PcieRpSlotImplemented[9]" = "1" register "PcieRpEnable[9]" = "1" register "PcieClkSrcUsage[3]" = "9" register "PcieClkSrcClkReq[3]" = "3" -- To view, visit https://review.coreboot.org/c/coreboot/+/47252 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I77ee7ee8c944b7942ca78d35cd881277c4030ab9 Gerrit-Change-Number: 47252 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/purism/librem_mini: Update smbios_slot_desc for M.2/WLAN
by Matt DeVillier (Code Review) Nov. 8, 2020

Nov. 8, 2020

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47251 ) Change subject: mb/purism/librem_mini: Update smbios_slot_desc for M.2/WLAN ...................................................................... mb/purism/librem_mini: Update smbios_slot_desc for M.2/WLAN Add strings for M.2 keying and number of PCIe lanes. Change-Id: I2e13749b50263ee5c2388a419bc8d784af6bd880 Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm> --- M src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/47251/1 diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb index e02586c..1a1c466 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb @@ -197,7 +197,7 @@ register "PcieRpLtrEnable[7]" = "1" # ClkSrcUsage must be set to free-run since SRCCLKREQ2 is NC register "PcieClkSrcUsage[2]" = "0x80" - smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (WLAN)" "SlotDataBusWidth1X" end device pci 1d.0 off end # PCI Express Port 9 device pci 1d.1 on # PCI Express Port 10 -- To view, visit https://review.coreboot.org/c/coreboot/+/47251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e13749b50263ee5c2388a419bc8d784af6bd880 Gerrit-Change-Number: 47251 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/purism/librem_mini: Fix PCIe clock source mapping in devicetree
by Matt DeVillier (Code Review) Nov. 8, 2020

Nov. 8, 2020

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47221 ) Change subject: mb/purism/librem_mini: Fix PCIe clock source mapping in devicetree ...................................................................... mb/purism/librem_mini: Fix PCIe clock source mapping in devicetree Correct PCIe clock source mapping in devicetree now that the GPIO config has been fixed. Move ClkSrcUsage/ClkSrcClkReq registers under their associated PCIe root ports. Change-Id: Ibdaba51d971a39a6da6df82652b7420d7324dee5 Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm> --- M src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb 1 file changed, 7 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/47221/1 diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb index 9fde5e9..267e408 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb @@ -19,22 +19,6 @@ # FSP Silicon (soc/intel/cannonlake/fsp_params.c) - # All SRCCLKREQ pins mapped directly - register "PcieClkSrcClkReq[0]" = "0" - register "PcieClkSrcClkReq[1]" = "1" - register "PcieClkSrcClkReq[2]" = "2" - register "PcieClkSrcClkReq[3]" = "3" - register "PcieClkSrcClkReq[4]" = "4" - register "PcieClkSrcClkReq[5]" = "5" - - # Set all SRCCLKREQ pins as free-use - register "PcieClkSrcUsage[0]" = "0x80" - register "PcieClkSrcUsage[1]" = "0x80" - register "PcieClkSrcUsage[2]" = "0x80" - register "PcieClkSrcUsage[3]" = "0x80" - register "PcieClkSrcUsage[4]" = "0x80" - register "PcieClkSrcUsage[5]" = "0x80" - # Misc register "AcousticNoiseMitigation" = "1" @@ -211,6 +195,9 @@ register "PcieRpSlotImplemented[7]" = "1" register "PcieRpEnable[7]" = "1" register "PcieRpLtrEnable[7]" = "1" + # ClkSrcUsage must be set to free-run or module not detected + register "PcieClkSrcUsage[2]" = "0x80" + register "PcieClkSrcClkReq[2]" = "2" smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" end device pci 1d.0 off end # PCI Express Port 9 @@ -218,6 +205,8 @@ device pci 00.0 on end # x1 (LAN) register "PcieRpSlotImplemented[9]" = "1" register "PcieRpEnable[9]" = "1" + register "PcieClkSrcUsage[3]" = "9" + register "PcieClkSrcClkReq[3]" = "3" end device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 @@ -226,6 +215,8 @@ register "PcieRpSlotImplemented[12]" = "1" register "PcieRpEnable[12]" = "1" register "PcieRpLtrEnable[12]" = "1" + register "PcieClkSrcUsage[1]" = "12" + register "PcieClkSrcClkReq[1]" = "1" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X" end device pci 1d.5 off end # PCI Express Port 14 -- To view, visit https://review.coreboot.org/c/coreboot/+/47221 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdaba51d971a39a6da6df82652b7420d7324dee5 Gerrit-Change-Number: 47221 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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