coreboot-gerrit October 2020

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Change in coreboot[master]: mrc_cache: Add data_size parameter to mrc_cache_load_current
by Shelley Chen (Code Review) 09 Oct '20

09 Oct '20

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46110 ) Change subject: mrc_cache: Add data_size parameter to mrc_cache_load_current ...................................................................... mrc_cache: Add data_size parameter to mrc_cache_load_current Add parameter so that caller will know what the actual size of the data returned is. This is needed for ARM devices like trogdor, which need to know the size of the training data when populating the QcLib interface table. BUG=b:150502246 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_NAMI -x -a Change-Id: Ia314717ad2a7d5232b37a19951c1aecd7f843c27 Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/drivers/mrc_cache/mrc_cache.c M src/include/mrc_cache.h 2 files changed, 7 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/46110/1 diff --git a/src/drivers/mrc_cache/mrc_cache.c b/src/drivers/mrc_cache/mrc_cache.c index d2991ac..ded3181 100644 --- a/src/drivers/mrc_cache/mrc_cache.c +++ b/src/drivers/mrc_cache/mrc_cache.c @@ -261,23 +261,23 @@ } int mrc_cache_load_current(int type, uint32_t version, void *buffer, - size_t buffer_size) + size_t buffer_size, size_t *data_size) { struct region_device rdev; struct mrc_metadata md; - size_t data_size; + size_t dsize; if (mrc_cache_find_current(type, version, &rdev, &md) < 0) return -1; - data_size = region_device_sz(&rdev); - if (buffer_size < data_size) + *data_size = dsize = region_device_sz(&rdev); + if (buffer_size < dsize) return -1; - if (rdev_readat(&rdev, buffer, 0, data_size) != data_size) + if (rdev_readat(&rdev, buffer, 0, dsize) != dsize) return -1; - if (mrc_data_valid(&md, buffer, data_size) < 0) + if (mrc_data_valid(&md, buffer, dsize) < 0) return -1; return 0; diff --git a/src/include/mrc_cache.h b/src/include/mrc_cache.h index da2bf79..cb713a1 100644 --- a/src/include/mrc_cache.h +++ b/src/include/mrc_cache.h @@ -31,7 +31,7 @@ * success. */ int mrc_cache_load_current(int type, uint32_t version, void *buffer, - size_t buffer_size); + size_t buffer_size, size_t *data_size); /** * mrc_cache_mmap_leak * -- To view, visit https://review.coreboot.org/c/coreboot/+/46110 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia314717ad2a7d5232b37a19951c1aecd7f843c27 Gerrit-Change-Number: 46110 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/jasperlake: Correct SaGv mapping
by Meera Ravindranath (Code Review) 09 Oct '20

09 Oct '20

Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45195 ) Change subject: soc/intel/jasperlake: Correct SaGv mapping ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/45195 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I366de1ea7cf41c56b2954b8032c69bfba81058e2 Gerrit-Change-Number: 45195 Gerrit-PatchSet: 2 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Comment-Date: Fri, 09 Oct 2020 03:44:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: src/lib/cbfs: Remove unused macro
by HAOUAS Elyes (Code Review) 09 Oct '20

09 Oct '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41781 ) Change subject: src/lib/cbfs: Remove unused macro ...................................................................... src/lib/cbfs: Remove unused macro Change-Id: I1efdb6355bec6f680e0fb1a4f4e19db93b3739a2 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/lib/cbfs.c 1 file changed, 0 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/41781/1 diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index a3294de..92a6fed 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -17,11 +17,6 @@ #define ERROR(x...) printk(BIOS_ERR, "CBFS: " x) #define LOG(x...) printk(BIOS_INFO, "CBFS: " x) -#if CONFIG(DEBUG_CBFS) -#define DEBUG(x...) printk(BIOS_SPEW, "CBFS: " x) -#else -#define DEBUG(x...) -#endif int cbfs_boot_locate(struct cbfsf *fh, const char *name, uint32_t *type) { -- To view, visit https://review.coreboot.org/c/coreboot/+/41781 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1efdb6355bec6f680e0fb1a4f4e19db93b3739a2 Gerrit-Change-Number: 41781 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork/berknip: Increase eMMC initial clock frequency
by Rob Barnes (Code Review) 09 Oct '20

09 Oct '20

Rob Barnes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45931 ) Change subject: mb/google/zork/berknip: Increase eMMC initial clock frequency ...................................................................... mb/google/zork/berknip: Increase eMMC initial clock frequency This will reduce boot time by 7ms. Some of the initial designs don't have a pull-up resistor on the CMD line. These designs still boot at 400 kHz despite not having the pull-up. BUG=b:158766134 TEST=Boot Berknip w/ eMMC to OS. Change-Id: I5d55f55b8208b4dc3fbdc9d1ec6333f9e211e3fd Signed-off-by: Rob Barnes <robbarnes(a)google.com> --- M src/mainboard/google/zork/variants/berknip/overridetree.cb 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/45931/1 diff --git a/src/mainboard/google/zork/variants/berknip/overridetree.cb b/src/mainboard/google/zork/variants/berknip/overridetree.cb index 9562939..674d557 100644 --- a/src/mainboard/google/zork/variants/berknip/overridetree.cb +++ b/src/mainboard/google/zork/variants/berknip/overridetree.cb @@ -38,6 +38,12 @@ .early_init = true, }" + register "emmc_config" = "{ + .timing = SD_EMMC_EMMC_HS400, + .sdr104_hs400_driver_strength = SD_EMMC_DRIVE_STRENGTH_A, + .init_khz_preset = 400, + }" + # See AMD 55570-B1 Table 13: PCI Device ID Assignments. device domain 0 on subsystemid 0x1022 0x1510 inherit -- To view, visit https://review.coreboot.org/c/coreboot/+/45931 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5d55f55b8208b4dc3fbdc9d1ec6333f9e211e3fd Gerrit-Change-Number: 45931 Gerrit-PatchSet: 1 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: zork/var/ezkinil: Add micron-MT40A1G16KD-062E-E in SPD table for Ezki...
by Lucas Chen (Code Review) 09 Oct '20

09 Oct '20

Lucas Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45810 ) Change subject: zork/var/ezkinil: Add micron-MT40A1G16KD-062E-E in SPD table for Ezkinil. ...................................................................... zork/var/ezkinil: Add micron-MT40A1G16KD-062E-E in SPD table for Ezkinil. Current Ram_Id: 0011 MT40A1G16KNR-075-E never be built before. Remove it and change use micron-MT40A1G16KD-062E-E for ram_id:0011. BRANCH=zork BUG=b:159316110 TEST=run gen_part_id then check the generated files. Signed-off-by: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Change-Id: I28fc39f17e06ecd39f6567613e6ff5919becb2fd --- M src/mainboard/google/zork/variants/ezkinil/spd/Makefile.inc M src/mainboard/google/zork/variants/ezkinil/spd/dram_id.generated.txt M src/mainboard/google/zork/variants/ezkinil/spd/mem_parts_used.txt 3 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/45810/1 diff --git a/src/mainboard/google/zork/variants/ezkinil/spd/Makefile.inc b/src/mainboard/google/zork/variants/ezkinil/spd/Makefile.inc index 65eb7b0..12e7fa9 100644 --- a/src/mainboard/google/zork/variants/ezkinil/spd/Makefile.inc +++ b/src/mainboard/google/zork/variants/ezkinil/spd/Makefile.inc @@ -3,7 +3,7 @@ SPD_SOURCES = SPD_SOURCES += ddr4-spd-3.hex # ID = 0(0b0000) Parts = H5AN8G6NCJR-VKC -SPD_SOURCES += ddr4-spd-empty.hex # ID = 1(0b0001) +SPD_SOURCES += ddr4-spd-empty.bin # ID = 1(0b0001) SPD_SOURCES += ddr4-spd-1.hex # ID = 2(0b0010) Parts = MT40A512M16TB-062E:J -SPD_SOURCES += ddr4-spd-4.hex # ID = 3(0b0011) Parts = MT40A1G16KNR-075:E +SPD_SOURCES += ddr4-spd-7.hex # ID = 3(0b0011) Parts = MT40A1G16KD-062E:E SPD_SOURCES += ddr4-spd-3.hex # ID = 4(0b0100) Parts = K4A8G165WC-BCTD diff --git a/src/mainboard/google/zork/variants/ezkinil/spd/dram_id.generated.txt b/src/mainboard/google/zork/variants/ezkinil/spd/dram_id.generated.txt index 99072f6..7e54cc1 100644 --- a/src/mainboard/google/zork/variants/ezkinil/spd/dram_id.generated.txt +++ b/src/mainboard/google/zork/variants/ezkinil/spd/dram_id.generated.txt @@ -1,5 +1,5 @@ DRAM Part Name ID to assign H5AN8G6NCJR-VKC 0 (0000) MT40A512M16TB-062E:J 2 (0010) -MT40A1G16KNR-075:E 3 (0011) +MT40A1G16KD-062E:E 3 (0011) K4A8G165WC-BCTD 4 (0100) diff --git a/src/mainboard/google/zork/variants/ezkinil/spd/mem_parts_used.txt b/src/mainboard/google/zork/variants/ezkinil/spd/mem_parts_used.txt index a9994a3..b4b1601 100644 --- a/src/mainboard/google/zork/variants/ezkinil/spd/mem_parts_used.txt +++ b/src/mainboard/google/zork/variants/ezkinil/spd/mem_parts_used.txt @@ -9,5 +9,5 @@ # Part Name, Fixed ID (optional) H5AN8G6NCJR-VKC,0 MT40A512M16TB-062E:J,2 -MT40A1G16KNR-075:E, 3 +MT40A1G16KD-062E:E,3 K4A8G165WC-BCTD,4 -- To view, visit https://review.coreboot.org/c/coreboot/+/45810 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28fc39f17e06ecd39f6567613e6ff5919becb2fd Gerrit-Change-Number: 45810 Gerrit-PatchSet: 1 Gerrit-Owner: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork/ezkinil: Increase eMMC initial clock frequency
by Raul Rangel (Code Review) 09 Oct '20

09 Oct '20

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45852 ) Change subject: mb/google/zork/ezkinil: Increase eMMC initial clock frequency ...................................................................... mb/google/zork/ezkinil: Increase eMMC initial clock frequency This will reduce boot time by over 30ms. Some of the initial designs don't have a pull-up resistor on the CMD line. These designs still boot at 400 kHz despite not having the pull-up. BUG=b:158766134 TEST=Boot Ezkinil w/ eMMC to OS. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ida0bbf9bd772ab7d384d5d097fa3b02b846a3efa --- M src/mainboard/google/zork/variants/ezkinil/overridetree.cb 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/45852/1 diff --git a/src/mainboard/google/zork/variants/ezkinil/overridetree.cb b/src/mainboard/google/zork/variants/ezkinil/overridetree.cb index 614d6ab..b0204de 100644 --- a/src/mainboard/google/zork/variants/ezkinil/overridetree.cb +++ b/src/mainboard/google/zork/variants/ezkinil/overridetree.cb @@ -39,6 +39,12 @@ .early_init = true, }" + register "emmc_config" = "{ + .timing = SD_EMMC_EMMC_HS400, + .sdr104_hs400_driver_strength = SD_EMMC_DRIVE_STRENGTH_A, + .init_khz_preset = 400, + }" + # See AMD 55570-B1 Table 13: PCI Device ID Assignments. device domain 0 on subsystemid 0x1022 0x1510 inherit -- To view, visit https://review.coreboot.org/c/coreboot/+/45852 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida0bbf9bd772ab7d384d5d097fa3b02b846a3efa Gerrit-Change-Number: 45852 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork/morphius: Increase eMMC initial clock frequency
by Rob Barnes (Code Review) 09 Oct '20

09 Oct '20

Rob Barnes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45932 ) Change subject: mb/google/zork/morphius: Increase eMMC initial clock frequency ...................................................................... mb/google/zork/morphius: Increase eMMC initial clock frequency This will reduce boot time by 7ms. Some of the initial designs don't have a pull-up resistor on the CMD line. These designs still boot at 400 kHz despite not having the pull-up. BUG=b:158766134 TEST=WIP Signed-off-by: Rob Barnes <robbarnes(a)google.com> Change-Id: I7f6efd3d5839f154f2487a07654be8e35634bbbc --- M src/mainboard/google/zork/variants/morphius/overridetree.cb 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/45932/1 diff --git a/src/mainboard/google/zork/variants/morphius/overridetree.cb b/src/mainboard/google/zork/variants/morphius/overridetree.cb index 3ba7851..bb92d7d 100644 --- a/src/mainboard/google/zork/variants/morphius/overridetree.cb +++ b/src/mainboard/google/zork/variants/morphius/overridetree.cb @@ -45,6 +45,12 @@ .early_init = true, }" + register "emmc_config" = "{ + .timing = SD_EMMC_EMMC_HS400, + .sdr104_hs400_driver_strength = SD_EMMC_DRIVE_STRENGTH_A, + .init_khz_preset = 400, + }" + # See AMD 55570-B1 Table 13: PCI Device ID Assignments. device domain 0 on subsystemid 0x1022 0x1510 inherit -- To view, visit https://review.coreboot.org/c/coreboot/+/45932 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f6efd3d5839f154f2487a07654be8e35634bbbc Gerrit-Change-Number: 45932 Gerrit-PatchSet: 1 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/i2c: Add chip driver for GPIO based I2C multiplexer
by Evan Green (Code Review) 08 Oct '20

08 Oct '20

Evan Green has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45911 ) Change subject: drivers/i2c: Add chip driver for GPIO based I2C multiplexer ...................................................................... Patch Set 6: (1 comment) https://review.coreboot.org/c/coreboot/+/45911/6/src/drivers/i2c/gpiomux/mu… File src/drivers/i2c/gpiomux/mux/mux.c: https://review.coreboot.org/c/coreboot/+/45911/6/src/drivers/i2c/gpiomux/mu… PS6, Line 37: "_HID", ACPI_DT_NAMESPACE_HID) > Would this be applicable: https://www.kernel. […] Thanks for the link. That makes sense to me, and the documentation link is something I can point at in the upstream reviews to defend against i2c-parent property comments. Thanks! -- To view, visit https://review.coreboot.org/c/coreboot/+/45911 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib371108cc6043c133681066bf7bf4b2e00771e8b Gerrit-Change-Number: 45911 Gerrit-PatchSet: 6 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 08 Oct 2020 21:17:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Evan Green <evgreen(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: Configure L1 substates for PCH root ports
by Nico Huber (Code Review) 08 Oct '20

08 Oct '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39538 ) Change subject: soc/intel/skylake: Configure L1 substates for PCH root ports ...................................................................... Patch Set 25: > > > Do you think that L1 substates should be guarded by that Kconfig? > > > > it wouldn't hurt to add 'CONFIG(PCIEXP_L1_SUB_STATE) &&' to the front of the if statement > > That's not the config that I meant. As Nico said, coreboot can enable L1 substates if the FSP says that it's capable. We can use this UPD to get finer-grained control over which devices have L1SS enabled. This may be useful if, for example, only one devices misbehaves with L1SS. In other words, as I understand it, "PCIEXP_L1_SUB_STATE" depends on the FSP UPD (per root-port). > > > One dependency for L1 substates is clock PM > > Should L1SS be guarded by PCIEXP_CLK_PM? It's all a bit foggy as these Kconfigs don't directly reflect hardware state. PCIEXP_CLK_PM makes us enable a feature in the downstream device of a link. This needs a working clock request signal. Same with L1SS (but this also checks support in the upstream device). But L1SS doesn't depend on the other feature. What we'd probably need would be a Kconfig that says ASSUME_CLK_REQ_SIGNALS, that would be something to depend on. But I don't think it's worth the trouble. Also, would be much nicer to directly tag links in the devicetree to have clock request signals. Now if FSP does the right thing if we say a port supports L1SS but no ASPM is a different story. But I don't expect any trouble if it doesn't filter the case, L1SS would just not work, I guess. Btw. there won't be a +2 from me as long as there is the confusing CamelCase thing (same option name as FSP but with different encoding). But I'm not blocking it. -- To view, visit https://review.coreboot.org/c/coreboot/+/39538 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36150858485715016158595c832c142b0582ddb8 Gerrit-Change-Number: 39538 Gerrit-PatchSet: 25 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 08 Oct 2020 20:57:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: device: Clarify use of `config_of()`
by Nico Huber (Code Review) 08 Oct '20

08 Oct '20

Hello Angel Pons, Werner Zeh, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46046 to review the following change. Change subject: device: Clarify use of `config_of()` ...................................................................... device: Clarify use of `config_of()` We don't want unnecessary die() calls to spread throughout coreboot. Chances are high that we'd add a NON_FATAL_DIE Kconfig eventually. Change-Id: I01c7efdf23672bad3a195b7dc1565a3cc8a087bd Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/include/device/device.h 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/46046/1 diff --git a/src/include/device/device.h b/src/include/device/device.h index b53b64a..031091a 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -339,6 +339,12 @@ void devtree_bug(const char *func, pci_devfn_t devfn); void __noreturn devtree_die(void); +/* + * Dies if `dev` or `dev->chip_info` are NULL. Returns `dev->chip_info` otherwise. + * + * Only use if missing `chip_info` is fatal and we can't boot. If it's + * not fatal, please handle the NULL case gracefully. + */ static inline DEVTREE_CONST void *config_of(const struct device *dev) { if (dev && dev->chip_info) -- To view, visit https://review.coreboot.org/c/coreboot/+/46046 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I01c7efdf23672bad3a195b7dc1565a3cc8a087bd Gerrit-Change-Number: 46046 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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coreboot-gerrit October 2020