coreboot-gerrit October 2020

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Change in coreboot[master]: soc/intel/cannonlake: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 09 Oct '20

09 Oct '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46239 ) Change subject: soc/intel/cannonlake: Convert to ASL 2.0 syntax ...................................................................... soc/intel/cannonlake: Convert to ASL 2.0 syntax Change-Id: Ia587ec4831fcd93d9f53aa219544c8078c360aae Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/cannonlake/acpi/gpio.asl M src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl M src/soc/intel/cannonlake/acpi/pch_hda.asl M src/soc/intel/cannonlake/acpi/scs.asl 4 files changed, 83 insertions(+), 85 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/46239/1 diff --git a/src/soc/intel/cannonlake/acpi/gpio.asl b/src/soc/intel/cannonlake/acpi/gpio.asl index f1284e1..aa74a5e 100644 --- a/src/soc/intel/cannonlake/acpi/gpio.asl +++ b/src/soc/intel/cannonlake/acpi/gpio.asl @@ -30,20 +30,20 @@ /* GPIO Community 0 */ CreateDWordField (^RBUF, ^COM0._BAS, BAS0) CreateDWordField (^RBUF, ^COM0._LEN, LEN0) - Store (^^PCRB (PID_GPIOCOM0), BAS0) - Store (GPIO_BASE_SIZE, LEN0) + BAS0 = ^^PCRB (PID_GPIOCOM0) + LEN0 = GPIO_BASE_SIZE /* GPIO Community 1 */ CreateDWordField (^RBUF, ^COM1._BAS, BAS1) CreateDWordField (^RBUF, ^COM1._LEN, LEN1) - Store (^^PCRB (PID_GPIOCOM1), BAS1) - Store (GPIO_BASE_SIZE, LEN1) + BAS1 = ^^PCRB (PID_GPIOCOM1) + LEN1 = GPIO_BASE_SIZE /* GPIO Community 4 */ CreateDWordField (^RBUF, ^COM4._BAS, BAS4) CreateDWordField (^RBUF, ^COM4._LEN, LEN4) - Store (^^PCRB (PID_GPIOCOM4), BAS4) - Store (GPIO_BASE_SIZE, LEN4) + BAS4 = ^^PCRB (PID_GPIOCOM4) + LEN4 = GPIO_BASE_SIZE Return (RBUF) } @@ -61,38 +61,38 @@ Method (GADD, 1, NotSerialized) { /* GPIO Community 0 */ - If (LAnd (LGreaterEqual (Arg0, GPP_A0), LLessEqual (Arg0, SPI0_CLK_LOOPBK))) + If ((Arg0 >= GPP_A0) && (Arg0 <= SPI0_CLK_LOOPBK)) { - Store (PID_GPIOCOM0, Local0) - Subtract (Arg0, GPP_A0, Local1) + Local0 = PID_GPIOCOM0 + Local1 = Arg0 - GPP_A0 } /* GPIO Community 1 */ - If (LAnd (LGreaterEqual (Arg0, GPP_D0), LLessEqual (Arg0, vSD3_CD_B))) + If ((Arg0 >= GPP_D0) && (Arg0 <= vSD3_CD_B)) { - Store (PID_GPIOCOM1, Local0) - Subtract (Arg0, GPP_D0, Local1) + Local0 = PID_GPIOCOM1 + Local1 = Arg0 - GPP_D0 } /* GPIO Community 2 */ - If (LAnd (LGreaterEqual (Arg0, GPD0), LLessEqual (Arg0, DRAM_RESET_B))) + If ((Arg0 >= GPD0) && (Arg0 <= DRAM_RESET_B)) { - Store (PID_GPIOCOM2, Local0) - Subtract (Arg0, GPD0, Local1) + Local0 = PID_GPIOCOM2 + Local1 = Arg0 - GPD0 } /* GPIO Community 3 */ - If (LAnd (LGreaterEqual (Arg0, HDA_BCLK), LLessEqual (Arg0, TRIGGER_OUT))) + If ((Arg0 >= HDA_BCLK) && (Arg0 <= TRIGGER_OUT)) { - Store (PID_GPIOCOM3, Local0) - Subtract (Arg0, HDA_BCLK, Local1) + Local0 = PID_GPIOCOM3 + Local1 = Arg0 - HDA_BCLK } /* GPIO Community 4*/ - If (LAnd (LGreaterEqual (Arg0, GPP_C0), LLessEqual (Arg0, CL_RST_B))) + If ((Arg0 >= GPP_C0) && (Arg0 <= CL_RST_B)) { - Store (PID_GPIOCOM4, Local0) - Subtract (Arg0, GPP_C0, Local1) + Local0 = PID_GPIOCOM4 + Local1 = Arg0 - GPP_C0 } - Store (PCRB (Local0), Local2) - Add (Local2, PAD_CFG_BASE, Local2) - Return (Add (Local2, Multiply (Local1, 16))) + Local2 = PCRB (Local0) + Local2 += PAD_CFG_BASE + Return (Local2 + (Local1 * 16)) } /* @@ -105,19 +105,19 @@ Switch (ToInteger (Arg0)) { Case (0) { - Store (PID_GPIOCOM0, Local0) + Local0 = PID_GPIOCOM0 } Case (1) { - Store (PID_GPIOCOM1, Local0) + Local0 = PID_GPIOCOM1 } Case (2) { - Store (PID_GPIOCOM2, Local0) + Local0 = PID_GPIOCOM2 } Case (3) { - Store (PID_GPIOCOM3, Local0) + Local0 = PID_GPIOCOM3 } Case (4) { - Store (PID_GPIOCOM4, Local0) + Local0 = PID_GPIOCOM4 } Default { Return (0) @@ -135,8 +135,8 @@ */ Method (CGPM, 2, Serialized) { - Store (GPID (Arg0), Local0) - If (LNotEqual (Local0, 0)) { + Local0 = GPID (Arg0) + If (Local0 != 0) { /* Mask off current PM bits */ PCRA (Local0, GPIO_MISCCFG, Not (MISCCFG_ENABLE_GPIO_PM_CONFIG)) /* Mask in requested bits */ diff --git a/src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl b/src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl index 5b3123d..f4177c1 100644 --- a/src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl +++ b/src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl @@ -30,26 +30,26 @@ /* GPIO Community 0 */ CreateDWordField (^RBUF, ^COM0._BAS, BAS0) CreateDWordField (^RBUF, ^COM0._LEN, LEN0) - Store (^^PCRB (PID_GPIOCOM0), BAS0) - Store (GPIO_BASE_SIZE, LEN0) + BAS0 = ^^PCRB (PID_GPIOCOM0) + LEN0 = GPIO_BASE_SIZE /* GPIO Community 1 */ CreateDWordField (^RBUF, ^COM1._BAS, BAS1) CreateDWordField (^RBUF, ^COM1._LEN, LEN1) - Store (^^PCRB (PID_GPIOCOM1), BAS1) - Store (GPIO_BASE_SIZE, LEN1) + BAS1 = ^^PCRB (PID_GPIOCOM1) + LEN1 = GPIO_BASE_SIZE /* GPIO Community 3 */ CreateDWordField (^RBUF, ^COM3._BAS, BAS3) CreateDWordField (^RBUF, ^COM3._LEN, LEN3) - Store (^^PCRB (PID_GPIOCOM3), BAS3) - Store (GPIO_BASE_SIZE, LEN3) + BAS3 = ^^PCRB (PID_GPIOCOM3) + LEN3 = GPIO_BASE_SIZE /* GPIO Community 4 */ CreateDWordField (^RBUF, ^COM4._BAS, BAS4) CreateDWordField (^RBUF, ^COM4._LEN, LEN4) - Store (^^PCRB (PID_GPIOCOM4), BAS4) - Store (GPIO_BASE_SIZE, LEN4) + BAS4 = ^^PCRB (PID_GPIOCOM4) + LEN4 = GPIO_BASE_SIZE Return (RBUF) } @@ -67,30 +67,30 @@ Method (GADD, 1, NotSerialized) { /* GPIO Community 0 */ - If (LAnd (LGreaterEqual (Arg0, GPP_A0), LLessEqual (Arg0, GSPI1_CLK_LOOPBK))) + If ((Arg0 >= GPP_A0) && (Arg0 <= GSPI1_CLK_LOOPBK)) { - Store (PID_GPIOCOM0, Local0) - Subtract (Arg0, GPP_A0, Local1) + Local0 = PID_GPIOCOM0 + Local1 = Arg0 - GPP_A0 } /* GPIO Community 1 */ - If (LAnd (LGreaterEqual (Arg0, GPP_C0), LLessEqual (Arg0, vSSP2_RXD))) + If ((Arg0 >= GPP_C0) && (Arg0 <= vSSP2_RXD)) { - Store (PID_GPIOCOM1, Local0) - Subtract (Arg0, GPP_C0, Local1) + Local0 = PID_GPIOCOM1 + Local1 = Arg0 - GPP_C0 } /* GPIO Community 3*/ - If (LAnd (LGreaterEqual (Arg0, GPP_K0), LLessEqual (Arg0, SPI0_CLK_LOOPBK))) + If ((Arg0 >= GPP_K0) && (Arg0 <= SPI0_CLK_LOOPBK)) { - Store (PID_GPIOCOM3, Local0) - Subtract (Arg0, GPP_K0, Local1) + Local0 = PID_GPIOCOM3 + Local1 = Arg0 - GPP_K0 } /* GPIO Community 4*/ - If (LAnd (LGreaterEqual (Arg0, HDACPU_SDI), LLessEqual (Arg0, GPP_J11))) + If ((Arg0 >= HDACPU_SDI) && (Arg0 <= GPP_J11)) { - Store (PID_GPIOCOM4, Local0) - Subtract (Arg0, GPP_I0, Local1) + Local0 = PID_GPIOCOM4 + Local1 = Arg0 - GPP_I0 } - Store (PCRB (Local0), Local2) - Add (Local2, PAD_CFG_BASE, Local2) - Return (Add (Local2, Multiply (Local1, 16))) + Local2 = PCRB (Local0) + Local2 += PAD_CFG_BASE + Return (Local2 + (Local1 * 16)) } diff --git a/src/soc/intel/cannonlake/acpi/pch_hda.asl b/src/soc/intel/cannonlake/acpi/pch_hda.asl index 04e974f..3de64b7 100644 --- a/src/soc/intel/cannonlake/acpi/pch_hda.asl +++ b/src/soc/intel/cannonlake/acpi/pch_hda.asl @@ -26,19 +26,17 @@ */ Method (_DSM, 4) { - If (LEqual (Arg0, ^UUID)) { + If (Arg0 == ^UUID) { /* * Function 0: Function Support Query * Returns a bitmask of functions supported. */ - If (LEqual (Arg2, Zero)) { + If (Arg2 == 0) { /* * NHLT Query only supported for revision 1 and * if NHLT address and length are set in NVS. */ - If (LAnd (LEqual (Arg1, One), - LAnd (LNotEqual (NHLA, Zero), - LNotEqual (NHLL, Zero)))) { + If ((Arg1 == 1) && (NHLA != 0) && (NHLL != 0)) { Return (Buffer (One) { 0x03 }) } Else { Return (Buffer (One) { 0x01 }) @@ -52,14 +50,14 @@ * * Returns a pointer to NHLT table in memory. */ - If (LEqual (Arg2, One)) { + If (Arg2 == 1) { CreateQWordField (NBUF, ^NHLT._MIN, NBAS) CreateQWordField (NBUF, ^NHLT._MAX, NMAS) CreateQWordField (NBUF, ^NHLT._LEN, NLEN) - Store (NHLA, NBAS) - Store (NHLA, NMAS) - Store (NHLL, NLEN) + NBAS = NHLA + NMAS = NHLA + NLEN = NHLL Return (NBUF) } diff --git a/src/soc/intel/cannonlake/acpi/scs.asl b/src/soc/intel/cannonlake/acpi/scs.asl index 8e1de1e..dd8d4cb 100644 --- a/src/soc/intel/cannonlake/acpi/scs.asl +++ b/src/soc/intel/cannonlake/acpi/scs.asl @@ -40,22 +40,22 @@ Method(_PS0, 0, Serialized) { Stall (50) // Sleep 50 us - Store(0, PGEN) // Disable PG + PGEN = 0 // Disable PG /* Clear register 0x1C20/0x4820 */ ^^SCSC (PID_EMMC) /* Set Power State to D0 */ - And (PMCR, 0xFFFC, PMCR) - Store (PMCR, ^TEMP) + PMCR &= 0xFFFC + ^TEMP = PMCR } Method(_PS3, 0, Serialized) { - Store(1, PGEN) // Enable PG + PGEN = 1 // Enable PG /* Set Power State to D3 */ - Or (PMCR, 0x0003, PMCR) - Store (PMCR, ^TEMP) + PMCR |= 0x0003 + ^TEMP = PMCR } Device (CARD) @@ -74,9 +74,9 @@ */ Method (_DSM, 4) { - If (LEqual (Arg0, ^DSUU)) { + If (Arg0 == ^DSUU) { /* Check the revision */ - If (LGreaterEqual (Arg1, Zero)) { + If (Arg1 >= 0) { /* * Function Index 0 the return value is a buffer * containing one bit for each function index, starting @@ -93,8 +93,8 @@ * Bit 6 - Indicates support for HS400 mode * Bit 9 - Indicates eMMC I/O Driver Strength */ - If (LEqual (Arg2, Zero)) { - If (Lequal (VDID, 0x02c48086) ) { + If (Arg2 == 0) { + If (VDID == 0x02c48086) { /* * Set bit 9 for CML eMMC to indicate * eMMC I/O driver strength is supported @@ -112,7 +112,7 @@ * 3 - 100 ohm * 4 - 40 ohm */ - If (LEqual (Arg2, 9)) { + If ((Arg2 == 9) { Return(Buffer() {0x4}) } } @@ -147,9 +147,9 @@ */ Method (_DSM, 4) { - If (LEqual (Arg0, ^DSUU)) { + If (Arg0 == ^DSUU) { /* Check the revision */ - If (LGreaterEqual (Arg1, Zero)) { + If (Arg1 >= 0) { /* * Function Index 0 the return value is a buffer containing * one bit for each function index, starting with zero. @@ -166,7 +166,7 @@ * For SD we have to support functions to * set 1.8V signalling and 3.3V signalling [BIT4, BIT3] */ - If (LEqual (Arg2, Zero)) { + If (Arg2 == 0) { Return (Buffer () { 0x19 }) } /* @@ -176,7 +176,7 @@ * UHS SD card on PCH. This is to compensate * for the SD VR slowness. */ - If (LEqual (Arg2, 3)) { + If (Arg2 == 3) { Sleep (100) Return(Buffer () { 0x00 }) } @@ -187,7 +187,7 @@ * UHS SD card on PCH. This is to compensate * for the SD VR slowness. */ - If (LEqual (Arg2, 4)) { + If (Arg2 == 4) { Sleep (100) Return(Buffer () { 0x00 }) } @@ -204,14 +204,14 @@ Method (_PS0, 0, Serialized) { - Store (0, PGEN) /* Disable PG */ + PGEN = 0 /* Disable PG */ /* Clear register 0x1C20/0x4820 */ ^^SCSC (PID_SDX) /* Set Power State to D0 */ - And (PMCR, 0xFFFC, PMCR) - Store (PMCR, ^TEMP) + PMCR &= 0xFFFC + ^TEMP = PMCR #if CONFIG(MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE) /* Change pad mode to Native */ @@ -221,11 +221,11 @@ Method (_PS3, 0, Serialized) { - Store (1, PGEN) /* Enable PG */ + PGEN = 1 /* Enable PG */ /* Set Power State to D3 */ - Or (PMCR, 0x0003, PMCR) - Store (PMCR, ^TEMP) + PMCR |= 0x0003 + ^TEMP = PMCR #if CONFIG(MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE) /* Change pad mode to GPIO control */ -- To view, visit https://review.coreboot.org/c/coreboot/+/46239 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia587ec4831fcd93d9f53aa219544c8078c360aae Gerrit-Change-Number: 46239 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: mb/google/dedede: Override GPIO PM configuration
by Karthik Ramasubramanian (Code Review) 09 Oct '20

09 Oct '20

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45857 ) Change subject: mb/google/dedede: Override GPIO PM configuration ...................................................................... mb/google/dedede: Override GPIO PM configuration If Cr50 is running old firmware version and hence does not ensure long interrupt pulses, override the GPIO PM configuration. BUG=None TEST=Build and boot waddledee to OS. Ensure that the suspend/resume sequence works fine. Change-Id: I455c51d4a63b1b5edadbf00c786ce61b0ba1ff00 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/dedede/mainboard.c M src/mainboard/google/dedede/variants/baseboard/devicetree.cb 2 files changed, 20 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/45857/1 diff --git a/src/mainboard/google/dedede/mainboard.c b/src/mainboard/google/dedede/mainboard.c index cb84e1f..150076f 100644 --- a/src/mainboard/google/dedede/mainboard.c +++ b/src/mainboard/google/dedede/mainboard.c @@ -4,9 +4,29 @@ #include <bootstate.h> #include <baseboard/variants.h> #include <device/device.h> +#include <drivers/spi/tpm/tpm.h> #include <ec/ec.h> +#include <security/tpm/tss.h> +#include <soc/ramstage.h> #include <vendorcode/google/chromeos/chromeos.h> +void mainboard_update_soc_chip_config(struct soc_intel_jasperlake_config *cfg) +{ + int ret; + ret = tlcl_lib_init(); + if (ret != VB2_SUCCESS) { + printk(BIOS_ERR, "tlcl_lib_init() failed: 0x%x\n", ret); + return; + } + + if (!cr50_is_long_interrupt_pulse_enabled()) { + /* Disable GPIO PM to allow for shorter IRQ pulses */ + printk(BIOS_INFO, "Override GPIO PM\n"); + cfg->gpio_override_pm = 1; + memset(cfg->gpio_pm, 0, sizeof(cfg->gpio_pm)); + } +} + __weak void variant_isst_override(void) { /* diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 1f72eb1..3ced742 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -129,14 +129,6 @@ # Select eDP for port A register "DdiPortAConfig" = "1" - # Disable PM to allow for shorter irq pulses - register "gpio_override_pm" = "1" - register "gpio_pm[0]" = "0" - register "gpio_pm[1]" = "0" - register "gpio_pm[2]" = "0" - register "gpio_pm[3]" = "0" - register "gpio_pm[4]" = "0" - # Enable HPD for DDI ports B/C register "DdiPortBHpd" = "1" register "DdiPortCHpd" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/45857 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I455c51d4a63b1b5edadbf00c786ce61b0ba1ff00 Gerrit-Change-Number: 45857 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

4 14

Change in coreboot[master]: mb/google/octopus: Disable Ambient Light Sensor (ALS)
by Karthik Ramasubramanian (Code Review) 09 Oct '20

09 Oct '20

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45741 ) Change subject: mb/google/octopus: Disable Ambient Light Sensor (ALS) ...................................................................... mb/google/octopus: Disable Ambient Light Sensor (ALS) ALS is not stuffed in octopus boards. Hence disable ALS ACPI devices. BUG=b:169245831 TEST=Ensure that ALS devices are disabled in ACPI tables. Change-Id: I5ad28f01b0515a41b314116eb2d05c520df0f86e Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/octopus/variants/baseboard/include/baseboard/ec.h 1 file changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/45741/1 diff --git a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/ec.h index ecc9355..fa86170f 100644 --- a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/ec.h @@ -54,9 +54,6 @@ * ACPI related definitions for ASL code. */ -/* Enable EC backed ALS device in ACPI */ -#define EC_ENABLE_ALS_DEVICE - /* Enable LID switch and provide wake pin for EC */ #define EC_ENABLE_LID_SWITCH #define EC_ENABLE_WAKE_PIN GPE_EC_WAKE -- To view, visit https://review.coreboot.org/c/coreboot/+/45741 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ad28f01b0515a41b314116eb2d05c520df0f86e Gerrit-Change-Number: 45741 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: mb/google/dedede: Enable SaGv support
by Karthik Ramasubramanian (Code Review) 09 Oct '20

09 Oct '20

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45196 ) Change subject: mb/google/dedede: Enable SaGv support ...................................................................... Patch Set 3: (2 comments) https://review.coreboot.org/c/coreboot/+/45196/2//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/45196/2//COMMIT_MSG@7 PS2, Line 7: intel/ > google Done https://review.coreboot.org/c/coreboot/+/45196/2//COMMIT_MSG@8 PS2, Line 8: > Can you please mention if there is a bug and any tests performed. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/45196 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f60aad031ce9dfe23e54426753311c35db46c05 Gerrit-Change-Number: 45196 Gerrit-PatchSet: 3 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 09 Oct 2020 14:39:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/dedede: Enable SaGv support
by Karthik Ramasubramanian (Code Review) 09 Oct '20

09 Oct '20

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45196 ) Change subject: mb/google/dedede: Enable SaGv support ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/45196 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f60aad031ce9dfe23e54426753311c35db46c05 Gerrit-Change-Number: 45196 Gerrit-PatchSet: 3 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 09 Oct 2020 14:38:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/skylake: Configure L1 substates for PCH root ports
by Benjamin Doron (Code Review) 09 Oct '20

09 Oct '20

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39538 ) Change subject: soc/intel/skylake: Configure L1 substates for PCH root ports ...................................................................... Patch Set 25: (1 comment) https://review.coreboot.org/c/coreboot/+/39538/14/src/soc/intel/skylake/chi… File src/soc/intel/skylake/chip.h: https://review.coreboot.org/c/coreboot/+/39538/14/src/soc/intel/skylake/chi… PS14, Line 286: PcieRpAspm > > I see the issue. In your opinion, should they be renamed? […] Not done. -- To view, visit https://review.coreboot.org/c/coreboot/+/39538 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36150858485715016158595c832c142b0582ddb8 Gerrit-Change-Number: 39538 Gerrit-PatchSet: 25 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 09 Oct 2020 14:10:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/dedede: Enable SaGv support
by Aamir Bohra (Code Review) 09 Oct '20

09 Oct '20

Hello Maulik V Vaghela, Meera Ravindranath, Krishna P Bhat D, Tim Wawrzynczak, Ronak Kanabar, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45196 to look at the new patch set (#3). Change subject: mb/google/dedede: Enable SaGv support ...................................................................... mb/google/dedede: Enable SaGv support Allow MRC training in SaGv low , mid and high frequencies. TEST=Verify memory trains at low , mid and high SaGv point through FSP debug logs enabled. Change-Id: I0f60aad031ce9dfe23e54426753311c35db46c05 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/45196/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/45196 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f60aad031ce9dfe23e54426753311c35db46c05 Gerrit-Change-Number: 45196 Gerrit-PatchSet: 3 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/tigerlake: log the memory part name
by Nick Vaccaro (Code Review) 09 Oct '20

09 Oct '20

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45459 ) Change subject: soc/intel/tigerlake: log the memory part name ...................................................................... soc/intel/tigerlake: log the memory part name THe BIOS log was looking in the spd data for the part name, but part names are stripped from generic SPDs. In those cases, devices define their DRAM Part Name in the CBI, which can be retrieved by calling mainboard_get_dram_part_num(). Add a spd_set_name() call to the spd library to allow logging the memory part name in cases where the name does not exist in the actual SPD data, and call it in cases where the mainboard is overriding the part name. BUG=b:168724473 TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot volteer to kernel and verify that the BIOS log shows a part name when logging SPD information: SPD: module part number is K4U6E3S4AA-MGCL Change-Id: I91971e07c450492dbb0588abd1c3c692ee0d3bb0 Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/include/spd_bin.h M src/lib/spd_bin.c M src/soc/intel/tigerlake/meminit.c 3 files changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/45459/1 diff --git a/src/include/spd_bin.h b/src/include/spd_bin.h index 11a0084..80c2e62 100644 --- a/src/include/spd_bin.h +++ b/src/include/spd_bin.h @@ -47,6 +47,7 @@ int get_spd_cbfs_rdev(struct region_device *spd_rdev, u8 spd_index); void dump_spd_info(struct spd_block *blk); void get_spd_smbus(struct spd_block *blk); +void spd_set_name(uint8_t spd[], char part_name[]); /* * get_spd_sn returns the SODIMM serial number. It only supports DDR3 and DDR4. diff --git a/src/lib/spd_bin.c b/src/lib/spd_bin.c index 3888896..78c3e98 100644 --- a/src/lib/spd_bin.c +++ b/src/lib/spd_bin.c @@ -136,8 +136,23 @@ return spd_busw[index]; } +static char *spd_dram_part_name; +static bool spd_part_name_overridden = false; +void spd_set_name(uint8_t spd[], char *part_name) +{ + spd_dram_part_name = part_name; + spd_part_name_overridden = true; +} + static void spd_get_name(const uint8_t spd[], char spd_name[], int dram_type) { + /* If memory part name is overridden, use override copy */ + if (spd_part_name_overridden) { + memcpy(spd_name, spd_dram_part_name, + strlen(spd_dram_part_name)); + return; + } + switch (dram_type) { case SPD_DRAM_DDR3: memcpy(spd_name, &spd[DDR3_SPD_PART_OFF], DDR3_SPD_PART_LEN); diff --git a/src/soc/intel/tigerlake/meminit.c b/src/soc/intel/tigerlake/meminit.c index 0c6f0b0..a027f2f 100644 --- a/src/soc/intel/tigerlake/meminit.c +++ b/src/soc/intel/tigerlake/meminit.c @@ -4,6 +4,7 @@ #include <console/console.h> #include <fsp/util.h> #include <soc/meminit.h> +#include <soc/romstage.h> #include <spd_bin.h> #include <string.h> @@ -216,6 +217,9 @@ static void read_md_spd(const struct spd_info *info, uintptr_t *data, size_t *len) { + const char *spd_name; + size_t spd_name_len; + if (info->md_spd_loc == SPD_MEMPTR) { *data = info->data_ptr; *len = info->data_len; @@ -225,6 +229,10 @@ die("Not a valid location(%d) for Memory-down SPD!\n", info->md_spd_loc); } + /* if mainboard overrides module name, use override name */ + if (mainboard_get_dram_part_num(&spd_name, &spd_name_len)) + spd_set_name((uint8_t *) *data, (char *) spd_name); + print_spd_info((uint8_t *) *data); } -- To view, visit https://review.coreboot.org/c/coreboot/+/45459 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I91971e07c450492dbb0588abd1c3c692ee0d3bb0 Gerrit-Change-Number: 45459 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newchange

5 87

Change in coreboot[master]: mb/google/jecht: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 09 Oct '20

09 Oct '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46174 ) Change subject: mb/google/jecht: Convert to ASL 2.0 syntax ...................................................................... mb/google/jecht: Convert to ASL 2.0 syntax Change-Id: Id1c8b0fce9feae90e2de944fa173cf719b7042a9 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/google/jecht/acpi/mainboard.asl M src/mainboard/google/jecht/variants/guado/include/variant/acpi/thermal.asl M src/mainboard/google/jecht/variants/jecht/include/variant/acpi/thermal.asl M src/mainboard/google/jecht/variants/rikku/include/variant/acpi/thermal.asl M src/mainboard/google/jecht/variants/tidus/include/variant/acpi/thermal.asl 5 files changed, 271 insertions(+), 311 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/46174/1 diff --git a/src/mainboard/google/jecht/acpi/mainboard.asl b/src/mainboard/google/jecht/acpi/mainboard.asl index da92d2c..8a90ae6 100644 --- a/src/mainboard/google/jecht/acpi/mainboard.asl +++ b/src/mainboard/google/jecht/acpi/mainboard.asl @@ -14,9 +14,9 @@ Method (_DSW, 3, NotSerialized) { - Store (JECHT_NIC_WAKE_GPIO, Local0) + Local0 = JECHT_NIC_WAKE_GPIO - If (LEqual (Arg0, 1)) { + If (Arg0 == 1) { // Enable GPIO as wake source \_SB.PCI0.LPCB.GPIO.GWAK (Local0) } @@ -36,9 +36,9 @@ Method (_DSW, 3, NotSerialized) { - Store (JECHT_WLAN_WAKE_GPIO, Local0) + Local0 = JECHT_WLAN_WAKE_GPIO - If (LEqual (Arg0, 1)) { + If (Arg0 == 1) { // Enable GPIO as wake source \_SB.PCI0.LPCB.GPIO.GWAK (Local0) } diff --git a/src/mainboard/google/jecht/variants/guado/include/variant/acpi/thermal.asl b/src/mainboard/google/jecht/variants/guado/include/variant/acpi/thermal.asl index 2a16352..1ea32a6 100644 --- a/src/mainboard/google/jecht/variants/guado/include/variant/acpi/thermal.asl +++ b/src/mainboard/google/jecht/variants/guado/include/variant/acpi/thermal.asl @@ -24,10 +24,10 @@ // Convert from Degrees C to 1/10 Kelvin for ACPI Method (CTOK, 1) { // 10th of Degrees C - Multiply (Arg0, 10, Local0) + Local0 = Arg0 * 10 // Convert to Kelvin - Add (Local0, 2732, Local0) + Local0 += 2732 Return (Local0) } @@ -53,66 +53,66 @@ // Start fan at state 4 = lowest temp state Method (_INI) { - Store (4, \FLVL) - Store (FAN4_PWM, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + \FLVL = 4 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN4_PWM Notify (\_TZ.THRM, 0x81) } Method (TCHK, 0, Serialized) { // Get CPU Temperature from PECI via SuperIO TMPIN3 - Store (\_SB.PCI0.LPCB.SIO.ENVC.TIN3, Local0) + Local0 = \_SB.PCI0.LPCB.SIO.ENVC.TIN3 // Check for "no reading available - If (LEqual (Local0, 0x80)) { + If (Local0 == 0x80) { Return (CTOK (FAN0_THRESHOLD_ON)) } // Check for invalid readings - If (LOr (LEqual (Local0, 255), LEqual (Local0, 0))) { + If ((Local0 == 255) || (Local0 == 0)) { Return (CTOK (FAN0_THRESHOLD_ON)) } // PECI raw value is an offset from Tj_max - Subtract (255, Local0, Local1) + Local1 = 255 - Local0 // Handle values greater than Tj_max - If (LGreaterEqual (Local1, \TMAX)) { + If (Local1 >= \TMAX) { Return (CTOK (\TMAX)) } // Subtract from Tj_max to get temperature - Subtract (\TMAX, Local1, Local0) + Local0 = \TMAX - Local1 Return (CTOK (Local0)) } Method (_TMP, 0, Serialized) { // Get temperature from SuperIO in deci-kelvin - Store (TCHK (), Local0) + Local0 = TCHK () // Critical temperature in deci-kelvin - Store (CTOK (\TMAX), Local1) + Local1 = CTOK (\TMAX) - If (LGreaterEqual (Local0, Local1)) { - Store ("CRITICAL TEMPERATURE", Debug) - Store (Local0, Debug) + If (Local0 >= Local1) { + Debug = "CRITICAL TEMPERATURE" + Debug = Local0 // Wait 1 second for SuperIO to re-poll Sleep (1000) // Re-read temperature from SuperIO - Store (TCHK (), Local0) + Local0 = TCHK () - Store ("RE-READ TEMPERATURE", Debug) - Store (Local0, Debug) + Debug = "RE-READ TEMPERATURE" + Debug = Local0 } Return (Local0) } Method (_AC0) { - If (LLessEqual (\FLVL, 0)) { + If (\FLVL <= 0) { Return (CTOK (FAN0_THRESHOLD_OFF)) } Else { Return (CTOK (FAN0_THRESHOLD_ON)) @@ -120,7 +120,7 @@ } Method (_AC1) { - If (LLessEqual (\FLVL, 1)) { + If (\FLVL <= 1) { Return (CTOK (FAN1_THRESHOLD_OFF)) } Else { Return (CTOK (FAN1_THRESHOLD_ON)) @@ -128,7 +128,7 @@ } Method (_AC2) { - If (LLessEqual (\FLVL, 2)) { + If (\FLVL <= 2) { Return (CTOK (FAN2_THRESHOLD_OFF)) } Else { Return (CTOK (FAN2_THRESHOLD_ON)) @@ -136,7 +136,7 @@ } Method (_AC3) { - If (LLessEqual (\FLVL, 3)) { + If (\FLVL <= 3) { Return (CTOK (FAN3_THRESHOLD_OFF)) } Else { Return (CTOK (FAN3_THRESHOLD_ON)) @@ -144,7 +144,7 @@ } Method (_AC4) { - If (LLessEqual (\FLVL, 4)) { + If (\FLVL <= 4) { Return (CTOK (0)) } Else { Return (CTOK (0)) @@ -160,25 +160,23 @@ PowerResource (FNP0, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 0)) { + If (\FLVL <= 0) { Return (One) } Else { Return (Zero) } } Method (_ON) { - If (LNot (_STA ())) { - Store (0, \FLVL) - Store (FAN0_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + If (!_STA ()) { + \FLVL = 0 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN0_PWM Notify (\_TZ.THRM, 0x81) } } Method (_OFF) { If (_STA ()) { - Store (1, \FLVL) - Store (FAN1_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + \FLVL = 1 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN1_PWM Notify (\_TZ.THRM, 0x81) } } @@ -187,25 +185,23 @@ PowerResource (FNP1, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 1)) { + If (\FLVL <= 1) { Return (One) } Else { Return (Zero) } } Method (_ON) { - If (LNot (_STA ())) { - Store (1, \FLVL) - Store (FAN1_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + If (!_STA ()) { + \FLVL = 1 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN1_PWM Notify (\_TZ.THRM, 0x81) } } Method (_OFF) { If (_STA ()) { - Store (2, \FLVL) - Store (FAN2_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + \FLVL = 2 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN2_PWM Notify (\_TZ.THRM, 0x81) } } @@ -214,25 +210,23 @@ PowerResource (FNP2, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 2)) { + If (\FLVL <= 2) { Return (One) } Else { Return (Zero) } } Method (_ON) { - If (LNot (_STA ())) { - Store (2, \FLVL) - Store (FAN2_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + If (!_STA ()) { + \FLVL = 2 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN2_PWM Notify (\_TZ.THRM, 0x81) } } Method (_OFF) { If (_STA ()) { - Store (3, \FLVL) - Store (FAN3_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + \FLVL = 3 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN3_PWM Notify (\_TZ.THRM, 0x81) } } @@ -241,25 +235,23 @@ PowerResource (FNP3, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 3)) { + If (\FLVL <= 3) { Return (One) } Else { Return (Zero) } } Method (_ON) { - If (LNot (_STA ())) { - Store (3, \FLVL) - Store (FAN3_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + If (!_STA ()) { + \FLVL = 3 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN3_PWM Notify (\_TZ.THRM, 0x81) } } Method (_OFF) { If (_STA ()) { - Store (4, \FLVL) - Store (FAN4_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + \FLVL = 4 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN4_PWM Notify (\_TZ.THRM, 0x81) } } @@ -268,25 +260,23 @@ PowerResource (FNP4, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 4)) { + If (\FLVL <= 4) { Return (One) } Else { Return (Zero) } } Method (_ON) { - If (LNot (_STA ())) { - Store (4, \FLVL) - Store (FAN4_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + If (!_STA ()) { + \FLVL = 4 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN4_PWM Notify (\_TZ.THRM, 0x81) } } Method (_OFF) { If (_STA ()) { - Store (4, \FLVL) - Store (FAN4_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + \FLVL = 4 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN4_PWM Notify (\_TZ.THRM, 0x81) } } diff --git a/src/mainboard/google/jecht/variants/jecht/include/variant/acpi/thermal.asl b/src/mainboard/google/jecht/variants/jecht/include/variant/acpi/thermal.asl index 2a16352..1ea32a6 100644 --- a/src/mainboard/google/jecht/variants/jecht/include/variant/acpi/thermal.asl +++ b/src/mainboard/google/jecht/variants/jecht/include/variant/acpi/thermal.asl @@ -24,10 +24,10 @@ // Convert from Degrees C to 1/10 Kelvin for ACPI Method (CTOK, 1) { // 10th of Degrees C - Multiply (Arg0, 10, Local0) + Local0 = Arg0 * 10 // Convert to Kelvin - Add (Local0, 2732, Local0) + Local0 += 2732 Return (Local0) } @@ -53,66 +53,66 @@ // Start fan at state 4 = lowest temp state Method (_INI) { - Store (4, \FLVL) - Store (FAN4_PWM, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + \FLVL = 4 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN4_PWM Notify (\_TZ.THRM, 0x81) } Method (TCHK, 0, Serialized) { // Get CPU Temperature from PECI via SuperIO TMPIN3 - Store (\_SB.PCI0.LPCB.SIO.ENVC.TIN3, Local0) + Local0 = \_SB.PCI0.LPCB.SIO.ENVC.TIN3 // Check for "no reading available - If (LEqual (Local0, 0x80)) { + If (Local0 == 0x80) { Return (CTOK (FAN0_THRESHOLD_ON)) } // Check for invalid readings - If (LOr (LEqual (Local0, 255), LEqual (Local0, 0))) { + If ((Local0 == 255) || (Local0 == 0)) { Return (CTOK (FAN0_THRESHOLD_ON)) } // PECI raw value is an offset from Tj_max - Subtract (255, Local0, Local1) + Local1 = 255 - Local0 // Handle values greater than Tj_max - If (LGreaterEqual (Local1, \TMAX)) { + If (Local1 >= \TMAX) { Return (CTOK (\TMAX)) } // Subtract from Tj_max to get temperature - Subtract (\TMAX, Local1, Local0) + Local0 = \TMAX - Local1 Return (CTOK (Local0)) } Method (_TMP, 0, Serialized) { // Get temperature from SuperIO in deci-kelvin - Store (TCHK (), Local0) + Local0 = TCHK () // Critical temperature in deci-kelvin - Store (CTOK (\TMAX), Local1) + Local1 = CTOK (\TMAX) - If (LGreaterEqual (Local0, Local1)) { - Store ("CRITICAL TEMPERATURE", Debug) - Store (Local0, Debug) + If (Local0 >= Local1) { + Debug = "CRITICAL TEMPERATURE" + Debug = Local0 // Wait 1 second for SuperIO to re-poll Sleep (1000) // Re-read temperature from SuperIO - Store (TCHK (), Local0) + Local0 = TCHK () - Store ("RE-READ TEMPERATURE", Debug) - Store (Local0, Debug) + Debug = "RE-READ TEMPERATURE" + Debug = Local0 } Return (Local0) } Method (_AC0) { - If (LLessEqual (\FLVL, 0)) { + If (\FLVL <= 0) { Return (CTOK (FAN0_THRESHOLD_OFF)) } Else { Return (CTOK (FAN0_THRESHOLD_ON)) @@ -120,7 +120,7 @@ } Method (_AC1) { - If (LLessEqual (\FLVL, 1)) { + If (\FLVL <= 1) { Return (CTOK (FAN1_THRESHOLD_OFF)) } Else { Return (CTOK (FAN1_THRESHOLD_ON)) @@ -128,7 +128,7 @@ } Method (_AC2) { - If (LLessEqual (\FLVL, 2)) { + If (\FLVL <= 2) { Return (CTOK (FAN2_THRESHOLD_OFF)) } Else { Return (CTOK (FAN2_THRESHOLD_ON)) @@ -136,7 +136,7 @@ } Method (_AC3) { - If (LLessEqual (\FLVL, 3)) { + If (\FLVL <= 3) { Return (CTOK (FAN3_THRESHOLD_OFF)) } Else { Return (CTOK (FAN3_THRESHOLD_ON)) @@ -144,7 +144,7 @@ } Method (_AC4) { - If (LLessEqual (\FLVL, 4)) { + If (\FLVL <= 4) { Return (CTOK (0)) } Else { Return (CTOK (0)) @@ -160,25 +160,23 @@ PowerResource (FNP0, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 0)) { + If (\FLVL <= 0) { Return (One) } Else { Return (Zero) } } Method (_ON) { - If (LNot (_STA ())) { - Store (0, \FLVL) - Store (FAN0_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + If (!_STA ()) { + \FLVL = 0 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN0_PWM Notify (\_TZ.THRM, 0x81) } } Method (_OFF) { If (_STA ()) { - Store (1, \FLVL) - Store (FAN1_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + \FLVL = 1 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN1_PWM Notify (\_TZ.THRM, 0x81) } } @@ -187,25 +185,23 @@ PowerResource (FNP1, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 1)) { + If (\FLVL <= 1) { Return (One) } Else { Return (Zero) } } Method (_ON) { - If (LNot (_STA ())) { - Store (1, \FLVL) - Store (FAN1_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + If (!_STA ()) { + \FLVL = 1 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN1_PWM Notify (\_TZ.THRM, 0x81) } } Method (_OFF) { If (_STA ()) { - Store (2, \FLVL) - Store (FAN2_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + \FLVL = 2 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN2_PWM Notify (\_TZ.THRM, 0x81) } } @@ -214,25 +210,23 @@ PowerResource (FNP2, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 2)) { + If (\FLVL <= 2) { Return (One) } Else { Return (Zero) } } Method (_ON) { - If (LNot (_STA ())) { - Store (2, \FLVL) - Store (FAN2_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + If (!_STA ()) { + \FLVL = 2 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN2_PWM Notify (\_TZ.THRM, 0x81) } } Method (_OFF) { If (_STA ()) { - Store (3, \FLVL) - Store (FAN3_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + \FLVL = 3 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN3_PWM Notify (\_TZ.THRM, 0x81) } } @@ -241,25 +235,23 @@ PowerResource (FNP3, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 3)) { + If (\FLVL <= 3) { Return (One) } Else { Return (Zero) } } Method (_ON) { - If (LNot (_STA ())) { - Store (3, \FLVL) - Store (FAN3_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + If (!_STA ()) { + \FLVL = 3 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN3_PWM Notify (\_TZ.THRM, 0x81) } } Method (_OFF) { If (_STA ()) { - Store (4, \FLVL) - Store (FAN4_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + \FLVL = 4 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN4_PWM Notify (\_TZ.THRM, 0x81) } } @@ -268,25 +260,23 @@ PowerResource (FNP4, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 4)) { + If (\FLVL <= 4) { Return (One) } Else { Return (Zero) } } Method (_ON) { - If (LNot (_STA ())) { - Store (4, \FLVL) - Store (FAN4_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + If (!_STA ()) { + \FLVL = 4 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN4_PWM Notify (\_TZ.THRM, 0x81) } } Method (_OFF) { If (_STA ()) { - Store (4, \FLVL) - Store (FAN4_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + \FLVL = 4 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN4_PWM Notify (\_TZ.THRM, 0x81) } } diff --git a/src/mainboard/google/jecht/variants/rikku/include/variant/acpi/thermal.asl b/src/mainboard/google/jecht/variants/rikku/include/variant/acpi/thermal.asl index 2a16352..1ea32a6 100644 --- a/src/mainboard/google/jecht/variants/rikku/include/variant/acpi/thermal.asl +++ b/src/mainboard/google/jecht/variants/rikku/include/variant/acpi/thermal.asl @@ -24,10 +24,10 @@ // Convert from Degrees C to 1/10 Kelvin for ACPI Method (CTOK, 1) { // 10th of Degrees C - Multiply (Arg0, 10, Local0) + Local0 = Arg0 * 10 // Convert to Kelvin - Add (Local0, 2732, Local0) + Local0 += 2732 Return (Local0) } @@ -53,66 +53,66 @@ // Start fan at state 4 = lowest temp state Method (_INI) { - Store (4, \FLVL) - Store (FAN4_PWM, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + \FLVL = 4 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN4_PWM Notify (\_TZ.THRM, 0x81) } Method (TCHK, 0, Serialized) { // Get CPU Temperature from PECI via SuperIO TMPIN3 - Store (\_SB.PCI0.LPCB.SIO.ENVC.TIN3, Local0) + Local0 = \_SB.PCI0.LPCB.SIO.ENVC.TIN3 // Check for "no reading available - If (LEqual (Local0, 0x80)) { + If (Local0 == 0x80) { Return (CTOK (FAN0_THRESHOLD_ON)) } // Check for invalid readings - If (LOr (LEqual (Local0, 255), LEqual (Local0, 0))) { + If ((Local0 == 255) || (Local0 == 0)) { Return (CTOK (FAN0_THRESHOLD_ON)) } // PECI raw value is an offset from Tj_max - Subtract (255, Local0, Local1) + Local1 = 255 - Local0 // Handle values greater than Tj_max - If (LGreaterEqual (Local1, \TMAX)) { + If (Local1 >= \TMAX) { Return (CTOK (\TMAX)) } // Subtract from Tj_max to get temperature - Subtract (\TMAX, Local1, Local0) + Local0 = \TMAX - Local1 Return (CTOK (Local0)) } Method (_TMP, 0, Serialized) { // Get temperature from SuperIO in deci-kelvin - Store (TCHK (), Local0) + Local0 = TCHK () // Critical temperature in deci-kelvin - Store (CTOK (\TMAX), Local1) + Local1 = CTOK (\TMAX) - If (LGreaterEqual (Local0, Local1)) { - Store ("CRITICAL TEMPERATURE", Debug) - Store (Local0, Debug) + If (Local0 >= Local1) { + Debug = "CRITICAL TEMPERATURE" + Debug = Local0 // Wait 1 second for SuperIO to re-poll Sleep (1000) // Re-read temperature from SuperIO - Store (TCHK (), Local0) + Local0 = TCHK () - Store ("RE-READ TEMPERATURE", Debug) - Store (Local0, Debug) + Debug = "RE-READ TEMPERATURE" + Debug = Local0 } Return (Local0) } Method (_AC0) { - If (LLessEqual (\FLVL, 0)) { + If (\FLVL <= 0) { Return (CTOK (FAN0_THRESHOLD_OFF)) } Else { Return (CTOK (FAN0_THRESHOLD_ON)) @@ -120,7 +120,7 @@ } Method (_AC1) { - If (LLessEqual (\FLVL, 1)) { + If (\FLVL <= 1) { Return (CTOK (FAN1_THRESHOLD_OFF)) } Else { Return (CTOK (FAN1_THRESHOLD_ON)) @@ -128,7 +128,7 @@ } Method (_AC2) { - If (LLessEqual (\FLVL, 2)) { + If (\FLVL <= 2) { Return (CTOK (FAN2_THRESHOLD_OFF)) } Else { Return (CTOK (FAN2_THRESHOLD_ON)) @@ -136,7 +136,7 @@ } Method (_AC3) { - If (LLessEqual (\FLVL, 3)) { + If (\FLVL <= 3) { Return (CTOK (FAN3_THRESHOLD_OFF)) } Else { Return (CTOK (FAN3_THRESHOLD_ON)) @@ -144,7 +144,7 @@ } Method (_AC4) { - If (LLessEqual (\FLVL, 4)) { + If (\FLVL <= 4) { Return (CTOK (0)) } Else { Return (CTOK (0)) @@ -160,25 +160,23 @@ PowerResource (FNP0, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 0)) { + If (\FLVL <= 0) { Return (One) } Else { Return (Zero) } } Method (_ON) { - If (LNot (_STA ())) { - Store (0, \FLVL) - Store (FAN0_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + If (!_STA ()) { + \FLVL = 0 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN0_PWM Notify (\_TZ.THRM, 0x81) } } Method (_OFF) { If (_STA ()) { - Store (1, \FLVL) - Store (FAN1_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + \FLVL = 1 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN1_PWM Notify (\_TZ.THRM, 0x81) } } @@ -187,25 +185,23 @@ PowerResource (FNP1, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 1)) { + If (\FLVL <= 1) { Return (One) } Else { Return (Zero) } } Method (_ON) { - If (LNot (_STA ())) { - Store (1, \FLVL) - Store (FAN1_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + If (!_STA ()) { + \FLVL = 1 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN1_PWM Notify (\_TZ.THRM, 0x81) } } Method (_OFF) { If (_STA ()) { - Store (2, \FLVL) - Store (FAN2_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + \FLVL = 2 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN2_PWM Notify (\_TZ.THRM, 0x81) } } @@ -214,25 +210,23 @@ PowerResource (FNP2, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 2)) { + If (\FLVL <= 2) { Return (One) } Else { Return (Zero) } } Method (_ON) { - If (LNot (_STA ())) { - Store (2, \FLVL) - Store (FAN2_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + If (!_STA ()) { + \FLVL = 2 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN2_PWM Notify (\_TZ.THRM, 0x81) } } Method (_OFF) { If (_STA ()) { - Store (3, \FLVL) - Store (FAN3_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + \FLVL = 3 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN3_PWM Notify (\_TZ.THRM, 0x81) } } @@ -241,25 +235,23 @@ PowerResource (FNP3, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 3)) { + If (\FLVL <= 3) { Return (One) } Else { Return (Zero) } } Method (_ON) { - If (LNot (_STA ())) { - Store (3, \FLVL) - Store (FAN3_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + If (!_STA ()) { + \FLVL = 3 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN3_PWM Notify (\_TZ.THRM, 0x81) } } Method (_OFF) { If (_STA ()) { - Store (4, \FLVL) - Store (FAN4_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + \FLVL = 4 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN4_PWM Notify (\_TZ.THRM, 0x81) } } @@ -268,25 +260,23 @@ PowerResource (FNP4, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 4)) { + If (\FLVL <= 4) { Return (One) } Else { Return (Zero) } } Method (_ON) { - If (LNot (_STA ())) { - Store (4, \FLVL) - Store (FAN4_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + If (!_STA ()) { + \FLVL = 4 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN4_PWM Notify (\_TZ.THRM, 0x81) } } Method (_OFF) { If (_STA ()) { - Store (4, \FLVL) - Store (FAN4_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + \FLVL = 4 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN4_PWM Notify (\_TZ.THRM, 0x81) } } diff --git a/src/mainboard/google/jecht/variants/tidus/include/variant/acpi/thermal.asl b/src/mainboard/google/jecht/variants/tidus/include/variant/acpi/thermal.asl index e2f2675..80893f6 100644 --- a/src/mainboard/google/jecht/variants/tidus/include/variant/acpi/thermal.asl +++ b/src/mainboard/google/jecht/variants/tidus/include/variant/acpi/thermal.asl @@ -39,99 +39,99 @@ // Convert from Degrees C to 1/10 Kelvin for ACPI Method (CTOK, 1) { // 10th of Degrees C - Multiply (Arg0, 10, Local0) + Local0 = Arg0 * 10 // Convert to Kelvin - Add (Local0, 2732, Local0) + Local0 += 2732 Return (Local0) } // Thermal Table 0 Method (TTB0, 0) { - Store (FAN0_0_THRESHOLD_ON, F0ON) - Store (FAN0_0_THRESHOLD_OFF, F0OF) - Store (FAN0_0_PWM, F0PW) - Store (FAN1_0_THRESHOLD_ON, F1ON) - Store (FAN1_0_THRESHOLD_OFF, F1OF) - Store (FAN1_0_PWM, F1PW) - Store (FAN2_0_THRESHOLD_ON, F2ON) - Store (FAN2_0_THRESHOLD_OFF, F2OF) - Store (FAN2_0_PWM, F2PW) - Store (FAN3_0_THRESHOLD_ON, F3ON) - Store (FAN3_0_THRESHOLD_OFF, F3OF) - Store (FAN3_0_PWM, F3PW) - Store (FAN4_0_PWM, F4PW) - Store (0, THTB) + F0ON = FAN0_0_THRESHOLD_ON + F0OF = FAN0_0_THRESHOLD_OFF + F0PW = FAN0_0_PWM + F1ON = FAN1_0_THRESHOLD_ON + F1OF = FAN1_0_THRESHOLD_OFF + F1PW = FAN1_0_PWM + F2ON = FAN2_0_THRESHOLD_ON + F2OF = FAN2_0_THRESHOLD_OFF + F2PW = FAN2_0_PWM + F3ON = FAN3_0_THRESHOLD_ON + F3OF = FAN3_0_THRESHOLD_OFF + F3PW = FAN3_0_PWM + F4PW = FAN4_0_PWM + THTB = 0 } // Thermal Table 1 Method (TTB1, 0) { - Store (FAN0_1_THRESHOLD_ON, F0ON) - Store (FAN0_1_THRESHOLD_OFF, F0OF) - Store (FAN0_1_PWM, F0PW) - Store (FAN1_1_THRESHOLD_ON, F1ON) - Store (FAN1_1_THRESHOLD_OFF, F1OF) - Store (FAN1_1_PWM, F1PW) - Store (FAN2_1_THRESHOLD_ON, F2ON) - Store (FAN2_1_THRESHOLD_OFF, F2OF) - Store (FAN2_1_PWM, F2PW) - Store (FAN3_1_THRESHOLD_ON, F3ON) - Store (FAN3_1_THRESHOLD_OFF, F3OF) - Store (FAN3_1_PWM, F3PW) - Store (FAN4_1_PWM, F4PW) - Store (1, THTB) + F0ON = FAN0_1_THRESHOLD_ON + F0OF = FAN0_1_THRESHOLD_OFF + F0PW = FAN0_1_PWM + F1ON = FAN1_1_THRESHOLD_ON + F1OF = FAN1_1_THRESHOLD_OFF + F1PW = FAN1_1_PWM + F2ON = FAN2_1_THRESHOLD_ON + F2OF = FAN2_1_THRESHOLD_OFF + F2PW = FAN2_1_PWM + F3ON = FAN3_1_THRESHOLD_ON + F3OF = FAN3_1_THRESHOLD_OFF + F3PW = FAN3_1_PWM + F4PW = FAN4_1_PWM + THTB = 1 } // Thermal Table 2 Method (TTB2, 0) { - Store (FAN0_2_THRESHOLD_ON, F0ON) - Store (FAN0_2_THRESHOLD_OFF, F0OF) - Store (FAN0_2_PWM, F0PW) - Store (FAN1_2_THRESHOLD_ON, F1ON) - Store (FAN1_2_THRESHOLD_OFF, F1OF) - Store (FAN1_2_PWM, F1PW) - Store (FAN2_2_THRESHOLD_ON, F2ON) - Store (FAN2_2_THRESHOLD_OFF, F2OF) - Store (FAN2_2_PWM, F2PW) - Store (FAN3_2_THRESHOLD_ON, F3ON) - Store (FAN3_2_THRESHOLD_OFF, F3OF) - Store (FAN3_2_PWM, F3PW) - Store (FAN4_2_PWM, F4PW) - Store (2, THTB) + F0ON = FAN0_2_THRESHOLD_ON + F0OF = FAN0_2_THRESHOLD_OFF + F0PW = FAN0_2_PWM + F1ON = FAN1_2_THRESHOLD_ON + F1OF = FAN1_2_THRESHOLD_OFF + F1PW = FAN1_2_PWM + F2ON = FAN2_2_THRESHOLD_ON + F2OF = FAN2_2_THRESHOLD_OFF + F2PW = FAN2_2_PWM + F3ON = FAN3_2_THRESHOLD_ON + F3OF = FAN3_2_THRESHOLD_OFF + F3PW = FAN3_2_PWM + F4PW = FAN4_2_PWM + THTB = 2 } // Update Thermal Table Method (UPTB, 0) { // Get System Temperature via SuperIO TMPIN2 - Store (\_SB.PCI0.LPCB.SIO.ENVC.TIN2, Local0) + Local0 = \_SB.PCI0.LPCB.SIO.ENVC.TIN2 // Check for "no reading available - If (LEqual (Local0, 0x80)) { - Store (THERMAL_POLICY_0_THRESHOLD_ON, Local0) + If (Local0 == 0x80) { + Local0 = THERMAL_POLICY_0_THRESHOLD_ON } // Check for invalid readings - If (LOr (LEqual (Local0, 255), LEqual (Local0, 0))) { - Store (THERMAL_POLICY_0_THRESHOLD_ON, Local0) + If ((Local0 == 255) || (Local0 == 0)) { + Local0 = THERMAL_POLICY_0_THRESHOLD_ON } - If (LEqual (THTB, 2)) { - If (LGreaterEqual (Local0, THERMAL_POLICY_0_THRESHOLD_ON)) { + If (THTB == 2) { + If (Local0 >= THERMAL_POLICY_0_THRESHOLD_ON) { TTB0 () - } ElseIf (LGreaterEqual (Local0, THERMAL_POLICY_1_THRESHOLD_ON)) { + } ElseIf (Local0 >= THERMAL_POLICY_1_THRESHOLD_ON) { TTB1 () } - } ElseIf (LEqual (THTB, 1)) { - If (LGreaterEqual (Local0, THERMAL_POLICY_0_THRESHOLD_ON)) { + } ElseIf (THTB == 1) { + If (Local0 >= THERMAL_POLICY_0_THRESHOLD_ON) { TTB0 () - } ElseIf (LLessEqual (Local0, THERMAL_POLICY_1_THRESHOLD_OFF)) { + } ElseIf (Local0 <= THERMAL_POLICY_1_THRESHOLD_OFF) { TTB2 () } } Else { - If (LLess (Local0, THERMAL_POLICY_1_THRESHOLD_OFF)) { + If (Local0 < THERMAL_POLICY_1_THRESHOLD_OFF) { TTB2 () - } ElseIf (LLessEqual (Local0, THERMAL_POLICY_0_THRESHOLD_OFF)) { + } ElseIf (Local0 <= THERMAL_POLICY_0_THRESHOLD_OFF) { TTB1 () } } @@ -158,8 +158,8 @@ // Start fan at state 4 = lowest temp state Method (_INI) { - Store (4, \FLVL) - Store (FAN4_2_PWM, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + \FLVL = 4 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN4_2_PWM Notify (\_TZ.THRM, 0x81) } @@ -169,58 +169,58 @@ UPTB () // Get CPU Temperature from PECI via SuperIO TMPIN3 - Store (\_SB.PCI0.LPCB.SIO.ENVC.TIN3, Local0) + Local0 = \_SB.PCI0.LPCB.SIO.ENVC.TIN3 // Check for "no reading available - If (LEqual (Local0, 0x80)) { + If (Local0 == 0x80) { Return (CTOK (FAN0_0_THRESHOLD_ON)) } // Check for invalid readings - If (LOr (LEqual (Local0, 255), LEqual (Local0, 0))) { + If ((Local0 == 255) || (Local0 == 0)) { Return (CTOK (FAN0_0_THRESHOLD_ON)) } // PECI raw value is an offset from Tj_max - Subtract (255, Local0, Local1) + Local1 = 255 - Local0 // Handle values greater than Tj_max - If (LGreaterEqual (Local1, \TMAX)) { + If (Local1 >= \TMAX) { Return (CTOK (\TMAX)) } // Subtract from Tj_max to get temperature - Subtract (\TMAX, Local1, Local0) + Local0 = \TMAX - Local1 Return (CTOK (Local0)) } Method (_TMP, 0, Serialized) { // Get temperature from SuperIO in deci-kelvin - Store (TCHK (), Local0) + Local0 = TCHK () // Critical temperature in deci-kelvin - Store (CTOK (\TMAX), Local1) + Local1 = CTOK (\TMAX) - If (LGreaterEqual (Local0, Local1)) { - Store ("CRITICAL TEMPERATURE", Debug) - Store (Local0, Debug) + If (Local0 >= Local1) { + Debug = "CRITICAL TEMPERATURE" + Debug = Local0 // Wait 1 second for SuperIO to re-poll Sleep (1000) // Re-read temperature from SuperIO - Store (TCHK (), Local0) + Local0 = TCHK () - Store ("RE-READ TEMPERATURE", Debug) - Store (Local0, Debug) + Debug = "RE-READ TEMPERATURE" + Debug = Local0 } Return (Local0) } Method (_AC0) { - If (LLessEqual (\FLVL, 0)) { + If (\FLVL <= 0) { Return (CTOK (F0OF)) } Else { Return (CTOK (F0ON)) @@ -228,7 +228,7 @@ } Method (_AC1) { - If (LLessEqual (\FLVL, 1)) { + If (\FLVL <= 1) { Return (CTOK (F1OF)) } Else { Return (CTOK (F1ON)) @@ -236,7 +236,7 @@ } Method (_AC2) { - If (LLessEqual (\FLVL, 2)) { + If (\FLVL <= 2) { Return (CTOK (F2OF)) } Else { Return (CTOK (F2ON)) @@ -244,7 +244,7 @@ } Method (_AC3) { - If (LLessEqual (\FLVL, 3)) { + If (\FLVL <= 3) { Return (CTOK (F3OF)) } Else { Return (CTOK (F3ON)) @@ -252,7 +252,7 @@ } Method (_AC4) { - If (LLessEqual (\FLVL, 4)) { + If (\FLVL <= 4) { Return (CTOK (0)) } Else { Return (CTOK (0)) @@ -268,25 +268,23 @@ PowerResource (FNP0, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 0)) { + If (\FLVL <= 0) { Return (One) } Else { Return (Zero) } } Method (_ON) { - If (LNot (_STA ())) { - Store (0, \FLVL) - Store (F0PW, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + If (!_STA ()) { + \FLVL = 0 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = F0PW Notify (\_TZ.THRM, 0x81) } } Method (_OFF) { If (_STA ()) { - Store (1, \FLVL) - Store (F1PW, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + \FLVL = 1 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = F1PW Notify (\_TZ.THRM, 0x81) } } @@ -295,25 +293,23 @@ PowerResource (FNP1, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 1)) { + If (\FLVL <= 1) { Return (One) } Else { Return (Zero) } } Method (_ON) { - If (LNot (_STA ())) { - Store (1, \FLVL) - Store (F1PW, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + If (!_STA ()) { + \FLVL = 1 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = F1PW Notify (\_TZ.THRM, 0x81) } } Method (_OFF) { If (_STA ()) { - Store (2, \FLVL) - Store (F2PW, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + \FLVL = 2 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = F2PW Notify (\_TZ.THRM, 0x81) } } @@ -322,25 +318,23 @@ PowerResource (FNP2, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 2)) { + If (\FLVL <= 2) { Return (One) } Else { Return (Zero) } } Method (_ON) { - If (LNot (_STA ())) { - Store (2, \FLVL) - Store (F2PW, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + If (!_STA ()) { + \FLVL = 2 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = F2PW Notify (\_TZ.THRM, 0x81) } } Method (_OFF) { If (_STA ()) { - Store (3, \FLVL) - Store (F3PW, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + \FLVL = 3 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = F3PW Notify (\_TZ.THRM, 0x81) } } @@ -349,25 +343,23 @@ PowerResource (FNP3, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 3)) { + If (\FLVL <= 3) { Return (One) } Else { Return (Zero) } } Method (_ON) { - If (LNot (_STA ())) { - Store (3, \FLVL) - Store (F3PW, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + If (!_STA ()) { + \FLVL = 3 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = F3PW Notify (\_TZ.THRM, 0x81) } } Method (_OFF) { If (_STA ()) { - Store (4, \FLVL) - Store (F4PW, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + \FLVL = 4 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = F4PW Notify (\_TZ.THRM, 0x81) } } @@ -376,25 +368,23 @@ PowerResource (FNP4, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 4)) { + If (\FLVL <= 4) { Return (One) } Else { Return (Zero) } } Method (_ON) { - If (LNot (_STA ())) { - Store (4, \FLVL) - Store (F4PW, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + If (!_STA ()) { + \FLVL = 4 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = F4PW Notify (\_TZ.THRM, 0x81) } } Method (_OFF) { If (_STA ()) { - Store (4, \FLVL) - Store (F4PW, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + \FLVL = 4 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = F4PW Notify (\_TZ.THRM, 0x81) } } -- To view, visit https://review.coreboot.org/c/coreboot/+/46174 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id1c8b0fce9feae90e2de944fa173cf719b7042a9 Gerrit-Change-Number: 46174 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/kahlee: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 09 Oct '20

09 Oct '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46175 ) Change subject: mb/google/kahlee: Convert to ASL 2.0 syntax ...................................................................... mb/google/kahlee: Convert to ASL 2.0 syntax Change-Id: Ieba23eb41c48e03b54ec90e86acace03f696fbe3 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/sleep.asl M src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/thermal.asl 2 files changed, 14 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/46175/1 diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/sleep.asl b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/sleep.asl index d151e1d..ced2e2d 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/sleep.asl +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/sleep.asl @@ -29,10 +29,10 @@ \_SB.PCI0.FPTS () /* Clear wake status structure. */ - Store (0, PEWD) - Store (0, Index(WKST,0)) - Store (0, Index(WKST,1)) - Store (7, UPWS) + PEWD = 0 + WKST [0] = 0 + WKST [1] = 0 + UPWS = 7 } /* diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/thermal.asl b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/thermal.asl index 32a6549..73499b0 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/thermal.asl +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/thermal.asl @@ -21,10 +21,10 @@ /* Convert from Degrees C to 1/10 Kelvin for ACPI */ Method (CTOK, 1) { /* 10th of Degrees C */ - Multiply (Arg0, 10, Local0) + Local0 = Arg0 * 10 /* Convert to Kelvin */ - Add (Local0, 2732, Local0) + Local0 += 2732 Return (Local0) } @@ -50,23 +50,23 @@ Method (_TMP, 0, Serialized) { /* Get temperature from EC in deci-kelvin */ - Store (\_SB.PCI0.LPCB.EC0.TSRD (TMPS), Local0) + Local0 =\_SB.PCI0.LPCB.EC0.TSRD (TMPS) /* Critical temperature in deci-kelvin */ - Store (CTOK (\TCRT), Local1) + Local1 = CTOK (\TCRT) - If (LGreaterEqual (Local0, Local1)) { - Store ("CRITICAL TEMPERATURE", Debug) - Store (Local0, Debug) + If (Local0 >= Local1) { + Debug = "CRITICAL TEMPERATURE" + Debug = Local0 /* Wait 1 second for EC to re-poll */ Sleep (1000) /* Re-read temperature from EC */ - Store (\_SB.PCI0.LPCB.EC0.TSRD (TMPS), Local0) + Local0 =\_SB.PCI0.LPCB.EC0.TSRD (TMPS) - Store ("RE-READ TEMPERATURE", Debug) - Store (Local0, Debug) + Debug = "RE-READ TEMPERATURE" + Debug = Local0 } Return (Local0) -- To view, visit https://review.coreboot.org/c/coreboot/+/46175 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieba23eb41c48e03b54ec90e86acace03f696fbe3 Gerrit-Change-Number: 46175 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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