coreboot-gerrit October 2020

coreboot-gerrit@coreboot.org

1 participants
3474 discussions

Change in coreboot[master]: mb/google/poppy/variant/atlas: Reset bluetooth in BIOS
by Tim Wawrzynczak (Code Review) 09 Oct '20

09 Oct '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46120 ) Change subject: mb/google/poppy/variant/atlas: Reset bluetooth in BIOS ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/c/coreboot/+/46120/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/46120/1//COMMIT_MSG@20 PS1, Line 20: > We usually merge coreboot changes to top-of-tree first, and then cherry-pick on the chromium side to […] For sure :) I just mean to tag this with BRANCH=poppy or something -- To view, visit https://review.coreboot.org/c/coreboot/+/46120 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I361caa49e82aa086c3c35962164fb078fa30139e Gerrit-Change-Number: 46120 Gerrit-PatchSet: 1 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 09 Oct 2020 19:05:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/poppy/variant/atlas: Reset bluetooth in BIOS
by Nick Vaccaro (Code Review) 09 Oct '20

09 Oct '20

Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46120 ) Change subject: mb/google/poppy/variant/atlas: Reset bluetooth in BIOS ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/c/coreboot/+/46120/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/46120/1//COMMIT_MSG@20 PS1, Line 20: > Shouldn't this go in the poppy branch? We usually merge coreboot changes to top-of-tree first, and then cherry-pick on the chromium side to the firmware branch to assure TOT stays up-to-date. -- To view, visit https://review.coreboot.org/c/coreboot/+/46120 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I361caa49e82aa086c3c35962164fb078fa30139e Gerrit-Change-Number: 46120 Gerrit-PatchSet: 1 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 09 Oct 2020 18:52:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/volteer/variants/volteer2: Update DPTF parameters
by Terry Chen (Code Review) 09 Oct '20

09 Oct '20

Terry Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46087 ) Change subject: mb/google/volteer/variants/volteer2: Update DPTF parameters ...................................................................... mb/google/volteer/variants/volteer2: Update DPTF parameters 1. Apply the DPTF parameters received from the thermal team. BUG=b:169183507 TEST=build and verify by thermal tool Signed-off-by: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Change-Id: I1a1a0f9e86e519ac15904fac80cf3c2299213e52 --- M src/mainboard/google/volteer/variants/volteer2/overridetree.cb 1 file changed, 74 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/46087/1 diff --git a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb index 0bb82f1..f9d54ca 100644 --- a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb @@ -6,6 +6,80 @@ register "DdiPort2Hpd" = "0" device domain 0 on + device pci 04.0 on + chip drivers/intel/dptf + ## Active Policy + register "policies.active" = "{ + [3] = {.target = DPTF_TEMP_SENSOR_2, + .thresholds = {TEMP_PCT(53, 90), + TEMP_PCT(50, 69), + TEMP_PCT(48, 56), + TEMP_PCT(45, 46), + TEMP_PCT(42, 36),}}, + [4] = {.target = DPTF_TEMP_SENSOR_3, + .thresholds = {TEMP_PCT(53, 90), + TEMP_PCT(50, 69), + TEMP_PCT(48, 56), + TEMP_PCT(45, 46), + TEMP_PCT(42, 36),}}}" + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 65, 6000), + [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_0, 65, 6000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 65, 6000), + [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 65, 6000)}" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 75, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 75, SHUTDOWN), + [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 75, SHUTDOWN)}" + + ## Power Limits Control + # 10-15W PL1 in 200mW increments, avg over 28-32s interval + # PL2 is fixed at 64W, avg over 28-32s interval + register "controls.power_limits" = "{ + .pl1 = {.min_power = 3000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200,}, + .pl2 = {.min_power = 15000, + .max_power = 60000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}}" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 1700 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 }}" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf" = "{ + [0] = { 90, 6700, 220, 2200, }, + [1] = { 80, 5800, 180, 1800, }, + [2] = { 70, 5000, 145, 1450, }, + [3] = { 60, 4900, 115, 1150, }, + [4] = { 50, 3838, 90, 900, }, + [5] = { 40, 2904, 55, 550, }, + [6] = { 30, 2337, 30, 300, }, + [7] = { 20, 1608, 15, 150, }, + [8] = { 10, 800, 10, 100, }, + [9] = { 0, 0, 0, 50, }}" + + # Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 0 on end + end + end # DPTF 0x9A03 device pci 05.0 on end # IPU 0x9A19 device pci 15.0 on chip drivers/i2c/generic -- To view, visit https://review.coreboot.org/c/coreboot/+/46087 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1a1a0f9e86e519ac15904fac80cf3c2299213e52 Gerrit-Change-Number: 46087 Gerrit-PatchSet: 1 Gerrit-Owner: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-MessageType: newchange

5 16

Change in coreboot[master]: soc/intel/tigerlake: Replace soc_get_pmc_mux_device with device pointers
by Duncan Laurie (Code Review) 09 Oct '20

09 Oct '20

Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45747 ) Change subject: soc/intel/tigerlake: Replace soc_get_pmc_mux_device with device pointers ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/45747 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie00834c79bd5304998adaccb388ae74a108192b1 Gerrit-Change-Number: 45747 Gerrit-PatchSet: 5 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 09 Oct 2020 16:29:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/xeon_sp/cpx: Set CPU_ADDR_BITS to 46
by Christian Walter (Code Review) 09 Oct '20

09 Oct '20

Christian Walter has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45868 ) Change subject: soc/intel/xeon_sp/cpx: Set CPU_ADDR_BITS to 46 ...................................................................... soc/intel/xeon_sp/cpx: Set CPU_ADDR_BITS to 46 According to document number 338846 this should be set to 46 bits. Change-Id: I0bbe6c962ffc7d5dc722f1cacf55bc0d0615db59 Signed-off-by: Christian Walter <christian.walter(a)9elements.com> --- M src/soc/intel/xeon_sp/cpx/Kconfig 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/45868/1 diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig index 8e7e6f1..975afc9 100644 --- a/src/soc/intel/xeon_sp/cpx/Kconfig +++ b/src/soc/intel/xeon_sp/cpx/Kconfig @@ -15,6 +15,10 @@ int default 255 +config CPU_ADDR_BITS + int + default 46 + config PCR_BASE_ADDRESS hex default 0xfd000000 -- To view, visit https://review.coreboot.org/c/coreboot/+/45868 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0bbe6c962ffc7d5dc722f1cacf55bc0d0615db59 Gerrit-Change-Number: 45868 Gerrit-PatchSet: 1 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: soc/intel/xeon_sp/cpx: skip DRHD generation for non-PCIe stack
by Jonathan Zhang (Code Review) 09 Oct '20

09 Oct '20

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45887 ) Change subject: soc/intel/xeon_sp/cpx: skip DRHD generation for non-PCIe stack ...................................................................... soc/intel/xeon_sp/cpx: skip DRHD generation for non-PCIe stack This is a temporary patch to unblock test/release. It will be replaced by following patches: * A patch to correct ioapic GSIs. * A patch to skip DRHD generation for non-PCIe stack (this can only be done when the IPS ticket is resolved). With the patch to correct ioapic GSIs, there are following target OS boot errors: [ 1.098771] IOAPIC[0]: apic_id 8, version 32, address 0xfec00000, GSI 0-119 [ 1.099159] GSI range [24-31] for new IOAPIC conflicts with GSI[0-119] With the patch, these are the messages: [ 0.399498] IOAPIC[0]: apic_id 8, version 32, address 0xfec00000, GSI 0-119 [ 0.399848] IOAPIC[1]: apic_id 9, version 32, address 0xfec01000, GSI 120-127 I also suspect this causes the reboot instability issue. During some reboots (like once every 30 reboots), following failures happen: [ 4.325795] mce: [Hardware Error]: Machine check events logged [ 4.326597] mce: [Hardware Error]: CPU 0: Machine Check: 0 Bank 9: ee2000000003110a [ 4.327594] mce: [Hardware Error]: TSC 0 ADDR fe9e0000 MISC 228aa040101086 [ 4.328596] mce: [Hardware Error]: PROCESSOR 0:5065b TIME 1601443875 SOCKET 0 APIC 0 microcode 700001d The MCE errors is happen in bank 9, 10 and 11. The Model specific error code shows it is about SAD_ERR_WB_TO_MMIO error (doc 604926), which means something goes wrong when cache write back to mmio. It is a generic transaction type error in level 2. Since the error happens during smpboot of PBSP, I suspect this is an issue related to ioapic, hence found the issue with MADT table. Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Change-Id: I098605daf12a264f390613581427ec722afcddaf --- M src/soc/intel/xeon_sp/cpx/acpi.c 1 file changed, 19 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/45887/1 diff --git a/src/soc/intel/xeon_sp/cpx/acpi.c b/src/soc/intel/xeon_sp/cpx/acpi.c index cd497c5..8792131 100644 --- a/src/soc/intel/xeon_sp/cpx/acpi.c +++ b/src/soc/intel/xeon_sp/cpx/acpi.c @@ -187,7 +187,7 @@ int cur_index; struct iiostack_resource stack_info = {0}; - int gsi_bases[] = { 0, 0x18, 0x20, 0x28, 0x30, 0x48, 0x50, 0x58, 0x60 }; + int gsi_bases[] = { 0, 0x78, 0x80, 0x88, 0x90, 0x98, 0xA0, 0xA8, 0xB0 }; int ioapic_ids[] = { 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0x10, 0x11, 0x12 }; /* Local APICs */ @@ -612,9 +612,20 @@ if (get_stack_for_port(port) != stack) return 0; - const uint32_t bus = iio_resource.StackRes[stack].BusBase; - const uint32_t dev = iio_resource.PcieInfo.PortInfo[port].Device; - const uint32_t func = iio_resource.PcieInfo.PortInfo[port].Function; + uint32_t bus = iio_resource.StackRes[stack].BusBase; + uint32_t dev = iio_resource.PcieInfo.PortInfo[port].Device; + uint32_t func = iio_resource.PcieInfo.PortInfo[port].Function; + + /* TODO: remove this workaround when the IPS ticket is resolved. */ + if (port == PORT_1A || port == PORT_2A || port == PORT_3A) + dev = 0x0; + else if (port == PORT_1B || port == PORT_2B || port == PORT_3B) + dev = 0x1; + else if (port == PORT_1C || port == PORT_2C || port == PORT_3C) + dev = 0x2; + else if (port == PORT_1D || port == PORT_2D || port == PORT_3D) + dev = 0x3; + func = 0x0; const uint32_t id = pci_mmio_read_config32(PCI_DEV(bus, dev, func), PCI_VENDOR_ID); @@ -660,6 +671,10 @@ printk(BIOS_SPEW, "%s socket: %d, stack: %d, bus: 0x%x, pcie_seg: 0x%x, reg_base: 0x%x\n", __func__, socket, stack, bus, pcie_seg, reg_base); + /* Do not generate DRHD for non-PCIe stack */ + if (reg_base == 0x0) + return current; + // Add DRHD Hardware Unit if (socket == 0 && stack == CSTACK) { printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, " -- To view, visit https://review.coreboot.org/c/coreboot/+/45887 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I098605daf12a264f390613581427ec722afcddaf Gerrit-Change-Number: 45887 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: newchange

3 11

Change in coreboot[master]: soc/intel/tigerlake: Replace soc_get_pmc_mux_device with device pointers
by Tim Wawrzynczak (Code Review) 09 Oct '20

09 Oct '20

Hello build bot (Jenkins), Furquan Shaikh, Caveh Jalali, Duncan Laurie, Nick Vaccaro, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45747 to look at the new patch set (#5). Change subject: soc/intel/tigerlake: Replace soc_get_pmc_mux_device with device pointers ...................................................................... soc/intel/tigerlake: Replace soc_get_pmc_mux_device with device pointers Now that device aliases can be used in the devicetree, the hacky function 'soc_get_pmc_mux_device' can be removed and replaced with pointers to the devices the function was supposed to return (1 for each port). Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: Ie00834c79bd5304998adaccb388ae74a108192b1 --- M src/ec/google/chromeec/chip.h M src/ec/google/chromeec/ec_acpi.c M src/soc/intel/common/block/include/intelblocks/pmc.h M src/soc/intel/tigerlake/pmc.c 4 files changed, 15 insertions(+), 73 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/45747/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/45747 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie00834c79bd5304998adaccb388ae74a108192b1 Gerrit-Change-Number: 45747 Gerrit-PatchSet: 5 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: drivers/intel/gma/acpi: Convert 'configure_brightness_levels.asl' to ...
by HAOUAS Elyes (Code Review) 09 Oct '20

09 Oct '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45782 ) Change subject: drivers/intel/gma/acpi: Convert 'configure_brightness_levels.asl' to ASL+ syntax ...................................................................... drivers/intel/gma/acpi: Convert 'configure_brightness_levels.asl' to ASL+ syntax Generated build/dsdt.dsl are same. Change-Id: I8789ee129d1c42a36f30344655286b3c55f4f2c7 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/drivers/intel/gma/acpi/configure_brightness_levels.asl 1 file changed, 27 insertions(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/45782/1 diff --git a/src/drivers/intel/gma/acpi/configure_brightness_levels.asl b/src/drivers/intel/gma/acpi/configure_brightness_levels.asl index 0ab93d8..9db6bfb 100644 --- a/src/drivers/intel/gma/acpi/configure_brightness_levels.asl +++ b/src/drivers/intel/gma/acpi/configure_brightness_levels.asl @@ -42,48 +42,48 @@ */ Method (XBCM, 1, Serialized) { - If (LEqual(ASLS, Zero)) + If (ASLS == 0) { Return (Ones) } - If (LEqual(And(MBOX, 0x4), Zero)) + If ((MBOX & 0x4) == 0) { Return (Ones) } /* Always keep BCLP up to date, even if driver is not ready. It requires a full 8-bit brightness value. 255 = 100% */ - Store (Divide (Multiply (Arg0, 255), 100), Local1) - If (LGreater(Local1, 255)) { - Store (255, Local1) + Local1 = (Arg0 * 255) / 100 + If (Local1 > 255) { + Local1 = 255 } /* also set valid bit */ - Store (Or (Local1, 0x80000000), BCLP) + BCLP = Local1 | 0x80000000 - If (LEqual(ARDY, Zero)) + If (ARDY == 0) { Return (Ones) } /* Request back-light change */ - Store (0x2, ASLC) + ASLC = 0x2 /* Trigger IRQ */ - Store (0x1, ASLE) + ASLE = 0x1 - Store (0x20, Local0) - While (LGreater(Local0, Zero)) + Local0 = 0x20 + While (Local0 > 0) { Sleep (1) - If (LEqual (And (ASLC, 0x2), 0)) { + If ((ASLC & 0x2) == 0) { /* Request has been processed, check status: */ - And (ShiftRight (ASLC, 12), 0x3, Local1) - If (LEqual (Local1, 0)) { + Local1 = (ASLC >> 12) & 0x3 + If (Local1 == 0) { Return (Zero) } Else { Return (Ones) } } - Decrement (Local0) + Local0-- } Return (Ones) @@ -100,12 +100,12 @@ /* Divide round closest */ Method (DRCL, 2) { - Return (Divide (Add (Arg0, Divide (Arg1, 2)), Arg1)) + Return ((Arg0 + (Arg1 / 0x02)) / Arg1) } Method (XBCM, 1, NotSerialized) { - Store (DRCL (Multiply (Arg0, BCLM), 100), BCLV) + BCLV = DRCL ((Arg0 * BCLM), 100) } /* Find value closest to BCLV in BRIG (which must be ordered) */ @@ -117,26 +117,24 @@ Return (Zero) } /* Local0: current percentage */ - Store (DRCL (Multiply (BCLV, 100), BCLM), Local0) + Local0 = DRCL ((BCLV * 0x64), BCLM) /* Local1: loop index (selectable values start at 2 in BRIG) */ - Store (2, Local1) - While (LLess (Local1, Subtract (SizeOf (BRIG), 1))) { + Local1 = 2 + While (Local1 < (SizeOf (BRIG) -1)) { /* Local[23]: adjacent values in BRIG */ - Store (DeRefOf (Index (BRIG, Local1)), Local2) - Store (DeRefOf (Index (BRIG, Add (Local1, 1))), Local3) - - If (LLess (Local0, Local3)) { - If (LOr (LLess (Local0, Local2), - LLess (Subtract (Local0, Local2), - Subtract (Local3, Local0)))) { + Local2 = DerefOf (BRIG [Local1]) + Local3 = DerefOf (BRIG [(Local1 + 1)]) + If (Local0 < Local3) { + If ((Local0 < Local2) || + ((Local0 - Local2) < (Local3 - Local0))) { Return (Local2) } Else { Return (Local3) } } - Increment (Local1) + Local1++ } /* Didn't find greater/equal value: use the last */ @@ -146,7 +144,7 @@ Method (XBCM, 1, NotSerialized) { - If (LEqual(^BOX3.XBCM (Arg0), Ones)) + If (^BOX3.XBCM (Arg0) == Ones) { ^LEGA.XBCM (Arg0) } -- To view, visit https://review.coreboot.org/c/coreboot/+/45782 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8789ee129d1c42a36f30344655286b3c55f4f2c7 Gerrit-Change-Number: 45782 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 7

Change in coreboot[master]: soc/intel/jasperlake: Correct SaGv mapping
by Tim Wawrzynczak (Code Review) 09 Oct '20

09 Oct '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45195 ) Change subject: soc/intel/jasperlake: Correct SaGv mapping ...................................................................... Patch Set 2: Hm, buildbot didn't pick this up, maybe try a rebase? -- To view, visit https://review.coreboot.org/c/coreboot/+/45195 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I366de1ea7cf41c56b2954b8032c69bfba81058e2 Gerrit-Change-Number: 45195 Gerrit-PatchSet: 2 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Comment-Date: Fri, 09 Oct 2020 15:37:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/mediatek: Add function to get clock frequency of MT8192
by CK HU (Code Review) 09 Oct '20

09 Oct '20

Hello Weiyi Lu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45402 to review the following change. Change subject: soc/mediatek: Add function to get clock frequency of MT8192 ...................................................................... soc/mediatek: Add function to get clock frequency of MT8192 Implement mt_fmeter_get_freq() in MT8192 to get frequency of some pre-defined clocks in the frequency meter. Signed-off-by: Weiyi Lu <weiyi.lu(a)mediatek.com> Change-Id: I75df0b040ed7ea73d25724a3c80040f4e731118f --- M src/soc/mediatek/common/include/soc/pll_common.h M src/soc/mediatek/mt8192/include/soc/pll.h M src/soc/mediatek/mt8192/pll.c 3 files changed, 80 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/45402/1 diff --git a/src/soc/mediatek/common/include/soc/pll_common.h b/src/soc/mediatek/common/include/soc/pll_common.h index 0f8732f..1787c4b 100644 --- a/src/soc/mediatek/common/include/soc/pll_common.h +++ b/src/soc/mediatek/common/include/soc/pll_common.h @@ -60,4 +60,10 @@ void mt_pll_init(void); void mt_pll_raise_little_cpu_freq(u32 freq); +enum fmeter_type { + FMETER_ABIST = 0, + FMETER_CKGEN +}; +unsigned int mt_fmeter_get_freq(enum fmeter_type type, unsigned int id); + #endif diff --git a/src/soc/mediatek/mt8192/include/soc/pll.h b/src/soc/mediatek/mt8192/include/soc/pll.h index 177bd33..f4a7180 100644 --- a/src/soc/mediatek/mt8192/include/soc/pll.h +++ b/src/soc/mediatek/mt8192/include/soc/pll.h @@ -299,4 +299,10 @@ DEFINE_BITFIELD(PLLGP1_LVRREF, 18, 17) DEFINE_BITFIELD(PLLGP2_LVRREF, 10, 9) +DEFINE_BITFIELD(CLK_DBG_CFG_ABIST_CK_SEL, 21, 16) +DEFINE_BITFIELD(CLK_DBG_CFG_CKGEN_CK_SEL, 13, 8) +DEFINE_BITFIELD(CLK_DBG_CFG_METER_CK_SEL, 1, 0) +DEFINE_BITFIELD(CLK_MISC_CFG_0_METER_DIV, 31, 24) +DEFINE_BITFIELD(CLK26CALI_1_LOAD_CNT, 25, 16) + #endif /* SOC_MEDIATEK_MT8192_PLL_H */ diff --git a/src/soc/mediatek/mt8192/pll.c b/src/soc/mediatek/mt8192/pll.c index e8849df..94dc469 100644 --- a/src/soc/mediatek/mt8192/pll.c +++ b/src/soc/mediatek/mt8192/pll.c @@ -459,3 +459,71 @@ /* disable [4] intermediate clock armpll_divider_pll1_ck */ clrbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 4); } + +unsigned int mt_fmeter_get_freq(enum fmeter_type type, unsigned int id) +{ + unsigned int output = 0, i = 0, count, clk_dbg_cfg, clk_misc_cfg_0; + bool timeout = false; + + /* backup */ + clk_dbg_cfg = read32(&mtk_topckgen->clk_dbg_cfg); + clk_misc_cfg_0 = read32(&mtk_topckgen->clk_misc_cfg_0); + + /* set up frequency meter */ + if (type == FMETER_ABIST) { + SET32_BITFIELDS(&mtk_topckgen->clk_dbg_cfg, + CLK_DBG_CFG_ABIST_CK_SEL, id, + CLK_DBG_CFG_CKGEN_CK_SEL, 0, + CLK_DBG_CFG_METER_CK_SEL, 0); + SET32_BITFIELDS(&mtk_topckgen->clk_misc_cfg_0, + CLK_MISC_CFG_0_METER_DIV, 1); + } else if (type == FMETER_CKGEN) { + SET32_BITFIELDS(&mtk_topckgen->clk_dbg_cfg, + CLK_DBG_CFG_ABIST_CK_SEL, 0, + CLK_DBG_CFG_CKGEN_CK_SEL, id, + CLK_DBG_CFG_METER_CK_SEL, 1); + SET32_BITFIELDS(&mtk_topckgen->clk_misc_cfg_0, + CLK_MISC_CFG_0_METER_DIV, 0); + } else + return 0; + + /* enable frequency meter */ + write32(&mtk_topckgen->clk26cali_0, 0x1000); + + /* set load count = 1024-1 */ + SET32_BITFIELDS(&mtk_topckgen->clk26cali_1, + CLK26CALI_1_LOAD_CNT, 0x3ff); + + /* trigger frequency meter */ + setbits32(&mtk_topckgen->clk26cali_0, 0x10); + + /* wait frequency meter until finished */ + while (read32(&mtk_topckgen->clk26cali_0) & 0x10) { + udelay(10); + i++; + if (i > 20) { + timeout = true; + break; + } + } + + count = read32(&mtk_topckgen->clk26cali_1) & 0xffff; + + output = (count * 26000) / 1024; /* KHz */ + + /* disable frequency meter */ + write32(&mtk_topckgen->clk26cali_0, 0x0000); + + /* restore */ + write32(&mtk_topckgen->clk_dbg_cfg, clk_dbg_cfg); + write32(&mtk_topckgen->clk_misc_cfg_0, clk_misc_cfg_0); + + if (!timeout) { + if (type == FMETER_ABIST) + return (output * 2); + else if (type == FMETER_CKGEN) + return output; + } + + return 0; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/45402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I75df0b040ed7ea73d25724a3c80040f4e731118f Gerrit-Change-Number: 45402 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Weiyi Lu <weiyi.lu(a)mediatek.com> Gerrit-MessageType: newchange

5 19

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit October 2020