Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46033 )
Change subject: drivers/wifi: Drop maxsleep parameter from chip config
......................................................................
drivers/wifi: Drop maxsleep parameter from chip config
This change drops maxsleep parameter from chip config and instead
hardcodes the deepest sleep state from which the WiFi device can wake
the system up from to SLP_TYP_S3. This is similar to how other device
drivers in coreboot report _PRW property in ACPI. It relieves the
users from adding another register attribute to devicetree since all
mainboards configure the same value. If this changes in the future, it
should be easy to bring the maxsleep config parameter back.
BUG=b:169802515
BRANCH=zork
Change-Id: I42131fced008da0d51f0f777b7f2d99deaf68827
Signed-off-by: Furquan Shaikh <furquan(a)google.com>
---
M src/drivers/intel/wifi/wifi.c
M src/drivers/wifi/generic/chip.h
M src/drivers/wifi/generic/generic.c
M src/mainboard/google/dedede/variants/madoo/overridetree.cb
M src/mainboard/google/dedede/variants/magolor/overridetree.cb
M src/mainboard/google/dedede/variants/waddledee/overridetree.cb
6 files changed, 3 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/46033/1
diff --git a/src/drivers/intel/wifi/wifi.c b/src/drivers/intel/wifi/wifi.c
index f768b04..6010673 100644
--- a/src/drivers/intel/wifi/wifi.c
+++ b/src/drivers/intel/wifi/wifi.c
@@ -49,11 +49,9 @@
struct drivers_intel_wifi_config *config = dev->chip_info;
struct drivers_wifi_generic_config generic_config;
- if (config) {
+ if (config)
generic_config.wake = config->wake;
- /* By default, all intel wifi chips wake from S3 */
- generic_config.maxsleep = 3;
- }
+
wifi_generic_fill_ssdt(dev, config ? &generic_config : NULL);
}
#endif
diff --git a/src/drivers/wifi/generic/chip.h b/src/drivers/wifi/generic/chip.h
index fe3a1d1..02ab504 100644
--- a/src/drivers/wifi/generic/chip.h
+++ b/src/drivers/wifi/generic/chip.h
@@ -6,11 +6,9 @@
/**
* struct drivers_wifi_generic_config - Data structure to contain generic wifi config
* @wake: Wake pin for ACPI _PRW
- * @maxsleep: Maximum sleep state to wake from
*/
struct drivers_wifi_generic_config {
unsigned int wake;
- unsigned int maxsleep;
};
/**
diff --git a/src/drivers/wifi/generic/generic.c b/src/drivers/wifi/generic/generic.c
index 059185d..903afdc 100644
--- a/src/drivers/wifi/generic/generic.c
+++ b/src/drivers/wifi/generic/generic.c
@@ -189,7 +189,7 @@
/* Wake capabilities */
if (config)
- acpigen_write_PRW(config->wake, config->maxsleep);
+ acpigen_write_PRW(config->wake, SLP_TYP_S3);
/* Fill regulatory domain structure */
if (CONFIG(HAVE_REGULATORY_DOMAIN)) {
diff --git a/src/mainboard/google/dedede/variants/madoo/overridetree.cb b/src/mainboard/google/dedede/variants/madoo/overridetree.cb
index 039fd10..257f917 100644
--- a/src/mainboard/google/dedede/variants/madoo/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/madoo/overridetree.cb
@@ -103,7 +103,6 @@
device pci 1c.7 on
chip drivers/wifi/generic
register "wake" = "GPE0_DW2_03"
- register "maxsleep" = "3"
device pci 00.0 on end
end
end # PCI Express Root Port 8 - WLAN
diff --git a/src/mainboard/google/dedede/variants/magolor/overridetree.cb b/src/mainboard/google/dedede/variants/magolor/overridetree.cb
index 8a83b83..f41e9fa 100644
--- a/src/mainboard/google/dedede/variants/magolor/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/magolor/overridetree.cb
@@ -287,7 +287,6 @@
device pci 1c.7 on
chip drivers/wifi/generic
register "wake" = "GPE0_DW2_03"
- register "maxsleep" = "3"
device pci 00.0 on end
end
end # PCI Express Root Port 8 - WLAN
diff --git a/src/mainboard/google/dedede/variants/waddledee/overridetree.cb b/src/mainboard/google/dedede/variants/waddledee/overridetree.cb
index a525a0f..22a08a0 100644
--- a/src/mainboard/google/dedede/variants/waddledee/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/waddledee/overridetree.cb
@@ -147,7 +147,6 @@
device pci 1c.7 on
chip drivers/wifi/generic
register "wake" = "GPE0_DW2_03"
- register "maxsleep" = "3"
device pci 00.0 on end
end
end # PCI Express Root Port 8 - WLAN
--
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Gerrit-Change-Id: I42131fced008da0d51f0f777b7f2d99deaf68827
Gerrit-Change-Number: 46033
Gerrit-PatchSet: 1
Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>
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Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46030 )
Change subject: pci_device: Add a helper function for logging PCI device as wake source
......................................................................
pci_device: Add a helper function for logging PCI device as wake source
This change adds a helper function `pci_dev_log_wake()` that checks
PME_STATUS and PME_ENABLE bits in PM control and status register to
determine if the given device is the source of wake and logs it in
eventlog if CONFIG_ELOG is selected. The caller is expected to pass in
the source_id and instance that will be passed into
`elog_add_event_wake()`.
BUG=b:169802515
BRANCH=zork
Change-Id: I06e9530b568543ab2f05a4f38dc5c3a527ff391e
Signed-off-by: Furquan Shaikh <furquan(a)google.com>
---
M src/device/pci_device.c
M src/include/device/pci.h
2 files changed, 33 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/46030/1
diff --git a/src/device/pci_device.c b/src/device/pci_device.c
index 8a6f123..06e1228 100644
--- a/src/device/pci_device.c
+++ b/src/device/pci_device.c
@@ -20,6 +20,7 @@
#include <device/pcix.h>
#include <device/pciexp.h>
#include <device/hypertransport.h>
+#include <elog.h>
#include <pc80/i8259.h>
#include <security/vboot/vbnv.h>
#include <timestamp.h>
@@ -1643,3 +1644,28 @@
pci_update_config16(dev, PCI_COMMAND, ~PCI_COMMAND_MASTER, 0x0);
}
#endif
+
+void pci_dev_log_wake(const struct device *dev, uint8_t source_id, uint32_t instance)
+{
+ unsigned int pm_cap;
+ uint16_t pmcs;
+
+ if (!CONFIG(ELOG))
+ return;
+
+ if (dev->path.type != DEVICE_PATH_PCI)
+ return;
+
+ pm_cap = pci_find_capability(dev, PCI_CAP_ID_PM);
+ if (!pm_cap)
+ return;
+
+ pmcs = pci_read_config16(dev, pm_cap + PCI_PM_CTRL);
+ if (!(pmcs & PCI_PM_CTRL_PME_ENABLE))
+ return;
+
+ if (!(pmcs & PCI_PM_CTRL_PME_STATUS))
+ return;
+
+ elog_add_event_wake(source_id, instance);
+}
diff --git a/src/include/device/pci.h b/src/include/device/pci.h
index 6e28cb7..87702e2 100644
--- a/src/include/device/pci.h
+++ b/src/include/device/pci.h
@@ -80,6 +80,13 @@
struct device *pci_probe_dev(struct device *dev, struct bus *bus,
unsigned int devfn);
+/*
+ * Determine if the given PCI device is the source of wake from sleep by checking PME_STATUS and
+ * PME_ENABLE bits in PM control and status register and log the given source_id and instance in
+ * elog.
+ */
+void pci_dev_log_wake(const struct device *dev, uint8_t source_id, uint32_t instance);
+
void do_pci_scan_bridge(struct device *dev,
void (*do_scan_bus)(struct bus *bus,
unsigned int min_devfn, unsigned int max_devfn));
--
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Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46270 )
Change subject: mb/google/puff: Enable SATA0 on wyvern
......................................................................
Patch Set 2: Code-Review+2
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Gerrit-Change-Number: 46270
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Sam McNally has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46270 )
Change subject: mb/google/puff: Enable SATA0 on wyvern
......................................................................
Patch Set 2:
This change is ready for review.
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45196 )
Change subject: mb/google/dedede: Enable SaGv support
......................................................................
Patch Set 4: Code-Review+1
(3 comments)
https://review.coreboot.org/c/coreboot/+/45196/4//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/coreboot/+/45196/4//COMMIT_MSG@7
PS4, Line 7: SaGv support
Does SaGv support depend on mainboard components (e.g. VR), or can it be enabled on any mainboard?
I've been thinking about moving the SaGv settings to Kconfig, so that one can easily choose which mode to use without having to edit the devicetree.
https://review.coreboot.org/c/coreboot/+/45196/4//COMMIT_MSG@9
PS4, Line 9:
nit: no space before the comma
https://review.coreboot.org/c/coreboot/+/45196/4//COMMIT_MSG@11
PS4, Line 11:
same here
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