coreboot-gerrit October 2020

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Change in coreboot[master]: soc/intel/cnl: lock AES-NI feature
by Michael Niewöhner (Code Review) 11 Oct '20

11 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46273 ) Change subject: soc/intel/cnl: lock AES-NI feature ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/46273 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79495bfbd3ebf3b712ce9ecf2040cecfd954178d Gerrit-Change-Number: 46273 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Sun, 11 Oct 2020 11:23:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/{common,skl}: move AES-NI locking to common code
by Michael Niewöhner (Code Review) 11 Oct '20

11 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46272 ) Change subject: soc/intel/{common,skl}: move AES-NI locking to common code ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/46272 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81ad5c0d4797b139435c57d3af0a95db94a5c15e Gerrit-Change-Number: 46272 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Sun, 11 Oct 2020 11:23:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: ec/kontron: add option to configure I2C frequency
by Maxim Polyakov (Code Review) 11 Oct '20

11 Oct '20

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44476 ) Change subject: ec/kontron: add option to configure I2C frequency ...................................................................... ec/kontron: add option to configure I2C frequency Allows to change the frequency for the I2C bus by overriding i2c_freq_khz option from the devicetree of the board. Tested on Kontron mAL10 COMe module with T10-TNI carrierboard [1,2]. [1] https: //review.coreboot.org/c/coreboot/+/39133 [2] https: //review.coreboot.org/c/coreboot/+/39846 Change-Id: If0eb477af10d00eb4f17f9c01209f170b746ad3d Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/ec/kontron/kempld/chip.h M src/ec/kontron/kempld/kempld_i2c.c 2 files changed, 22 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/44476/1 diff --git a/src/ec/kontron/kempld/chip.h b/src/ec/kontron/kempld/chip.h index 8ca8d24..2ac0949 100644 --- a/src/ec/kontron/kempld/chip.h +++ b/src/ec/kontron/kempld/chip.h @@ -19,6 +19,7 @@ struct ec_kontron_kempld_config { struct kempld_uart uart[KEMPLD_NUM_UARTS]; + unsigned short i2c_freq_khz; }; #endif /* EC_KONTRON_KEMPLD_CHIP_H */ diff --git a/src/ec/kontron/kempld/kempld_i2c.c b/src/ec/kontron/kempld/kempld_i2c.c index 296cf76..9ba2f71 100644 --- a/src/ec/kontron/kempld/kempld_i2c.c +++ b/src/ec/kontron/kempld/kempld_i2c.c @@ -13,6 +13,7 @@ #include <timer.h> #include <delay.h> +#include "chip.h" #include "kempld.h" #include "kempld_internal.h" @@ -40,8 +41,8 @@ #define I2C_CMD_READ_NACK 0x29 #define I2C_CMD_IACK 0x01 -#define KEMPLD_I2C_FREQ_MAX 2700 /* 2.7 mHz */ -#define KEMPLD_I2C_FREQ_STD 100 /* 100 kHz */ +#define KEMPLD_I2C_FREQ_MAX 2700 /* 2.7 mHz */ +#define KEMPLD_I2C_FREQ_STD_DEFAULT 100 /* 100 kHz */ #define EIO 5 #define ENXIO 6 @@ -230,12 +231,17 @@ void kempld_i2c_device_init(struct device *const dev) { + const struct ec_kontron_kempld_config *const config = dev->chip_info; + unsigned short frequency; u16 prescale_corr; long prescale; u8 ctrl; u8 stat; u8 cfg; + if (!config) + return; + if (kempld_get_mutex(100) < 0) return; @@ -244,11 +250,22 @@ ctrl &= ~(I2C_CTRL_EN | I2C_CTRL_IEN); kempld_write8(KEMPLD_I2C_CTRL, ctrl); + frequency = KEMPLD_I2C_FREQ_STD_DEFAULT; + if (config->i2c_freq_khz) { + if (config->i2c_freq_khz <= KEMPLD_I2C_FREQ_MAX) + frequency = config->i2c_freq_khz; + else + printk(BIOS_WARNING, + "kempld_i2c: %d kHz is an invalid frequency value\n", + config->i2c_freq_khz); + } + printk(BIOS_INFO, "kempld_i2c: Use frequency %d\n", frequency); + const u8 spec_major = KEMPLD_SPEC_GET_MAJOR(kempld_read8(KEMPLD_SPEC)); if (spec_major == 1) - prescale = KEMPLD_CLK / (KEMPLD_I2C_FREQ_STD * 5) - 1000; + prescale = KEMPLD_CLK / (frequency * 5) - 1000; else - prescale = KEMPLD_CLK / (KEMPLD_I2C_FREQ_STD * 4) - 3000; + prescale = KEMPLD_CLK / (frequency * 4) - 3000; if (prescale < 0) prescale = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/44476 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If0eb477af10d00eb4f17f9c01209f170b746ad3d Gerrit-Change-Number: 44476 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/clevo/l140cu: drop disabled SPD indices
by Michael Niewöhner (Code Review) 11 Oct '20

11 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46248 ) Change subject: mb/clevo/l140cu: drop disabled SPD indices ...................................................................... Patch Set 2: (2 comments) https://review.coreboot.org/c/coreboot/+/46248/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/46248/1//COMMIT_MSG@7 PS1, Line 7: channels > what is being dropped corresponds to the 2nd slot of each channel, so `indices` would be more correc […] indeed, done https://review.coreboot.org/c/coreboot/+/46248/1//COMMIT_MSG@9 PS1, Line 9: channels > indices Done -- To view, visit https://review.coreboot.org/c/coreboot/+/46248 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d88bdac17222c2c5c35439517fe0bea46744b2b Gerrit-Change-Number: 46248 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 11 Oct 2020 09:32:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/clevo/l140cu: set PS/2 timeout for SeaBIOS
by Michael Niewöhner (Code Review) 11 Oct '20

11 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45959 ) Change subject: mb/clevo/l140cu: set PS/2 timeout for SeaBIOS ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/45959/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/45959/1//COMMIT_MSG@12 PS1, Line 12: successfully > Please elaborate. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/45959 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2be75961035f04a7ffa6f7e1dbaabb1243b857f9 Gerrit-Change-Number: 45959 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 11 Oct 2020 09:32:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/clevo/l140cu: rework memcfg
by Michael Niewöhner (Code Review) 11 Oct '20

11 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46249 ) Change subject: mb/clevo/l140cu: rework memcfg ...................................................................... Patch Set 2: (8 comments) https://review.coreboot.org/c/coreboot/+/46249/1/src/mainboard/clevo/cml-u/… File src/mainboard/clevo/cml-u/variants/l140cu/romstage.c: https://review.coreboot.org/c/coreboot/+/46249/1/src/mainboard/clevo/cml-u/… PS1, Line 7: /* Parameters required to access SPD for CH0D0/CH0D1/CH1D0/CH1D1. */ > Please drop this comment Done https://review.coreboot.org/c/coreboot/+/46249/1/src/mainboard/clevo/cml-u/… PS1, Line 10: .spd_spec = {.spd_index = 0}, > reading my previous comment again, don't remove the index = 0. it's intentionally zero. whatever I was thinking (probably I was *not* thinking at all)... just ignore my comment o.O https://review.coreboot.org/c/coreboot/+/46249/1/src/mainboard/clevo/cml-u/… PS1, Line 20: DRAM > lol. no. Done https://review.coreboot.org/c/coreboot/+/46249/1/src/mainboard/clevo/cml-u/… PS1, Line 25: These will typically be the following : * values for Cannon Lake : { 80, 40, 40, 40, 30 } > Drop these Done https://review.coreboot.org/c/coreboot/+/46249/1/src/mainboard/clevo/cml-u/… PS1, Line 31: Indicates whether memory is interleaved. : * Set to 1 for an interleaved design, : * set to 0 for non-interleaved design. > 😄 Done https://review.coreboot.org/c/coreboot/+/46249/1/src/mainboard/clevo/cml-u/… PS1, Line 38: * VREF_CA configuration. : * Set to 0 VREF_CA goes to both CH_A and CH_B, : * set to 1 VREF_CA goes to CH_A and VREF_DQ_A goes to CH_B, : * set to 2 VREF_CA goes to CH_A and VREF_DQ_B goes to CH_B. > Replace this with something that explains the chosen value: https://review.coreboot. […] Done https://review.coreboot.org/c/coreboot/+/46249/1/src/mainboard/clevo/cml-u/… PS1, Line 45: /* Early Command Training */ > Same here: https://review.coreboot. […] Done https://review.coreboot.org/c/coreboot/+/46249/1/src/mainboard/clevo/cml-u/… PS1, Line 46: .ect = 0, already initialized to zero. dropped -- To view, visit https://review.coreboot.org/c/coreboot/+/46249 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32f1b7bb46eaaf0f0ecad1df310f5de988f64c85 Gerrit-Change-Number: 46249 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 11 Oct 2020 09:32:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/clevo/l140cu: rework memcfg
by Michael Niewöhner (Code Review) 11 Oct '20

11 Oct '20

Hello Felix Singer, build bot (Jenkins), Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46249 to look at the new patch set (#2). Change subject: mb/clevo/l140cu: rework memcfg ...................................................................... mb/clevo/l140cu: rework memcfg The DQ and DQS byte maps do not apply to DDR4 configurations, thus simply drop them. Also drop ect, as it's already initialized to zero. Further, correct all the meaningless and/or wrong comments. Change-Id: I32f1b7bb46eaaf0f0ecad1df310f5de988f64c85 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/mainboard/clevo/cml-u/variants/l140cu/romstage.c 1 file changed, 5 insertions(+), 51 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/46249/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/46249 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32f1b7bb46eaaf0f0ecad1df310f5de988f64c85 Gerrit-Change-Number: 46249 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/clevo/l140cu: drop disabled SPD indices
by Michael Niewöhner (Code Review) 11 Oct '20

11 Oct '20

Hello Felix Singer, build bot (Jenkins), Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46248 to look at the new patch set (#2). Change subject: mb/clevo/l140cu: drop disabled SPD indices ...................................................................... mb/clevo/l140cu: drop disabled SPD indices Drop the disabled SPD indices from memcfg, since they're already initialized to 0. Change-Id: I6d88bdac17222c2c5c35439517fe0bea46744b2b Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/mainboard/clevo/cml-u/variants/l140cu/romstage.c 1 file changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/46248/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/46248 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d88bdac17222c2c5c35439517fe0bea46744b2b Gerrit-Change-Number: 46248 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/clevo/l140cu: drop USE_LEGACY_8254_TIMER
by Michael Niewöhner (Code Review) 11 Oct '20

11 Oct '20

Hello Felix Singer, build bot (Jenkins), Angel Pons, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45960 to look at the new patch set (#2). Change subject: mb/clevo/l140cu: drop USE_LEGACY_8254_TIMER ...................................................................... mb/clevo/l140cu: drop USE_LEGACY_8254_TIMER Drop USE_LEGACY_8254_TIMER, since it's not required anymore for booting grub, despite the comment. The issue was resolved upstream three years ago: http://git.savannah.gnu.org/cgit/grub.git/commit/?id=446794de8da4329ea532cb… Test: - Boot EFI GRUB2 from TianoCore payload (Debian Live, Ubuntu installer) - Boot GRUB2 payload Change-Id: I5ce4f5168586bf305969b2e24b6ee895c8552749 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/mainboard/clevo/cml-u/Kconfig 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/45960/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/45960 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ce4f5168586bf305969b2e24b6ee895c8552749 Gerrit-Change-Number: 45960 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/clevo/l140cu: set PS/2 timeout for SeaBIOS
by Michael Niewöhner (Code Review) 11 Oct '20

11 Oct '20

Hello Felix Singer, build bot (Jenkins), Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45959 to look at the new patch set (#2). Change subject: mb/clevo/l140cu: set PS/2 timeout for SeaBIOS ...................................................................... mb/clevo/l140cu: set PS/2 timeout for SeaBIOS The keyboard only works randomly, because SeaBIOS initializes PS/2 before the EC is ready. Set the PS/2 timeout for SeaBIOS to 500 ms, to wait for the EC before initializing the keyboard. Test: keyboard works fine. Change-Id: I2be75961035f04a7ffa6f7e1dbaabb1243b857f9 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/mainboard/clevo/cml-u/Kconfig 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/45959/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/45959 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2be75961035f04a7ffa6f7e1dbaabb1243b857f9 Gerrit-Change-Number: 45959 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit October 2020