coreboot-gerrit October 2020

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Change in coreboot[master]: mb/google/dedede: Enable SaGv support
by Angel Pons (Code Review) 10 Oct '20

10 Oct '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45196 ) Change subject: mb/google/dedede: Enable SaGv support ...................................................................... Patch Set 4: Code-Review+1 (3 comments) https://review.coreboot.org/c/coreboot/+/45196/4//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/45196/4//COMMIT_MSG@7 PS4, Line 7: SaGv support Does SaGv support depend on mainboard components (e.g. VR), or can it be enabled on any mainboard? I've been thinking about moving the SaGv settings to Kconfig, so that one can easily choose which mode to use without having to edit the devicetree. https://review.coreboot.org/c/coreboot/+/45196/4//COMMIT_MSG@9 PS4, Line 9: nit: no space before the comma https://review.coreboot.org/c/coreboot/+/45196/4//COMMIT_MSG@11 PS4, Line 11: same here -- To view, visit https://review.coreboot.org/c/coreboot/+/45196 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f60aad031ce9dfe23e54426753311c35db46c05 Gerrit-Change-Number: 45196 Gerrit-PatchSet: 4 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 10 Oct 2020 21:31:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/clevo/l140cu: drop USE_LEGACY_8254_TIMER
by Angel Pons (Code Review) 10 Oct '20

10 Oct '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45960 ) Change subject: mb/clevo/l140cu: drop USE_LEGACY_8254_TIMER ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/45960 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ce4f5168586bf305969b2e24b6ee895c8552749 Gerrit-Change-Number: 45960 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sat, 10 Oct 2020 21:22:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/clevo/l140cu: set PS/2 timeout for SeaBIOS
by Angel Pons (Code Review) 10 Oct '20

10 Oct '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45959 ) Change subject: mb/clevo/l140cu: set PS/2 timeout for SeaBIOS ...................................................................... Patch Set 1: Code-Review+1 (1 comment) https://review.coreboot.org/c/coreboot/+/45959/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/45959/1//COMMIT_MSG@12 PS1, Line 12: successfully Please elaborate. Was something not working before? Is it working now? -- To view, visit https://review.coreboot.org/c/coreboot/+/45959 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2be75961035f04a7ffa6f7e1dbaabb1243b857f9 Gerrit-Change-Number: 45959 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 10 Oct 2020 21:22:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/clevo/l140cu: drop disabled SPD channels
by Angel Pons (Code Review) 10 Oct '20

10 Oct '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46248 ) Change subject: mb/clevo/l140cu: drop disabled SPD channels ...................................................................... Patch Set 1: Code-Review+2 (2 comments) https://review.coreboot.org/c/coreboot/+/46248/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/46248/1//COMMIT_MSG@7 PS1, Line 7: channels what is being dropped corresponds to the 2nd slot of each channel, so `indices` would be more correct. https://review.coreboot.org/c/coreboot/+/46248/1//COMMIT_MSG@9 PS1, Line 9: channels indices -- To view, visit https://review.coreboot.org/c/coreboot/+/46248 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d88bdac17222c2c5c35439517fe0bea46744b2b Gerrit-Change-Number: 46248 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 10 Oct 2020 21:21:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/clevo/l140cu: Correct FSP-M UPDs
by Angel Pons (Code Review) 10 Oct '20

10 Oct '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46249 ) Change subject: mb/clevo/l140cu: Correct FSP-M UPDs ...................................................................... Patch Set 1: (2 comments) https://review.coreboot.org/c/coreboot/+/46249/1/src/mainboard/clevo/cml-u/… File src/mainboard/clevo/cml-u/variants/l140cu/romstage.c: https://review.coreboot.org/c/coreboot/+/46249/1/src/mainboard/clevo/cml-u/… PS1, Line 7: /* Parameters required to access SPD for CH0D0/CH0D1/CH1D0/CH1D1. */ Please drop this comment https://review.coreboot.org/c/coreboot/+/46249/1/src/mainboard/clevo/cml-u/… PS1, Line 10: .spd_spec = {.spd_index = 0}, > already done in CB:46248 ;) reading my previous comment again, don't remove the index = 0. it's intentionally zero. -- To view, visit https://review.coreboot.org/c/coreboot/+/46249 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32f1b7bb46eaaf0f0ecad1df310f5de988f64c85 Gerrit-Change-Number: 46249 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 10 Oct 2020 21:20:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/clevo/l140cu: Correct FSP-M UPDs
by Michael Niewöhner (Code Review) 10 Oct '20

10 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46249 ) Change subject: mb/clevo/l140cu: Correct FSP-M UPDs ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/c/coreboot/+/46249/1/src/mainboard/clevo/cml-u/… File src/mainboard/clevo/cml-u/variants/l140cu/romstage.c: https://review.coreboot.org/c/coreboot/+/46249/1/src/mainboard/clevo/cml-u/… PS1, Line 10: .spd_spec = {.spd_index = 0}, > nit: this is redundant, as the non-initialized struct members default to zero already done in CB:46248 ;) -- To view, visit https://review.coreboot.org/c/coreboot/+/46249 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32f1b7bb46eaaf0f0ecad1df310f5de988f64c85 Gerrit-Change-Number: 46249 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 10 Oct 2020 20:09:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/ironlake: Move register headers into a subfolder
by Angel Pons (Code Review) 10 Oct '20

10 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45381 ) Change subject: nb/intel/ironlake: Move register headers into a subfolder ...................................................................... nb/intel/ironlake: Move register headers into a subfolder Move all files with register definitions into a `registers` subfolder. Subsequent commits will move the remaining registers into this folder. Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical. Change-Id: I872269ca3c7fbbcffe83327a20bcf8d98b356beb Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/ironlake/ironlake.h R src/northbridge/intel/ironlake/registers/host_bridge.h 2 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/45381/1 diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h index 9ff9760..5a846d1 100644 --- a/src/northbridge/intel/ironlake/ironlake.h +++ b/src/northbridge/intel/ironlake/ironlake.h @@ -36,7 +36,7 @@ /* Device 0:0.0 PCI configuration space (Host Bridge) */ -#include "hostbridge_regs.h" +#include "registers/host_bridge.h" /* * Generic Non-Core Registers diff --git a/src/northbridge/intel/ironlake/hostbridge_regs.h b/src/northbridge/intel/ironlake/registers/host_bridge.h similarity index 78% rename from src/northbridge/intel/ironlake/hostbridge_regs.h rename to src/northbridge/intel/ironlake/registers/host_bridge.h index a681734..0322a51 100644 --- a/src/northbridge/intel/ironlake/hostbridge_regs.h +++ b/src/northbridge/intel/ironlake/registers/host_bridge.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __IRONLAKE_HOSTBRIDGE_REGS_H__ -#define __IRONLAKE_HOSTBRIDGE_REGS_H__ +#ifndef __IRONLAKE_REGISTERS_HOST_BRIDGE_H__ +#define __IRONLAKE_REGISTERS_HOST_BRIDGE_H__ #define EPBAR 0x40 #define MCHBAR 0x48 @@ -28,4 +28,4 @@ #define CAPID0 0xe0 -#endif /* __IRONLAKE_HOSTBRIDGE_REGS_H__ */ +#endif /* __IRONLAKE_REGISTERS_HOST_BRIDGE_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/45381 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I872269ca3c7fbbcffe83327a20bcf8d98b356beb Gerrit-Change-Number: 45381 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/ironlake: Clean up DMIBAR/EPBAR registers
by Angel Pons (Code Review) 10 Oct '20

10 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45380 ) Change subject: nb/intel/ironlake: Clean up DMIBAR/EPBAR registers ...................................................................... nb/intel/ironlake: Clean up DMIBAR/EPBAR registers Several registers have been copy-pasted from i945 and do not exist on Sandy Bridge. Moreover, other register definitions were missing. Use the newly-added definitions in existing code, in place of numerical offsets. Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical. Change-Id: I8ac99166a8029dcdbb59028b4a7ee297249de5db Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/ironlake/ironlake.h M src/northbridge/intel/ironlake/northbridge.c M src/northbridge/intel/ironlake/raminit.c 3 files changed, 29 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/45380/1 diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h index 7198446a..9ff9760 100644 --- a/src/northbridge/intel/ironlake/ironlake.h +++ b/src/northbridge/intel/ironlake/ironlake.h @@ -125,9 +125,6 @@ #define EPVC1RCTL 0x020 /* 32bit */ #define EPVC1RSTS 0x026 /* 16bit */ -#define EPVC1MTS 0x028 /* 32bit */ -#define EPVC1IST 0x038 /* 64bit */ - #define EPESD 0x044 /* 32bit */ #define EPLE1D 0x050 /* 32bit */ @@ -135,8 +132,6 @@ #define EPLE2D 0x060 /* 32bit */ #define EPLE2A 0x068 /* 64bit */ -#define PORTARB 0x100 /* 256bit */ - /* * DMIBAR */ @@ -154,10 +149,22 @@ #define DMIVC0RCAP 0x010 /* 32bit */ #define DMIVC0RCTL 0x014 /* 32bit */ #define DMIVC0RSTS 0x01a /* 16bit */ +#define VC0NP (1 << 1) #define DMIVC1RCAP 0x01c /* 32bit */ #define DMIVC1RCTL 0x020 /* 32bit */ #define DMIVC1RSTS 0x026 /* 16bit */ +#define VC1NP (1 << 1) + +#define DMIVCPRCAP 0x028 /* 32bit */ +#define DMIVCPRCTL 0x02c /* 32bit */ +#define DMIVCPRSTS 0x032 /* 16bit */ +#define VCPNP (1 << 1) + +#define DMIVCMRCAP 0x034 /* 32bit */ +#define DMIVCMRCTL 0x038 /* 32bit */ +#define DMIVCMRSTS 0x03e /* 16bit */ +#define VCMNP (1 << 1) #define DMILE1D 0x050 /* 32bit */ #define DMILE1A 0x058 /* 64bit */ @@ -168,12 +175,12 @@ #define DMILCTL 0x088 /* 16bit */ #define DMILSTS 0x08a /* 16bit */ -#define DMICTL1 0x0f0 /* 32bit */ -#define DMICTL2 0x0fc /* 32bit */ +#define DMIUESTS 0x1c4 /* 32bit */ +#define DMICESTS 0x1d0 /* 32bit */ #define DMICC 0x208 /* 32bit */ -#define DMIDRCCFG 0xeb4 /* 32bit */ +#define DMILLTC 0x238 /* 32bit */ #ifndef __ASSEMBLER__ diff --git a/src/northbridge/intel/ironlake/northbridge.c b/src/northbridge/intel/ironlake/northbridge.c index 1272f5a..6e3ef2c 100644 --- a/src/northbridge/intel/ironlake/northbridge.c +++ b/src/northbridge/intel/ironlake/northbridge.c @@ -148,20 +148,20 @@ u32 reg32; /* Clear error status bits */ - DMIBAR32(0x1c4) = 0xffffffff; - DMIBAR32(0x1d0) = 0xffffffff; + DMIBAR32(DMIUESTS) = 0xffffffff; + DMIBAR32(DMICESTS) = 0xffffffff; - reg32 = DMIBAR32(0x238); + reg32 = DMIBAR32(DMILLTC); reg32 |= (1 << 29); - DMIBAR32(0x238) = reg32; + DMIBAR32(DMILLTC) = reg32; reg32 = DMIBAR32(0x1f8); reg32 |= (1 << 16); DMIBAR32(0x1f8) = reg32; - reg32 = DMIBAR32(0x88); + reg32 = DMIBAR32(DMILCTL); reg32 |= (1 << 1) | (1 << 0); - DMIBAR32(0x88) = reg32; + DMIBAR32(DMILCTL) = reg32; } /* Disable unused PEG devices based on devicetree before PCI enumeration */ diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index 89babdd..3cbc4a8 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -1815,20 +1815,20 @@ pci_read_config32(NORTHBRIDGE, DMIBAR); if (info->memory_reserved_for_heci_mb) { - DMIBAR32(0x14) &= ~0x80; + DMIBAR32(DMIVC0RCTL) &= ~0x80; write32(DEFAULT_RCBA + 0x14, read32(DEFAULT_RCBA + 0x14) & ~0x80); - DMIBAR32(0x20) &= ~0x80; + DMIBAR32(DMIVC1RCTL) &= ~0x80; write32(DEFAULT_RCBA + 0x20, read32(DEFAULT_RCBA + 0x20) & ~0x80); - DMIBAR32(0x2c) &= ~0x80; + DMIBAR32(DMIVCPRCTL) &= ~0x80; write32(DEFAULT_RCBA + 0x30, read32(DEFAULT_RCBA + 0x30) & ~0x80); - DMIBAR32(0x38) &= ~0x80; + DMIBAR32(DMIVCMRCTL) &= ~0x80; write32(DEFAULT_RCBA + 0x40, read32(DEFAULT_RCBA + 0x40) & ~0x80); write32(DEFAULT_RCBA + 0x40, 0x87000080); // OK - DMIBAR32(0x38) = 0x87000080; // OK + DMIBAR32(DMIVCMRCTL) = 0x87000080; // OK while ((read16(DEFAULT_RCBA + 0x46) & 2) && - DMIBAR16(0x3e) & 2) + DMIBAR16(DMIVCMRSTS) & VCMNP) ; } @@ -4605,9 +4605,9 @@ } u32 reg1c; pci_read_config32(NORTHBRIDGE, 0x40); // = DEFAULT_EPBAR | 0x001 // OK - reg1c = EPBAR32(0x01c); // = 0x8001 // OK + reg1c = EPBAR32(EPVC1RCAP); // = 0x8001 // OK pci_read_config32(NORTHBRIDGE, 0x40); // = DEFAULT_EPBAR | 0x001 // OK - EPBAR32(0x01c) = reg1c; // OK + EPBAR32(EPVC1RCAP) = reg1c; // OK MCHBAR8(0xe08); // = 0x0 pci_read_config32(NORTHBRIDGE, 0xe4); // = 0x316126 MCHBAR8_OR(0x1210, 2); -- To view, visit https://review.coreboot.org/c/coreboot/+/45380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ac99166a8029dcdbb59028b4a7ee297249de5db Gerrit-Change-Number: 45380 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/tglrvp: Convert mipi_camera.asl to ASL 2.0 syntax
by Subrata Banik (Code Review) 10 Oct '20

10 Oct '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46269 ) Change subject: mb/intel/tglrvp: Convert mipi_camera.asl to ASL 2.0 syntax ...................................................................... mb/intel/tglrvp: Convert mipi_camera.asl to ASL 2.0 syntax Change-Id: I9e81729213a6f7a2579d10adfb37b145b6d9204b Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/mainboard/intel/tglrvp/acpi/mipi_camera.asl 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/46269/1 diff --git a/src/mainboard/intel/tglrvp/acpi/mipi_camera.asl b/src/mainboard/intel/tglrvp/acpi/mipi_camera.asl index 0f83b05..08bc26b 100644 --- a/src/mainboard/intel/tglrvp/acpi/mipi_camera.asl +++ b/src/mainboard/intel/tglrvp/acpi/mipi_camera.asl @@ -170,7 +170,7 @@ STXS(GPP_C15) Sleep(1) /* t2 */ - Store(1,STA) + STA = 1 } } Method (_OFF, 0, Serialized) /* Rear camera _OFF: Power Off */ @@ -187,7 +187,7 @@ /* Pull PWREN low */ CTXS(GPP_B23) - Store(0,STA) + STA = 0 } } Method (_STA, 0, NotSerialized) /* _STA: Status */ @@ -389,7 +389,7 @@ STXS(GPP_H12) Sleep(1) /* t2 */ - Store(1,STA) + STA = 1 } } Method (_OFF, 0, Serialized) /* Front camera_OFF_: Power Off */ @@ -410,7 +410,7 @@ CTXS(GPP_R6) #endif - Store(0,STA) + STA = 0 } } Method (_STA, 0, NotSerialized) /* _STA: Status */ -- To view, visit https://review.coreboot.org/c/coreboot/+/46269 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e81729213a6f7a2579d10adfb37b145b6d9204b Gerrit-Change-Number: 46269 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/amd/pi/*/dimmSpd.c: Reduce difference
by HAOUAS Elyes (Code Review) 10 Oct '20

10 Oct '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46264 ) Change subject: nb/amd/pi/*/dimmSpd.c: Reduce difference ...................................................................... nb/amd/pi/*/dimmSpd.c: Reduce difference Also add missing <commonlib/helpers.h> to pi/00660F01/dimmSpd.c. Change-Id: Ie072b23e8bac3901c120bc238c415160e992d40c Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/amd/pi/00630F01/dimmSpd.c M src/northbridge/amd/pi/00660F01/dimmSpd.c M src/northbridge/amd/pi/00730F01/dimmSpd.c 3 files changed, 10 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/46264/1 diff --git a/src/northbridge/amd/pi/00630F01/dimmSpd.c b/src/northbridge/amd/pi/00630F01/dimmSpd.c index be3613d..063e4d0 100644 --- a/src/northbridge/amd/pi/00630F01/dimmSpd.c +++ b/src/northbridge/amd/pi/00630F01/dimmSpd.c @@ -8,7 +8,6 @@ #include <Porting.h> #include <AGESA.h> #include "chip.h" - #include <northbridge/amd/pi/dimmSpd.h> AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINTN unused2, AGESA_READ_SPD_PARAMS *info) @@ -26,8 +25,10 @@ if (info->SocketId >= ARRAY_SIZE(config->spdAddrLookup)) return AGESA_ERROR; + if (info->MemChannelId >= ARRAY_SIZE(config->spdAddrLookup[0])) return AGESA_ERROR; + if (info->DimmId >= ARRAY_SIZE(config->spdAddrLookup[0][0])) return AGESA_ERROR; diff --git a/src/northbridge/amd/pi/00660F01/dimmSpd.c b/src/northbridge/amd/pi/00660F01/dimmSpd.c index 0a1281f..591cf34 100644 --- a/src/northbridge/amd/pi/00660F01/dimmSpd.c +++ b/src/northbridge/amd/pi/00660F01/dimmSpd.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <commonlib/helpers.h> #include <device/pci_def.h> #include <device/device.h> @@ -24,14 +25,19 @@ if (info->SocketId >= ARRAY_SIZE(config->spdAddrLookup)) return AGESA_ERROR; + if (info->MemChannelId >= ARRAY_SIZE(config->spdAddrLookup[0])) return AGESA_ERROR; + if (info->DimmId >= ARRAY_SIZE(config->spdAddrLookup[0][0])) return AGESA_ERROR; + spdAddress = config->spdAddrLookup [info->SocketId] [info->MemChannelId] [info->DimmId]; + if (spdAddress == 0) return AGESA_ERROR; + int err = hudson_readSpd(spdAddress, (void *) info->Buffer, 128); if (err) return AGESA_ERROR; diff --git a/src/northbridge/amd/pi/00730F01/dimmSpd.c b/src/northbridge/amd/pi/00730F01/dimmSpd.c index 42dd5a2..05e4f9b 100644 --- a/src/northbridge/amd/pi/00730F01/dimmSpd.c +++ b/src/northbridge/amd/pi/00730F01/dimmSpd.c @@ -8,7 +8,6 @@ #include <Porting.h> #include <AGESA.h> #include "chip.h" - #include <northbridge/amd/pi/dimmSpd.h> AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINTN unused2, AGESA_READ_SPD_PARAMS *info) @@ -26,8 +25,10 @@ if (info->SocketId >= ARRAY_SIZE(config->spdAddrLookup)) return AGESA_ERROR; + if (info->MemChannelId >= ARRAY_SIZE(config->spdAddrLookup[0])) return AGESA_ERROR; + if (info->DimmId >= ARRAY_SIZE(config->spdAddrLookup[0][0])) return AGESA_ERROR; -- To view, visit https://review.coreboot.org/c/coreboot/+/46264 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie072b23e8bac3901c120bc238c415160e992d40c Gerrit-Change-Number: 46264 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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