coreboot-gerrit October 2020

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Change in coreboot[master]: mb/clevo/l140cu: set PS/2 timeout for SeaBIOS
by Angel Pons (Code Review) 10 Oct '20

10 Oct '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45959 ) Change subject: mb/clevo/l140cu: set PS/2 timeout for SeaBIOS ...................................................................... Patch Set 1: Code-Review+1 (1 comment) https://review.coreboot.org/c/coreboot/+/45959/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/45959/1//COMMIT_MSG@12 PS1, Line 12: successfully Please elaborate. Was something not working before? Is it working now? -- To view, visit https://review.coreboot.org/c/coreboot/+/45959 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2be75961035f04a7ffa6f7e1dbaabb1243b857f9 Gerrit-Change-Number: 45959 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 10 Oct 2020 21:22:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/clevo/l140cu: drop disabled SPD channels
by Angel Pons (Code Review) 10 Oct '20

10 Oct '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46248 ) Change subject: mb/clevo/l140cu: drop disabled SPD channels ...................................................................... Patch Set 1: Code-Review+2 (2 comments) https://review.coreboot.org/c/coreboot/+/46248/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/46248/1//COMMIT_MSG@7 PS1, Line 7: channels what is being dropped corresponds to the 2nd slot of each channel, so `indices` would be more correct. https://review.coreboot.org/c/coreboot/+/46248/1//COMMIT_MSG@9 PS1, Line 9: channels indices -- To view, visit https://review.coreboot.org/c/coreboot/+/46248 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d88bdac17222c2c5c35439517fe0bea46744b2b Gerrit-Change-Number: 46248 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 10 Oct 2020 21:21:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/clevo/l140cu: Correct FSP-M UPDs
by Angel Pons (Code Review) 10 Oct '20

10 Oct '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46249 ) Change subject: mb/clevo/l140cu: Correct FSP-M UPDs ...................................................................... Patch Set 1: (2 comments) https://review.coreboot.org/c/coreboot/+/46249/1/src/mainboard/clevo/cml-u/… File src/mainboard/clevo/cml-u/variants/l140cu/romstage.c: https://review.coreboot.org/c/coreboot/+/46249/1/src/mainboard/clevo/cml-u/… PS1, Line 7: /* Parameters required to access SPD for CH0D0/CH0D1/CH1D0/CH1D1. */ Please drop this comment https://review.coreboot.org/c/coreboot/+/46249/1/src/mainboard/clevo/cml-u/… PS1, Line 10: .spd_spec = {.spd_index = 0}, > already done in CB:46248 ;) reading my previous comment again, don't remove the index = 0. it's intentionally zero. -- To view, visit https://review.coreboot.org/c/coreboot/+/46249 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32f1b7bb46eaaf0f0ecad1df310f5de988f64c85 Gerrit-Change-Number: 46249 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 10 Oct 2020 21:20:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/clevo/l140cu: Correct FSP-M UPDs
by Michael Niewöhner (Code Review) 10 Oct '20

10 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46249 ) Change subject: mb/clevo/l140cu: Correct FSP-M UPDs ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/c/coreboot/+/46249/1/src/mainboard/clevo/cml-u/… File src/mainboard/clevo/cml-u/variants/l140cu/romstage.c: https://review.coreboot.org/c/coreboot/+/46249/1/src/mainboard/clevo/cml-u/… PS1, Line 10: .spd_spec = {.spd_index = 0}, > nit: this is redundant, as the non-initialized struct members default to zero already done in CB:46248 ;) -- To view, visit https://review.coreboot.org/c/coreboot/+/46249 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32f1b7bb46eaaf0f0ecad1df310f5de988f64c85 Gerrit-Change-Number: 46249 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 10 Oct 2020 20:09:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/ironlake: Move register headers into a subfolder
by Angel Pons (Code Review) 10 Oct '20

10 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45381 ) Change subject: nb/intel/ironlake: Move register headers into a subfolder ...................................................................... nb/intel/ironlake: Move register headers into a subfolder Move all files with register definitions into a `registers` subfolder. Subsequent commits will move the remaining registers into this folder. Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical. Change-Id: I872269ca3c7fbbcffe83327a20bcf8d98b356beb Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/ironlake/ironlake.h R src/northbridge/intel/ironlake/registers/host_bridge.h 2 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/45381/1 diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h index 9ff9760..5a846d1 100644 --- a/src/northbridge/intel/ironlake/ironlake.h +++ b/src/northbridge/intel/ironlake/ironlake.h @@ -36,7 +36,7 @@ /* Device 0:0.0 PCI configuration space (Host Bridge) */ -#include "hostbridge_regs.h" +#include "registers/host_bridge.h" /* * Generic Non-Core Registers diff --git a/src/northbridge/intel/ironlake/hostbridge_regs.h b/src/northbridge/intel/ironlake/registers/host_bridge.h similarity index 78% rename from src/northbridge/intel/ironlake/hostbridge_regs.h rename to src/northbridge/intel/ironlake/registers/host_bridge.h index a681734..0322a51 100644 --- a/src/northbridge/intel/ironlake/hostbridge_regs.h +++ b/src/northbridge/intel/ironlake/registers/host_bridge.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __IRONLAKE_HOSTBRIDGE_REGS_H__ -#define __IRONLAKE_HOSTBRIDGE_REGS_H__ +#ifndef __IRONLAKE_REGISTERS_HOST_BRIDGE_H__ +#define __IRONLAKE_REGISTERS_HOST_BRIDGE_H__ #define EPBAR 0x40 #define MCHBAR 0x48 @@ -28,4 +28,4 @@ #define CAPID0 0xe0 -#endif /* __IRONLAKE_HOSTBRIDGE_REGS_H__ */ +#endif /* __IRONLAKE_REGISTERS_HOST_BRIDGE_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/45381 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I872269ca3c7fbbcffe83327a20bcf8d98b356beb Gerrit-Change-Number: 45381 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/ironlake: Clean up DMIBAR/EPBAR registers
by Angel Pons (Code Review) 10 Oct '20

10 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45380 ) Change subject: nb/intel/ironlake: Clean up DMIBAR/EPBAR registers ...................................................................... nb/intel/ironlake: Clean up DMIBAR/EPBAR registers Several registers have been copy-pasted from i945 and do not exist on Sandy Bridge. Moreover, other register definitions were missing. Use the newly-added definitions in existing code, in place of numerical offsets. Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical. Change-Id: I8ac99166a8029dcdbb59028b4a7ee297249de5db Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/ironlake/ironlake.h M src/northbridge/intel/ironlake/northbridge.c M src/northbridge/intel/ironlake/raminit.c 3 files changed, 29 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/45380/1 diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h index 7198446a..9ff9760 100644 --- a/src/northbridge/intel/ironlake/ironlake.h +++ b/src/northbridge/intel/ironlake/ironlake.h @@ -125,9 +125,6 @@ #define EPVC1RCTL 0x020 /* 32bit */ #define EPVC1RSTS 0x026 /* 16bit */ -#define EPVC1MTS 0x028 /* 32bit */ -#define EPVC1IST 0x038 /* 64bit */ - #define EPESD 0x044 /* 32bit */ #define EPLE1D 0x050 /* 32bit */ @@ -135,8 +132,6 @@ #define EPLE2D 0x060 /* 32bit */ #define EPLE2A 0x068 /* 64bit */ -#define PORTARB 0x100 /* 256bit */ - /* * DMIBAR */ @@ -154,10 +149,22 @@ #define DMIVC0RCAP 0x010 /* 32bit */ #define DMIVC0RCTL 0x014 /* 32bit */ #define DMIVC0RSTS 0x01a /* 16bit */ +#define VC0NP (1 << 1) #define DMIVC1RCAP 0x01c /* 32bit */ #define DMIVC1RCTL 0x020 /* 32bit */ #define DMIVC1RSTS 0x026 /* 16bit */ +#define VC1NP (1 << 1) + +#define DMIVCPRCAP 0x028 /* 32bit */ +#define DMIVCPRCTL 0x02c /* 32bit */ +#define DMIVCPRSTS 0x032 /* 16bit */ +#define VCPNP (1 << 1) + +#define DMIVCMRCAP 0x034 /* 32bit */ +#define DMIVCMRCTL 0x038 /* 32bit */ +#define DMIVCMRSTS 0x03e /* 16bit */ +#define VCMNP (1 << 1) #define DMILE1D 0x050 /* 32bit */ #define DMILE1A 0x058 /* 64bit */ @@ -168,12 +175,12 @@ #define DMILCTL 0x088 /* 16bit */ #define DMILSTS 0x08a /* 16bit */ -#define DMICTL1 0x0f0 /* 32bit */ -#define DMICTL2 0x0fc /* 32bit */ +#define DMIUESTS 0x1c4 /* 32bit */ +#define DMICESTS 0x1d0 /* 32bit */ #define DMICC 0x208 /* 32bit */ -#define DMIDRCCFG 0xeb4 /* 32bit */ +#define DMILLTC 0x238 /* 32bit */ #ifndef __ASSEMBLER__ diff --git a/src/northbridge/intel/ironlake/northbridge.c b/src/northbridge/intel/ironlake/northbridge.c index 1272f5a..6e3ef2c 100644 --- a/src/northbridge/intel/ironlake/northbridge.c +++ b/src/northbridge/intel/ironlake/northbridge.c @@ -148,20 +148,20 @@ u32 reg32; /* Clear error status bits */ - DMIBAR32(0x1c4) = 0xffffffff; - DMIBAR32(0x1d0) = 0xffffffff; + DMIBAR32(DMIUESTS) = 0xffffffff; + DMIBAR32(DMICESTS) = 0xffffffff; - reg32 = DMIBAR32(0x238); + reg32 = DMIBAR32(DMILLTC); reg32 |= (1 << 29); - DMIBAR32(0x238) = reg32; + DMIBAR32(DMILLTC) = reg32; reg32 = DMIBAR32(0x1f8); reg32 |= (1 << 16); DMIBAR32(0x1f8) = reg32; - reg32 = DMIBAR32(0x88); + reg32 = DMIBAR32(DMILCTL); reg32 |= (1 << 1) | (1 << 0); - DMIBAR32(0x88) = reg32; + DMIBAR32(DMILCTL) = reg32; } /* Disable unused PEG devices based on devicetree before PCI enumeration */ diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index 89babdd..3cbc4a8 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -1815,20 +1815,20 @@ pci_read_config32(NORTHBRIDGE, DMIBAR); if (info->memory_reserved_for_heci_mb) { - DMIBAR32(0x14) &= ~0x80; + DMIBAR32(DMIVC0RCTL) &= ~0x80; write32(DEFAULT_RCBA + 0x14, read32(DEFAULT_RCBA + 0x14) & ~0x80); - DMIBAR32(0x20) &= ~0x80; + DMIBAR32(DMIVC1RCTL) &= ~0x80; write32(DEFAULT_RCBA + 0x20, read32(DEFAULT_RCBA + 0x20) & ~0x80); - DMIBAR32(0x2c) &= ~0x80; + DMIBAR32(DMIVCPRCTL) &= ~0x80; write32(DEFAULT_RCBA + 0x30, read32(DEFAULT_RCBA + 0x30) & ~0x80); - DMIBAR32(0x38) &= ~0x80; + DMIBAR32(DMIVCMRCTL) &= ~0x80; write32(DEFAULT_RCBA + 0x40, read32(DEFAULT_RCBA + 0x40) & ~0x80); write32(DEFAULT_RCBA + 0x40, 0x87000080); // OK - DMIBAR32(0x38) = 0x87000080; // OK + DMIBAR32(DMIVCMRCTL) = 0x87000080; // OK while ((read16(DEFAULT_RCBA + 0x46) & 2) && - DMIBAR16(0x3e) & 2) + DMIBAR16(DMIVCMRSTS) & VCMNP) ; } @@ -4605,9 +4605,9 @@ } u32 reg1c; pci_read_config32(NORTHBRIDGE, 0x40); // = DEFAULT_EPBAR | 0x001 // OK - reg1c = EPBAR32(0x01c); // = 0x8001 // OK + reg1c = EPBAR32(EPVC1RCAP); // = 0x8001 // OK pci_read_config32(NORTHBRIDGE, 0x40); // = DEFAULT_EPBAR | 0x001 // OK - EPBAR32(0x01c) = reg1c; // OK + EPBAR32(EPVC1RCAP) = reg1c; // OK MCHBAR8(0xe08); // = 0x0 pci_read_config32(NORTHBRIDGE, 0xe4); // = 0x316126 MCHBAR8_OR(0x1210, 2); -- To view, visit https://review.coreboot.org/c/coreboot/+/45380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ac99166a8029dcdbb59028b4a7ee297249de5db Gerrit-Change-Number: 45380 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/tglrvp: Convert mipi_camera.asl to ASL 2.0 syntax
by Subrata Banik (Code Review) 10 Oct '20

10 Oct '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46269 ) Change subject: mb/intel/tglrvp: Convert mipi_camera.asl to ASL 2.0 syntax ...................................................................... mb/intel/tglrvp: Convert mipi_camera.asl to ASL 2.0 syntax Change-Id: I9e81729213a6f7a2579d10adfb37b145b6d9204b Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/mainboard/intel/tglrvp/acpi/mipi_camera.asl 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/46269/1 diff --git a/src/mainboard/intel/tglrvp/acpi/mipi_camera.asl b/src/mainboard/intel/tglrvp/acpi/mipi_camera.asl index 0f83b05..08bc26b 100644 --- a/src/mainboard/intel/tglrvp/acpi/mipi_camera.asl +++ b/src/mainboard/intel/tglrvp/acpi/mipi_camera.asl @@ -170,7 +170,7 @@ STXS(GPP_C15) Sleep(1) /* t2 */ - Store(1,STA) + STA = 1 } } Method (_OFF, 0, Serialized) /* Rear camera _OFF: Power Off */ @@ -187,7 +187,7 @@ /* Pull PWREN low */ CTXS(GPP_B23) - Store(0,STA) + STA = 0 } } Method (_STA, 0, NotSerialized) /* _STA: Status */ @@ -389,7 +389,7 @@ STXS(GPP_H12) Sleep(1) /* t2 */ - Store(1,STA) + STA = 1 } } Method (_OFF, 0, Serialized) /* Front camera_OFF_: Power Off */ @@ -410,7 +410,7 @@ CTXS(GPP_R6) #endif - Store(0,STA) + STA = 0 } } Method (_STA, 0, NotSerialized) /* _STA: Status */ -- To view, visit https://review.coreboot.org/c/coreboot/+/46269 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e81729213a6f7a2579d10adfb37b145b6d9204b Gerrit-Change-Number: 46269 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/amd/pi/*/dimmSpd.c: Reduce difference
by HAOUAS Elyes (Code Review) 10 Oct '20

10 Oct '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46264 ) Change subject: nb/amd/pi/*/dimmSpd.c: Reduce difference ...................................................................... nb/amd/pi/*/dimmSpd.c: Reduce difference Also add missing <commonlib/helpers.h> to pi/00660F01/dimmSpd.c. Change-Id: Ie072b23e8bac3901c120bc238c415160e992d40c Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/amd/pi/00630F01/dimmSpd.c M src/northbridge/amd/pi/00660F01/dimmSpd.c M src/northbridge/amd/pi/00730F01/dimmSpd.c 3 files changed, 10 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/46264/1 diff --git a/src/northbridge/amd/pi/00630F01/dimmSpd.c b/src/northbridge/amd/pi/00630F01/dimmSpd.c index be3613d..063e4d0 100644 --- a/src/northbridge/amd/pi/00630F01/dimmSpd.c +++ b/src/northbridge/amd/pi/00630F01/dimmSpd.c @@ -8,7 +8,6 @@ #include <Porting.h> #include <AGESA.h> #include "chip.h" - #include <northbridge/amd/pi/dimmSpd.h> AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINTN unused2, AGESA_READ_SPD_PARAMS *info) @@ -26,8 +25,10 @@ if (info->SocketId >= ARRAY_SIZE(config->spdAddrLookup)) return AGESA_ERROR; + if (info->MemChannelId >= ARRAY_SIZE(config->spdAddrLookup[0])) return AGESA_ERROR; + if (info->DimmId >= ARRAY_SIZE(config->spdAddrLookup[0][0])) return AGESA_ERROR; diff --git a/src/northbridge/amd/pi/00660F01/dimmSpd.c b/src/northbridge/amd/pi/00660F01/dimmSpd.c index 0a1281f..591cf34 100644 --- a/src/northbridge/amd/pi/00660F01/dimmSpd.c +++ b/src/northbridge/amd/pi/00660F01/dimmSpd.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <commonlib/helpers.h> #include <device/pci_def.h> #include <device/device.h> @@ -24,14 +25,19 @@ if (info->SocketId >= ARRAY_SIZE(config->spdAddrLookup)) return AGESA_ERROR; + if (info->MemChannelId >= ARRAY_SIZE(config->spdAddrLookup[0])) return AGESA_ERROR; + if (info->DimmId >= ARRAY_SIZE(config->spdAddrLookup[0][0])) return AGESA_ERROR; + spdAddress = config->spdAddrLookup [info->SocketId] [info->MemChannelId] [info->DimmId]; + if (spdAddress == 0) return AGESA_ERROR; + int err = hudson_readSpd(spdAddress, (void *) info->Buffer, 128); if (err) return AGESA_ERROR; diff --git a/src/northbridge/amd/pi/00730F01/dimmSpd.c b/src/northbridge/amd/pi/00730F01/dimmSpd.c index 42dd5a2..05e4f9b 100644 --- a/src/northbridge/amd/pi/00730F01/dimmSpd.c +++ b/src/northbridge/amd/pi/00730F01/dimmSpd.c @@ -8,7 +8,6 @@ #include <Porting.h> #include <AGESA.h> #include "chip.h" - #include <northbridge/amd/pi/dimmSpd.h> AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINTN unused2, AGESA_READ_SPD_PARAMS *info) @@ -26,8 +25,10 @@ if (info->SocketId >= ARRAY_SIZE(config->spdAddrLookup)) return AGESA_ERROR; + if (info->MemChannelId >= ARRAY_SIZE(config->spdAddrLookup[0])) return AGESA_ERROR; + if (info->DimmId >= ARRAY_SIZE(config->spdAddrLookup[0][0])) return AGESA_ERROR; -- To view, visit https://review.coreboot.org/c/coreboot/+/46264 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie072b23e8bac3901c120bc238c415160e992d40c Gerrit-Change-Number: 46264 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8192: enable CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE
by Ikjoon Jang (Code Review) 10 Oct '20

10 Oct '20

Ikjoon Jang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46121 ) Change subject: soc/mediatek/mt8192: enable CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE ...................................................................... soc/mediatek/mt8192: enable CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE BUG=159079785 TEST=boot asurada Change-Id: Ieb93073beff7ec95eb5406eecbfba8192f91edce Signed-off-by: Ikjoon Jang <ikjn(a)chromium.org> --- M src/soc/mediatek/mt8192/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/46121/1 diff --git a/src/soc/mediatek/mt8192/Kconfig b/src/soc/mediatek/mt8192/Kconfig index 2412204..d97b017 100644 --- a/src/soc/mediatek/mt8192/Kconfig +++ b/src/soc/mediatek/mt8192/Kconfig @@ -5,6 +5,7 @@ select ARCH_VERSTAGE_ARMV8_64 select ARCH_ROMSTAGE_ARMV8_64 select ARCH_RAMSTAGE_ARMV8_64 + select ARM64_USE_ARM_TRUSTED_FIRMWARE select HAVE_UART_SPECIAL if SOC_MEDIATEK_MT8192 -- To view, visit https://review.coreboot.org/c/coreboot/+/46121 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb93073beff7ec95eb5406eecbfba8192f91edce Gerrit-Change-Number: 46121 Gerrit-PatchSet: 1 Gerrit-Owner: Ikjoon Jang <ikjn(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP] soc/intel/tigerlake: Add chipset devicetree
by Duncan Laurie (Code Review) 10 Oct '20

10 Oct '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44038 ) Change subject: [WIP] soc/intel/tigerlake: Add chipset devicetree ...................................................................... [WIP] soc/intel/tigerlake: Add chipset devicetree Add aliases for devices and set most of them to off with the exception of some essential devices. Set a default register value as an example. Change-Id: If50269808645ddc019e0d94fa8296df58ab7c367 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/soc/intel/tigerlake/Kconfig A src/soc/intel/tigerlake/chipset.cb 2 files changed, 77 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/44038/1 diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 2659357..3baf193 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -89,6 +89,10 @@ Refer to Platform FSP integration guide document to know the exact FSP requirement for Heap setup. +config CHIPSET_DEVICETREE + string + default "soc/intel/tigerlake/chipset.cb" + config IFD_CHIPSET string default "tgl" diff --git a/src/soc/intel/tigerlake/chipset.cb b/src/soc/intel/tigerlake/chipset.cb new file mode 100644 index 0000000..4dcd14e --- /dev/null +++ b/src/soc/intel/tigerlake/chipset.cb @@ -0,0 +1,73 @@ +chip soc/intel/tigerlake + register "SaGv" = "SaGv_Enabled" + + device domain 0 on + device pci 00.0 alias system_agent on end + device pci 02.0 alias igpu off end + device pci 04.0 alias dptf off end + device pci 05.0 alias ipu off end + device pci 06.0 alias peg off end + device pci 07.0 alias tbt_pcie_rp0 off end + device pci 07.1 alias tbt_pcie_rp1 off end + device pci 07.2 alias tbt_pcie_rp2 off end + device pci 07.3 alias tbt_pcie_rp3 off end + device pci 08.0 alias gna off end + device pci 09.0 alias npk off end + device pci 0a.0 alias crashlog off end + device pci 0d.0 alias north_xhci off end + device pci 0d.1 alias north_xdci off end + device pci 0d.2 alias tbt_dma0 off end + device pci 0d.3 alias tbt_dma1 off end + device pci 0e.0 alias vmd off end + device pci 10.2 alias cnvi_bt off end + device pci 10.6 alias thc0 off end + device pci 10.7 alias thc1 off end + device pci 12.0 alias ish off end + device pci 12.6 alias gspi2 off end + device pci 13.0 alias gspi3 off end + device pci 14.0 alias south_xhci off end + device pci 14.1 alias south_xdci off end + device pci 14.2 alias shared_ram off end + chip drivers/intel/wifi + device pci 14.3 alias cnvi_wifi off end + end + device pci 15.0 alias i2c0 off end + device pci 15.1 alias i2c1 off end + device pci 15.2 alias i2c2 off end + device pci 15.3 alias i2c3 off end + device pci 16.0 alias heci1 off end + device pci 16.1 alias heci2 off end + device pci 16.2 alias csme1 off end + device pci 16.3 alias csme2 off end + device pci 16.4 alias heci3 off end + device pci 16.5 alias heci4 off end + device pci 17.0 alias sata off end + device pci 19.0 alias i2c4 off end + device pci 19.1 alias i2c5 off end + device pci 19.2 alias uart2 off end + device pci 1c.0 alias pcie_rp1 off end + device pci 1c.1 alias pcie_rp2 off end + device pci 1c.2 alias pcie_rp3 off end + device pci 1c.3 alias pcie_rp4 off end + device pci 1c.4 alias pcie_rp5 off end + device pci 1c.5 alias pcie_rp6 off end + device pci 1c.6 alias pcie_rp7 off end + device pci 1c.7 alias pcie_rp8 off end + device pci 1d.0 alias pcie_rp9 off end + device pci 1d.1 alias pcie_rp10 off end + device pci 1d.2 alias pcie_rp11 off end + device pci 1d.3 alias pcie_rp12 off end + device pci 1e.0 alias uart0 off end + device pci 1e.1 alias uart1 off end + device pci 1e.2 alias gspi0 off end + device pci 1e.3 alias gspi1 off end + device pci 1f.0 alias pch_espi on end + device pci 1f.1 alias p2sb off end + device pci 1f.2 alias pmc hidden end + device pci 1f.3 alias hda off end + device pci 1f.4 alias smbus off end + device pci 1f.5 alias fast_spi on end + device pci 1f.6 alias gbe off end + device pci 1f.7 alias thermal off end + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/44038 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If50269808645ddc019e0d94fa8296df58ab7c367 Gerrit-Change-Number: 44038 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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coreboot-gerrit October 2020