Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44038 )
Change subject: [WIP] soc/intel/tigerlake: Add chipset devicetree
......................................................................
[WIP] soc/intel/tigerlake: Add chipset devicetree
Add aliases for devices and set most of them to off with the exception
of some essential devices.
Set a default register value as an example.
Change-Id: If50269808645ddc019e0d94fa8296df58ab7c367
Signed-off-by: Duncan Laurie <dlaurie(a)google.com>
---
M src/soc/intel/tigerlake/Kconfig
A src/soc/intel/tigerlake/chipset.cb
2 files changed, 77 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/44038/1
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index 2659357..3baf193 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -89,6 +89,10 @@
Refer to Platform FSP integration guide document to know
the exact FSP requirement for Heap setup.
+config CHIPSET_DEVICETREE
+ string
+ default "soc/intel/tigerlake/chipset.cb"
+
config IFD_CHIPSET
string
default "tgl"
diff --git a/src/soc/intel/tigerlake/chipset.cb b/src/soc/intel/tigerlake/chipset.cb
new file mode 100644
index 0000000..4dcd14e
--- /dev/null
+++ b/src/soc/intel/tigerlake/chipset.cb
@@ -0,0 +1,73 @@
+chip soc/intel/tigerlake
+ register "SaGv" = "SaGv_Enabled"
+
+ device domain 0 on
+ device pci 00.0 alias system_agent on end
+ device pci 02.0 alias igpu off end
+ device pci 04.0 alias dptf off end
+ device pci 05.0 alias ipu off end
+ device pci 06.0 alias peg off end
+ device pci 07.0 alias tbt_pcie_rp0 off end
+ device pci 07.1 alias tbt_pcie_rp1 off end
+ device pci 07.2 alias tbt_pcie_rp2 off end
+ device pci 07.3 alias tbt_pcie_rp3 off end
+ device pci 08.0 alias gna off end
+ device pci 09.0 alias npk off end
+ device pci 0a.0 alias crashlog off end
+ device pci 0d.0 alias north_xhci off end
+ device pci 0d.1 alias north_xdci off end
+ device pci 0d.2 alias tbt_dma0 off end
+ device pci 0d.3 alias tbt_dma1 off end
+ device pci 0e.0 alias vmd off end
+ device pci 10.2 alias cnvi_bt off end
+ device pci 10.6 alias thc0 off end
+ device pci 10.7 alias thc1 off end
+ device pci 12.0 alias ish off end
+ device pci 12.6 alias gspi2 off end
+ device pci 13.0 alias gspi3 off end
+ device pci 14.0 alias south_xhci off end
+ device pci 14.1 alias south_xdci off end
+ device pci 14.2 alias shared_ram off end
+ chip drivers/intel/wifi
+ device pci 14.3 alias cnvi_wifi off end
+ end
+ device pci 15.0 alias i2c0 off end
+ device pci 15.1 alias i2c1 off end
+ device pci 15.2 alias i2c2 off end
+ device pci 15.3 alias i2c3 off end
+ device pci 16.0 alias heci1 off end
+ device pci 16.1 alias heci2 off end
+ device pci 16.2 alias csme1 off end
+ device pci 16.3 alias csme2 off end
+ device pci 16.4 alias heci3 off end
+ device pci 16.5 alias heci4 off end
+ device pci 17.0 alias sata off end
+ device pci 19.0 alias i2c4 off end
+ device pci 19.1 alias i2c5 off end
+ device pci 19.2 alias uart2 off end
+ device pci 1c.0 alias pcie_rp1 off end
+ device pci 1c.1 alias pcie_rp2 off end
+ device pci 1c.2 alias pcie_rp3 off end
+ device pci 1c.3 alias pcie_rp4 off end
+ device pci 1c.4 alias pcie_rp5 off end
+ device pci 1c.5 alias pcie_rp6 off end
+ device pci 1c.6 alias pcie_rp7 off end
+ device pci 1c.7 alias pcie_rp8 off end
+ device pci 1d.0 alias pcie_rp9 off end
+ device pci 1d.1 alias pcie_rp10 off end
+ device pci 1d.2 alias pcie_rp11 off end
+ device pci 1d.3 alias pcie_rp12 off end
+ device pci 1e.0 alias uart0 off end
+ device pci 1e.1 alias uart1 off end
+ device pci 1e.2 alias gspi0 off end
+ device pci 1e.3 alias gspi1 off end
+ device pci 1f.0 alias pch_espi on end
+ device pci 1f.1 alias p2sb off end
+ device pci 1f.2 alias pmc hidden end
+ device pci 1f.3 alias hda off end
+ device pci 1f.4 alias smbus off end
+ device pci 1f.5 alias fast_spi on end
+ device pci 1f.6 alias gbe off end
+ device pci 1f.7 alias thermal off end
+ end
+end
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: If50269808645ddc019e0d94fa8296df58ab7c367
Gerrit-Change-Number: 44038
Gerrit-PatchSet: 1
Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-MessageType: newchange
Ravi kumar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45706 )
Change subject: sc7180: Remove the delay to force hpd detection and always disable HPD
......................................................................
sc7180: Remove the delay to force hpd detection and always disable HPD
HPD on this bridge chip is a bit useless. This is an eDP bridge so the HPD is
an internal signal that's only there to signal that the panel is done powering up.
But the bridge chip debounces this signal by between 100 ms and 400 ms (depending on process,
voltage, and temperate). One particular panel asserted HPD 84 ms after it was powered on
meaning that we saw HPD 284 ms after power on. Assume that the panel driver will have the
hardcoded delay in its prepare and always disable HPD.
Change-Id: Iea7dd75b57fa55ec182c0bee09b0f35208357892
Signed-off-by: Vinod Polimera <vpolimer(a)codeaurora.org>
---
M src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c
1 file changed, 2 insertions(+), 30 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/45706/1
diff --git a/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c b/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c
index e0058c4..a73d6d7 100644
--- a/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c
+++ b/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c
@@ -426,35 +426,6 @@
}
-static enum cb_err sn65dsi86_bridge_get_plug_in_status(uint8_t bus, uint8_t chip)
-{
- int val;
- uint8_t buf;
-
- val = i2c_readb(bus, chip, SN_HPD_DISABLE_REG, &buf);
- if (val == 0 && (buf & HPD_DISABLE))
- return CB_SUCCESS;
-
- return CB_ERR;
-}
-
-/*
- * support bridge HPD function some hardware versions do not support bridge hdp,
- * we use 360ms to try to get the hpd single now, if we can not get bridge hpd single,
- * it will delay 360ms, also meet the bridge power timing request, to be compatible
- * all of the hardware versions
- */
-static void sn65dsi86_bridge_wait_hpd(uint8_t bus, uint8_t chip)
-{
- if (wait_ms(400, sn65dsi86_bridge_get_plug_in_status(bus, chip)))
- return;
-
- printk(BIOS_WARNING, "HPD detection failed, force hpd\n");
-
- /* Force HPD */
- i2c_write_field(bus, chip, SN_HPD_DISABLE_REG, HPD_DISABLE, 1, 0);
-}
-
static void sn65dsi86_bridge_assr_config(uint8_t bus, uint8_t chip, int enable)
{
if (enable)
@@ -476,7 +447,8 @@
void sn65dsi86_bridge_init(uint8_t bus, uint8_t chip, enum dp_pll_clk_src ref_clk)
{
- sn65dsi86_bridge_wait_hpd(bus, chip);
+ /* disable HPD */
+ i2c_write_field(bus, chip, SN_HPD_DISABLE_REG, HPD_DISABLE, 1, 0);
/* set refclk to 19.2 MHZ */
i2c_write_field(bus, chip, SN_DPPLL_SRC_REG, ref_clk, 7, 1);
--
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Gerrit-Change-Id: Iea7dd75b57fa55ec182c0bee09b0f35208357892
Gerrit-Change-Number: 45706
Gerrit-PatchSet: 1
Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org>
Gerrit-MessageType: newchange
Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46057 )
Change subject: soc/intel/xeon_sp: Use generic config_t
......................................................................
soc/intel/xeon_sp: Use generic config_t
Don't use the silicon specific typedef to get common config options.
Use the generic config_t pointer. This allows the function to be
moved to common code in upcoming patches.
Change-Id: If80b678037b4d79387e0a0f722c540df4aae2416
Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com>
---
M src/soc/intel/xeon_sp/cpx/soc_acpi.c
M src/soc/intel/xeon_sp/skx/soc_acpi.c
2 files changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/46057/1
diff --git a/src/soc/intel/xeon_sp/cpx/soc_acpi.c b/src/soc/intel/xeon_sp/cpx/soc_acpi.c
index b711727..1ae51d2 100644
--- a/src/soc/intel/xeon_sp/cpx/soc_acpi.c
+++ b/src/soc/intel/xeon_sp/cpx/soc_acpi.c
@@ -684,7 +684,7 @@
acpi_slit_t *slit;
acpi_dmar_t *dmar;
- const struct soc_intel_xeon_sp_cpx_config *const config = config_of(device);
+ const config_t *const config = config_of(device);
/* SRAT */
current = ALIGN(current, 8);
diff --git a/src/soc/intel/xeon_sp/skx/soc_acpi.c b/src/soc/intel/xeon_sp/skx/soc_acpi.c
index 2a3c04e..9c07ec7 100644
--- a/src/soc/intel/xeon_sp/skx/soc_acpi.c
+++ b/src/soc/intel/xeon_sp/skx/soc_acpi.c
@@ -586,7 +586,7 @@
acpi_slit_t *slit;
acpi_dmar_t *dmar;
- const struct soc_intel_xeon_sp_skx_config *const config = config_of(device);
+ const config_t *const config = config_of(device);
/* SRAT */
current = ALIGN(current, 8);
--
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Gerrit-Change-Id: If80b678037b4d79387e0a0f722c540df4aae2416
Gerrit-Change-Number: 46057
Gerrit-PatchSet: 1
Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-MessageType: newchange
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46249 )
Change subject: mb/clevo/l140cu: Correct FSP-M UPDs
......................................................................
Patch Set 1:
This change is ready for review.
--
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Gerrit-Change-Id: I32f1b7bb46eaaf0f0ecad1df310f5de988f64c85
Gerrit-Change-Number: 46249
Gerrit-PatchSet: 1
Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de>
Gerrit-Comment-Date: Fri, 09 Oct 2020 19:55:12 +0000
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46248 )
Change subject: mb/clevo/l140cu: drop disabled SPD channels
......................................................................
Patch Set 1:
This change is ready for review.
--
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Gerrit-Change-Number: 46248
Gerrit-PatchSet: 1
Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de>
Gerrit-Comment-Date: Fri, 09 Oct 2020 19:54:56 +0000
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