Ravi kumar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45706 )
Change subject: sc7180: Remove the delay to force hpd detection and always disable HPD
......................................................................
sc7180: Remove the delay to force hpd detection and always disable HPD
HPD on this bridge chip is a bit useless. This is an eDP bridge so the HPD is
an internal signal that's only there to signal that the panel is done powering up.
But the bridge chip debounces this signal by between 100 ms and 400 ms (depending on process,
voltage, and temperate). One particular panel asserted HPD 84 ms after it was powered on
meaning that we saw HPD 284 ms after power on. Assume that the panel driver will have the
hardcoded delay in its prepare and always disable HPD.
Change-Id: Iea7dd75b57fa55ec182c0bee09b0f35208357892
Signed-off-by: Vinod Polimera <vpolimer(a)codeaurora.org>
---
M src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c
1 file changed, 2 insertions(+), 30 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/45706/1
diff --git a/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c b/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c
index e0058c4..a73d6d7 100644
--- a/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c
+++ b/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c
@@ -426,35 +426,6 @@
}
-static enum cb_err sn65dsi86_bridge_get_plug_in_status(uint8_t bus, uint8_t chip)
-{
- int val;
- uint8_t buf;
-
- val = i2c_readb(bus, chip, SN_HPD_DISABLE_REG, &buf);
- if (val == 0 && (buf & HPD_DISABLE))
- return CB_SUCCESS;
-
- return CB_ERR;
-}
-
-/*
- * support bridge HPD function some hardware versions do not support bridge hdp,
- * we use 360ms to try to get the hpd single now, if we can not get bridge hpd single,
- * it will delay 360ms, also meet the bridge power timing request, to be compatible
- * all of the hardware versions
- */
-static void sn65dsi86_bridge_wait_hpd(uint8_t bus, uint8_t chip)
-{
- if (wait_ms(400, sn65dsi86_bridge_get_plug_in_status(bus, chip)))
- return;
-
- printk(BIOS_WARNING, "HPD detection failed, force hpd\n");
-
- /* Force HPD */
- i2c_write_field(bus, chip, SN_HPD_DISABLE_REG, HPD_DISABLE, 1, 0);
-}
-
static void sn65dsi86_bridge_assr_config(uint8_t bus, uint8_t chip, int enable)
{
if (enable)
@@ -476,7 +447,8 @@
void sn65dsi86_bridge_init(uint8_t bus, uint8_t chip, enum dp_pll_clk_src ref_clk)
{
- sn65dsi86_bridge_wait_hpd(bus, chip);
+ /* disable HPD */
+ i2c_write_field(bus, chip, SN_HPD_DISABLE_REG, HPD_DISABLE, 1, 0);
/* set refclk to 19.2 MHZ */
i2c_write_field(bus, chip, SN_DPPLL_SRC_REG, ref_clk, 7, 1);
--
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Gerrit-Change-Id: Iea7dd75b57fa55ec182c0bee09b0f35208357892
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Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46057 )
Change subject: soc/intel/xeon_sp: Use generic config_t
......................................................................
soc/intel/xeon_sp: Use generic config_t
Don't use the silicon specific typedef to get common config options.
Use the generic config_t pointer. This allows the function to be
moved to common code in upcoming patches.
Change-Id: If80b678037b4d79387e0a0f722c540df4aae2416
Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com>
---
M src/soc/intel/xeon_sp/cpx/soc_acpi.c
M src/soc/intel/xeon_sp/skx/soc_acpi.c
2 files changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/46057/1
diff --git a/src/soc/intel/xeon_sp/cpx/soc_acpi.c b/src/soc/intel/xeon_sp/cpx/soc_acpi.c
index b711727..1ae51d2 100644
--- a/src/soc/intel/xeon_sp/cpx/soc_acpi.c
+++ b/src/soc/intel/xeon_sp/cpx/soc_acpi.c
@@ -684,7 +684,7 @@
acpi_slit_t *slit;
acpi_dmar_t *dmar;
- const struct soc_intel_xeon_sp_cpx_config *const config = config_of(device);
+ const config_t *const config = config_of(device);
/* SRAT */
current = ALIGN(current, 8);
diff --git a/src/soc/intel/xeon_sp/skx/soc_acpi.c b/src/soc/intel/xeon_sp/skx/soc_acpi.c
index 2a3c04e..9c07ec7 100644
--- a/src/soc/intel/xeon_sp/skx/soc_acpi.c
+++ b/src/soc/intel/xeon_sp/skx/soc_acpi.c
@@ -586,7 +586,7 @@
acpi_slit_t *slit;
acpi_dmar_t *dmar;
- const struct soc_intel_xeon_sp_skx_config *const config = config_of(device);
+ const config_t *const config = config_of(device);
/* SRAT */
current = ALIGN(current, 8);
--
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46249 )
Change subject: mb/clevo/l140cu: Correct FSP-M UPDs
......................................................................
Patch Set 1:
This change is ready for review.
--
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46248 )
Change subject: mb/clevo/l140cu: drop disabled SPD channels
......................................................................
Patch Set 1:
This change is ready for review.
--
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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46120 )
Change subject: mb/google/poppy/variant/atlas: Reset bluetooth in BIOS
......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46120/1//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/coreboot/+/46120/1//COMMIT_MSG@20
PS1, Line 20:
> We usually merge coreboot changes to top-of-tree first, and then cherry-pick on the chromium side to […]
For sure :) I just mean to tag this with BRANCH=poppy or something
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Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46120 )
Change subject: mb/google/poppy/variant/atlas: Reset bluetooth in BIOS
......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46120/1//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/coreboot/+/46120/1//COMMIT_MSG@20
PS1, Line 20:
> Shouldn't this go in the poppy branch?
We usually merge coreboot changes to top-of-tree first, and then cherry-pick on the chromium side to the firmware branch to assure TOT stays up-to-date.
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