Hello Felix Singer, build bot (Jenkins), Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46249
to look at the new patch set (#4).
Change subject: mb/clevo/l140cu: clean up memcfg
......................................................................
mb/clevo/l140cu: clean up memcfg
The DQ and DQS byte maps do not apply to DDR4 configurations, thus
simply drop them.
Also drop ECT, as it's already initialized to zero and can't be used on
DDR4 anyway.
Further, trim down all the meaningless and/or wrong comments.
Change-Id: I32f1b7bb46eaaf0f0ecad1df310f5de988f64c85
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/mainboard/clevo/cml-u/variants/l140cu/romstage.c
1 file changed, 5 insertions(+), 51 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/46249/4
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Gerrit-Change-Id: I32f1b7bb46eaaf0f0ecad1df310f5de988f64c85
Gerrit-Change-Number: 46249
Gerrit-PatchSet: 4
Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de>
Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net>
Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-MessageType: newpatchset
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46249 )
Change subject: mb/clevo/l140cu: clean up memcfg
......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46249/2/src/mainboard/clevo/cml-u/…
File src/mainboard/clevo/cml-u/variants/l140cu/romstage.c:
https://review.coreboot.org/c/coreboot/+/46249/2/src/mainboard/clevo/cml-u/…
PS2, Line 16: Values of the rcomp resistors attached to the DDR_RCOMP_* pins
> maybe: […]
Done
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Gerrit-Change-Id: I32f1b7bb46eaaf0f0ecad1df310f5de988f64c85
Gerrit-Change-Number: 46249
Gerrit-PatchSet: 3
Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de>
Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net>
Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Comment-Date: Sun, 11 Oct 2020 16:59:24 +0000
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Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-MessageType: comment
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46249 )
Change subject: mb/clevo/l140cu: clean up memcfg
......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/46249/2//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/coreboot/+/46249/2//COMMIT_MSG@7
PS2, Line 7: rework
> maybe "clean up memcfg"?
Done
https://review.coreboot.org/c/coreboot/+/46249/2//COMMIT_MSG@12
PS2, Line 12: ect
> ECT (Early Command Training) is an acronym, please spell it in uppercase. […]
well, I dropped the option .ect :P
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Gerrit-Change-Number: 46249
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Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de>
Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net>
Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com>
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Gerrit-Comment-Date: Sun, 11 Oct 2020 16:57:36 +0000
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Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-MessageType: comment
Hello Felix Singer, build bot (Jenkins), Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46249
to look at the new patch set (#3).
Change subject: mb/clevo/l140cu: clean up memcfg
......................................................................
mb/clevo/l140cu: clean up memcfg
The DQ and DQS byte maps do not apply to DDR4 configurations, thus
simply drop them.
Also drop ECT, as it's already initialized to zero and can't be used on
DDR4 anyway.
Further, trim down all the meaningless and/or wrong comments.
Change-Id: I32f1b7bb46eaaf0f0ecad1df310f5de988f64c85
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/mainboard/clevo/cml-u/variants/l140cu/romstage.c
1 file changed, 5 insertions(+), 51 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/46249/3
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Gerrit-Change-Number: 46249
Gerrit-PatchSet: 3
Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de>
Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net>
Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-MessageType: newpatchset
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45959 )
Change subject: mb/clevo/l140cu: set PS/2 timeout for SeaBIOS
......................................................................
Patch Set 2: Code-Review+2
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Gerrit-Comment-Date: Sun, 11 Oct 2020 15:40:57 +0000
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Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46248 )
Change subject: mb/clevo/l140cu: drop disabled SPD indices
......................................................................
Patch Set 2: Code-Review+2
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Gerrit-Comment-Date: Sun, 11 Oct 2020 15:37:02 +0000
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46249 )
Change subject: mb/clevo/l140cu: rework memcfg
......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46249/2/src/mainboard/clevo/cml-u/…
File src/mainboard/clevo/cml-u/variants/l140cu/romstage.c:
https://review.coreboot.org/c/coreboot/+/46249/2/src/mainboard/clevo/cml-u/…
PS2, Line 16: Values of the rcomp resistors attached to the DDR_RCOMP_* pins
maybe:
Values of the resistors connected to the DDR_RCOMP_[2:0] pins of the CPU
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45959 )
Change subject: mb/clevo/l140cu: set PS/2 timeout for SeaBIOS
......................................................................
Patch Set 2: Code-Review+2
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