coreboot-gerrit October 2020

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Change in coreboot[master]: mb/google/jechto: Disable PCIe AER
by Matt DeVillier (Code Review) 12 Oct '20

12 Oct '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46137 ) Change subject: mb/google/jechto: Disable PCIe AER ...................................................................... mb/google/jechto: Disable PCIe AER Ethernet hardware on jecht variants doesn't support AER, so disable it to mitigate continuous AER timeout errors in dmesg. Change-Id: Ieda82c6e13c2bbc4b3a051a3d2a7ae90728ccdc6 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/jecht/Kconfig 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/46137/1 diff --git a/src/mainboard/google/jecht/Kconfig b/src/mainboard/google/jecht/Kconfig index 7065081..4851bd7 100644 --- a/src/mainboard/google/jecht/Kconfig +++ b/src/mainboard/google/jecht/Kconfig @@ -56,4 +56,7 @@ string default "GOOGLE" +config PCIEXP_AER + def_bool n + endif -- To view, visit https://review.coreboot.org/c/coreboot/+/46137 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieda82c6e13c2bbc4b3a051a3d2a7ae90728ccdc6 Gerrit-Change-Number: 46137 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/beltino: Disable PCIe AER
by Matt DeVillier (Code Review) 12 Oct '20

12 Oct '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46136 ) Change subject: mb/google/beltino: Disable PCIe AER ...................................................................... mb/google/beltino: Disable PCIe AER Ethernet hardware on beltino variants doesn't support AER, so disable it to mitigate continuous AER timeout errors in dmesg. Change-Id: I0f592a21d08e79cda251e80cd1f1184c4311e9df Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/beltino/Kconfig 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/46136/1 diff --git a/src/mainboard/google/beltino/Kconfig b/src/mainboard/google/beltino/Kconfig index 0ac6805..cbf9dc4 100644 --- a/src/mainboard/google/beltino/Kconfig +++ b/src/mainboard/google/beltino/Kconfig @@ -59,4 +59,7 @@ config ENABLE_DDR_2X_REFRESH default y +config PCIEXP_AER + def_bool n + endif # BOARD_GOOGLE_BASEBOARD_BELTINO -- To view, visit https://review.coreboot.org/c/coreboot/+/46136 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f592a21d08e79cda251e80cd1f1184c4311e9df Gerrit-Change-Number: 46136 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/lynxpoint: fix typo
by Matt DeVillier (Code Review) 12 Oct '20

12 Oct '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46135 ) Change subject: sb/intel/lynxpoint: fix typo ...................................................................... sb/intel/lynxpoint: fix typo Change-Id: I741b66e08d977f514f2512d626e3bcf22ce7d46c Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/southbridge/intel/lynxpoint/pcie.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/46135/1 diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 66e46d3..e0d09fd 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -659,7 +659,7 @@ pci_update_config32(dev, 0x33c, ~0x00ffffff, 0x854c74); - /* Set Invalid Recieve Range Check Enable in MPC register. */ + /* Set Invalid Receive Range Check Enable in MPC register. */ pci_or_config32(dev, 0xd8, 1 << 25); pci_and_config8(dev, 0xf5, 0x3f); -- To view, visit https://review.coreboot.org/c/coreboot/+/46135 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I741b66e08d977f514f2512d626e3bcf22ce7d46c Gerrit-Change-Number: 46135 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/lnyxpoint: Set PCIe L1 substate capabilities register
by Matt DeVillier (Code Review) 12 Oct '20

12 Oct '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46134 ) Change subject: sb/intel/lnyxpoint: Set PCIe L1 substate capabilities register ...................................................................... sb/intel/lnyxpoint: Set PCIe L1 substate capabilities register Copied from soc/intel/broadwell. Test: build/boot gogole/beltino variants Change-Id: Ib2ae3d9539de9f7e22975f00450d9d60d1fd938a Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/southbridge/intel/lynxpoint/pcie.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/46134/1 diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 42e002b..66e46d3 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -678,6 +678,12 @@ pci_update_config32(dev, 0x100, ~(1 << 29) & ~0xfffff, (1 << 29)); + /* Set L1 Sub-State Cap ID to 1Eh and Next Cap Pointer to None. */ + if (CONFIG(PCIEXP_L1_SUB_STATE)) + pci_update_config32(dev, 0x200, ~0xfffff, 0x001e); + else + pci_update_config32(dev, 0x200, ~0xfffff, 0); + if (is_lp) pci_or_config32(dev, 0x100, 1 << 29); -- To view, visit https://review.coreboot.org/c/coreboot/+/46134 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2ae3d9539de9f7e22975f00450d9d60d1fd938a Gerrit-Change-Number: 46134 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/lynxpoint: Enable/disable AER via Kconfig
by Matt DeVillier (Code Review) 12 Oct '20

12 Oct '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46133 ) Change subject: sb/intel/lynxpoint: Enable/disable AER via Kconfig ...................................................................... sb/intel/lynxpoint: Enable/disable AER via Kconfig Semi-recent changes to the Linux kernel now enable AER for many devices for which it was previously disabled. This, coupled with the SB enabling AER for all PCIe devices, has resulted in a large amount of AER timeout errors in the kernel log for devices which do not support AER. To mitigate this, guard AER enablement via Kconfig, select it by default (as to maintain current default behavior), and allow boards which need to disable it to do so. This implementation is identical to/copied from soc/intel/broadwell. Test: build/boot google/beltino variants with AER disabled, verify dmesg log free of AER errors. Change-Id: Ia03ef0d111335892c65122954c1248191ded7cb8 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/southbridge/intel/lynxpoint/Kconfig M src/southbridge/intel/lynxpoint/pcie.c 2 files changed, 11 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/46133/1 diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index c104cbb..43f8bce 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -58,4 +58,8 @@ If you set this option to y, the USB ports will be routed to the XHCI controller during the finalize SMM callback. +config PCIEXP_AER + bool + default y + endif diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 35ce5c47..42e002b 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -670,8 +670,13 @@ /* Set EOI forwarding disable. */ pci_or_config32(dev, 0xd4, 1 << 1); - /* Set something involving advanced error reporting. */ - pci_update_config32(dev, 0x100, ~((1 << 20) - 1), 0x10001); + /* Set AER Extended Cap ID to 01h and Next Cap Pointer to 200h. */ + if (CONFIG(PCIEXP_AER)) + pci_update_config32(dev, 0x100, ~(1 << 29) & ~0xfffff, + (1 << 29) | 0x10001); + else + pci_update_config32(dev, 0x100, ~(1 << 29) & ~0xfffff, + (1 << 29)); if (is_lp) pci_or_config32(dev, 0x100, 1 << 29); -- To view, visit https://review.coreboot.org/c/coreboot/+/46133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia03ef0d111335892c65122954c1248191ded7cb8 Gerrit-Change-Number: 46133 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/puff: Enable SATA0 on wyvern
by Edward O'Callaghan (Code Review) 12 Oct '20

12 Oct '20

Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46270 ) Change subject: mb/google/puff: Enable SATA0 on wyvern ...................................................................... mb/google/puff: Enable SATA0 on wyvern A SATA drive may be connected to SATA0. BUG=b:162909831 BRANCH=puff TEST=none Change-Id: I2a4ce2f89fa6d786358e01add15f2eedfbe4b20f Signed-off-by: Sam McNally <sammc(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46270 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org> --- M src/mainboard/google/hatch/variants/wyvern/overridetree.cb 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Edward O'Callaghan: Looks good to me, approved diff --git a/src/mainboard/google/hatch/variants/wyvern/overridetree.cb b/src/mainboard/google/hatch/variants/wyvern/overridetree.cb index 3320455..8ca9ce4 100644 --- a/src/mainboard/google/hatch/variants/wyvern/overridetree.cb +++ b/src/mainboard/google/hatch/variants/wyvern/overridetree.cb @@ -3,6 +3,8 @@ # Auto-switch between X4 NVMe and X2 NVMe. register "TetonGlacierMode" = "1" + register "SataPortsEnable[0]" = "1" + register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoDisabled, [PchSerialIoIndexI2C1] = PchSerialIoDisabled, -- To view, visit https://review.coreboot.org/c/coreboot/+/46270 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a4ce2f89fa6d786358e01add15f2eedfbe4b20f Gerrit-Change-Number: 46270 Gerrit-PatchSet: 3 Gerrit-Owner: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: device/i2c_bus: Add i2c_dev_writeb_at16()
by shkim (Code Review) 12 Oct '20

12 Oct '20

Hello SH Kim, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46290 to review the following change. Change subject: device/i2c_bus: Add i2c_dev_writeb_at16() ...................................................................... device/i2c_bus: Add i2c_dev_writeb_at16() i2c_dev_writeb_at16() sends a 16-bit offset to the I2C chip (for larger EEPROM parts), then write a byte. Change-Id: Ic8ee87fd2175d7c2d4359ece425519aa25df9a16 Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.corp-partner.google.com> --- M src/device/i2c_bus.c M src/include/device/i2c_bus.h 2 files changed, 35 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/46290/1 diff --git a/src/device/i2c_bus.c b/src/device/i2c_bus.c index a65cdad..bbe1094 100644 --- a/src/device/i2c_bus.c +++ b/src/device/i2c_bus.c @@ -184,3 +184,32 @@ return -1; } } + +int i2c_dev_writeb_at16(struct device *const dev, + const uint16_t off, const uint8_t val) +{ + struct device *const busdev = i2c_busdev(dev); + if (!busdev) + return -1; + + if (busdev->ops->ops_i2c_bus) { + uint8_t buf[3]; + const struct i2c_msg msg = { + .flags = 0, + .slave = dev->path.i2c.device, + .buf = buf, + .len = sizeof(buf), + }; + + write_be16((uint16_t *)buf, off); + buf[2] = val; + + return busdev->ops->ops_i2c_bus->transfer(busdev, &msg, 1); + } else if (busdev->ops->ops_smbus_bus->write_byte) { + return busdev->ops->ops_smbus_bus->write_byte(dev, off, val); + } else { + printk(BIOS_ERR, "%s Missing ops_smbus_bus->write_byte", + dev_path(busdev)); + return -1; + } +} diff --git a/src/include/device/i2c_bus.h b/src/include/device/i2c_bus.h index b5e7710..6028e41 100644 --- a/src/include/device/i2c_bus.h +++ b/src/include/device/i2c_bus.h @@ -86,4 +86,10 @@ */ int i2c_dev_read_at16(struct device *, uint8_t *buf, size_t len, uint16_t off); +/* + * Sends the 16-bit register offset `off` followed by the byte `val`. + * + * Returns 0 on success, negative `enum cb_err` value on error. + */ +int i2c_dev_writeb_at16(struct device *, uint16_t off, uint8_t val); #endif /* _DEVICE_I2C_BUS_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/46290 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8ee87fd2175d7c2d4359ece425519aa25df9a16 Gerrit-Change-Number: 46290 Gerrit-PatchSet: 1 Gerrit-Owner: shkim <sh_.kim(a)samsung.com> Gerrit-Reviewer: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[4.11_branch]: mb/siemens/mc_bdx1: Fix IASL warning reported as error
by Mario Scheithauer (Code Review) 12 Oct '20

12 Oct '20

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46129 ) Change subject: mb/siemens/mc_bdx1: Fix IASL warning reported as error ...................................................................... mb/siemens/mc_bdx1: Fix IASL warning reported as error Latest IASL version (20200717) leads to a build error on 4.11_branch. dsdt.asl 1121: Device (UNC0) Warning 3073 - Multiple types (Device object requires either a _HID or _ADR, but not both) This warning reported as error was ignored in older IASL versions. The address object (_ADR) is not needed because a valid hardware ID (_HID) for the device is available. Change-Id: Iae5c91739ed9caea2dbb5996e2f093ed6fc47e93 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_bdx1/dsdt.asl 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/46129/1 diff --git a/src/mainboard/siemens/mc_bdx1/dsdt.asl b/src/mainboard/siemens/mc_bdx1/dsdt.asl index 1248703..76845f5 100644 --- a/src/mainboard/siemens/mc_bdx1/dsdt.asl +++ b/src/mainboard/siemens/mc_bdx1/dsdt.asl @@ -261,7 +261,6 @@ Return (0xff) } - Name (_ADR, 0x00) Method (_STA, 0, NotSerialized) { Return (0xf) -- To view, visit https://review.coreboot.org/c/coreboot/+/46129 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: Iae5c91739ed9caea2dbb5996e2f093ed6fc47e93 Gerrit-Change-Number: 46129 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP] skl: PEG for Optimus
by Benjamin Doron (Code Review) 12 Oct '20

12 Oct '20

Hello build bot (Jenkins), Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/40625 to look at the new patch set (#11). Change subject: [WIP] skl: PEG for Optimus ...................................................................... [WIP] skl: PEG for Optimus Creates PEG ACPI device for Optimus. Bugs: - "Data Link Layer Link Active not set in 1000ms" Tested, nouveau driver works on an Acer Aspire VN7-572G (Skylake-U) and `DRI_PRIME=1 glxinfo` reports the dGPU as renderer. Change-Id: I107bd5f7c192b8ffc83de6d8f1ac314bb5dcbfbd Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> --- M src/soc/intel/skylake/acpi/pch.asl A src/soc/intel/skylake/acpi/peg.asl 2 files changed, 227 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/40625/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/40625 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I107bd5f7c192b8ffc83de6d8f1ac314bb5dcbfbd Gerrit-Change-Number: 40625 Gerrit-PatchSet: 11 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/dedede: Enable SaGv support
by Aamir Bohra (Code Review) 12 Oct '20

12 Oct '20

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45196 ) Change subject: mb/google/dedede: Enable SaGv support ...................................................................... Patch Set 5: (3 comments) https://review.coreboot.org/c/coreboot/+/45196/4//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/45196/4//COMMIT_MSG@7 PS4, Line 7: SaGv support > Does SaGv support depend on mainboard components (e.g. VR), or can it be enabled on any mainboard? […] It can be enabled for any Mainboard. It is more of SoC specific feature. Can be done, But I find it better to be mainboard controlled . given that some early Si samples might recommend the SaGv to be disabled. In that scenario a board control helps. https://review.coreboot.org/c/coreboot/+/45196/4//COMMIT_MSG@9 PS4, Line 9: > nit: no space before the comma Done https://review.coreboot.org/c/coreboot/+/45196/4//COMMIT_MSG@11 PS4, Line 11: > same here Done -- To view, visit https://review.coreboot.org/c/coreboot/+/45196 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f60aad031ce9dfe23e54426753311c35db46c05 Gerrit-Change-Number: 45196 Gerrit-PatchSet: 5 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 12 Oct 2020 05:00:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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coreboot-gerrit October 2020