coreboot-gerrit October 2020

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Change in coreboot[master]: mb/google/dedede: Enable SaGv support
by Patrick Georgi (Code Review) 12 Oct '20

12 Oct '20

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45196 ) Change subject: mb/google/dedede: Enable SaGv support ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/c/coreboot/+/45196/4//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/45196/4//COMMIT_MSG@7 PS4, Line 7: SaGv support > It can be enabled for any Mainboard. It is more of SoC specific feature. […] We (and by this I mean "you" ;-) ) can look for better ways to implement the toggle, but for now this is how it's implemented. -- To view, visit https://review.coreboot.org/c/coreboot/+/45196 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f60aad031ce9dfe23e54426753311c35db46c05 Gerrit-Change-Number: 45196 Gerrit-PatchSet: 5 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Comment-Date: Mon, 12 Oct 2020 08:52:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/jasperlake: Correct SaGv mapping
by Patrick Georgi (Code Review) 12 Oct '20

12 Oct '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45195 ) Change subject: soc/intel/jasperlake: Correct SaGv mapping ...................................................................... soc/intel/jasperlake: Correct SaGv mapping Jasper Lake support 3 Memory train frequencies low. mid and high. Update the SaGv configuration accordingly. Change-Id: I366de1ea7cf41c56b2954b8032c69bfba81058e2 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45195 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Meera Ravindranath <meera.ravindranath(a)intel.com> --- M src/soc/intel/jasperlake/chip.h 1 file changed, 4 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved Meera Ravindranath: Looks good to me, but someone else must approve diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h index 5a87a91..4410de9 100644 --- a/src/soc/intel/jasperlake/chip.h +++ b/src/soc/intel/jasperlake/chip.h @@ -60,16 +60,15 @@ /* TCC activation offset */ uint32_t tcc_offset; - /* System Agent dynamic frequency support. Only effects ULX/ULT CPUs. - * When enabled memory will be training at two different frequencies. - * 0:Disabled, 1:FixedPoint0, 2:FixedPoint1, 3:FixedPoint2, - * 4:FixedPoint3, 5:Enabled */ + /* System Agent dynamic frequency support. + * When enabled memory will be training at different frequencies. + * 0:Disabled, 1:FixedPoint0(low), 2:FixedPoint1(mid), 3:FixedPoint2 + * (high), 4:Enabled */ enum { SaGv_Disabled, SaGv_FixedPoint0, SaGv_FixedPoint1, SaGv_FixedPoint2, - SaGv_FixedPoint3, SaGv_Enabled, } SaGv; -- To view, visit https://review.coreboot.org/c/coreboot/+/45195 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I366de1ea7cf41c56b2954b8032c69bfba81058e2 Gerrit-Change-Number: 45195 Gerrit-PatchSet: 4 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: security/intel/stm: Add options for STM build
by Eugene Myers (Code Review) 12 Oct '20

12 Oct '20

Hello Eugene Myers, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44686 to review the following change. Change subject: security/intel/stm: Add options for STM build ...................................................................... security/intel/stm: Add options for STM build This patch adds options that support building the STM as a part of the coreboot build. The option defaults are set so that the STM can be built for a majority of coreboot platforms. Change-Id: I80ed7cbcb93468c5ff93d089d77742ce7b671a37 Signed-off-by: Eugene D Myers <cedarhouse(a)comcast.net> --- M src/security/intel/stm/Kconfig 1 file changed, 77 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/44686/1 diff --git a/src/security/intel/stm/Kconfig b/src/security/intel/stm/Kconfig index f7dd363..4d963aa 100644 --- a/src/security/intel/stm/Kconfig +++ b/src/security/intel/stm/Kconfig @@ -1,3 +1,4 @@ + config STM bool "Enable STM" default n @@ -27,20 +28,93 @@ config MSEG_SIZE hex "mseg size" - default 0x400000 + default 0x100000 help - STM only - 0x100000 + The MSEG_SIZE of 0x100000 assumes that: + IED_REGION_SIZE = 0x400000 + SMM_RESERVED_SIZE = 0x200000 + SMM_TSEG_SIZE = 0x800000 + To use STM/PE, a larger MSEG_SIZE is necessary. This can be + done by either increasing SMM_TSEG_SIZE or reducing the + IED_REGION_SIZE and/or SMM_RESERVED_SIZE or some combination + of the three. + NOTE: The authors experience is that these configuration + parameters have to be changed at the soc Konfig for them to + be applied. + Minimum sizes: + STM only - 0x100000 - Supports up to 38 processor threads + - 0x200000 - Supports up to 102 processor threads STM/PE - 0x300000+ depending on the amount of memory needed for the protected execution virtual machine (VM/PE) +config STM_STMPE_ENABLED + bool "STM/PE Enabled" + default n + help + STM/PE provides for additional virtual machines in SMRAM + that provides a protected execution environment for + applications such as introspection, which need to be + protected from malicious code. More information can be + found on the stmpe branch of + ssh://review.coreboot.org/STM + + config BIOS_RESOURCE_LIST_SIZE hex "bios_resource_list_size" default 0x1000 + help + The BIOS resource list defines the resources that the + SMI Handler needs. This list is created during the + coreboot bootup. Unless there has been a lot of elements + added to this list, this value should not change. config STM_BINARY_FILE string "STM binary file" - default "3rdparty/blobs/cpu/intel/stm/stm.bin" + default "payloads/external/stm/STM/Stm/build/StmPkg/Core/stm.bin" + help + Location of the STM binary file. The default location is + where the file will be located when coreboot builds + the STM. + Old location is "3rdparty/blobs/cpu/intel/stm/stm.bin" + +config STM_HEAPSIZE + hex "stm_heapsize" + default 0x46000 + help + The STM_HEAPSIZE defines the heap space that is available + to the STM. The default size assumes a MSEG_SIZE of 0x100000. + For STM/PE this size should be a minimum of 0x246000. + +config STM_UART + hex "stm_uart" + default 0x3F8 + help + Defines the serial port for the STM to send its console + output to. + +config STM_CBMEM_CONSOLE + bool "STM cbmem console" + default n + depends on CONSOLE_CBMEM + help + Places the STM console output into the cbmem. + + +config STM_BUILD + string "stm_build" + default "debug" + help + The default (debug) build will generate runtime console output. + "release" will deactivate the console output. + +config STM_GIT_REPO + string "stm_git_repo" + default "https://review.coreboot.org/STM" + +config STM_GIT_BRANCH + string "stm_git_branch" + default "stmpe" endmenu #STM -- To view, visit https://review.coreboot.org/c/coreboot/+/44686 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I80ed7cbcb93468c5ff93d089d77742ce7b671a37 Gerrit-Change-Number: 44686 Gerrit-PatchSet: 1 Gerrit-Owner: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-Reviewer: Eugene Myers <cedarhouse(a)comcast.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer/variants/baseboard: Fix the typo for power limit va...
by Sumeet R Pawnikar (Code Review) 12 Oct '20

12 Oct '20

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46220 ) Change subject: mb/google/volteer/variants/baseboard: Fix the typo for power limit values ...................................................................... mb/google/volteer/variants/baseboard: Fix the typo for power limit values Fix the typo for power limit values under comment section BUG=None BRANCH=None TEST=Build for volteer system Change-Id: I879b9587e863360bf4efda4099d96b42b904377e Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/46220/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 7790230..a32d711 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -376,8 +376,8 @@ [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 75, SHUTDOWN)}" ## Power Limits Control - # 10-15W PL1 in 200mW increments, avg over 28-32s interval - # PL2 is fixed at 64W, avg over 28-32s interval + # 3-15W PL1 in 200mW increments, avg over 28-32s interval + # PL2 is fixed at 60W, avg over 28-32s interval register "controls.power_limits" = "{ .pl1 = {.min_power = 3000, .max_power = 15000, -- To view, visit https://review.coreboot.org/c/coreboot/+/46220 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I879b9587e863360bf4efda4099d96b42b904377e Gerrit-Change-Number: 46220 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/block/smm: Fix compilation without intel uart code
by Patrick Rudolph (Code Review) 12 Oct '20

12 Oct '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46224 ) Change subject: soc/intel/common/block/smm: Fix compilation without intel uart code ...................................................................... soc/intel/common/block/smm: Fix compilation without intel uart code Allow to link the smihandler when not selecting SOC_INTEL_COMMON_BLOCK_UART. Change-Id: Iabca81c958d00c48e0616579cbba61d254c5eb68 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/common/block/smm/smihandler.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/46224/1 diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index ab88a51..270b1aa 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -200,8 +200,8 @@ break; case ACPI_S3: printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n"); - - gnvs->uior = uart_is_controller_initialized(); + if (CONFIG(SOC_INTEL_COMMON_BLOCK_UART)) + gnvs->uior = uart_is_controller_initialized(); /* Invalidate the cache before going to S3 */ wbinvd(); -- To view, visit https://review.coreboot.org/c/coreboot/+/46224 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iabca81c958d00c48e0616579cbba61d254c5eb68 Gerrit-Change-Number: 46224 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/ocp/deltalake: Select correct uart for console
by Patrick Rudolph (Code Review) 12 Oct '20

12 Oct '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46223 ) Change subject: mb/ocp/deltalake: Select correct uart for console ...................................................................... mb/ocp/deltalake: Select correct uart for console Tested on OCP deltalake. The console now shows up on the serial. Change-Id: If4c412c1ca749f1feba47b2ce0beb52d0111be86 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/ocp/deltalake/Kconfig 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/46223/1 diff --git a/src/mainboard/ocp/deltalake/Kconfig b/src/mainboard/ocp/deltalake/Kconfig index 9d9b259..ff5599c 100644 --- a/src/mainboard/ocp/deltalake/Kconfig +++ b/src/mainboard/ocp/deltalake/Kconfig @@ -16,6 +16,10 @@ select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM2 +config UART_FOR_CONSOLE + int + default 1 + config POWER_STATE_DEFAULT_ON_AFTER_FAILURE default n -- To view, visit https://review.coreboot.org/c/coreboot/+/46223 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4c412c1ca749f1feba47b2ce0beb52d0111be86 Gerrit-Change-Number: 46223 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/block/i2c: Scan bridge devices behind I2C controllers
by Karthik Ramasubramanian (Code Review) 12 Oct '20

12 Oct '20

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45949 ) Change subject: soc/intel/common/block/i2c: Scan bridge devices behind I2C controllers ...................................................................... soc/intel/common/block/i2c: Scan bridge devices behind I2C controllers Scan bridge devices like I2C Mutiplexers behind I2C controllers using scan_static_bus. BUG=b:169444894 TEST=Build and boot waddledee to OS. Ensure that all the bridge devices behind I2C controller are scanned and enabled. Change-Id: I9d8159a507683d8c56dd5e59d20c30ed7e4b2cab Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/soc/intel/common/block/i2c/i2c.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/45949/1 diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c index 0de3bd3..5aa7729 100644 --- a/src/soc/intel/common/block/i2c/i2c.c +++ b/src/soc/intel/common/block/i2c/i2c.c @@ -166,7 +166,7 @@ .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .scan_bus = scan_smbus, + .scan_bus = scan_static_bus, .ops_i2c_bus = &dw_i2c_bus_ops, .ops_pci = &pci_dev_ops_pci, .init = dw_i2c_device_init, -- To view, visit https://review.coreboot.org/c/coreboot/+/45949 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d8159a507683d8c56dd5e59d20c30ed7e4b2cab Gerrit-Change-Number: 45949 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/tglrvp: Enable early EC sync
by Anil Kumar K (Code Review) 12 Oct '20

12 Oct '20

Anil Kumar K has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44689 ) Change subject: mb/intel/tglrvp: Enable early EC sync ...................................................................... mb/intel/tglrvp: Enable early EC sync - This change is required to execute EC sync in coreboot instead of depthcharge Bug=none Test=build and boot coreboot on TGLRVP Signed-off-by: Anil Kumar <anil.kumar.k(a)intel.com> Change-Id: I40ae104d4de93c12097e049253a33b23a46c6203 --- M src/mainboard/intel/tglrvp/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/44689/1 diff --git a/src/mainboard/intel/tglrvp/Kconfig b/src/mainboard/intel/tglrvp/Kconfig index 3e55f56..eeeecc1 100644 --- a/src/mainboard/intel/tglrvp/Kconfig +++ b/src/mainboard/intel/tglrvp/Kconfig @@ -28,6 +28,7 @@ select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN select GBB_FLAG_FORCE_DEV_SWITCH_ON select GBB_FLAG_FORCE_DEV_BOOT_USB + select VBOOT_EARLY_EC_SYNC config MAINBOARD_DIR string -- To view, visit https://review.coreboot.org/c/coreboot/+/44689 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40ae104d4de93c12097e049253a33b23a46c6203 Gerrit-Change-Number: 44689 Gerrit-PatchSet: 1 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/tglrvp: Enable TPM
by Anil Kumar K (Code Review) 12 Oct '20

12 Oct '20

Anil Kumar K has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44698 ) Change subject: mb/intel/tglrvp: Enable TPM ...................................................................... mb/intel/tglrvp: Enable TPM Bug=none Test=emerge build successful on tglrvpwq Signed-off-by: Anil Kumar <anil.kumar.k(a)intel.com> Change-Id: I4a3aec98f72524e8e2a1834878ef75b9f933ae3e --- M src/drivers/spi/tpm/tpm.c M src/mainboard/intel/tglrvp/Kconfig 2 files changed, 9 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/44698/1 diff --git a/src/drivers/spi/tpm/tpm.c b/src/drivers/spi/tpm/tpm.c index 4263dce..bc9f06e 100644 --- a/src/drivers/spi/tpm/tpm.c +++ b/src/drivers/spi/tpm/tpm.c @@ -157,6 +157,8 @@ for (i = 0; i < 3; i++) header.body[i + 1] = (addr >> (8 * (2 - i))) & 0xff; + udelay(100); + /* CS assert wakes up the slave. */ spi_claim_bus(&spi_slave); diff --git a/src/mainboard/intel/tglrvp/Kconfig b/src/mainboard/intel/tglrvp/Kconfig index eeeecc1..e4c29f8 100644 --- a/src/mainboard/intel/tglrvp/Kconfig +++ b/src/mainboard/intel/tglrvp/Kconfig @@ -18,6 +18,9 @@ select DRIVERS_INTEL_ISH select EC_ACPI select PCIEXP_HOTPLUG + select MAINBOARD_HAS_TPM2 + select MAINBOARD_HAS_SPI_TPM_CR50 + select SPI_TPM config CHROMEOS bool @@ -100,9 +103,12 @@ config VBOOT select VBOOT_LID_SWITCH - select VBOOT_MOCK_SECDATA config UART_FOR_CONSOLE int default 2 + +config DRIVER_TPM_SPI_BUS + default 0x2 + endif -- To view, visit https://review.coreboot.org/c/coreboot/+/44698 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a3aec98f72524e8e2a1834878ef75b9f933ae3e Gerrit-Change-Number: 44698 Gerrit-PatchSet: 1 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/intelp2m: Update output fotmat of generated gpio.h
by Maxim Polyakov (Code Review) 12 Oct '20

12 Oct '20

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45168 ) Change subject: util/intelp2m: Update output fotmat of generated gpio.h ...................................................................... util/intelp2m: Update output fotmat of generated gpio.h Update the format of the generated gpio.h file: For PAD_CFG*() macro: /* GPIO_39 - LPSS_UART0_TXD */ --> (i) /* DW0: 0x44000400, DW1: 0x00003100 */ --> (ii) /* DW0 : PAD_TRIG(OFF) - IGNORED */ --> (iii, iiii) PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), For fields: /* GPIO_39 - LPSS_UART0_TXD */ --> (i) /* DW0: 0x44000400, DW1: 0x00003100 */ --> (ii) /* PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), */ --> (iii) /* DW0 : PAD_TRIG(OFF) - IGNORED */ --> (iiii) _PAD_CFG_STRUCT(GPIO_39, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(UP_20K) | PAD_IOSTERM(DISPUPD)), TEST = ./intelp2m -n -file inteltool.log; ./intelp2m -fld cb -file inteltool.log; ./intelp2m -fld fsp -file inteltool.log; ./intelp2m -fld raw -file inteltool.log. Before and after the patch, gpio.h is no different. Change-Id: I760f4aadece786ea455fb7569f42e06fefce2b61 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M util/intelp2m/description.md M util/intelp2m/fields/cb/cb.go M util/intelp2m/parser/parser.go M util/intelp2m/platforms/common/macro.go 4 files changed, 84 insertions(+), 93 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/45168/1 diff --git a/util/intelp2m/description.md b/util/intelp2m/description.md index add9c2c..0380d1f 100644 --- a/util/intelp2m/description.md +++ b/util/intelp2m/description.md @@ -79,34 +79,13 @@ ``` ```c -/* GPP_A10 - CLKOUT_LPC1 DW0: 0x44000500, DW1: 0x00000000 */ +/* GPP_A10 - CLKOUT_LPC1 */ +/* DW0: 0x44000500, DW1: 0x00000000 */ /* PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), */ /* DW0 : 0x04000100 - IGNORED */ _PAD_CFG_STRUCT(GPP_A10, 0x44000500, 0x00000000), ``` -### FSP-style macro - -The utility allows to generate macros that include fsp/edk2-palforms style bitfields: - -```bash -(shell)$ ./intelp2m -fld fsp -p lbg -file ../crb-inteltool.log -``` - -```c -{ GPIO_SKL_H_GPP_A12, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInvOut, GpioOutLow, GpioIntSci | GpioIntLvlEdgDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock }, /* GPIO */ -``` - -```bash -(shell)$ ./intelp2m -iiii -fld fsp -p lbg -file ../crb-inteltool.log -``` - -```c -/* GPP_A12 - GPIO DW0: 0x80880102, DW1: 0x00000000 */ -/* PAD_CFG_GPI_SCI(GPP_A12, NONE, PLTRST, LEVEL, INVERT), */ -{ GPIO_SKL_H_GPP_A12, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInvOut, GpioOutLow, GpioIntSci | GpioIntLvlEdgDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock }, -``` - ### Macro Check After generating the macro, the utility checks all used @@ -129,17 +108,9 @@ ### Information level The utility can generate additional information about the bit -fields of the DW0 and DW1 configuration registers: - -```c -/* GPIO_39 - LPSS_UART0_TXD (DW0: 0x44000400, DW1: 0x00003100) */ --> (2) -/* PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), */ --> (3) -/* DW0 : PAD_TRIG(OFF) - IGNORED */ --> (4) -_PAD_CFG_STRUCT(GPIO_39, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(UP_20K) | PAD_IOSTERM(DISPUPD)), -``` - -Using the options -i, -ii, -iii, -iiii you can set the info level -from (1) to (4): +fields of the DW0 and DW1 configuration registers. Using the +options -i, -ii, -iii, -iiii you can set the info level from +1 to 4: ```bash (shell)$./intelp2m -i -file /path/to/inteltool.log @@ -147,33 +118,13 @@ (shell)$./intelp2m -iii -file /path/to/inteltool.log (shell)$./intelp2m -iiii -file /path/to/inteltool.log ``` -(1) : print /* GPIO_39 - LPSS_UART0_TXD */ - -(2) : print initial raw values of configuration registers from -inteltool dump -DW0: 0x44000400, DW1: 0x00003100 - -(3) : print the target macro that will generate if you use the --n option -PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), - -(4) : print decoded fields from (3) as macros -DW0 : PAD_TRIG(OFF) - IGNORED - -### Ignoring Fields - -Utilities can generate the _PAD_CFG_STRUCT macro and exclude fields -from it that are not in the corresponding PAD_CFG_*() macro: - -```bash -(shell)$ ./intelp2m -iiii -fld cb -ign -file /path/to/inteltool.log -``` ```c -/* GPIO_39 - LPSS_UART0_TXD DW0: 0x44000400, DW1: 0x00003100 */ -/* PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), */ -/* DW0 : PAD_TRIG(OFF) - IGNORED */ -_PAD_CFG_STRUCT(GPIO_39, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(UP_20K) | PAD_IOSTERM(DISPUPD)), +/* GPIO_39 - LPSS_UART0_TXD */ --> (i) +/* DW0: 0x44000400, DW1: 0x00003100 */ --> (ii) +/* PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), */ --> (iii) +/* DW0 : PAD_TRIG(OFF) - IGNORED */ --> (iiii) +_PAD_CFG_STRUCT(GPIO_39, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(UP_20K) | PAD_IOSTERM(DISPUPD)), ``` If you generate macros without checking, you can see bit fields that @@ -184,19 +135,51 @@ ``` ```c -/* GPIO_39 - LPSS_UART0_TXD DW0: 0x44000400, DW1: 0x00003100 */ +/* GPIO_39 - LPSS_UART0_TXD */ --> (i) +/* DW0: 0x44000400, DW1: 0x00003100 */ --> (ii) +/* DW0 : PAD_TRIG(OFF) - IGNORED */ --> (iii, iiii) PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), -/* DW0 : PAD_TRIG(OFF) - IGNORED */ ``` +### Ignoring Fields + +Utilities can generate the _PAD_CFG_STRUCT macro and exclude fields +from it that are not in the corresponding PAD_CFG_*() macro: ```bash -(shell)$ ./intelp2m -n -file /path/to/inteltool.log +(shell)$ ./intelp2m -iiii -fld cb -ign -file /path/to/inteltool.log ``` ```c /* GPIO_39 - LPSS_UART0_TXD */ -PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), +/* DW0: 0x44000400, DW1: 0x00003100 */ +/* PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), */ +/* DW0 : PAD_TRIG(OFF) - IGNORED */ +_PAD_CFG_STRUCT(GPIO_39, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(UP_20K) | PAD_IOSTERM(DISPUPD)), ``` + +### FSP-style macro + +The utility allows to generate macros that include fsp/edk2-palforms style bitfields: + +```bash +(shell)$ ./intelp2m -fld fsp -p lbg -file ../crb-inteltool.log +``` + +```c +{ GPIO_SKL_H_GPP_A12, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInvOut, GpioOutLow, GpioIntSci | GpioIntLvlEdgDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock }, /* GPIO */ +``` + +```bash +(shell)$ ./intelp2m -iiii -fld fsp -p lbg -file ../crb-inteltool.log +``` + +```c +/* GPP_A12 - GPIO */ +/* DW0: 0x80880102, DW1: 0x00000000 */ +/* PAD_CFG_GPI_SCI(GPP_A12, NONE, PLTRST, LEVEL, INVERT), */ +{ GPIO_SKL_H_GPP_A12, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInvOut, GpioOutLow, GpioIntSci | GpioIntLvlEdgDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock }, +``` + ### Supports Chipsets Sunrise PCH, Lewisburg PCH, Apollo Lake SoC, CannonLake-LP SoCs diff --git a/util/intelp2m/fields/cb/cb.go b/util/intelp2m/fields/cb/cb.go index 61f59c4..0e254dd 100644 --- a/util/intelp2m/fields/cb/cb.go +++ b/util/intelp2m/fields/cb/cb.go @@ -50,7 +50,7 @@ generate( &field { prefix : "PAD_FUNC", - unhide : config.InfoLevelGet() <= 3 || dw0.GetPadMode() != 0, + unhide : config.InfoLevelGet() < 3 || dw0.GetPadMode() != 0, configurator : func() { macro.Padfn() }, }, diff --git a/util/intelp2m/parser/parser.go b/util/intelp2m/parser/parser.go index d4c04cd..c35d4e7 100644 --- a/util/intelp2m/parser/parser.go +++ b/util/intelp2m/parser/parser.go @@ -66,9 +66,9 @@ // macro : string of the generated macro func (info *padInfo) padInfoMacroFprint(macro string) { info.generate(2, "\n") - info.generate(1, "\t/* %s - %s ", info.id, info.function) - info.generate(2, "DW0: 0x%0.8x, DW1: 0x%0.8x ", info.dw0, info.dw1) - info.generate(1, "*/\n") + info.generate(1, "\t/* %s - %s */", info.id, info.function) + info.generate(2, "\n\t/* DW0: 0x%0.8x, DW1: 0x%0.8x */", info.dw0, info.dw1) + info.generate(1, "\n") info.generate(0, "\t%s", macro) if config.InfoLevelGet() == 0 { info.generate(0, "\t/* %s */", info.function) diff --git a/util/intelp2m/platforms/common/macro.go b/util/intelp2m/platforms/common/macro.go index e30ef22..51705bb 100644 --- a/util/intelp2m/platforms/common/macro.go +++ b/util/intelp2m/platforms/common/macro.go @@ -292,32 +292,33 @@ return macro } -// AddToMacroIgnoredMask - Print info about ignored field mask -// title - warning message -func (macro *Macro) AddToMacroIgnoredMask() *Macro { - if config.InfoLevelGet() < 4 || config.IsFspStyleMacro() { +// DecodeIgnored - Add info about ignored field mask +// reg : PAD_CFG_DW0 or PAD_CFG_DW1 register +func (macro *Macro) DecodeIgnored(reg uint8) *Macro { + var decode = map[uint8]func() { + PAD_CFG_DW0: macro.Fields.DecodeDW0, + PAD_CFG_DW1: macro.Fields.DecodeDW1, + } + decodefn, valid := decode[reg] + if !valid || config.IsFspStyleMacro() { return macro } - dw0 := macro.Register(PAD_CFG_DW0) - dw1 := macro.Register(PAD_CFG_DW1) - // Get mask of ignored bit fields. - dw0Ignored := dw0.IgnoredFieldsGet() - dw1Ignored := dw1.IgnoredFieldsGet() - if dw0Ignored != 0 { - dw0temp := dw0.ValueGet() - dw0.ValueSet(dw0Ignored) - macro.Add("\n\t/* DW0 : ") - macro.Fields.DecodeDW0() + dw := macro.Register(reg) + ignored := dw.IgnoredFieldsGet() + if ignored != 0 { + temp := dw.ValueGet() + dw.ValueSet(ignored) + if !config.IsNonCheckingFlagUsed() { + macro.Add("\n\t") + } + regnum := strconv.Itoa(int(reg)) + macro.Add("/* DW" + regnum + " : ") + decodefn() macro.Add(" - IGNORED */") - dw0.ValueSet(dw0temp) - } - if dw1Ignored != 0 { - dw1temp := dw1.ValueGet() - dw1.ValueSet(dw1Ignored) - macro.Add("\n\t/* DW1 : ") - macro.Fields.DecodeDW1() - macro.Add(" - IGNORED */") - dw1.ValueSet(dw1temp) + if config.IsNonCheckingFlagUsed() { + macro.Add("\n\t") + } + dw.ValueSet(temp) } return macro } @@ -338,7 +339,9 @@ reference := macro.Get() macro.Clear() macro.Add("/* ").Add(reference).Add(" */") - macro.AddToMacroIgnoredMask() + if config.InfoLevelGet() >= 4 { + macro.DecodeIgnored(PAD_CFG_DW0).DecodeIgnored(PAD_CFG_DW1) + } macro.Add("\n\t") } if config.AreFieldsIgnored() { @@ -409,8 +412,13 @@ } if config.IsNonCheckingFlagUsed() { - macro.AddToMacroIgnoredMask() - return macro.Get() + body := macro.Get() + if config.InfoLevelGet() >= 3 { + macro.Clear().DecodeIgnored(PAD_CFG_DW0).DecodeIgnored(PAD_CFG_DW1) + comment := macro.Get() + return comment + body + } + return body } return macro.check().Get() -- To view, visit https://review.coreboot.org/c/coreboot/+/45168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I760f4aadece786ea455fb7569f42e06fefce2b61 Gerrit-Change-Number: 45168 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit October 2020