Change in coreboot[master]: soc/intel/common/block/smm: Fix compilation without intel uart code

[Patrick Rudolph (Code Review)]

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46224 )

Change subject: soc/intel/common/block/smm: Fix compilation without intel uart code
......................................................................

soc/intel/common/block/smm: Fix compilation without intel uart code

Allow to link the smihandler when not selecting SOC_INTEL_COMMON_BLOCK_UART.

Change-Id: Iabca81c958d00c48e0616579cbba61d254c5eb68
Signed-off-by: Patrick Rudolph 
---
M src/soc/intel/common/block/smm/smihandler.c
1 file changed, 2 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/46224/1

diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c
index ab88a51..270b1aa 100644
--- a/src/soc/intel/common/block/smm/smihandler.c
+++ b/src/soc/intel/common/block/smm/smihandler.c
@@ -200,8 +200,8 @@
    	break;
    case ACPI_S3:
    	printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n");
-
-		gnvs->uior = uart_is_controller_initialized();
+		if (CONFIG(SOC_INTEL_COMMON_BLOCK_UART))
+			gnvs->uior = uart_is_controller_initialized();

/* Invalidate the cache before going to S3 */
    	wbinvd();

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46224 )

Change subject: soc/intel/common/block/smm: Fix compilation without intel uart code
......................................................................

Patch Set 1: Code-Review+2

[Christian Walter (Code Review)]

Christian Walter has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46224 )

Change subject: soc/intel/common/block/smm: Fix compilation without intel uart code
......................................................................

Patch Set 1: Code-Review+2

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46224 )

Change subject: soc/intel/common/block/smm: Fix compilation without intel uart code
......................................................................

soc/intel/common/block/smm: Fix compilation without intel uart code

Allow to link the smihandler when not selecting SOC_INTEL_COMMON_BLOCK_UART.

Change-Id: Iabca81c958d00c48e0616579cbba61d254c5eb68
Signed-off-by: Patrick Rudolph 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46224
Tested-by: build bot (Jenkins) 
Reviewed-by: Furquan Shaikh 
Reviewed-by: Christian Walter 
---
M src/soc/intel/common/block/smm/smihandler.c
1 file changed, 2 insertions(+), 2 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved
  Christian Walter: Looks good to me, approved

diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c
index ab88a51..270b1aa 100644
--- a/src/soc/intel/common/block/smm/smihandler.c
+++ b/src/soc/intel/common/block/smm/smihandler.c
@@ -200,8 +200,8 @@
    	break;
    case ACPI_S3:
    	printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n");
-
-		gnvs->uior = uart_is_controller_initialized();
+		if (CONFIG(SOC_INTEL_COMMON_BLOCK_UART))
+			gnvs->uior = uart_is_controller_initialized();

/* Invalidate the cache before going to S3 */
    	wbinvd();