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Change in coreboot[master]: arch/x86/smbios: Update SMBIOS type 0 ec version
by Tim Chu (Code Review) 12 Oct '20

12 Oct '20

Tim Chu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45138 ) Change subject: arch/x86/smbios: Update SMBIOS type 0 ec version ...................................................................... arch/x86/smbios: Update SMBIOS type 0 ec version Get embedded controller firmware version and update to SMBIOS type 0. Here BMC version is used to represent ec version. TEST=Execute "dmidecode -t 0" to check if the ec version is correct Signed-off-by: Tim Chu <Tim.Chu(a)quantatw.com> Change-Id: Ibd5ee27a1b8fa4e5bc66e359d3b62e052e19e8a2 --- M src/arch/x86/smbios.c M src/arch/x86/smbios_defaults.c M src/drivers/ipmi/ipmi_kcs_ops.c M src/include/smbios.h 4 files changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/45138/1 diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 6c92d03..4a3a2e1 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -396,6 +396,7 @@ { struct smbios_type0 *t = (struct smbios_type0 *)*current; int len = sizeof(struct smbios_type0); + u8 ipmi_bmc_major_revision, ipmi_bmc_minor_revision; memset(t, 0, sizeof(struct smbios_type0)); t->type = SMBIOS_BIOS_INFORMATION; @@ -424,6 +425,10 @@ t->system_bios_major_release = coreboot_major_revision; t->system_bios_minor_release = coreboot_minor_revision; + smbios_ec_revision(&ipmi_bmc_major_revision, &ipmi_bmc_minor_revision); + t->ec_major_release = ipmi_bmc_major_revision; + t->ec_minor_release = ipmi_bmc_minor_revision; + t->bios_characteristics = BIOS_CHARACTERISTICS_PCI_SUPPORTED | BIOS_CHARACTERISTICS_SELECTABLE_BOOT | diff --git a/src/arch/x86/smbios_defaults.c b/src/arch/x86/smbios_defaults.c index 22ce7a5..9ff645c 100644 --- a/src/arch/x86/smbios_defaults.c +++ b/src/arch/x86/smbios_defaults.c @@ -63,6 +63,12 @@ return SMBIOS_BOARD_TYPE_UNKNOWN; } +__weak void smbios_ec_revision(uint8_t *ipmi_bmc_major_revision, uint8_t *ipmi_bmc_minor_revision) +{ + *ipmi_bmc_major_revision = 0x0; + *ipmi_bmc_minor_revision = 0x0; +} + /* * System Enclosure or Chassis Types as defined in SMBIOS specification. * The default value is SMBIOS_ENCLOSURE_DESKTOP (0x03) but laptop, diff --git a/src/drivers/ipmi/ipmi_kcs_ops.c b/src/drivers/ipmi/ipmi_kcs_ops.c index 7fa28e3..aa07aa9 100644 --- a/src/drivers/ipmi/ipmi_kcs_ops.c +++ b/src/drivers/ipmi/ipmi_kcs_ops.c @@ -28,6 +28,9 @@ static u8 ipmi_revision_major = 0x1; static u8 ipmi_revision_minor = 0x0; +static u8 bmc_revision_major = 0x0; +static u8 bmc_revision_minor = 0x0; + static int ipmi_get_device_id(struct device *dev, struct ipmi_devid_rsp *rsp) { int ret; @@ -144,6 +147,9 @@ ipmi_revision_minor = IPMI_IPMI_VERSION_MINOR(rsp.ipmi_version); ipmi_revision_major = IPMI_IPMI_VERSION_MAJOR(rsp.ipmi_version); + bmc_revision_major = rsp.fw_rev1; + bmc_revision_minor = rsp.fw_rev2; + memcpy(&man_id, rsp.manufacturer_id, sizeof(rsp.manufacturer_id)); @@ -272,6 +278,12 @@ } #endif +void smbios_ec_revision(uint8_t *ipmi_bmc_major_revision, uint8_t *ipmi_bmc_minor_revision) +{ + *ipmi_bmc_major_revision = ((bmc_revision_major / 16) * 10) + (bmc_revision_major % 16); + *ipmi_bmc_minor_revision = ((bmc_revision_minor / 16) * 10) + (bmc_revision_minor % 16); +} + #if CONFIG(GENERATE_SMBIOS_TABLES) static int ipmi_smbios_data(struct device *dev, int *handle, unsigned long *current) diff --git a/src/include/smbios.h b/src/include/smbios.h index 521339e..fdc6b10 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -54,6 +54,9 @@ const char *smbios_chassis_serial_number(void); const char *smbios_processor_serial_number(void); +void smbios_ec_revision(uint8_t *ipmi_bmc_major_revision, + uint8_t *ipmi_bmc_minor_revision); + unsigned int smbios_processor_external_clock(void); unsigned int smbios_processor_characteristics(void); struct cpuid_result; -- To view, visit https://review.coreboot.org/c/coreboot/+/45138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd5ee27a1b8fa4e5bc66e359d3b62e052e19e8a2 Gerrit-Change-Number: 45138 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

7 21

Change in coreboot[master]: arch/x86/smbios: Update SMBIOS type 4 socket designation
by Tim Chu (Code Review) 12 Oct '20

12 Oct '20

Tim Chu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45443 ) Change subject: arch/x86/smbios: Update SMBIOS type 4 socket designation ...................................................................... arch/x86/smbios: Update SMBIOS type 4 socket designation Add socket designation in type 4 smbios. TEST=Execute "dmidecode -t 4" to check if the socket designation is correct Signed-off-by: Tim Chu <Tim.Chu(a)quantatw.com> Change-Id: Icfdc201bd5b5921816bdce6c009a9db48c997e2e --- M src/arch/x86/smbios.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/45443/1 diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 7516305..0600bf4 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -552,6 +552,8 @@ struct smbios_type4 *t = (struct smbios_type4 *)*current; int len = sizeof(struct smbios_type4); uint16_t characteristics = 0; + uint8_t cnt = 0; + char buf[8]; /* Provide sane defaults even for CPU without CPUID */ res.eax = res.edx = 0; @@ -564,6 +566,10 @@ t->type = SMBIOS_PROCESSOR_INFORMATION; t->handle = handle; t->length = len - 2; + + snprintf(buf, sizeof(buf), "CPU%x", cnt++); + t->socket_designation = smbios_add_string(t->eos, buf); + t->processor_id[0] = res.eax; t->processor_id[1] = res.edx; t->processor_manufacturer = smbios_cpu_vendor(t->eos); -- To view, visit https://review.coreboot.org/c/coreboot/+/45443 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icfdc201bd5b5921816bdce6c009a9db48c997e2e Gerrit-Change-Number: 45443 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

5 10

Change in coreboot[master]: mb/google/dedede: update devicetree for Boten
by Alec Wang (Code Review) 12 Oct '20

12 Oct '20

Alec Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45732 ) Change subject: mb/google/dedede: update devicetree for Boten ...................................................................... mb/google/dedede: update devicetree for Boten Add trackpad, touchscreen, and usb port to devicetree BUG=b:160664447 BRANCH=NONE TEST=build bios and verify theirs function for boten Signed-off-by: alec.wang <alec.wang(a)lcfc.corp-partner.google.com> Change-Id: I057f7d15d20d1a78acd733cc5463357e9c87afb2 --- M src/mainboard/google/dedede/variants/boten/overridetree.cb 1 file changed, 75 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/45732/1 diff --git a/src/mainboard/google/dedede/variants/boten/overridetree.cb b/src/mainboard/google/dedede/variants/boten/overridetree.cb index 61dff93..33911d3 100644 --- a/src/mainboard/google/dedede/variants/boten/overridetree.cb +++ b/src/mainboard/google/dedede/variants/boten/overridetree.cb @@ -35,7 +35,82 @@ .speed = I2C_SPEED_FAST, }, }" + + # USB Port Configuration + register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Not Used + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # UF Camera + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # WF Camera + device domain 0 on + device pci 14.0 on + chip drivers/usb/acpi + register "desc" = ""Root Hub"" + register "type" = "UPC_TYPE_HUB" + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""Right Type-A Port"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 2.1 on end + end + chip drivers/usb/acpi + register "desc" = ""UFCamera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.5 on end + end + chip drivers/usb/acpi + register "desc" = ""WFCamera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.6 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 3.1 on end + end + end + end + end # USB xHCI + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_B3)" + register "wake" = "GPE0_DW0_03" + register "probed" = "1" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_B3)" + register "generic.wake" = "GPE0_DW0_03" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 0x2c on end + end + end # I2C 0 + device pci 15.1 off end # I2C 1 + device pci 15.2 on + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D4)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" + register "generic.reset_delay_ms" = "120" + register "generic.reset_off_delay_ms" = "3" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" + register "generic.enable_delay_ms" = "12" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 0x5d on end + end + end # I2C 2 + device pci 15.3 off end # I2C 3 device pci 19.0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" -- To view, visit https://review.coreboot.org/c/coreboot/+/45732 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I057f7d15d20d1a78acd733cc5463357e9c87afb2 Gerrit-Change-Number: 45732 Gerrit-PatchSet: 1 Gerrit-Owner: Alec Wang <alec.wang(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newchange

4 26

Change in coreboot[master]: intelmetool: Add PCI ID for Cometlake-U
by Matt DeVillier (Code Review) 12 Oct '20

12 Oct '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45929 ) Change subject: intelmetool: Add PCI ID for Cometlake-U ...................................................................... intelmetool: Add PCI ID for Cometlake-U Tested on out-of-tree CML-U Purism board Change-Id: I0371e913a75e47b8e6f5a3e4da47b1e401a72b5d Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm> --- M util/intelmetool/intelmetool.h 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/45929/1 diff --git a/util/intelmetool/intelmetool.h b/util/intelmetool/intelmetool.h index bab661f..d6dd3b2 100644 --- a/util/intelmetool/intelmetool.h +++ b/util/intelmetool/intelmetool.h @@ -426,6 +426,7 @@ #define PCI_DEVICE_ID_INTEL_WILDCAT_2 0x9CBB /* Wildcat Point LP 2 */ #define PCI_DEVICE_ID_INTEL_SUNRISE_LP 0x9d3a /* SUNRISE Point-LP */ #define PCI_DEVICE_ID_INTEL_CANNONPOINT_LP 0x9de0 /* Cannon Point-LP */ +#define PCI_DEVICE_ID_INTEL_COMETPOINT_LP 0x02e0 /* Comet Point-LP (Cometlake-U) */ #define PCI_DEVICE_ID_INTEL_SUNRISE_H1_ME 0xa13a /* SUNRISE Point-H 1 */ #define PCI_DEVICE_ID_INTEL_SUNRISE_H2_ME 0xa13b /* SUNRISE Point-H 2 */ #define PCI_DEVICE_ID_INTEL_SUNRISE_H3_ME 0xA13E /* SUNRISE Point-H 3 */ @@ -479,6 +480,7 @@ ((x) == PCI_DEVICE_ID_INTEL_WILDCAT_2) || \ ((x) == PCI_DEVICE_ID_INTEL_SUNRISE_LP) || \ ((x) == PCI_DEVICE_ID_INTEL_CANNONPOINT_LP) || \ + ((x) == PCI_DEVICE_ID_INTEL_COMETPOINT_LP) || \ ((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H1_ME) || \ ((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H2_ME) || \ ((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H3_ME) || \ -- To view, visit https://review.coreboot.org/c/coreboot/+/45929 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0371e913a75e47b8e6f5a3e4da47b1e401a72b5d Gerrit-Change-Number: 45929 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: mb/google/volteer/variants/eldrid: add spd for H5ANAG6NCJR-XNC
by Nick Vaccaro (Code Review) 12 Oct '20

12 Oct '20

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45963 ) Change subject: mb/google/volteer/variants/eldrid: add spd for H5ANAG6NCJR-XNC ...................................................................... mb/google/volteer/variants/eldrid: add spd for H5ANAG6NCJR-XNC Add spd support for DDR4 memory part H5ANAG6NCJR-XNC. Eldrid should use DRAM_ID strap ID 4 (0100) on SKUs populated with H5ANAG6NCJR-XNC DDR4 memory parts. BUG=b:161772961 TEST="FW_NAME=eldrid emerge-volteer coreboot" and verify it builds successfully. Change-Id: Ia26315479ce1a749a0f7c9e81f134f7068d7eb0b Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/volteer/variants/eldrid/memory/Makefile.inc M src/mainboard/google/volteer/variants/eldrid/memory/dram_id.generated.txt M src/mainboard/google/volteer/variants/eldrid/memory/mem_list_variant.txt 3 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/45963/1 diff --git a/src/mainboard/google/volteer/variants/eldrid/memory/Makefile.inc b/src/mainboard/google/volteer/variants/eldrid/memory/Makefile.inc index cfc038e..b966612 100644 --- a/src/mainboard/google/volteer/variants/eldrid/memory/Makefile.inc +++ b/src/mainboard/google/volteer/variants/eldrid/memory/Makefile.inc @@ -6,3 +6,4 @@ SPD_SOURCES += ddr4-spd-1.hex # ID = 1(0b0001) Parts = MT40A512M16TB-062E:J SPD_SOURCES += ddr4-spd-2.hex # ID = 2(0b0010) Parts = H5ANAG6NCMR-XNC SPD_SOURCES += ddr4-spd-7.hex # ID = 3(0b0011) Parts = K4AAG165WA-BCWE, MT40A1G16KD-062E:E +SPD_SOURCES += ddr4-spd-9.hex # ID = 4(0b0100) Parts = H5ANAG6NCJR-XNC diff --git a/src/mainboard/google/volteer/variants/eldrid/memory/dram_id.generated.txt b/src/mainboard/google/volteer/variants/eldrid/memory/dram_id.generated.txt index 867eca8..3e298dc 100644 --- a/src/mainboard/google/volteer/variants/eldrid/memory/dram_id.generated.txt +++ b/src/mainboard/google/volteer/variants/eldrid/memory/dram_id.generated.txt @@ -5,3 +5,4 @@ K4A8G165WC-BCWE 0 (0000) K4AAG165WA-BCWE 3 (0011) MT40A1G16KD-062E:E 3 (0011) +H5ANAG6NCJR-XNC 4 (0100) diff --git a/src/mainboard/google/volteer/variants/eldrid/memory/mem_list_variant.txt b/src/mainboard/google/volteer/variants/eldrid/memory/mem_list_variant.txt index 36e0f68..dbe7ecb 100644 --- a/src/mainboard/google/volteer/variants/eldrid/memory/mem_list_variant.txt +++ b/src/mainboard/google/volteer/variants/eldrid/memory/mem_list_variant.txt @@ -4,3 +4,4 @@ K4A8G165WC-BCWE K4AAG165WA-BCWE MT40A1G16KD-062E:E +H5ANAG6NCJR-XNC -- To view, visit https://review.coreboot.org/c/coreboot/+/45963 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia26315479ce1a749a0f7c9e81f134f7068d7eb0b Gerrit-Change-Number: 45963 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

6 8

Change in coreboot[master]: util: add DDR4 generic spd for H5ANAG6NCJR-XNC
by Nick Vaccaro (Code Review) 12 Oct '20

12 Oct '20

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45962 ) Change subject: util: add DDR4 generic spd for H5ANAG6NCJR-XNC ...................................................................... util: add DDR4 generic spd for H5ANAG6NCJR-XNC Add SPD support for DDR4 memory part H5ANAG6NCJR-XNC. BUG=b:161772961 TEST=none Change-Id: I71e4de9a28f78bbf8c7de1fcafa3596276a5f2f9 Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- A src/soc/intel/tigerlake/spd/ddr4-spd-9.hex M src/soc/intel/tigerlake/spd/ddr4_spd_manifest.generated.txt M util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt 3 files changed, 45 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/45962/1 diff --git a/src/soc/intel/tigerlake/spd/ddr4-spd-9.hex b/src/soc/intel/tigerlake/spd/ddr4-spd-9.hex new file mode 100644 index 0000000..1ce7c21 --- /dev/null +++ b/src/soc/intel/tigerlake/spd/ddr4-spd-9.hex @@ -0,0 +1,32 @@ +23 11 0C 03 46 29 00 08 00 00 00 00 02 03 00 00 +00 00 05 06 F8 FF 02 00 6E 6E 6E 11 00 6E 30 11 +F0 0A 20 08 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 BC 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/soc/intel/tigerlake/spd/ddr4_spd_manifest.generated.txt b/src/soc/intel/tigerlake/spd/ddr4_spd_manifest.generated.txt index 202f173..21565c6 100644 --- a/src/soc/intel/tigerlake/spd/ddr4_spd_manifest.generated.txt +++ b/src/soc/intel/tigerlake/spd/ddr4_spd_manifest.generated.txt @@ -13,3 +13,4 @@ H5AN8G6NCJR-XNC,ddr4-spd-1.hex K4AAG165WA-BCTD,ddr4-spd-8.hex H5ANAG6NDMR-XNC,ddr4-spd-2.hex +H5ANAG6NCJR-XNC,ddr4-spd-9.hex diff --git a/util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt b/util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt index 776bce7..72b0ccd 100644 --- a/util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt +++ b/util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt @@ -191,6 +191,18 @@ "packageBusWidth": 16, "ranksPerPackage": 1 } + }, + { + // Datasheet Revision: Rev. 1.4, May. 2020 + "name": "H5ANAG6NCJR-XNC", + "attribs": { + "speedMTps": 3200, + "CL_nRCD_nRP": 22, + "capacityPerDieGb": 16, + "diesPerPackage": 1, + "packageBusWidth": 16, + "ranksPerPackage": 1 + } } ] } -- To view, visit https://review.coreboot.org/c/coreboot/+/45962 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71e4de9a28f78bbf8c7de1fcafa3596276a5f2f9 Gerrit-Change-Number: 45962 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: soc/intel/jasperlake: Remove GPIO community 2 from DSDT
by Evan Green (Code Review) 12 Oct '20

12 Oct '20

Evan Green has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46115 ) Change subject: soc/intel/jasperlake: Remove GPIO community 2 from DSDT ...................................................................... soc/intel/jasperlake: Remove GPIO community 2 from DSDT The kernel driver enumerates communities 0, 1, 4, and 5, and assigns these addresses based on the BARs enumerated by coreboot. Coreboot was defining communities 0, 1, 2, 4, and 5. This meant the kernel was not controlling GPIOs in communities 4 and 5, since the resources were wrong. Remove community 2 for now. We can add it back if the kernel ends up needing it. BUG=b:169444894 TEST=Test controlling GPP_E5, verify actually toggles register. Signed-off-by: Evan Green <evgreen(a)chromium.org> Change-Id: I823e1aa942cfccadde01b9371d481457ab088c31 --- M src/soc/intel/jasperlake/acpi/gpio.asl 1 file changed, 0 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/46115/1 diff --git a/src/soc/intel/jasperlake/acpi/gpio.asl b/src/soc/intel/jasperlake/acpi/gpio.asl index e39ac8a..421abc3 100644 --- a/src/soc/intel/jasperlake/acpi/gpio.asl +++ b/src/soc/intel/jasperlake/acpi/gpio.asl @@ -18,7 +18,6 @@ { Memory32Fixed (ReadWrite, 0, 0, COM0) Memory32Fixed (ReadWrite, 0, 0, COM1) - Memory32Fixed (ReadWrite, 0, 0, COM2) Memory32Fixed (ReadWrite, 0, 0, COM4) Memory32Fixed (ReadWrite, 0, 0, COM5) Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) @@ -39,12 +38,6 @@ BAS1 = ^^PCRB (PID_GPIOCOM1) LEN1 = GPIO_BASE_SIZE - /* GPIO Community 2 */ - CreateDWordField (^RBUF, ^COM2._BAS, BAS2) - CreateDWordField (^RBUF, ^COM2._LEN, LEN2) - BAS2 = ^^PCRB (PID_GPIOCOM2) - LEN2 = GPIO_BASE_SIZE - /* GPIO Community 4 */ CreateDWordField (^RBUF, ^COM4._BAS, BAS4) CreateDWordField (^RBUF, ^COM4._LEN, LEN4) -- To view, visit https://review.coreboot.org/c/coreboot/+/46115 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I823e1aa942cfccadde01b9371d481457ab088c31 Gerrit-Change-Number: 46115 Gerrit-PatchSet: 1 Gerrit-Owner: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork/dirinboz: Increase eMMC initial clock frequency
by Rob Barnes (Code Review) 12 Oct '20

12 Oct '20

Rob Barnes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45934 ) Change subject: mb/google/zork/dirinboz: Increase eMMC initial clock frequency ...................................................................... mb/google/zork/dirinboz: Increase eMMC initial clock frequency This will reduce boot time by 7ms. Some of the initial designs don't have a pull-up resistor on the CMD line. These designs still boot at 400 kHz despite not having the pull-up. BUG=b:158766134 TEST=WIP Signed-off-by: Rob Barnes <robbarnes(a)google.com> Change-Id: I6bac8284b67070ff2c5838257f4ae2ead0e69c22 --- M src/mainboard/google/zork/variants/dirinboz/overridetree.cb 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/45934/1 diff --git a/src/mainboard/google/zork/variants/dirinboz/overridetree.cb b/src/mainboard/google/zork/variants/dirinboz/overridetree.cb index 905bc88..a11fa5e 100644 --- a/src/mainboard/google/zork/variants/dirinboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/dirinboz/overridetree.cb @@ -36,6 +36,12 @@ .early_init = true, }" + register "emmc_config" = "{ + .timing = SD_EMMC_EMMC_HS400, + .sdr104_hs400_driver_strength = SD_EMMC_DRIVE_STRENGTH_A, + .init_khz_preset = 400, + }" + # See AMD 55570-B1 Table 13: PCI Device ID Assignments. device domain 0 on subsystemid 0x1022 0x1510 inherit -- To view, visit https://review.coreboot.org/c/coreboot/+/45934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6bac8284b67070ff2c5838257f4ae2ead0e69c22 Gerrit-Change-Number: 45934 Gerrit-PatchSet: 1 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork/woomax: Increase eMMC initial clock frequency
by Rob Barnes (Code Review) 12 Oct '20

12 Oct '20

Rob Barnes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45936 ) Change subject: mb/google/zork/woomax: Increase eMMC initial clock frequency ...................................................................... mb/google/zork/woomax: Increase eMMC initial clock frequency This will reduce boot time by 7ms. Some of the initial designs don't have a pull-up resistor on the CMD line. These designs still boot at 400 kHz despite not having the pull-up. BUG=b:158766134 TEST=WIP Signed-off-by: Rob Barnes <robbarnes(a)google.com> Change-Id: I2fcbe35103020c3444902c077b4985f87f970671 --- M src/mainboard/google/zork/variants/woomax/overridetree.cb 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/45936/1 diff --git a/src/mainboard/google/zork/variants/woomax/overridetree.cb b/src/mainboard/google/zork/variants/woomax/overridetree.cb index 8d94a97..19d66fc 100644 --- a/src/mainboard/google/zork/variants/woomax/overridetree.cb +++ b/src/mainboard/google/zork/variants/woomax/overridetree.cb @@ -65,6 +65,12 @@ .early_init = true, }" + register "emmc_config" = "{ + .timing = SD_EMMC_EMMC_HS400, + .sdr104_hs400_driver_strength = SD_EMMC_DRIVE_STRENGTH_A, + .init_khz_preset = 400, + }" + # See AMD 55570-B1 Table 13: PCI Device ID Assignments. device domain 0 on subsystemid 0x1022 0x1510 inherit -- To view, visit https://review.coreboot.org/c/coreboot/+/45936 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2fcbe35103020c3444902c077b4985f87f970671 Gerrit-Change-Number: 45936 Gerrit-PatchSet: 1 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork/vilboz: Increase eMMC initial clock frequency
by Rob Barnes (Code Review) 12 Oct '20

12 Oct '20

Rob Barnes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45933 ) Change subject: mb/google/zork/vilboz: Increase eMMC initial clock frequency ...................................................................... mb/google/zork/vilboz: Increase eMMC initial clock frequency This will reduce boot time by 7ms. Some of the initial designs don't have a pull-up resistor on the CMD line. These designs still boot at 400 kHz despite not having the pull-up. BUG=b:158766134 TEST=WIP Signed-off-by: Rob Barnes <robbarnes(a)google.com> Change-Id: I9a1e47dbee3fcc7317857d40c5418be30d755d61 --- M src/mainboard/google/zork/variants/vilboz/overridetree.cb 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/45933/1 diff --git a/src/mainboard/google/zork/variants/vilboz/overridetree.cb b/src/mainboard/google/zork/variants/vilboz/overridetree.cb index 3d9ff7c..b75beaf 100644 --- a/src/mainboard/google/zork/variants/vilboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/vilboz/overridetree.cb @@ -41,6 +41,12 @@ .early_init = true, }" + register "emmc_config" = "{ + .timing = SD_EMMC_EMMC_HS400, + .sdr104_hs400_driver_strength = SD_EMMC_DRIVE_STRENGTH_A, + .init_khz_preset = 400, + }" + # See AMD 55570-B1 Table 13: PCI Device ID Assignments. device domain 0 on subsystemid 0x1022 0x1510 inherit -- To view, visit https://review.coreboot.org/c/coreboot/+/45933 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9a1e47dbee3fcc7317857d40c5418be30d755d61 Gerrit-Change-Number: 45933 Gerrit-PatchSet: 1 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-MessageType: newchange

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