coreboot-gerrit October 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/google/dedede: Enable SaGv support
by Aamir Bohra (Code Review) 12 Oct '20

12 Oct '20

Hello build bot (Jenkins), Maulik V Vaghela, Angel Pons, Meera Ravindranath, Krishna P Bhat D, Tim Wawrzynczak, Ronak Kanabar, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45196 to look at the new patch set (#5). Change subject: mb/google/dedede: Enable SaGv support ...................................................................... mb/google/dedede: Enable SaGv support Allow MRC training in SaGv low, mid and high frequencies. TEST=Verify memory trains at low, mid and high SaGv point through FSP debug logs enabled. Change-Id: I0f60aad031ce9dfe23e54426753311c35db46c05 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/45196/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/45196 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f60aad031ce9dfe23e54426753311c35db46c05 Gerrit-Change-Number: 45196 Gerrit-PatchSet: 5 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/acer/aspire_vn7_572g: Resolve WLAN errors
by Benjamin Doron (Code Review) 12 Oct '20

12 Oct '20

Benjamin Doron has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/40627 ) Change subject: mb/acer/aspire_vn7_572g: Resolve WLAN errors ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/40627 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b154dcb69aa9e0545883768eccd0782e0fb1b34 Gerrit-Change-Number: 40627 Gerrit-PatchSet: 6 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: soc/intel: Configure PAVP at compile-time
by Benjamin Doron (Code Review) 12 Oct '20

12 Oct '20

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42745 ) Change subject: soc/intel: Configure PAVP at compile-time ...................................................................... Patch Set 13: (2 comments) https://review.coreboot.org/c/coreboot/+/42745/13//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/42745/13//COMMIT_MSG@11 PS13, Line 11: multimedia content) to Kconfig. > Maybe mention that it was hard enabled and this adds the option […] I thought this was implied by "configure at compile-time?" https://review.coreboot.org/c/coreboot/+/42745/13/src/soc/intel/common/Kcon… File src/soc/intel/common/Kconfig.common: https://review.coreboot.org/c/coreboot/+/42745/13/src/soc/intel/common/Kcon… PS13, Line 43: the Management Engine, which is where this technology is implemented. > I would also recommend to disable it if one likes coreboot in general. I suspect […] I agree that DRM keeps technology closed, but I don't follow why this would be a reason to choose to enable/disable a feature. Do you think the number of people enabling PAVP motivates Intel to continue supporting DRM? This could be the case. Early CSME 11.0 versions of the pavp module aren't encrypted and contain some certificates. It may connect with a central server. -- To view, visit https://review.coreboot.org/c/coreboot/+/42745 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2aae741bb30e3be3c64324cd6334778bd271a903 Gerrit-Change-Number: 42745 Gerrit-PatchSet: 13 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 12 Oct 2020 04:50:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: Rename PcieRpAspm devicetree config
by Benjamin Doron (Code Review) 12 Oct '20

12 Oct '20

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45001 ) Change subject: soc/intel/skylake: Rename PcieRpAspm devicetree config ...................................................................... Patch Set 3: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/45001 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id74f043ecd549bde4501320bff1dc080bde64057 Gerrit-Change-Number: 45001 Gerrit-PatchSet: 3 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 12 Oct 2020 04:35:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: Configure L1 substates for PCH root ports
by Benjamin Doron (Code Review) 12 Oct '20

12 Oct '20

Hello build bot (Jenkins), Nico Huber, Matt DeVillier, Paul Menzel, Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/39538 to look at the new patch set (#26). Change subject: soc/intel/skylake: Configure L1 substates for PCH root ports ...................................................................... soc/intel/skylake: Configure L1 substates for PCH root ports Exposes PcieRpL1Substates to devicetree to allow boards to override this configuration. Tested on an Acer Aspire VN7-572G (Skylake-U). Change-Id: I36150858485715016158595c832c142b0582ddb8 Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> --- M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h 2 files changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/39538/26 -- To view, visit https://review.coreboot.org/c/coreboot/+/39538 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36150858485715016158595c832c142b0582ddb8 Gerrit-Change-Number: 39538 Gerrit-PatchSet: 26 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: acpi: Support MSDM table signature as SLIC
by Benjamin Doron (Code Review) 12 Oct '20

12 Oct '20

Hello build bot (Jenkins), Matt DeVillier, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/44995 to look at the new patch set (#5). Change subject: acpi: Support MSDM table signature as SLIC ...................................................................... acpi: Support MSDM table signature as SLIC Accept an MSDM table (a newer revision of SLIC, with similar ACPI structure) to advertise SLIC support. Tested, Windows registers the digital license. Change-Id: Ic3a1374c8a4880111a30662823c3be99008eedd3 Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> --- M src/acpi/acpi.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/44995/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/44995 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3a1374c8a4880111a30662823c3be99008eedd3 Gerrit-Change-Number: 44995 Gerrit-PatchSet: 5 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: nb/intel/haswell: Get rid of MCHBARxx_{AND_OR,AND,OR} macros
by HAOUAS Elyes (Code Review) 12 Oct '20

12 Oct '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46280 ) Change subject: nb/intel/haswell: Get rid of MCHBARxx_{AND_OR,AND,OR} macros ...................................................................... nb/intel/haswell: Get rid of MCHBARxx_{AND_OR,AND,OR} macros Change-Id: I1752a038f1e1ad537539396d62363a7a8829b6e3 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/haswell/haswell.h 1 file changed, 0 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/46280/1 diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index 098ad43..4ee85e1 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -30,16 +30,6 @@ * MCHBAR */ -#define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) -#define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) -#define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) -#define MCHBAR8_OR(x, or) (MCHBAR8(x) = MCHBAR8(x) | (or)) -#define MCHBAR16_OR(x, or) (MCHBAR16(x) = MCHBAR16(x) | (or)) -#define MCHBAR32_OR(x, or) (MCHBAR32(x) = MCHBAR32(x) | (or)) -#define MCHBAR8_AND_OR(x, and, or) (MCHBAR8(x) = (MCHBAR8(x) & (and)) | (or)) -#define MCHBAR16_AND_OR(x, and, or) (MCHBAR16(x) = (MCHBAR16(x) & (and)) | (or)) -#define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or)) - /* As there are many registers, define them on a separate file */ #include "registers/mchbar.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/46280 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1752a038f1e1ad537539396d62363a7a8829b6e3 Gerrit-Change-Number: 46280 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: payloads/iPXE: Enable support for verifying images
by Felix Singer (Code Review) 12 Oct '20

12 Oct '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31087 Change subject: payloads/iPXE: Enable support for verifying images ...................................................................... payloads/iPXE: Enable support for verifying images Change-Id: Ic3356062758dba80f74116ff3ab82b3b9e8375b1 Signed-off-by: Felix Singer <migy(a)darmstadt.ccc.de> --- M payloads/external/iPXE/Makefile 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/31087/1 diff --git a/payloads/external/iPXE/Makefile b/payloads/external/iPXE/Makefile index a8b1245..a5bf7be 100644 --- a/payloads/external/iPXE/Makefile +++ b/payloads/external/iPXE/Makefile @@ -54,6 +54,7 @@ sed 's|#define\s*COMCONSOLE.*|#define COMCONSOLE $(IPXE_UART)|' "$(project_dir)/src/config/serial.h" > "$(project_dir)/src/config/serial.h.tmp" sed 's|#define\s*COMSPEED.*|#define COMSPEED $(CONFIG_TTYS0_BAUD)|' "$(project_dir)/src/config/serial.h.tmp" > "$(project_dir)/src/config/serial.h" endif + sed -ie 's|.*IMAGE_TRUST_CMD|#define IMAGE_TRUST_CMD|g' "$(project_dir)/src/config/general.h" build: config echo " MAKE $(project_name) $(TAG-y)" -- To view, visit https://review.coreboot.org/c/coreboot/+/31087 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3356062758dba80f74116ff3ab82b3b9e8375b1 Gerrit-Change-Number: 31087 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/clevo/l140cu: drop USE_LEGACY_8254_TIMER
by Michael Niewöhner (Code Review) 12 Oct '20

12 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45960 ) Change subject: mb/clevo/l140cu: drop USE_LEGACY_8254_TIMER ...................................................................... Patch Set 3: Just realized I had referred to the wrong change in grub. The change fixing the problem for coreboot was even two years earlier, where grub introduced alternative timers. I have corrected the link in the commit message. -- To view, visit https://review.coreboot.org/c/coreboot/+/45960 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ce4f5168586bf305969b2e24b6ee895c8552749 Gerrit-Change-Number: 45960 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sun, 11 Oct 2020 22:30:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/clevo/l140cu: clean up memcfg
by Michael Niewöhner (Code Review) 12 Oct '20

12 Oct '20

Hello Felix Singer, build bot (Jenkins), Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46249 to look at the new patch set (#5). Change subject: mb/clevo/l140cu: clean up memcfg ...................................................................... mb/clevo/l140cu: clean up memcfg The DQ and DQS byte maps do not apply to DDR4 configurations, thus simply drop them. Also drop ECT, as it's already initialized to zero and can't be used on DDR4 anyway. Further, trim down all the meaningless and/or wrong comments. Change-Id: I32f1b7bb46eaaf0f0ecad1df310f5de988f64c85 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/mainboard/clevo/cml-u/variants/l140cu/romstage.c 1 file changed, 5 insertions(+), 51 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/46249/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/46249 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32f1b7bb46eaaf0f0ecad1df310f5de988f64c85 Gerrit-Change-Number: 46249 Gerrit-PatchSet: 5 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit October 2020