Hello Felix Singer, build bot (Jenkins), Thomas Heijligen,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34170
to look at the new patch set (#3).
Change subject: libpayload/x86: Try to discover invariant TSC rate
......................................................................
libpayload/x86: Try to discover invariant TSC rate
We can skip the PIT-based TSC calibration if we can derive the invariant
TSC rate from CPUID/MSR data. This is necessary if the PIT is disabled,
which is the default, for instance, on Coffee Lake CPUs.
This implementation should cover all Intel Core i processors at least.
For older processors, we fall back to the PIT calibration.
Change-Id: Ic6607ee2a8b41c2be9dc1bb4f1e23e652bb33889
Signed-off-by: Nico Huber <nico.huber(a)secunet.com>
---
M payloads/libpayload/arch/x86/timer.c
1 file changed, 118 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/34170/3
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Michael Niewöhner has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/44775 )
Change subject: treewide: stop using hexdumps for SPD files
......................................................................
Abandoned
I have too many open patches... feel free to continue this
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46016 )
Change subject: soc/intel/*: drop useless XTAL shutdown qualification code
......................................................................
Patch Set 5:
Subrata, have a look, please
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46273 )
Change subject: soc/intel/cnl: lock AES-NI feature if selected
......................................................................
Patch Set 4:
This change is ready for review.
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46277 )
Change subject: cpu/intel/common: add a Kconfig to control AES-NI locking
......................................................................
Patch Set 1:
This change is ready for review.
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46276 )
Change subject: cpu/intel/common: only lock AES-NI when supported
......................................................................
Patch Set 1:
This change is ready for review.
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46275 )
Change subject: cpu/intel/common: rework AES-NI locking
......................................................................
Patch Set 1:
This change is ready for review.
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46272 )
Change subject: soc/intel/skl + cpu/intel/common: move AES-NI locking to common cpu code
......................................................................
Patch Set 4:
This change is ready for review.
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Hello Felix Singer, build bot (Jenkins), Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46249
to look at the new patch set (#4).
Change subject: mb/clevo/l140cu: clean up memcfg
......................................................................
mb/clevo/l140cu: clean up memcfg
The DQ and DQS byte maps do not apply to DDR4 configurations, thus
simply drop them.
Also drop ECT, as it's already initialized to zero and can't be used on
DDR4 anyway.
Further, trim down all the meaningless and/or wrong comments.
Change-Id: I32f1b7bb46eaaf0f0ecad1df310f5de988f64c85
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/mainboard/clevo/cml-u/variants/l140cu/romstage.c
1 file changed, 5 insertions(+), 51 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/46249/4
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46249 )
Change subject: mb/clevo/l140cu: clean up memcfg
......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46249/2/src/mainboard/clevo/cml-u/…
File src/mainboard/clevo/cml-u/variants/l140cu/romstage.c:
https://review.coreboot.org/c/coreboot/+/46249/2/src/mainboard/clevo/cml-u/…
PS2, Line 16: Values of the rcomp resistors attached to the DDR_RCOMP_* pins
> maybe: […]
Done
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