coreboot-gerrit October 2020

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Change in coreboot[master]: acpi: Support MSDM table signature as SLIC
by Angel Pons (Code Review) 12 Oct '20

12 Oct '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44995 ) Change subject: acpi: Support MSDM table signature as SLIC ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/44995 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3a1374c8a4880111a30662823c3be99008eedd3 Gerrit-Change-Number: 44995 Gerrit-PatchSet: 5 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 12 Oct 2020 09:20:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: acpi: Support MSDM table signature as SLIC
by Angel Pons (Code Review) 12 Oct '20

12 Oct '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44995 ) Change subject: acpi: Support MSDM table signature as SLIC ...................................................................... Patch Set 5: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/44995 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3a1374c8a4880111a30662823c3be99008eedd3 Gerrit-Change-Number: 44995 Gerrit-PatchSet: 5 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 12 Oct 2020 09:20:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: Configure PAVP at compile-time
by Angel Pons (Code Review) 12 Oct '20

12 Oct '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42745 ) Change subject: soc/intel: Configure PAVP at compile-time ...................................................................... Patch Set 13: Code-Review+2 (1 comment) https://review.coreboot.org/c/coreboot/+/42745/13//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/42745/13//COMMIT_MSG@11 PS13, Line 11: multimedia content) to Kconfig. > I thought this was implied by "configure at compile-time?" It does not imply that it was always enabled, though. -- To view, visit https://review.coreboot.org/c/coreboot/+/42745 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2aae741bb30e3be3c64324cd6334778bd271a903 Gerrit-Change-Number: 42745 Gerrit-PatchSet: 13 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 12 Oct 2020 09:19:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede: Enable SaGv support
by Angel Pons (Code Review) 12 Oct '20

12 Oct '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45196 ) Change subject: mb/google/dedede: Enable SaGv support ...................................................................... Patch Set 6: Code-Review+2 (1 comment) https://review.coreboot.org/c/coreboot/+/45196/4//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/45196/4//COMMIT_MSG@7 PS4, Line 7: SaGv support > We (and by this I mean "you" ;-) ) can look for better ways to implement the toggle, but for now thi […] Alright, thanks for confirming. So, I can make it controllable through Kconfig, but allow mainboards to specify the default value for SaGv. -- To view, visit https://review.coreboot.org/c/coreboot/+/45196 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f60aad031ce9dfe23e54426753311c35db46c05 Gerrit-Change-Number: 45196 Gerrit-PatchSet: 6 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 12 Oct 2020 09:16:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Patrick Georgi <pgeorgi(a)google.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/asurada: Add USB support
by CK HU (Code Review) 12 Oct '20

12 Oct '20

CK HU has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45397 ) Change subject: mb/google/asurada: Add USB support ...................................................................... mb/google/asurada: Add USB support Change-Id: I35dc4be65f0843c3c74695c443dd958676e6c12c Signed-off-by: CK Hu <ck.hu(a)mediatek.com> --- M src/mainboard/google/asurada/mainboard.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/45397/1 diff --git a/src/mainboard/google/asurada/mainboard.c b/src/mainboard/google/asurada/mainboard.c index e6040fa..9146d7b 100644 --- a/src/mainboard/google/asurada/mainboard.c +++ b/src/mainboard/google/asurada/mainboard.c @@ -1,9 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <console/console.h> #include <device/device.h> +#include <soc/usb.h> static void mainboard_init(struct device *dev) { + setup_usb_host(); } static void mainboard_enable(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/45397 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35dc4be65f0843c3c74695c443dd958676e6c12c Gerrit-Change-Number: 45397 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8192: Add usb host support
by CK HU (Code Review) 12 Oct '20

12 Oct '20

CK HU has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45396 ) Change subject: soc/mediatek/mt8192: Add usb host support ...................................................................... soc/mediatek/mt8192: Add usb host support Add usb host function support Signed-off-by: Tianping Fang <tianping.fang(a)mediatek.com> Signed-off-by: Zhanyong Wang <zhanyong.wang(a)mediatek.com> Change-Id: Icb4cc304654b5fb7cf20b96ab83a22663bfeab63 --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/include/soc/usb.h A src/soc/mediatek/mt8192/usb.c 3 files changed, 39 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/45396/1 diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc old mode 100644 new mode 100755 index c7dbe51..533eae2 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -32,6 +32,7 @@ ramstage-y += soc.c ramstage-y += ../common/timer.c ramstage-y += ../common/uart.c +ramstage-y += ../common/usb.c usb.c CPPFLAGS_common += -Isrc/soc/mediatek/mt8192/include CPPFLAGS_common += -Isrc/soc/mediatek/common/include diff --git a/src/soc/mediatek/mt8192/include/soc/usb.h b/src/soc/mediatek/mt8192/include/soc/usb.h new file mode 100755 index 0000000..3537ba2 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/usb.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef SOC_MEDIATEK_MT8192_USB_H +#define SOC_MEDIATEK_MT8192_USB_H + +#include <soc/usb_common.h> + +struct ssusb_sif_port { + struct sif_u2_phy_com u2phy; + u32 reserved0[64*5]; + struct sif_u3phyd u3phyd; + u32 reserved1[64]; + struct sif_u3phya u3phya; + struct sif_u3phya_da u3phya_da; + u32 reserved2[64 * 3]; +}; +check_member(ssusb_sif_port, u3phyd, 0x600); +check_member(ssusb_sif_port, u3phya, 0x800); +check_member(ssusb_sif_port, u3phya_da, 0x900); +check_member(ssusb_sif_port, reserved2, 0xa00); + +#define USB_PORT_NUMBER 2 + +#endif diff --git a/src/soc/mediatek/mt8192/usb.c b/src/soc/mediatek/mt8192/usb.c new file mode 100755 index 0000000..4beab9c --- /dev/null +++ b/src/soc/mediatek/mt8192/usb.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#include <soc/addressmap.h> +#include <device/mmio.h> +#include <soc/usb.h> + +#define REG_SPM_POWERON_CONFIG_EN (void *)(SPM_BASE + 0x000) +#define REG_SPM_SSPM_PWR_CON (void *)(SPM_BASE + 0x390) + +void mtk_usb_prepare(void) +{ + /* power on SSUSB SRAM FIFO */ + setbits32(REG_SPM_POWERON_CONFIG_EN, 0xB160001); + clrbits32(REG_SPM_SSPM_PWR_CON, 0x000001FF); +} + -- To view, visit https://review.coreboot.org/c/coreboot/+/45396 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb4cc304654b5fb7cf20b96ab83a22663bfeab63 Gerrit-Change-Number: 45396 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/jasperlake: Allow mainboard to override chip configuration
by Karthik Ramasubramanian (Code Review) 12 Oct '20

12 Oct '20

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45856 ) Change subject: soc/intel/jasperlake: Allow mainboard to override chip configuration ...................................................................... soc/intel/jasperlake: Allow mainboard to override chip configuration Add a weak override function to allow mainboard to override chip configuration like GPIO PM. BUG=None TEST=Build and boot waddledee to OS. Ensure that the suspend/resume sequence works fine. Change-Id: I40fa655b0324dc444182b988f0089587e3877a47 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/soc/intel/jasperlake/fsp_params.c M src/soc/intel/jasperlake/include/soc/ramstage.h 2 files changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/45856/1 diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c index cdd088e..d140213 100644 --- a/src/soc/intel/jasperlake/fsp_params.c +++ b/src/soc/intel/jasperlake/fsp_params.c @@ -78,6 +78,11 @@ sizeof(config->SerialIoUartMode)); } +__weak void mainboard_update_soc_chip_config(struct soc_intel_jasperlake_config *config) +{ + /* Override settings per board. */ +} + /* UPD parameters to be initialized before SiliconInit */ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) { @@ -86,6 +91,9 @@ FSP_S_CONFIG *params = &supd->FspsConfig; struct soc_intel_jasperlake_config *config = config_of_soc(); + /* Allow mainboard to override any chip config */ + mainboard_update_soc_chip_config(config); + /* Parse device tree and fill in FSP UPDs */ parse_devicetree(params); diff --git a/src/soc/intel/jasperlake/include/soc/ramstage.h b/src/soc/intel/jasperlake/include/soc/ramstage.h index 8188fbd..1de8e37 100644 --- a/src/soc/intel/jasperlake/include/soc/ramstage.h +++ b/src/soc/intel/jasperlake/include/soc/ramstage.h @@ -9,6 +9,7 @@ #include <soc/soc_chip.h> void mainboard_silicon_init_params(FSP_S_CONFIG *params); +void mainboard_update_soc_chip_config(struct soc_intel_jasperlake_config *config); void soc_init_pre_device(void *chip_info); #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/45856 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40fa655b0324dc444182b988f0089587e3877a47 Gerrit-Change-Number: 45856 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: security/intel/txt: Add and use DPR register layout
by Angel Pons (Code Review) 12 Oct '20

12 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46050 ) Change subject: security/intel/txt: Add and use DPR register layout ...................................................................... security/intel/txt: Add and use DPR register layout This simplifies operations with this register's bitfields, and can also be used by TXT-enabled platforms on the register in PCI config space. Change-Id: I10a26bc8f4457158dd09e91d666fb29ad16a2087 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/security/intel/txt/ramstage.c M src/security/intel/txt/txt_register.h 2 files changed, 27 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/46050/1 diff --git a/src/security/intel/txt/ramstage.c b/src/security/intel/txt/ramstage.c index fb84777e..bc30da5 100644 --- a/src/security/intel/txt/ramstage.c +++ b/src/security/intel/txt/ramstage.c @@ -64,16 +64,14 @@ TXT_PUBLIC_SPACE - TXT_PRIVATE_SPACE, BM_MEM_RESERVED); - const uint32_t txt_dev_memory = read32((void *)TXT_DPR) & - (TXT_DPR_TOP_ADDR_MASK << TXT_DPR_TOP_ADDR_SHIFT); - const uint32_t txt_dev_size = - (read32((void *)TXT_DPR) >> TXT_DPR_LOCK_SIZE_SHIFT) & - TXT_DPR_LOCK_SIZE_MASK; + const union dpr_register dpr = { + .raw = read32((void *)TXT_DPR), + }; + + const uint32_t dpr_base = dpr.top - dpr.size * MiB; /* Chapter 5.5.6 Intel TXT Device Memory */ - bootmem_add_range(txt_dev_memory - txt_dev_size * MiB, - txt_dev_size * MiB, - BM_MEM_RESERVED); + bootmem_add_range(dpr_base, dpr.size * MiB, BM_MEM_RESERVED); } static bool get_wake_error_status(void) @@ -228,12 +226,15 @@ const u8 dpr_capable = !!(read64((void *)TXT_CAPABILITIES) & TXT_CAPABILITIES_DPR); printk(BIOS_INFO, "TEE-TXT: DPR capable %x\n", dpr_capable); - if (dpr_capable) { + if (dpr_capable) { /* Protect 3 MiB below TSEG and lock register */ - write64((void *)TXT_DPR, (TXT_DPR_TOP_ADDR(tseg) | - TXT_DPR_LOCK_SIZE(3) | - TXT_DPR_LOCK_MASK)); + union dpr_register dpr = { + .lock = 1, + .size = 3, + .top = tseg, + }; + write64((void *)TXT_DPR, dpr.raw); // DPR TODO: implement SA_ENABLE_DPR in the intelblocks diff --git a/src/security/intel/txt/txt_register.h b/src/security/intel/txt/txt_register.h index bd546b5..bbf0a7e 100644 --- a/src/security/intel/txt/txt_register.h +++ b/src/security/intel/txt/txt_register.h @@ -91,15 +91,6 @@ #define TXT_BIOSACM_ERRORCODE (TXT_BASE + 0x328) #define TXT_DPR (TXT_BASE + 0x330) -#define TXT_DPR_LOCK_SHIFT 0 -#define TXT_DPR_LOCK_SIZE_SHIFT 4 -#define TXT_DPR_LOCK_SIZE_MASK 0xff -#define TXT_DPR_TOP_ADDR_SHIFT 20 -#define TXT_DPR_TOP_ADDR_MASK 0xfff - -#define TXT_DPR_LOCK_MASK (1 << TXT_DPR_LOCK_SHIFT) -#define TXT_DPR_LOCK_SIZE(x) ((x) << TXT_DPR_LOCK_SIZE_SHIFT) -#define TXT_DPR_TOP_ADDR(x) ((x) << TXT_DPR_TOP_ADDR_SHIFT) #define TXT_ACM_KEY_HASH (TXT_BASE + 0x400) #define TXT_ACM_KEY_HASH_LEN 0x4 @@ -160,6 +151,20 @@ /* MSRs */ #define IA32_MCG_STATUS 0x17a +/* DPR register layout, either in PCI config space or TXT MMIO space */ +union dpr_register { + struct { + uint32_t lock : 1; /* [ 0.. 0] */ + uint32_t prs : 1; /* [ 1.. 1] and only present on PCI config */ + uint32_t epm : 1; /* [ 2.. 2] and only present on PCI config */ + uint32_t : 1; + uint32_t size : 8; /* [11.. 4] */ + uint32_t : 8; + uint32_t top : 12; /* [31..20] */ + }; + uint32_t raw; +}; + typedef enum { CHIPSET_ACM = 2, } acm_module_type; -- To view, visit https://review.coreboot.org/c/coreboot/+/46050 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I10a26bc8f4457158dd09e91d666fb29ad16a2087 Gerrit-Change-Number: 46050 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: security/intel/txt: Clean up includes
by Angel Pons (Code Review) 12 Oct '20

12 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46049 ) Change subject: security/intel/txt: Clean up includes ...................................................................... security/intel/txt: Clean up includes Sort them alphabetically, and use <types.h> everywhere. Change-Id: Ib8f3339e5969cf8552984164fa7e08e070987a24 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/security/intel/txt/common.c M src/security/intel/txt/getsec.c M src/security/intel/txt/logging.c M src/security/intel/txt/ramstage.c M src/security/intel/txt/txt_getsec.h M src/security/intel/txt/txt_register.h 6 files changed, 13 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/46049/1 diff --git a/src/security/intel/txt/common.c b/src/security/intel/txt/common.c index 738cd54..e73defb 100644 --- a/src/security/intel/txt/common.c +++ b/src/security/intel/txt/common.c @@ -1,15 +1,15 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/mmio.h> -#include <string.h> #include <console/console.h> -#include <types.h> #include <cbfs.h> -#include <cpu/x86/lapic.h> #include <cpu/x86/cr.h> +#include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <lib.h> #include <smp/node.h> +#include <string.h> +#include <types.h> #if CONFIG(SOC_INTEL_COMMON_BLOCK_SA) #include <soc/intel/common/reset.h> diff --git a/src/security/intel/txt/getsec.c b/src/security/intel/txt/getsec.c index 412e243..422f10d 100644 --- a/src/security/intel/txt/getsec.c +++ b/src/security/intel/txt/getsec.c @@ -1,10 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <stdint.h> #include <cpu/x86/lapic.h> #include <cpu/x86/cr.h> #include <cpu/x86/cache.h> #include <cpu/x86/mp.h> +#include <types.h> #include "txt_register.h" #include "txt_getsec.h" diff --git a/src/security/intel/txt/logging.c b/src/security/intel/txt/logging.c index cf14b55..3cf2cea 100644 --- a/src/security/intel/txt/logging.c +++ b/src/security/intel/txt/logging.c @@ -1,13 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <arch/mmio.h> #include <console/console.h> +#include <string.h> +#include <types.h> + #if CONFIG(SOC_INTEL_COMMON_BLOCK_SA) #include <intelblocks/systemagent.h> #endif -#include <arch/mmio.h> -#include <string.h> - #include "txt.h" #include "txt_register.h" diff --git a/src/security/intel/txt/ramstage.c b/src/security/intel/txt/ramstage.c index 145182f..fb84777e 100644 --- a/src/security/intel/txt/ramstage.c +++ b/src/security/intel/txt/ramstage.c @@ -1,16 +1,15 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/mmio.h> #include <acpi/acpi.h> -#include <bootstate.h> +#include <arch/mmio.h> #include <bootmem.h> -#include <console/console.h> -#include <stdint.h> +#include <bootstate.h> #include <cbfs.h> +#include <console/console.h> #include <cpu/intel/common/common.h> #include <cpu/x86/msr.h> - #include <device/pci_ops.h> +#include <types.h> #include "txt.h" #include "txt_register.h" diff --git a/src/security/intel/txt/txt_getsec.h b/src/security/intel/txt/txt_getsec.h index 7c4a1a4..8e663d5 100644 --- a/src/security/intel/txt/txt_getsec.h +++ b/src/security/intel/txt/txt_getsec.h @@ -3,7 +3,7 @@ #ifndef SECURITY_INTEL_TXT_GETSEC_H_ #define SECURITY_INTEL_TXT_GETSEC_H_ -#include <stdint.h> +#include <types.h> bool getsec_parameter(uint32_t *version_mask, uint32_t *version_numbers_supported, diff --git a/src/security/intel/txt/txt_register.h b/src/security/intel/txt/txt_register.h index c7f1575..bd546b5 100644 --- a/src/security/intel/txt/txt_register.h +++ b/src/security/intel/txt/txt_register.h @@ -4,7 +4,6 @@ #define SECURITY_INTEL_TXT_REGISTER_H_ #include <types.h> -#include <stddef.h> /* * Document: 315168-016 -- To view, visit https://review.coreboot.org/c/coreboot/+/46049 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8f3339e5969cf8552984164fa7e08e070987a24 Gerrit-Change-Number: 46049 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede: Enable SaGv support
by Patrick Georgi (Code Review) 12 Oct '20

12 Oct '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45196 ) Change subject: mb/google/dedede: Enable SaGv support ...................................................................... mb/google/dedede: Enable SaGv support Allow MRC training in SaGv low, mid and high frequencies. TEST=Verify memory trains at low, mid and high SaGv point through FSP debug logs enabled. Change-Id: I0f60aad031ce9dfe23e54426753311c35db46c05 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45196 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, but someone else must approve Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index fe232e6..b2ed21a 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -168,6 +168,9 @@ # Skip the CPU repalcement check register "SkipCpuReplacementCheck" = "1" + # Sagv Configuration + register "SaGv" = "SaGv_Enabled" + # Set the minimum assertion width register "PchPmSlpS3MinAssert" = "3" # 50ms register "PchPmSlpS4MinAssert" = "1" # 1s -- To view, visit https://review.coreboot.org/c/coreboot/+/45196 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f60aad031ce9dfe23e54426753311c35db46c05 Gerrit-Change-Number: 45196 Gerrit-PatchSet: 6 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit October 2020