coreboot-gerrit October 2020

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Change in coreboot[master]: soc/intel: Configure PAVP at compile-time
by Benjamin Doron (Code Review) 12 Oct '20

12 Oct '20

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42745 ) Change subject: soc/intel: Configure PAVP at compile-time ...................................................................... Patch Set 14: (1 comment) https://review.coreboot.org/c/coreboot/+/42745/13//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/42745/13//COMMIT_MSG@11 PS13, Line 11: multimedia content) to Kconfig. > It does not imply that it was always enabled, though. Fair point, done. -- To view, visit https://review.coreboot.org/c/coreboot/+/42745 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2aae741bb30e3be3c64324cd6334778bd271a903 Gerrit-Change-Number: 42745 Gerrit-PatchSet: 14 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 12 Oct 2020 19:23:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Benjamin Doron <benjamin.doron00(a)gmail.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: Configure PAVP at compile-time
by Benjamin Doron (Code Review) 12 Oct '20

12 Oct '20

Hello build bot (Jenkins), Nico Huber, Justin TerAvest, Angel Pons, Subrata Banik, Ronak Kanabar, Andrey Petrov, Patrick Rudolph, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/42745 to look at the new patch set (#14). Change subject: soc/intel: Configure PAVP at compile-time ...................................................................... soc/intel: Configure PAVP at compile-time Expose configuration of Intel PAVP (Protected Audio-Video Path, a digital rights protection/management (DRM) technology for multimedia content) to Kconfig. Per the FSP default, this was always being enabled previously. Change-Id: I2aae741bb30e3be3c64324cd6334778bd271a903 Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> --- M src/soc/intel/apollolake/chip.c M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/common/Kconfig.common M src/soc/intel/icelake/fsp_params.c M src/soc/intel/jasperlake/fsp_params.c M src/soc/intel/skylake/chip.c 6 files changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/42745/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/42745 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2aae741bb30e3be3c64324cd6334778bd271a903 Gerrit-Change-Number: 42745 Gerrit-PatchSet: 14 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/clevo/l140cu: clean up memcfg
by Michael Niewöhner (Code Review) 12 Oct '20

12 Oct '20

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46249 ) Change subject: mb/clevo/l140cu: clean up memcfg ...................................................................... mb/clevo/l140cu: clean up memcfg The DQ and DQS byte maps do not apply to DDR4 configurations, thus simply drop them. Also drop ECT, as it's already initialized to zero and can't be used on DDR4 anyway. Further, trim down all the meaningless and/or wrong comments. Change-Id: I32f1b7bb46eaaf0f0ecad1df310f5de988f64c85 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46249 Reviewed-by: Felix Singer <felixsinger(a)posteo.net> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/clevo/cml-u/variants/l140cu/romstage.c 1 file changed, 5 insertions(+), 51 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/romstage.c b/src/mainboard/clevo/cml-u/variants/l140cu/romstage.c index 4401483..4cad131 100644 --- a/src/mainboard/clevo/cml-u/variants/l140cu/romstage.c +++ b/src/mainboard/clevo/cml-u/variants/l140cu/romstage.c @@ -13,66 +13,20 @@ .spd_spec = {.spd_smbus_address = 0xa4}, }, - /* - * For each channel, there are 3 sets of DQ byte mappings, - * where each set has a package 0 and a package 1 value (package 0 - * represents the first 64-bit lpddr4 chip combination, and package 1 - * represents the second 64-bit lpddr4 chip combination). - * The first three sets are for CLK, CMD, and CTL. - * The fsp package actually expects 6 sets, but the last 3 sets are - * not used in CNL, so we only define the three sets that are used - * and let the meminit_lpddr4() routine take care of clearing the - * unused fields for the caller. - */ - .dq_map[DDR_CH0] = { - {0x0F, 0xF0}, {0x00, 0xF0}, {0x0F, 0xF0}, - //{0x0F, 0x00}, {0xFF, 0x00}, {0xFF, 0x00} - }, - .dq_map[DDR_CH1] = { - {0x33, 0xCC}, {0x00, 0xCC}, {0x33, 0xCC}, - //{0x33, 0x00}, {0xFF, 0x00}, {0xFF, 0x00} - }, - - /* - * DQS CPU<>DRAM map Ch0 and Ch1. Each array entry represents a - * mapping of a dq bit on the CPU to the bit it's connected to on - * the memory part. The array index represents the dqs bit number - * on the memory part, and the values in the array represent which - * pin on the CPU that DRAM pin connects to. - */ - .dqs_map[DDR_CH0] = {0, 1, 2, 3, 4, 5, 6, 7}, - .dqs_map[DDR_CH1] = {1, 0, 2, 3, 4, 5, 6, 7}, - - /* - * Rcomp resistor values. These values represent the resistance in - * ohms of the three rcomp resistors attached to the DDR_COMP_0, - * DDR_COMP_1, and DDR_COMP_2 pins on the DRAM. - */ + /* Values of the resistors connected to the DDR_RCOMP_[2:0] pins of the CPU */ .rcomp_resistor = { 121, 81, 100 }, - /* - * Rcomp target values. These will typically be the following - * values for Cannon Lake : { 80, 40, 40, 40, 30 } - */ + /* Rcomp target values */ .rcomp_targets = { 100, 40, 20, 20, 26 }, - /* - * Indicates whether memory is interleaved. - * Set to 1 for an interleaved design, - * set to 0 for non-interleaved design. - */ + /* Interleaved ("back-to-back") pin mapping */ .dq_pins_interleaved = 1, /* - * VREF_CA configuration. - * Set to 0 VREF_CA goes to both CH_A and CH_B, - * set to 1 VREF_CA goes to CH_A and VREF_DQ_A goes to CH_B, - * set to 2 VREF_CA goes to CH_A and VREF_DQ_B goes to CH_B. + * DDR4 Vref mapping + * VREF_CA goes to CH_A and VREF_DQ_B (DDR1_VREF_DQ) goes to CH_B. */ .vref_ca_config = 2, - - /* Early Command Training */ - .ect = 0, }; void mainboard_memory_init_params(FSPM_UPD *memupd) -- To view, visit https://review.coreboot.org/c/coreboot/+/46249 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32f1b7bb46eaaf0f0ecad1df310f5de988f64c85 Gerrit-Change-Number: 46249 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/clevo/l140cu: clean up memcfg
by Felix Singer (Code Review) 12 Oct '20

12 Oct '20

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46249 ) Change subject: mb/clevo/l140cu: clean up memcfg ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/46249 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32f1b7bb46eaaf0f0ecad1df310f5de988f64c85 Gerrit-Change-Number: 46249 Gerrit-PatchSet: 5 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 12 Oct 2020 19:20:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/clevo/l140cu: drop disabled SPD indices
by Michael Niewöhner (Code Review) 12 Oct '20

12 Oct '20

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46248 ) Change subject: mb/clevo/l140cu: drop disabled SPD indices ...................................................................... mb/clevo/l140cu: drop disabled SPD indices Drop the disabled SPD indices from memcfg, since they're already initialized to 0. Change-Id: I6d88bdac17222c2c5c35439517fe0bea46744b2b Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46248 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/clevo/cml-u/variants/l140cu/romstage.c 1 file changed, 0 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/romstage.c b/src/mainboard/clevo/cml-u/variants/l140cu/romstage.c index 1af8ce6..4401483 100644 --- a/src/mainboard/clevo/cml-u/variants/l140cu/romstage.c +++ b/src/mainboard/clevo/cml-u/variants/l140cu/romstage.c @@ -4,17 +4,14 @@ #include <soc/romstage.h> static const struct cnl_mb_cfg memcfg = { - /* Parameters required to access SPD for CH0D0/CH0D1/CH1D0/CH1D1. */ .spd[0] = { .read_type = READ_SPD_CBFS, .spd_spec = {.spd_index = 0}, }, - .spd[1] = {.read_type = NOT_EXISTING}, .spd[2] = { .read_type = READ_SMBUS, .spd_spec = {.spd_smbus_address = 0xa4}, }, - .spd[3] = {.read_type = NOT_EXISTING}, /* * For each channel, there are 3 sets of DQ byte mappings, -- To view, visit https://review.coreboot.org/c/coreboot/+/46248 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d88bdac17222c2c5c35439517fe0bea46744b2b Gerrit-Change-Number: 46248 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/clevo/l140cu: drop USE_LEGACY_8254_TIMER
by Michael Niewöhner (Code Review) 12 Oct '20

12 Oct '20

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45960 ) Change subject: mb/clevo/l140cu: drop USE_LEGACY_8254_TIMER ...................................................................... mb/clevo/l140cu: drop USE_LEGACY_8254_TIMER Drop USE_LEGACY_8254_TIMER, since it's not required anymore for booting grub, despite the comment. The issue was resolved upstream five years ago: http://git.savannah.gnu.org/cgit/grub.git/commit/?id=d43a5ee65143f384357fbf… Test: - Boot EFI GRUB2 from TianoCore payload (Debian Live, Ubuntu installer) - Boot GRUB2 payload Change-Id: I5ce4f5168586bf305969b2e24b6ee895c8552749 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45960 Reviewed-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/clevo/cml-u/Kconfig 1 file changed, 0 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Felix Singer: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/mainboard/clevo/cml-u/Kconfig b/src/mainboard/clevo/cml-u/Kconfig index 082bf62..c08b321 100644 --- a/src/mainboard/clevo/cml-u/Kconfig +++ b/src/mainboard/clevo/cml-u/Kconfig @@ -19,7 +19,6 @@ select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SPD_READ_BY_WORD select SYSTEM_TYPE_LAPTOP - select USE_LEGACY_8254_TIMER # Fix failure to boot GRUB config MAINBOARD_DIR string -- To view, visit https://review.coreboot.org/c/coreboot/+/45960 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ce4f5168586bf305969b2e24b6ee895c8552749 Gerrit-Change-Number: 45960 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/clevo/l140cu: set PS/2 timeout for SeaBIOS
by Michael Niewöhner (Code Review) 12 Oct '20

12 Oct '20

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45959 ) Change subject: mb/clevo/l140cu: set PS/2 timeout for SeaBIOS ...................................................................... mb/clevo/l140cu: set PS/2 timeout for SeaBIOS The keyboard only works randomly, because SeaBIOS initializes PS/2 before the EC is ready. Set the PS/2 timeout for SeaBIOS to 500 ms, to wait for the EC before initializing the keyboard. Test: keyboard works fine. Change-Id: I2be75961035f04a7ffa6f7e1dbaabb1243b857f9 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45959 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/clevo/cml-u/Kconfig 1 file changed, 5 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/mainboard/clevo/cml-u/Kconfig b/src/mainboard/clevo/cml-u/Kconfig index ae79794..082bf62 100644 --- a/src/mainboard/clevo/cml-u/Kconfig +++ b/src/mainboard/clevo/cml-u/Kconfig @@ -81,4 +81,9 @@ string default "l140cu" if BOARD_CLEVO_L140CU +config SEABIOS_PS2_TIMEOUT + int + depends on PAYLOAD_SEABIOS + default 500 + endif -- To view, visit https://review.coreboot.org/c/coreboot/+/45959 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2be75961035f04a7ffa6f7e1dbaabb1243b857f9 Gerrit-Change-Number: 45959 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common: rewrite and clarify the Legacy 8254 Timer Kconfig
by Michael Niewöhner (Code Review) 12 Oct '20

12 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46302 ) Change subject: soc/intel/common: rewrite and clarify the Legacy 8254 Timer Kconfig ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/46302 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9637c549db1ce29f259708f316852fc2ae9e7c38 Gerrit-Change-Number: 46302 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Mon, 12 Oct 2020 18:24:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: drop default to enable the PIT if SeaBIOS is chosen
by Michael Niewöhner (Code Review) 12 Oct '20

12 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46301 ) Change subject: soc/intel/common: drop default to enable the PIT if SeaBIOS is chosen ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/46301 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd75800678707a92110682347c7cfb93e25109a4 Gerrit-Change-Number: 46301 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Mon, 12 Oct 2020 18:23:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer/var/voxel: disable DdiPortHpd
by Sheng-Liang Pan (Code Review) 12 Oct '20

12 Oct '20

Sheng-Liang Pan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46069 ) Change subject: mb/google/volteer/var/voxel: disable DdiPortHpd ...................................................................... mb/google/volteer/var/voxel: disable DdiPortHpd GPP_A19 and GPP_A20 set no connection, disables DdiPort1Hpd and DdiPort2Hpd BUG=b:169690329 TEST=build and verify type-c(C0/C1) port functional normally Signed-off-by: Pan Sheng-Liang <sheng-liang.pan(a)quanta.corp-partner.google.com> Change-Id: I4405526ae777332d3c72041db7b4eda25ae31b8e --- M src/mainboard/google/volteer/variants/voxel/overridetree.cb 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/46069/1 diff --git a/src/mainboard/google/volteer/variants/voxel/overridetree.cb b/src/mainboard/google/volteer/variants/voxel/overridetree.cb index 330d852..f3a04b4 100644 --- a/src/mainboard/google/volteer/variants/voxel/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voxel/overridetree.cb @@ -1,4 +1,6 @@ chip soc/intel/tigerlake + register "DdiPort1Hpd" = "0" + register "DdiPort2Hpd" = "0" register "tcc_offset" = "5" # TCC of 95 register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ -- To view, visit https://review.coreboot.org/c/coreboot/+/46069 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4405526ae777332d3c72041db7b4eda25ae31b8e Gerrit-Change-Number: 46069 Gerrit-PatchSet: 1 Gerrit-Owner: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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coreboot-gerrit October 2020