coreboot-gerrit October 2020

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Change in coreboot[master]: mb/clevo/l140cu: clean up memcfg
by Michael Niewöhner (Code Review) 12 Oct '20

12 Oct '20

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46249 ) Change subject: mb/clevo/l140cu: clean up memcfg ...................................................................... mb/clevo/l140cu: clean up memcfg The DQ and DQS byte maps do not apply to DDR4 configurations, thus simply drop them. Also drop ECT, as it's already initialized to zero and can't be used on DDR4 anyway. Further, trim down all the meaningless and/or wrong comments. Change-Id: I32f1b7bb46eaaf0f0ecad1df310f5de988f64c85 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46249 Reviewed-by: Felix Singer <felixsinger(a)posteo.net> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/clevo/cml-u/variants/l140cu/romstage.c 1 file changed, 5 insertions(+), 51 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/romstage.c b/src/mainboard/clevo/cml-u/variants/l140cu/romstage.c index 4401483..4cad131 100644 --- a/src/mainboard/clevo/cml-u/variants/l140cu/romstage.c +++ b/src/mainboard/clevo/cml-u/variants/l140cu/romstage.c @@ -13,66 +13,20 @@ .spd_spec = {.spd_smbus_address = 0xa4}, }, - /* - * For each channel, there are 3 sets of DQ byte mappings, - * where each set has a package 0 and a package 1 value (package 0 - * represents the first 64-bit lpddr4 chip combination, and package 1 - * represents the second 64-bit lpddr4 chip combination). - * The first three sets are for CLK, CMD, and CTL. - * The fsp package actually expects 6 sets, but the last 3 sets are - * not used in CNL, so we only define the three sets that are used - * and let the meminit_lpddr4() routine take care of clearing the - * unused fields for the caller. - */ - .dq_map[DDR_CH0] = { - {0x0F, 0xF0}, {0x00, 0xF0}, {0x0F, 0xF0}, - //{0x0F, 0x00}, {0xFF, 0x00}, {0xFF, 0x00} - }, - .dq_map[DDR_CH1] = { - {0x33, 0xCC}, {0x00, 0xCC}, {0x33, 0xCC}, - //{0x33, 0x00}, {0xFF, 0x00}, {0xFF, 0x00} - }, - - /* - * DQS CPU<>DRAM map Ch0 and Ch1. Each array entry represents a - * mapping of a dq bit on the CPU to the bit it's connected to on - * the memory part. The array index represents the dqs bit number - * on the memory part, and the values in the array represent which - * pin on the CPU that DRAM pin connects to. - */ - .dqs_map[DDR_CH0] = {0, 1, 2, 3, 4, 5, 6, 7}, - .dqs_map[DDR_CH1] = {1, 0, 2, 3, 4, 5, 6, 7}, - - /* - * Rcomp resistor values. These values represent the resistance in - * ohms of the three rcomp resistors attached to the DDR_COMP_0, - * DDR_COMP_1, and DDR_COMP_2 pins on the DRAM. - */ + /* Values of the resistors connected to the DDR_RCOMP_[2:0] pins of the CPU */ .rcomp_resistor = { 121, 81, 100 }, - /* - * Rcomp target values. These will typically be the following - * values for Cannon Lake : { 80, 40, 40, 40, 30 } - */ + /* Rcomp target values */ .rcomp_targets = { 100, 40, 20, 20, 26 }, - /* - * Indicates whether memory is interleaved. - * Set to 1 for an interleaved design, - * set to 0 for non-interleaved design. - */ + /* Interleaved ("back-to-back") pin mapping */ .dq_pins_interleaved = 1, /* - * VREF_CA configuration. - * Set to 0 VREF_CA goes to both CH_A and CH_B, - * set to 1 VREF_CA goes to CH_A and VREF_DQ_A goes to CH_B, - * set to 2 VREF_CA goes to CH_A and VREF_DQ_B goes to CH_B. + * DDR4 Vref mapping + * VREF_CA goes to CH_A and VREF_DQ_B (DDR1_VREF_DQ) goes to CH_B. */ .vref_ca_config = 2, - - /* Early Command Training */ - .ect = 0, }; void mainboard_memory_init_params(FSPM_UPD *memupd) -- To view, visit https://review.coreboot.org/c/coreboot/+/46249 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32f1b7bb46eaaf0f0ecad1df310f5de988f64c85 Gerrit-Change-Number: 46249 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/clevo/l140cu: clean up memcfg
by Felix Singer (Code Review) 12 Oct '20

12 Oct '20

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46249 ) Change subject: mb/clevo/l140cu: clean up memcfg ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/46249 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32f1b7bb46eaaf0f0ecad1df310f5de988f64c85 Gerrit-Change-Number: 46249 Gerrit-PatchSet: 5 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 12 Oct 2020 19:20:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/clevo/l140cu: drop disabled SPD indices
by Michael Niewöhner (Code Review) 12 Oct '20

12 Oct '20

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46248 ) Change subject: mb/clevo/l140cu: drop disabled SPD indices ...................................................................... mb/clevo/l140cu: drop disabled SPD indices Drop the disabled SPD indices from memcfg, since they're already initialized to 0. Change-Id: I6d88bdac17222c2c5c35439517fe0bea46744b2b Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46248 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/clevo/cml-u/variants/l140cu/romstage.c 1 file changed, 0 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/romstage.c b/src/mainboard/clevo/cml-u/variants/l140cu/romstage.c index 1af8ce6..4401483 100644 --- a/src/mainboard/clevo/cml-u/variants/l140cu/romstage.c +++ b/src/mainboard/clevo/cml-u/variants/l140cu/romstage.c @@ -4,17 +4,14 @@ #include <soc/romstage.h> static const struct cnl_mb_cfg memcfg = { - /* Parameters required to access SPD for CH0D0/CH0D1/CH1D0/CH1D1. */ .spd[0] = { .read_type = READ_SPD_CBFS, .spd_spec = {.spd_index = 0}, }, - .spd[1] = {.read_type = NOT_EXISTING}, .spd[2] = { .read_type = READ_SMBUS, .spd_spec = {.spd_smbus_address = 0xa4}, }, - .spd[3] = {.read_type = NOT_EXISTING}, /* * For each channel, there are 3 sets of DQ byte mappings, -- To view, visit https://review.coreboot.org/c/coreboot/+/46248 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d88bdac17222c2c5c35439517fe0bea46744b2b Gerrit-Change-Number: 46248 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/clevo/l140cu: drop USE_LEGACY_8254_TIMER
by Michael Niewöhner (Code Review) 12 Oct '20

12 Oct '20

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45960 ) Change subject: mb/clevo/l140cu: drop USE_LEGACY_8254_TIMER ...................................................................... mb/clevo/l140cu: drop USE_LEGACY_8254_TIMER Drop USE_LEGACY_8254_TIMER, since it's not required anymore for booting grub, despite the comment. The issue was resolved upstream five years ago: http://git.savannah.gnu.org/cgit/grub.git/commit/?id=d43a5ee65143f384357fbf… Test: - Boot EFI GRUB2 from TianoCore payload (Debian Live, Ubuntu installer) - Boot GRUB2 payload Change-Id: I5ce4f5168586bf305969b2e24b6ee895c8552749 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45960 Reviewed-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/clevo/cml-u/Kconfig 1 file changed, 0 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Felix Singer: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/mainboard/clevo/cml-u/Kconfig b/src/mainboard/clevo/cml-u/Kconfig index 082bf62..c08b321 100644 --- a/src/mainboard/clevo/cml-u/Kconfig +++ b/src/mainboard/clevo/cml-u/Kconfig @@ -19,7 +19,6 @@ select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SPD_READ_BY_WORD select SYSTEM_TYPE_LAPTOP - select USE_LEGACY_8254_TIMER # Fix failure to boot GRUB config MAINBOARD_DIR string -- To view, visit https://review.coreboot.org/c/coreboot/+/45960 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ce4f5168586bf305969b2e24b6ee895c8552749 Gerrit-Change-Number: 45960 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/clevo/l140cu: set PS/2 timeout for SeaBIOS
by Michael Niewöhner (Code Review) 12 Oct '20

12 Oct '20

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45959 ) Change subject: mb/clevo/l140cu: set PS/2 timeout for SeaBIOS ...................................................................... mb/clevo/l140cu: set PS/2 timeout for SeaBIOS The keyboard only works randomly, because SeaBIOS initializes PS/2 before the EC is ready. Set the PS/2 timeout for SeaBIOS to 500 ms, to wait for the EC before initializing the keyboard. Test: keyboard works fine. Change-Id: I2be75961035f04a7ffa6f7e1dbaabb1243b857f9 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45959 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/clevo/cml-u/Kconfig 1 file changed, 5 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/mainboard/clevo/cml-u/Kconfig b/src/mainboard/clevo/cml-u/Kconfig index ae79794..082bf62 100644 --- a/src/mainboard/clevo/cml-u/Kconfig +++ b/src/mainboard/clevo/cml-u/Kconfig @@ -81,4 +81,9 @@ string default "l140cu" if BOARD_CLEVO_L140CU +config SEABIOS_PS2_TIMEOUT + int + depends on PAYLOAD_SEABIOS + default 500 + endif -- To view, visit https://review.coreboot.org/c/coreboot/+/45959 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2be75961035f04a7ffa6f7e1dbaabb1243b857f9 Gerrit-Change-Number: 45959 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common: rewrite and clarify the Legacy 8254 Timer Kconfig
by Michael Niewöhner (Code Review) 12 Oct '20

12 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46302 ) Change subject: soc/intel/common: rewrite and clarify the Legacy 8254 Timer Kconfig ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/46302 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9637c549db1ce29f259708f316852fc2ae9e7c38 Gerrit-Change-Number: 46302 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Mon, 12 Oct 2020 18:24:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: drop default to enable the PIT if SeaBIOS is chosen
by Michael Niewöhner (Code Review) 12 Oct '20

12 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46301 ) Change subject: soc/intel/common: drop default to enable the PIT if SeaBIOS is chosen ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/46301 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd75800678707a92110682347c7cfb93e25109a4 Gerrit-Change-Number: 46301 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Mon, 12 Oct 2020 18:23:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer/var/voxel: disable DdiPortHpd
by Sheng-Liang Pan (Code Review) 12 Oct '20

12 Oct '20

Sheng-Liang Pan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46069 ) Change subject: mb/google/volteer/var/voxel: disable DdiPortHpd ...................................................................... mb/google/volteer/var/voxel: disable DdiPortHpd GPP_A19 and GPP_A20 set no connection, disables DdiPort1Hpd and DdiPort2Hpd BUG=b:169690329 TEST=build and verify type-c(C0/C1) port functional normally Signed-off-by: Pan Sheng-Liang <sheng-liang.pan(a)quanta.corp-partner.google.com> Change-Id: I4405526ae777332d3c72041db7b4eda25ae31b8e --- M src/mainboard/google/volteer/variants/voxel/overridetree.cb 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/46069/1 diff --git a/src/mainboard/google/volteer/variants/voxel/overridetree.cb b/src/mainboard/google/volteer/variants/voxel/overridetree.cb index 330d852..f3a04b4 100644 --- a/src/mainboard/google/volteer/variants/voxel/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voxel/overridetree.cb @@ -1,4 +1,6 @@ chip soc/intel/tigerlake + register "DdiPort1Hpd" = "0" + register "DdiPort2Hpd" = "0" register "tcc_offset" = "5" # TCC of 95 register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ -- To view, visit https://review.coreboot.org/c/coreboot/+/46069 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4405526ae777332d3c72041db7b4eda25ae31b8e Gerrit-Change-Number: 46069 Gerrit-PatchSet: 1 Gerrit-Owner: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede: refactor DPTF section for simpler overrides
by Sumeet R Pawnikar (Code Review) 12 Oct '20

12 Oct '20

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46090 ) Change subject: mb/google/dedede: refactor DPTF section for simpler overrides ...................................................................... mb/google/dedede: refactor DPTF section for simpler overrides Refactor DPTF section of code under the baseboard devicetree and overridetree. This makes override mechanism more simpler, because not all the DPTF fields need to be overridden. BUG=None BRANCH=None TEST=Built and tested on dedede system Change-Id: I8e7cfe60c010ed4c07f9089325b289519e861f84 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/dedede/variants/drawcia/overridetree.cb 2 files changed, 69 insertions(+), 45 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/46090/1 diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 1f72eb1..4bb0a3c 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -184,27 +184,39 @@ device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device device pci 04.0 on + # Default DPTF Policy for all Dedede boards if not overridden chip drivers/intel/dptf - register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 90, 10000)" - register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 80, 60000)" - register "policies.passive[2]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 55, 15000)" + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 90, 10000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 80, 60000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 55, 15000) + }" - register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 105, SHUTDOWN)" - register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 90, SHUTDOWN)" - register "policies.critical[2]" = "DPTF_CRITICAL(TEMP_SENSOR_1, 80, SHUTDOWN)" + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 90, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 80, SHUTDOWN) + }" - register "controls.power_limits.pl1" = "{ - .min_power = 3000, - .max_power = 6000, - .time_window_min = 1 * MSECS_PER_SEC, - .time_window_max = 1 * MSECS_PER_SEC, - .granularity = 200,}" - register "controls.power_limits.pl2" = "{ - .min_power = 6000, - .max_power = 20000, - .time_window_min = 1 * MSECS_PER_SEC, - .time_window_max = 1 * MSECS_PER_SEC, - .granularity = 1000,}" + ## Power Limits Control + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 3000, + .max_power = 6000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 200, + }, + .pl2 = { + .min_power = 6000, + .max_power = 20000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 1000, + } + }" register "options.tsr[0].desc" = ""Memory"" register "options.tsr[1].desc" = ""Ambient"" diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb index fa10152..685aeb5 100644 --- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb +++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb @@ -67,42 +67,54 @@ device domain 0 on device pci 04.0 on chip drivers/intel/dptf - + # Default DPTF Policy for all Volteer boards if not overridden register "options.tsr[0].desc" = ""Memory"" register "options.tsr[1].desc" = ""Ambient"" register "options.tsr[2].desc" = ""Charger"" register "options.tsr[3].desc" = ""5V regulator"" - register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 80, 1000)" - register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 70, 4000)" - register "policies.passive[2]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 1000)" - register "policies.passive[3]" = "DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 5000)" - register "policies.passive[4]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 60, 1000)" + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 80, 1000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 70, 4000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 1000), + [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 5000), + [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 60, 1000) + }" - register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 119, SHUTDOWN)" - register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 115, SHUTDOWN)" - register "policies.critical[2]" = "DPTF_CRITICAL(TEMP_SENSOR_1, 115, SHUTDOWN)" - register "policies.critical[3]" = "DPTF_CRITICAL(TEMP_SENSOR_2, 115, SHUTDOWN)" - register "policies.critical[4]" = "DPTF_CRITICAL(TEMP_SENSOR_3, 115, SHUTDOWN)" + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 119, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 115, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 115, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 115, SHUTDOWN), + [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 115, SHUTDOWN) + }" - register "controls.power_limits.pl1" = "{ - .min_power = 4800, - .max_power = 6000, - .time_window_min = 1 * MSECS_PER_SEC, - .time_window_max = 1 * MSECS_PER_SEC, - .granularity = 200,}" - register "controls.power_limits.pl2" = "{ - .min_power = 6000, - .max_power = 20000, - .time_window_min = 1 * MSECS_PER_SEC, - .time_window_max = 1 * MSECS_PER_SEC, - .granularity = 1000,}" + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 4800, + .max_power = 6000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 200, + }, + .pl2 = { + .min_power = 6000, + .max_power = 20000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 1000, + } + }" ## Charger Performance Control (Control, mA) - register "controls.charger_perf[0]" = "{ 255, 3000 }" - register "controls.charger_perf[1]" = "{ 24, 1500 }" - register "controls.charger_perf[2]" = "{ 16, 1000 }" - register "controls.charger_perf[3]" = "{ 8, 500 }" + register "controls.charger_perf" = "{ + [0] = { 255, 3000 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" device generic 0 on end end -- To view, visit https://review.coreboot.org/c/coreboot/+/46090 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8e7cfe60c010ed4c07f9089325b289519e861f84 Gerrit-Change-Number: 46090 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

3 11

Change in coreboot[master]: vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3373
by Srinidhi N Kaushik (Code Review) 12 Oct '20

12 Oct '20

Srinidhi N Kaushik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45630 ) Change subject: vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3373 ...................................................................... vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3373 Update FSP headers for Tiger Lake platform generated based FSP version 3373. Previous version was 3333. Changes Includes below UPDs: ITbtPcieTunnelingForUsb4 SlowSlewRate FastPkgCRampDisable BUG=b: BRANCH=none TEST=build and boot delbin/tglrvp Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Change-Id: I2e28905f8f7241940ea92ac3e83b52ff7948953a --- M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h 2 files changed, 55 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/45630/1 diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h index 0b3fe7d..28592cd 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h @@ -2498,7 +2498,7 @@ /** Offset 0x091C - Reserved **/ - UINT8 Reserved45[4]; + UINT8 Reserved45[12]; } FSP_M_CONFIG; /** Fsp M UPD Configuration @@ -2517,11 +2517,11 @@ **/ FSP_M_CONFIG FspmConfig; -/** Offset 0x0920 +/** Offset 0x0928 **/ - UINT8 UnusedUpdSpace25[6]; + UINT8 UnusedUpdSpace27[6]; -/** Offset 0x0926 +/** Offset 0x092E **/ UINT16 UpdTerminator; } FSPM_UPD; diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h index 315a0a7..b7ef000 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h @@ -923,9 +923,15 @@ **/ UINT8 D3ColdEnable; -/** Offset 0x04B9 - Reserved +/** Offset 0x04B9 - Enable/Disable PCIe tunneling for USB4 + Enable/Disable PCIe tunneling for USB4, default is enable + $EN_DIS **/ - UINT8 Reserved20[8]; + UINT8 ITbtPcieTunnelingForUsb4; + +/** Offset 0x04BA - Reserved +**/ + UINT8 Reserved20[7]; /** Offset 0x04C1 - Enable VMD controller Enable/disable to VMD controller.0: Disable(Default); 1: Enable @@ -1186,9 +1192,19 @@ **/ UINT8 AcousticNoiseMitigation; -/** Offset 0x054B - Reserved +/** Offset 0x054B - Disable Fast Slew Rate for Deep Package C States for VR domains + Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation + feature enabled. 0: False; 1: True + $EN_DIS **/ - UINT8 Reserved28[10]; + UINT8 FastPkgCRampDisable[5]; + +/** Offset 0x0550 - Slew Rate configuration for Deep Package C States for VR domains + Slew Rate configuration for Deep Package C States for VR domains based on Acoustic + Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16 + 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16 +**/ + UINT8 SlowSlewRate[5]; /** Offset 0x0555 - Enable multi phases silicon initialization A switch to determine MultiPhaseSiInit will be executed or not @@ -1198,7 +1214,7 @@ /** Offset 0x0556 - Reserved **/ - UINT8 Reserved29[10]; + UINT8 Reserved28[10]; /** Offset 0x0560 - AcLoadline PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is @@ -1247,7 +1263,7 @@ /** Offset 0x05A7 - Reserved **/ - UINT8 Reserved30; + UINT8 Reserved29; /** Offset 0x05A8 - Enable or Disable TXT Enable or Disable TXT; 0: Disable; 1: Enable. @@ -1278,7 +1294,7 @@ /** Offset 0x05AD - Reserved **/ - UINT8 Reserved31[3]; + UINT8 Reserved30[3]; /** Offset 0x05B0 - CpuBistData Pointer CPU BIST Data @@ -1299,7 +1315,7 @@ /** Offset 0x05BC - Reserved **/ - UINT8 Reserved32[16]; + UINT8 Reserved31[16]; /** Offset 0x05CC - PpinSupport to view Protected Processor Inventory Number Enable or Disable or Auto (Based on End of Manufacturing flag. Disabled if this @@ -1340,7 +1356,7 @@ /** Offset 0x05DE - Reserved **/ - UINT8 Reserved33[10]; + UINT8 Reserved32[10]; /** Offset 0x05E8 - Enable Power Optimizer Enable DMI Power Optimizer on PCH side. @@ -1360,7 +1376,7 @@ /** Offset 0x05F3 - Reserved **/ - UINT8 Reserved34; + UINT8 Reserved33; /** Offset 0x05F4 - PCH Protect Range Limit Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for @@ -1387,7 +1403,7 @@ /** Offset 0x060A - Reserved **/ - UINT8 Reserved35[3]; + UINT8 Reserved34[3]; /** Offset 0x060D - Enable PCH ISH SPI Cs0 pins assigned Set if ISH SPI Cs0 pins are to be enabled by BIOS. 0: Disable; 1: Enable. @@ -1452,7 +1468,7 @@ /** Offset 0x0622 - Reserved **/ - UINT8 Reserved36; + UINT8 Reserved35; /** Offset 0x0623 - RTC Cmos Memory Lock Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper @@ -1534,7 +1550,7 @@ /** Offset 0x075D - Reserved **/ - UINT8 Reserved37[7]; + UINT8 Reserved36[7]; /** Offset 0x0764 - Touch Host Controller Port 1 Assignment Assign THC Port 1 @@ -1544,7 +1560,7 @@ /** Offset 0x0765 - Reserved **/ - UINT8 Reserved38[7]; + UINT8 Reserved37[7]; /** Offset 0x076C - PCIE RP Pcie Speed Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see: @@ -1586,7 +1602,7 @@ /** Offset 0x0814 - Reserved **/ - UINT8 Reserved39[45]; + UINT8 Reserved38[45]; /** Offset 0x0841 - PCIE Enable Peer Memory Write This member describes whether Peer Memory Writes are enabled on the platform. @@ -1609,7 +1625,7 @@ /** Offset 0x0844 - Reserved **/ - UINT8 Reserved40[2]; + UINT8 Reserved39[2]; /** Offset 0x0846 - PCH Pm PME_B0_S5_DIS When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1. @@ -1805,7 +1821,7 @@ /** Offset 0x0899 - Reserved **/ - UINT8 Reserved41; + UINT8 Reserved40; /** Offset 0x089A - Enable SATA Port DmVal DEVSLP Idle Timeout (DITO), Default is 625. @@ -1912,7 +1928,7 @@ /** Offset 0x08C9 - Reserved **/ - UINT8 Reserved42; + UINT8 Reserved41; /** Offset 0x08CA - Thermal Throttling Custimized T0Level Value Custimized T0Level value. @@ -2087,7 +2103,7 @@ /** Offset 0x08EF - Reserved **/ - UINT8 Reserved43; + UINT8 Reserved42; /** Offset 0x08F0 - Thermal Device Temperature Decides the temperature. @@ -2112,7 +2128,7 @@ /** Offset 0x090D - Reserved **/ - UINT8 Reserved44[3]; + UINT8 Reserved43[3]; /** Offset 0x0910 - xHCI High Idle Time LTR override Value used for overriding LTR recommendation for xHCI High Idle Time LTR setting @@ -2174,7 +2190,7 @@ /** Offset 0x0922 - Reserved **/ - UINT8 Reserved45[6]; + UINT8 Reserved44[6]; /** Offset 0x0928 - BgpdtHash[4] BgpdtHash values @@ -2188,7 +2204,7 @@ /** Offset 0x094C - Reserved **/ - UINT8 Reserved46[4]; + UINT8 Reserved45[4]; /** Offset 0x0950 - BiosGuardModulePtr BiosGuardModulePtr default values @@ -2214,7 +2230,7 @@ /** Offset 0x0962 - Reserved **/ - UINT8 Reserved47[6]; + UINT8 Reserved46[6]; /** Offset 0x0968 - SgxEpoch0 SgxEpoch0 default values @@ -2240,7 +2256,7 @@ /** Offset 0x097A - Reserved **/ - UINT8 Reserved48[6]; + UINT8 Reserved47[6]; /** Offset 0x0980 - SVID SDID table Poniter. The address of the table of SVID SDID to customize each SVID SDID entry. This is @@ -2308,7 +2324,7 @@ /** Offset 0x099D - Reserved **/ - UINT8 Reserved49[315]; + UINT8 Reserved48[315]; /** Offset 0x0AD8 - RpPtmBytes **/ @@ -2316,7 +2332,7 @@ /** Offset 0x0ADC - Reserved **/ - UINT8 Reserved50[16]; + UINT8 Reserved49[16]; /** Offset 0x0AEC - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3 Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3, Each @@ -2427,7 +2443,7 @@ /** Offset 0x0B44 - Reserved **/ - UINT8 Reserved51[16]; + UINT8 Reserved50[16]; /** Offset 0x0B54 - 1-Core Ratio Limit 1-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused @@ -2709,7 +2725,7 @@ /** Offset 0x0B82 - Reserved **/ - UINT8 Reserved52; + UINT8 Reserved51; /** Offset 0x0B83 - Enable or Disable Thermal Monitor Enable or Disable Thermal Monitor; 0: Disable; 1: Enable @@ -2847,7 +2863,7 @@ /** Offset 0x0BCF - Reserved **/ - UINT8 Reserved53; + UINT8 Reserved52; /** Offset 0x0BD0 - Platform Power Pmax PCODE MMIO Mailbox: Platform Power Pmax. 0 - Auto Specified in 1/8 Watt increments. @@ -3085,7 +3101,7 @@ /** Offset 0x0C22 - Reserved **/ - UINT8 Reserved54[17]; + UINT8 Reserved53[17]; /** Offset 0x0C33 - SgxSinitDataFromTpm SgxSinitDataFromTpm default values @@ -3094,7 +3110,7 @@ /** Offset 0x0C34 - Reserved **/ - UINT8 Reserved55[16]; + UINT8 Reserved54[16]; /** Offset 0x0C44 - End of Post message Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1): @@ -3228,7 +3244,7 @@ /** Offset 0x0DB9 - Reserved **/ - UINT8 Reserved56[231]; + UINT8 Reserved55[239]; } FSP_S_CONFIG; /** Fsp S UPD Configuration @@ -3243,11 +3259,11 @@ **/ FSP_S_CONFIG FspsConfig; -/** Offset 0x0EA0 +/** Offset 0x0EA8 **/ - UINT8 UnusedUpdSpace35[6]; + UINT8 UnusedUpdSpace34[6]; -/** Offset 0x0EA6 +/** Offset 0x0EAE **/ UINT16 UpdTerminator; } FSPS_UPD; -- To view, visit https://review.coreboot.org/c/coreboot/+/45630 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e28905f8f7241940ea92ac3e83b52ff7948953a Gerrit-Change-Number: 45630 Gerrit-PatchSet: 1 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-MessageType: newchange

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