HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31196
Change subject: cpu/intel: Use macro instead of numbers ......................................................................
cpu/intel: Use macro instead of numbers
Change-Id: Ic18c219beaec3dad197916a1e235a027c1c74a89 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/cpu/intel/fsp_model_406dx/model_406dx_init.c M src/cpu/intel/haswell/haswell_init.c M src/cpu/intel/model_1067x/model_1067x_init.c M src/cpu/intel/model_106cx/model_106cx_init.c M src/cpu/intel/model_206ax/model_206ax_init.c M src/cpu/intel/model_6ex/model_6ex_init.c M src/cpu/intel/model_6fx/model_6fx_init.c 7 files changed, 10 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/31196/1
diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx_init.c b/src/cpu/intel/fsp_model_406dx/model_406dx_init.c index 7994f0b..06b37a9 100644 --- a/src/cpu/intel/fsp_model_406dx/model_406dx_init.c +++ b/src/cpu/intel/fsp_model_406dx/model_406dx_init.c @@ -47,9 +47,9 @@ msr_t msr;
msr = rdmsr(IA32_MISC_ENABLE); - msr.lo |= (1 << 0); /* Fast String enable */ + msr.lo |= FAST_STRINGS_ENABLE_BIT; msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ - msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ + msr.lo |= SPEED_STEP_ENABLE_BIT; wrmsr(IA32_MISC_ENABLE, msr);
/* Disable Thermal interrupts */ diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index aa77964..08abdf5 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -578,9 +578,9 @@ msr_t msr;
msr = rdmsr(IA32_MISC_ENABLE); - msr.lo |= (1 << 0); /* Fast String enable */ + msr.lo |= FAST_STRINGS_ENABLE_BIT; msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ - msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ + msr.lo |= SPEED_STEP_ENABLE_BIT; wrmsr(IA32_MISC_ENABLE, msr);
/* Disable Thermal interrupts */ diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index 6068be1..97ed39d 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -199,7 +199,7 @@ msr.lo |= (1 << 10); /* FERR# multiplexing */
if (eist) - msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ + msr.lo |= SPEED_STEP_ENABLE_BIT;
/* Enable C2E */ if (((sub_cstates >> (2 * 4)) & 0xf) >= 2) diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c index e443026..1c0d081 100644 --- a/src/cpu/intel/model_106cx/model_106cx_init.c +++ b/src/cpu/intel/model_106cx/model_106cx_init.c @@ -65,7 +65,7 @@ msr.lo |= (1 << 10); /* FERR# multiplexing */
// TODO: Only if IA32_PLATFORM_ID[17] = 0 and IA32_PLATFORM_ID[50] = 1 - msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ + msr.lo |= SPEED_STEP_ENABLE_BIT;
// TODO Do we want Deep C4 and Dynamic L2 shrinking? wrmsr(IA32_MISC_ENABLE, msr); diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 33ad1e7..c2e0364 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -338,9 +338,9 @@ msr_t msr;
msr = rdmsr(IA32_MISC_ENABLE); - msr.lo |= (1 << 0); /* Fast String enable */ + msr.lo |= FAST_STRINGS_ENABLE_BIT; msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ - msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ + msr.lo |= SPEED_STEP_ENABLE_BIT; wrmsr(IA32_MISC_ENABLE, msr);
/* Disable Thermal interrupts */ diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index 19a22f1..fbc6964 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -67,7 +67,7 @@ msr.lo |= (1 << 10); /* FERR# multiplexing */
// TODO: Only if IA32_PLATFORM_ID[17] = 0 and IA32_PLATFORM_ID[50] = 1 - msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ + msr.lo |= SPEED_STEP_ENABLE_BIT;
/* Enable C2E */ msr.lo |= (1 << 26); diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index 4e19896..adc0265 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -70,7 +70,7 @@ msr.lo |= (1 << 10); /* FERR# multiplexing */
// TODO: Only if IA32_PLATFORM_ID[17] = 0 and IA32_PLATFORM_ID[50] = 1 - msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ + msr.lo |= SPEED_STEP_ENABLE_BIT;
/* Enable C2E */ msr.lo |= (1 << 26);
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31196 )
Change subject: cpu/intel: Use macro instead of numbers ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/#/c/31196/1/src/cpu/intel/fsp_model_406dx/model_... File src/cpu/intel/fsp_model_406dx/model_406dx_init.c:
https://review.coreboot.org/#/c/31196/1/src/cpu/intel/fsp_model_406dx/model_... PS1, Line 51: TM2 TM2 is at (1 << 13) , right ?
David Guckian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31196 )
Change subject: cpu/intel: Use macro instead of numbers ......................................................................
Patch Set 1: Code-Review+1
(1 comment)
https://review.coreboot.org/#/c/31196/1/src/cpu/intel/fsp_model_406dx/model_... File src/cpu/intel/fsp_model_406dx/model_406dx_init.c:
https://review.coreboot.org/#/c/31196/1/src/cpu/intel/fsp_model_406dx/model_... PS1, Line 51: TM2
TM2 is at (1 << 13) , right ?
Yes, and BIT3 is Automatic Thermal Control Circuit Enable (R/W) 1 = Setting this bit enables the thermal control circuit (TCC) portion of the Intel Thermal Monitor feature. This allows the processor to automatically reduce power consumption in response to TCC activation. 0 = Disabled (default). Note: In some products clearing this bit might be ignored in critical thermal conditions, and TM1, TM2 and adaptive thermal throttling will still be activated.
I suppose the comment could be updated
Hello Patrick Rudolph, David Guckian, Angel Pons, build bot (Jenkins), David Guckian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31196
to look at the new patch set (#2).
Change subject: cpu/intel: Use macro instead of numbers ......................................................................
cpu/intel: Use macro instead of numbers
Change-Id: Ic18c219beaec3dad197916a1e235a027c1c74a89 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/cpu/intel/fsp_model_406dx/model_406dx_init.c M src/cpu/intel/haswell/haswell_init.c M src/cpu/intel/model_1067x/model_1067x_init.c M src/cpu/intel/model_106cx/model_106cx_init.c M src/cpu/intel/model_206ax/model_206ax_init.c M src/cpu/intel/model_6ex/model_6ex_init.c M src/cpu/intel/model_6fx/model_6fx_init.c M src/include/cpu/x86/msr.h 8 files changed, 23 insertions(+), 21 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/31196/2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31196 )
Change subject: cpu/intel: Use macro instead of numbers ......................................................................
Patch Set 2: Code-Review+1
HAOUAS Elyes has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/31196 )
Change subject: cpu/intel: Use macro instead of numbers ......................................................................
Abandoned
HAOUAS Elyes has restored this change. ( https://review.coreboot.org/c/coreboot/+/31196 )
Change subject: cpu/intel: Use macro instead of numbers ......................................................................
Restored
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31196 )
Change subject: cpu/intel: Use macro instead of numbers ......................................................................
Patch Set 2: Code-Review+1
Hello Patrick Rudolph, David Guckian, Angel Pons, Paul Menzel, build bot (Jenkins), David Guckian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31196
to look at the new patch set (#4).
Change subject: cpu/intel: Use macro instead of numbers ......................................................................
cpu/intel: Use macro instead of numbers
Change-Id: Ic18c219beaec3dad197916a1e235a027c1c74a89 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/cpu/intel/haswell/haswell_init.c M src/cpu/intel/model_1067x/model_1067x_init.c M src/cpu/intel/model_106cx/model_106cx_init.c M src/cpu/intel/model_206ax/model_206ax_init.c M src/cpu/intel/model_6ex/model_6ex_init.c M src/cpu/intel/model_6fx/model_6fx_init.c M src/include/cpu/x86/msr.h 7 files changed, 20 insertions(+), 18 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/31196/4
HAOUAS Elyes has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/31196 )
Change subject: cpu/intel: Use macro instead of numbers ......................................................................
Abandoned
HAOUAS Elyes has restored this change. ( https://review.coreboot.org/c/coreboot/+/31196 )
Change subject: cpu/intel: Use macro instead of numbers ......................................................................
Restored
Hello build bot (Jenkins), David Guckian, Paul Menzel, Angel Pons, Patrick Rudolph, David Guckian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31196
to look at the new patch set (#5).
Change subject: cpu/intel/{haswell,model_206ax}: Use FAST_STRINGS_ENABLE_BIT macro ......................................................................
cpu/intel/{haswell,model_206ax}: Use FAST_STRINGS_ENABLE_BIT macro
Change-Id: Ic18c219beaec3dad197916a1e235a027c1c74a89 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/cpu/intel/haswell/haswell_init.c M src/cpu/intel/model_206ax/model_206ax_init.c 2 files changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/31196/5
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Angel Pons (Code Review) -
David Guckian (Code Review)
-
HAOUAS Elyes (Code Review)
-
Paul Menzel (Code Review)