coreboot-gerrit October 2020

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Change in coreboot[master]: soc/intel: Configure PAVP at compile-time
by Benjamin Doron (Code Review) 08 Oct '20

08 Oct '20

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42745 ) Change subject: soc/intel: Configure PAVP at compile-time ...................................................................... Patch Set 13: (2 comments) > Patch Set 9: Code-Review+2 > > (2 comments) > > Looks good, but please remove the Jasper Lake special treatment > after rebase. Done https://review.coreboot.org/c/coreboot/+/42745/9//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/42745/9//COMMIT_MSG@9 PS9, Line 9: Expose configuration of Intel PAVP (Protected Audio-Video Path, a digital > Please break lines before 72 chars. Done https://review.coreboot.org/c/coreboot/+/42745/9//COMMIT_MSG@14 PS9, Line 14: Also add a period at the end of Kconfig help for MMA while editing the file. > Not a good idea generally, it makes individual changes harder to track […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/42745 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2aae741bb30e3be3c64324cd6334778bd271a903 Gerrit-Change-Number: 42745 Gerrit-PatchSet: 13 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 08 Oct 2020 19:48:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: Configure PAVP at compile-time
by Benjamin Doron (Code Review) 08 Oct '20

08 Oct '20

Hello build bot (Jenkins), Nico Huber, Justin TerAvest, Angel Pons, Subrata Banik, Ronak Kanabar, Andrey Petrov, Patrick Rudolph, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/42745 to look at the new patch set (#13). Change subject: soc/intel: Configure PAVP at compile-time ...................................................................... soc/intel: Configure PAVP at compile-time Expose configuration of Intel PAVP (Protected Audio-Video Path, a digital rights protection/management (DRM) technology for multimedia content) to Kconfig. Change-Id: I2aae741bb30e3be3c64324cd6334778bd271a903 Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> --- M src/soc/intel/apollolake/chip.c M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/common/Kconfig.common M src/soc/intel/icelake/fsp_params.c M src/soc/intel/jasperlake/fsp_params.c M src/soc/intel/skylake/chip.c 6 files changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/42745/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/42745 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2aae741bb30e3be3c64324cd6334778bd271a903 Gerrit-Change-Number: 42745 Gerrit-PatchSet: 13 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel: Configure PAVP at compile-time
by Benjamin Doron (Code Review) 08 Oct '20

08 Oct '20

Hello build bot (Jenkins), Nico Huber, Justin TerAvest, Angel Pons, Subrata Banik, Ronak Kanabar, Andrey Petrov, Patrick Rudolph, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/42745 to look at the new patch set (#12). Change subject: soc/intel: Configure PAVP at compile-time ...................................................................... soc/intel: Configure PAVP at compile-time Expose configuration of Intel PAVP (Protected Audio-Video Path, a digital rights protection/management (DRM) technology for multimedia content) to Kconfig. Note that Jasperlake can now enable PAVP, whereas previously it was disabled. Also add a period at the end of Kconfig help for MMA while editing the file. Change-Id: I2aae741bb30e3be3c64324cd6334778bd271a903 Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> --- M src/soc/intel/apollolake/chip.c M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/common/Kconfig.common M src/soc/intel/icelake/fsp_params.c M src/soc/intel/jasperlake/fsp_params.c M src/soc/intel/skylake/chip.c 6 files changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/42745/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/42745 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2aae741bb30e3be3c64324cd6334778bd271a903 Gerrit-Change-Number: 42745 Gerrit-PatchSet: 12 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/dedede/variants/drawcia: Update TSR1 passive trip temperature
by Sumeet R Pawnikar (Code Review) 08 Oct '20

08 Oct '20

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45859 ) Change subject: mb/google/dedede/variants/drawcia: Update TSR1 passive trip temperature ...................................................................... mb/google/dedede/variants/drawcia: Update TSR1 passive trip temperature Update TSR1 passive trip temperature BUG=b:169691800 BRANCH=None TEST=Built and tested on dedede system Change-Id: I172391daca981d5591fa9cc5eacad92521dd0dc5 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/dedede/variants/drawcia/overridetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/45859/1 diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb index fa10152..715da7a 100644 --- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb +++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb @@ -75,7 +75,7 @@ register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 80, 1000)" register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 70, 4000)" - register "policies.passive[2]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 1000)" + register "policies.passive[2]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 51, 1000)" register "policies.passive[3]" = "DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 5000)" register "policies.passive[4]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 60, 1000)" -- To view, visit https://review.coreboot.org/c/coreboot/+/45859 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I172391daca981d5591fa9cc5eacad92521dd0dc5 Gerrit-Change-Number: 45859 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel: Configure PAVP at compile-time
by Benjamin Doron (Code Review) 08 Oct '20

08 Oct '20

Hello build bot (Jenkins), Nico Huber, Justin TerAvest, Angel Pons, Subrata Banik, Ronak Kanabar, Andrey Petrov, Patrick Rudolph, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/42745 to look at the new patch set (#10). Change subject: soc/intel: Configure PAVP at compile-time ...................................................................... soc/intel: Configure PAVP at compile-time Expose configuration of Intel PAVP (Protected Audio-Video Path, a digital rights protection/management (DRM) technology for multimedia content) to Kconfig. Note that Jasperlake can now enable PAVP, whereas previously it was disabled. Also add a period at the end of Kconfig help for MMA while editing the file. Change-Id: I2aae741bb30e3be3c64324cd6334778bd271a903 Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> --- M src/soc/intel/apollolake/chip.c M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/common/Kconfig.common M src/soc/intel/icelake/fsp_params.c M src/soc/intel/skylake/chip.c 5 files changed, 24 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/42745/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/42745 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2aae741bb30e3be3c64324cd6334778bd271a903 Gerrit-Change-Number: 42745 Gerrit-PatchSet: 10 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/dedede: Fill VR Configuration Values from devicetree
by Meera Ravindranath (Code Review) 08 Oct '20

08 Oct '20

Meera Ravindranath has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45825 ) Change subject: mb/google/dedede: Fill VR Configuration Values from devicetree ...................................................................... mb/google/dedede: Fill VR Configuration Values from devicetree BUG=b:167472333 TEST=Build and boot dedede and observe the slope and offset values getting updated in the fsp debug log Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> Change-Id: I3ea32218040263f0abef9b9dd4c52efb16289fd7 --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/45825/1 diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 1f72eb1..22c62e7 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -163,6 +163,15 @@ # register "common_soc_config.<variable_name>" = "value" register "common_soc_config.chipset_lockdown" = CHIPSET_LOCKDOWN_COREBOOT + # VR config settings + # Imon Slope correction specified in 1/100 increment values. Range is 0-200. + # Eg: 125 = 1.25 + register "ImonSlope" = "100" + + # Imon offset correction. Value is a 2's complement signed integer. Units 1/1000, Range 0-63999. + # For an offset = 12.580, use 12580 + register "ImonOffset" = "0" + # Skip the CPU repalcement check register "SkipCpuReplacementCheck" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/45825 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ea32218040263f0abef9b9dd4c52efb16289fd7 Gerrit-Change-Number: 45825 Gerrit-PatchSet: 1 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/jasperlake: Update VR Configuration Values
by Meera Ravindranath (Code Review) 08 Oct '20

08 Oct '20

Meera Ravindranath has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45645 ) Change subject: soc/intel/jasperlake: Update VR Configuration Values ...................................................................... soc/intel/jasperlake: Update VR Configuration Values This patch fixes the CPU Throttling issue observed on Drawlat BRANCH=None BUG=b:167472333 Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> Change-Id: I3fa32218040263f0abef8b9dd4c52efb31289fd7 --- M src/soc/intel/jasperlake/fsp_params.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/45645/1 diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c index cdd088e..6c83503 100644 --- a/src/soc/intel/jasperlake/fsp_params.c +++ b/src/soc/intel/jasperlake/fsp_params.c @@ -177,6 +177,10 @@ sizeof(params->SataPortsDevSlp)); } + /* VR Configuration */ + params->IccMax[0] = 140; + params->TdcCurrentLimit[0] = 80; + /* SDCard related configuration */ dev = pcidev_path_on_root(PCH_DEVFN_SDCARD); params->ScsSdCardEnabled = is_dev_enabled(dev); -- To view, visit https://review.coreboot.org/c/coreboot/+/45645 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3fa32218040263f0abef8b9dd4c52efb31289fd7 Gerrit-Change-Number: 45645 Gerrit-PatchSet: 1 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel: Configure PAVP at compile-time
by Nico Huber (Code Review) 08 Oct '20

08 Oct '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42745 ) Change subject: soc/intel: Configure PAVP at compile-time ...................................................................... Patch Set 9: Code-Review+2 (2 comments) Looks good, but please remove the Jasper Lake special treatment after rebase. https://review.coreboot.org/c/coreboot/+/42745/9//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/42745/9//COMMIT_MSG@9 PS9, Line 9: Expose configuration of Intel PAVP (Protected Audio-Video Path, a digital Please break lines before 72 chars. https://review.coreboot.org/c/coreboot/+/42745/9//COMMIT_MSG@14 PS9, Line 14: Also add a period at the end of Kconfig help for MMA while editing the file. Not a good idea generally, it makes individual changes harder to track (and to revert). -- To view, visit https://review.coreboot.org/c/coreboot/+/42745 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2aae741bb30e3be3c64324cd6334778bd271a903 Gerrit-Change-Number: 42745 Gerrit-PatchSet: 9 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 08 Oct 2020 19:10:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: Revert "soc/intel/jasperlake: Disable PAVP UPD"
by Nico Huber (Code Review) 08 Oct '20

08 Oct '20

Hello Benjamin Doron, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46044 to review the following change. Change subject: Revert "soc/intel/jasperlake: Disable PAVP UPD" ...................................................................... Revert "soc/intel/jasperlake: Disable PAVP UPD" This reverts commit 69589294c205b616e80cafbbfb0b33e105a75386. No reason was given why this should deviate from the other platforms and the author can't explain it. Change-Id: I2e8d6f9bd4ebba69b6f7cdd9a1c5d08aaf2e798f Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/soc/intel/jasperlake/fsp_params.c 1 file changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/46044/1 diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c index cdd088e..d2e07e9 100644 --- a/src/soc/intel/jasperlake/fsp_params.c +++ b/src/soc/intel/jasperlake/fsp_params.c @@ -207,9 +207,6 @@ params->XdciEnable = 0; } - /* Disable Pavp */ - params->PavpEnable = 0; - /* Provide correct UART number for FSP debug logs */ params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE; -- To view, visit https://review.coreboot.org/c/coreboot/+/46044 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e8d6f9bd4ebba69b6f7cdd9a1c5d08aaf2e798f Gerrit-Change-Number: 46044 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/i2c: Add chip driver for GPIO based I2C multiplexer
by Tim Wawrzynczak (Code Review) 08 Oct '20

08 Oct '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45911 ) Change subject: drivers/i2c: Add chip driver for GPIO based I2C multiplexer ...................................................................... Patch Set 6: (1 comment) https://review.coreboot.org/c/coreboot/+/45911/6//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/45911/6//COMMIT_MSG@48 PS6, Line 48: Package (0x02) : { : "mux-gpios", : Package (0x04) : { : \_SB.PCI0.I2C3.MUX0, : Zero, : Zero, : Zero : } : } : } Where is this used? -- To view, visit https://review.coreboot.org/c/coreboot/+/45911 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib371108cc6043c133681066bf7bf4b2e00771e8b Gerrit-Change-Number: 45911 Gerrit-PatchSet: 6 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 08 Oct 2020 18:35:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit October 2020