coreboot-gerrit October 2020

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Change in coreboot[master]: soc/intel/xeon_sp/cpx: Add save_dimm_info for SMBIOS type 17
by Angel Pons (Code Review) 08 Oct '20

08 Oct '20

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45798 ) Change subject: soc/intel/xeon_sp/cpx: Add save_dimm_info for SMBIOS type 17 ...................................................................... soc/intel/xeon_sp/cpx: Add save_dimm_info for SMBIOS type 17 For now only implement for one socket and some of the fields are hard-coded for DDR4 including memory device type, data width and ECC support. Change-Id: I3cb72d18027d972140828970206834ff55b72022 Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45798 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang(a)fb.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/xeon_sp/cpx/Makefile.inc A src/soc/intel/xeon_sp/cpx/ddr.c A src/soc/intel/xeon_sp/cpx/include/soc/ddr.h M src/soc/intel/xeon_sp/cpx/romstage.c M src/soc/intel/xeon_sp/include/soc/romstage.h M src/soc/intel/xeon_sp/romstage.c 6 files changed, 229 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Jonathan Zhang: Looks good to me, but someone else must approve diff --git a/src/soc/intel/xeon_sp/cpx/Makefile.inc b/src/soc/intel/xeon_sp/cpx/Makefile.inc index b1fcd04..79a83b5 100644 --- a/src/soc/intel/xeon_sp/cpx/Makefile.inc +++ b/src/soc/intel/xeon_sp/cpx/Makefile.inc @@ -8,7 +8,7 @@ subdirs-y += ../../../../cpu/x86/tsc subdirs-y += ../../../../cpu/intel/microcode -romstage-y += romstage.c +romstage-y += romstage.c ddr.c romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c diff --git a/src/soc/intel/xeon_sp/cpx/ddr.c b/src/soc/intel/xeon_sp/cpx/ddr.c new file mode 100644 index 0000000..0fa36ab --- /dev/null +++ b/src/soc/intel/xeon_sp/cpx/ddr.c @@ -0,0 +1,84 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <soc/ddr.h> + +uint32_t get_ddr_voltage(uint8_t DdrVoltage) +{ + /* SPD Byte 11: Module Nominal Voltage, currently DDR4 only supports 1.2V. + Either Bit 0 or Bit 1 is set, return 1.2V */ + if (DdrVoltage & 0x3) + return 1200; + return 0; +} + +uint16_t get_max_memory_speed(uint32_t commonTck) +{ + if (commonTck <= DDR_8400_TCK_MIN) + return 8400; + else if (commonTck <= DDR_6400_TCK_MIN) + return 6400; + else if (commonTck <= DDR_6000_TCK_MIN) + return 6000; + else if (commonTck <= DDR_5600_TCK_MIN) + return 5600; + else if (commonTck <= DDR_5200_TCK_MIN) + return 5200; + else if (commonTck <= DDR_4800_TCK_MIN) + return 4800; + else if (commonTck <= DDR_4400_TCK_MIN) + return 4400; + else if (commonTck <= DDR_4266_TCK_MIN) + return 4266; + else if (commonTck <= DDR_4200_TCK_MIN) + return 4200; + else if (commonTck <= DDR_4000_TCK_MIN) + return 4000; + else if (commonTck <= DDR_3800_TCK_MIN) + return 3800; + else if (commonTck <= DDR_3733_TCK_MIN) + return 3733; + else if (commonTck <= DDR_3600_TCK_MIN) + return 3600; + else if (commonTck <= DDR_3466_TCK_MIN) + return 3466; + else if (commonTck <= DDR_3400_TCK_MIN) + return 3400; + else if (commonTck <= DDR_3200_TCK_MIN) + return 3200; + else if (commonTck <= DDR_3000_TCK_MIN) + return 3000; + else if (commonTck <= DDR_2933_TCK_MIN) + return 2933; + else if (commonTck <= DDR_2800_TCK_MIN) + return 2800; + else if (commonTck <= DDR_2666_TCK_MIN) + return 2666; + else if (commonTck <= DDR_2600_TCK_MIN) + return 2600; + else if (commonTck <= DDR_2400_TCK_MIN) + return 2400; + else if (commonTck <= DDR_2200_TCK_MIN) + return 2200; + else if (commonTck <= DDR_2133_TCK_MIN) + return 2133; + else if (commonTck <= DDR_2000_TCK_MIN) + return 2000; + else if (commonTck <= DDR_1866_TCK_MIN) + return 1866; + else if (commonTck <= DDR_1800_TCK_MIN) + return 1800; + else if (commonTck <= DDR_1600_TCK_MIN) + return 1600; + else if (commonTck <= DDR_1400_TCK_MIN) + return 1400; + else if (commonTck <= DDR_1333_TCK_MIN) + return 1333; + else if (commonTck <= DDR_1200_TCK_MIN) + return 1200; + else if (commonTck <= DDR_1066_TCK_MIN) + return 1066; + else if (commonTck <= DDR_1000_TCK_MIN) + return 1000; + else + return 800; +} diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/ddr.h b/src/soc/intel/xeon_sp/cpx/include/soc/ddr.h new file mode 100644 index 0000000..61a5ebe --- /dev/null +++ b/src/soc/intel/xeon_sp/cpx/include/soc/ddr.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef _CPX_DDR_H_ +#define _CPX_DDR_H_ + +#include <stdint.h> + +/* DDR_*_TCK_MIN are in picoseconds */ +#define DDR_800_TCK_MIN 2500 +#define DDR_1000_TCK_MIN 2000 +#define DDR_1066_TCK_MIN 1875 +#define DDR_1200_TCK_MIN 1667 +#define DDR_1333_TCK_MIN 1500 +#define DDR_1400_TCK_MIN 1429 +#define DDR_1600_TCK_MIN 1250 +#define DDR_1800_TCK_MIN 1110 +#define DDR_1866_TCK_MIN 1071 +#define DDR_2000_TCK_MIN 1000 +#define DDR_2133_TCK_MIN 938 +#define DDR_2200_TCK_MIN 909 +#define DDR_2400_TCK_MIN 833 +#define DDR_2600_TCK_MIN 769 +#define DDR_2666_TCK_MIN 750 +#define DDR_2800_TCK_MIN 714 +#define DDR_2933_TCK_MIN 682 +#define DDR_3000_TCK_MIN 667 +#define DDR_3200_TCK_MIN 625 +#define DDR_3400_TCK_MIN 589 +#define DDR_3466_TCK_MIN 577 +#define DDR_3600_TCK_MIN 556 +#define DDR_3733_TCK_MIN 536 +#define DDR_3800_TCK_MIN 527 +#define DDR_4000_TCK_MIN 500 +#define DDR_4200_TCK_MIN 477 +#define DDR_4266_TCK_MIN 469 +#define DDR_4400_TCK_MIN 455 +#define DDR_4800_TCK_MIN 417 +#define DDR_5200_TCK_MIN 385 +#define DDR_5600_TCK_MIN 358 +#define DDR_6000_TCK_MIN 334 +#define DDR_6400_TCK_MIN 313 +#define DDR_6800_TCK_MIN 295 +#define DDR_7200_TCK_MIN 278 +#define DDR_7600_TCK_MIN 264 +#define DDR_8000_TCK_MIN 250 +#define DDR_8400_TCK_MIN 239 + +uint16_t get_max_memory_speed(uint32_t commonTck); +uint32_t get_ddr_voltage(uint8_t DdrVoltage); + +#endif /* _CPX_DDR_H_ */ diff --git a/src/soc/intel/xeon_sp/cpx/romstage.c b/src/soc/intel/xeon_sp/cpx/romstage.c index a198c99..6f47a30 100644 --- a/src/soc/intel/xeon_sp/cpx/romstage.c +++ b/src/soc/intel/xeon_sp/cpx/romstage.c @@ -1,9 +1,19 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <assert.h> #include <arch/romstage.h> +#include <console/console.h> +#include <cbmem.h> #include <fsp/api.h> +#include <fsp/util.h> +#include <hob_iiouds.h> +#include <hob_memmap.h> +#include <soc/ddr.h> #include <soc/romstage.h> #include <soc/pci_devs.h> +#include <soc/intel/common/smbios.h> +#include <string.h> + #include "chip.h" void __weak mainboard_memory_init_params(FSPM_UPD *mupd) @@ -11,6 +21,86 @@ /* Default weak implementation */ } +static const struct SystemMemoryMapHob *get_system_memory_map(void) +{ + size_t hob_size; + const uint8_t mem_hob_guid[16] = FSP_SYSTEM_MEMORYMAP_HOB_GUID; + const struct SystemMemoryMapHob **memmap_addr; + + memmap_addr = (const struct SystemMemoryMapHob **) + fsp_find_extension_hob_by_guid(mem_hob_guid, &hob_size); + /* hob_size is the size of the 8-byte address not the hob data */ + assert(memmap_addr != NULL && hob_size != 0); + /* assert the pointer to the hob is not NULL */ + assert(*memmap_addr != NULL); + + return *memmap_addr; +} + +/* Save the DIMM information for SMBIOS table 17 */ +void save_dimm_info(void) +{ + struct dimm_info *dest_dimm; + struct memory_info *mem_info; + const struct SystemMemoryMapHob *hob; + MEMMAP_DIMM_DEVICE_INFO_STRUCT src_dimm; + int dimm_max, index = 0; + uint32_t vdd_voltage; + + hob = get_system_memory_map(); + assert(hob != NULL); + + /* + * Allocate CBMEM area for DIMM information used to populate SMBIOS + * table 17 + */ + mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); + if (mem_info == NULL) { + printk(BIOS_ERR, "CBMEM entry for DIMM info missing\n"); + return; + } + memset(mem_info, 0, sizeof(*mem_info)); + dimm_max = ARRAY_SIZE(mem_info->dimm); + vdd_voltage = get_ddr_voltage(hob->DdrVoltage); + /* For now only implement for one socket and hard-coded for DDR4 */ + for (int ch = 0; ch < MAX_CH; ch++) { + for (int dimm = 0; dimm < MAX_IMC; dimm++) { + src_dimm = hob->Socket[0].ChannelInfo[ch].DimmInfo[dimm]; + if (src_dimm.Present) { + if (index >= dimm_max) { + printk(BIOS_WARNING, "Too many DIMMs info for %s.\n", + __func__); + return; + } + dest_dimm = &mem_info->dimm[index]; + dest_dimm->max_speed_mts = + get_max_memory_speed(src_dimm.commonTck); + dest_dimm->configured_speed_mts = hob->memFreq; + dimm_info_fill(dest_dimm, + src_dimm.DimmSize << 6, + 0x1a, /* hard-coded memory device type as DDR4 */ + hob->memFreq, /* replaced by configured_speed_mts */ + src_dimm.NumRanks, + ch, /* for mainboard locator string override */ + dimm, /* for mainboard locator string override */ + (const char *)&src_dimm.PartNumber[0], + sizeof(src_dimm.PartNumber), + (const uint8_t *)&src_dimm.serialNumber[0], + 64, /* hard-coded for DDR4 data width */ + vdd_voltage, + true, /* hard-coded as ECC supported */ + src_dimm.VendorID, + src_dimm.actKeyByte2); + index++; + } + } + } + + /* Save available DIMM information */ + mem_info->dimm_cnt = index; + printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt); +} + void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { FSPM_CONFIG *m_cfg = &mupd->FspmConfig; diff --git a/src/soc/intel/xeon_sp/include/soc/romstage.h b/src/soc/intel/xeon_sp/include/soc/romstage.h index aa46067..90689af 100644 --- a/src/soc/intel/xeon_sp/include/soc/romstage.h +++ b/src/soc/intel/xeon_sp/include/soc/romstage.h @@ -8,5 +8,5 @@ /* These functions are weak and can be overridden by a mainboard functions. */ void mainboard_memory_init_params(FSPM_UPD * mupd); void mainboard_rtc_failed(void); - +void save_dimm_info(void); #endif /* _SOC_ROMSTAGE_H_ */ diff --git a/src/soc/intel/xeon_sp/romstage.c b/src/soc/intel/xeon_sp/romstage.c index a4853c0..f3e32fd 100644 --- a/src/soc/intel/xeon_sp/romstage.c +++ b/src/soc/intel/xeon_sp/romstage.c @@ -41,7 +41,7 @@ /* Cache the memory-mapped boot media. */ postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); - + save_dimm_info(); run_postcar_phase(&pcf); } @@ -54,3 +54,4 @@ { } +__weak void save_dimm_info(void) { } -- To view, visit https://review.coreboot.org/c/coreboot/+/45798 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3cb72d18027d972140828970206834ff55b72022 Gerrit-Change-Number: 45798 Gerrit-PatchSet: 12 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: John Looney <john.looney(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: vc/intel/fsp/fsp2_0/cpx_sp: Expose DIMM Present and DdrVoltage fields
by Angel Pons (Code Review) 08 Oct '20

08 Oct '20

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45797 ) Change subject: vc/intel/fsp/fsp2_0/cpx_sp: Expose DIMM Present and DdrVoltage fields ...................................................................... vc/intel/fsp/fsp2_0/cpx_sp: Expose DIMM Present and DdrVoltage fields The fields from SystemMemoryMapHob can be used to generate SMBIOS type 17. Tested=On OCP Delta Lake, verify the values are expected. Change-Id: I988e7341ddd3b701c698b41451a87890f21cc928 Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45797 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h 1 file changed, 9 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h index 7baa11a..dc870f1 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h @@ -89,7 +89,8 @@ } SYSTEM_MEMORY_MAP_ELEMENT; typedef struct DimmDevice { - UINT8 reserved1[2]; + UINT8 Present; + UINT8 reserved1[1]; UINT8 DcpmmPresent; UINT8 reserved2[1]; UINT8 NumRanks; @@ -139,22 +140,24 @@ UINT32 memSize; // Total physical memory size UINT16 memFreq; // Mem Frequency - UINT8 reserved2[61]; + UINT8 reserved2[22]; + UINT8 DdrVoltage; + UINT8 reserved3[38]; UINT8 NumChPerMC; UINT8 numberEntries; // Number of Memory Map Elements SYSTEM_MEMORY_MAP_ELEMENT Element[(MAX_SOCKET * MAX_DRAM_CLUSTERS * MAX_SAD_RULES) + MAX_FPGA_REMOTE_SAD_RULES]; - UINT8 reserved3[2213]; + UINT8 reserved4[2213]; MEMMAP_SOCKET Socket[MAX_SOCKET]; - UINT8 reserved4[1603]; + UINT8 reserved5[1603]; UINT16 BiosFisVersion; // Firmware Interface Specification version currently supported by BIOS - UINT8 reserved5[24]; + UINT8 reserved6[24]; UINT32 MmiohBase; // MMIOH base in 64MB granularity - UINT8 reserved6[5]; + UINT8 reserved7[5]; } SYSTEM_MEMORY_MAP_HOB; -- To view, visit https://review.coreboot.org/c/coreboot/+/45797 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I988e7341ddd3b701c698b41451a87890f21cc928 Gerrit-Change-Number: 45797 Gerrit-PatchSet: 9 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Isaac W Oram <isaac.w.oram(a)intel.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/xeon_sp/cpx: Prevent acpi to write invalid drhd
by Christian Walter (Code Review) 08 Oct '20

08 Oct '20

Christian Walter has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45950 ) Change subject: soc/intel/xeon_sp/cpx: Prevent acpi to write invalid drhd ...................................................................... soc/intel/xeon_sp/cpx: Prevent acpi to write invalid drhd This is only meant as a workaround until I found the core reason. Currently on CPX one acpi drhd entry will be written with reg_base equals zero. Tested on: OCP Deltalake Change-Id: Ib892aa68e8ebe78b2e917c93d73c18f98ac87c5f Signed-off-by: Christian Walter <christian.walter(a)9elements.com> --- M src/soc/intel/xeon_sp/cpx/acpi.c 1 file changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/45950/1 diff --git a/src/soc/intel/xeon_sp/cpx/acpi.c b/src/soc/intel/xeon_sp/cpx/acpi.c index cd497c5..df70ddf 100644 --- a/src/soc/intel/xeon_sp/cpx/acpi.c +++ b/src/soc/intel/xeon_sp/cpx/acpi.c @@ -665,12 +665,14 @@ printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, " "Register Base Address: 0x%x\n", DRHD_INCLUDE_PCI_ALL, pcie_seg, reg_base); - current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, + if (reg_base != 0) + current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, pcie_seg, reg_base); } else { printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, " "Register Base Address: 0x%x\n", 0, pcie_seg, reg_base); - current += acpi_create_dmar_drhd(current, 0, pcie_seg, reg_base); + if (reg_base != 0) + current += acpi_create_dmar_drhd(current, 0, pcie_seg, reg_base); } // Add PCH IOAPIC -- To view, visit https://review.coreboot.org/c/coreboot/+/45950 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib892aa68e8ebe78b2e917c93d73c18f98ac87c5f Gerrit-Change-Number: 45950 Gerrit-PatchSet: 1 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/xeon_sp/cpx: corrrect GSI bases for IO APICs
by Jonathan Zhang (Code Review) 08 Oct '20

08 Oct '20

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45941 ) Change subject: soc/intel/xeon_sp/cpx: corrrect GSI bases for IO APICs ...................................................................... soc/intel/xeon_sp/cpx: corrrect GSI bases for IO APICs With CPX-SP FSP, PCH IOAPIC handles the first 120(0x78) GSIs. Correct the coreboot assignment of GSIs for IO APICs. Without this patch, there are following target OS boot messages: [ 1.098771] IOAPIC[0]: apic_id 8, version 32, address 0xfec00000, GSI 0-119 [ 1.099159] GSI range [24-31] for new IOAPIC conflicts with GSI[0-119] After this patch, the boot messages are: [ 0.399498] IOAPIC[0]: apic_id 8, version 32, address 0xfec00000, GSI 0-119 [ 0.399848] IOAPIC[1]: apic_id 9, version 32, address 0xfec01000, GSI 120-127 Also without this patch, there is boot stability issue. About one in 20 reboots, the target OS fails to boot with following failure: [ 4.325795] mce: [Hardware Error]: Machine check events logged [ 4.326597] mce: [Hardware Error]: CPU 0: Machine Check: 0 Bank 9: ee2000000003110a [ 4.327594] mce: [Hardware Error]: TSC 0 ADDR fe9e0000 MISC 228aa040101086 [ 4.328596] mce: [Hardware Error]: PROCESSOR 0:5065b TIME 1601443875 SOCKET 0 APIC 0 microcode 700001d The MCE error happens in bank 9. The Model specific error code shows it is about SAD_ERR_WB_TO_MMIO error (doc 604926), which means something goes wrong when cache write back to mmio. It is a generic transaction type error in level 2. Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Change-Id: I45e941591300dad6d583a6dcb41f45e984753c07 --- M src/soc/intel/xeon_sp/cpx/acpi.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/45941/1 diff --git a/src/soc/intel/xeon_sp/cpx/acpi.c b/src/soc/intel/xeon_sp/cpx/acpi.c index cd497c5..a66550e 100644 --- a/src/soc/intel/xeon_sp/cpx/acpi.c +++ b/src/soc/intel/xeon_sp/cpx/acpi.c @@ -187,7 +187,7 @@ int cur_index; struct iiostack_resource stack_info = {0}; - int gsi_bases[] = { 0, 0x18, 0x20, 0x28, 0x30, 0x48, 0x50, 0x58, 0x60 }; + int gsi_bases[] = { 0, 0x78, 0x80, 0x28, 0x88, 0x90, 0x98, 0xA0, 0xA8, 0xB0 }; int ioapic_ids[] = { 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0x10, 0x11, 0x12 }; /* Local APICs */ -- To view, visit https://review.coreboot.org/c/coreboot/+/45941 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45e941591300dad6d583a6dcb41f45e984753c07 Gerrit-Change-Number: 45941 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: vc/intel/fsp/fsp2_0/CPX-SP: update to Intel ww40 release
by Jonathan Zhang (Code Review) 08 Oct '20

08 Oct '20

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45940 ) Change subject: vc/intel/fsp/fsp2_0/CPX-SP: update to Intel ww40 release ...................................................................... vc/intel/fsp/fsp2_0/CPX-SP: update to Intel ww40 release Intel CPX-SP FSP ww40 release adds MeUmaEnable FSP-M parameter, and adds some fields to HOBs. Update FspmUpd.h and HOB header files. Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Change-Id: I3d456be62a5feecdac267c1e8be52e2a25e8aac3 --- M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h 3 files changed, 21 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/45940/1 diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h index 6bd0bc8..37ff1bd 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h @@ -700,19 +700,32 @@ **/ UINT8 PchDciEn; -/** Offset 0x014D - SerialIoUartDebugEnable +/** Offset 0x014D - MeUmaEnable + Enable or disable ME UMA feature +**/ + UINT8 MeUmaEnable; + +/** Offset 0x014E - SerialIoUartDebugEnable Enable SerialIo Uart debug library in FSP. 0:Disable, 1:Enable **/ UINT8 SerialIoUartDebugEnable; -/** Offset 0x014E - ISA Serial Base selection +/** Offset 0x014F +**/ + UINT8 UnusedUpdSpace2; + +/** Offset 0x0150 - ISA Serial Base selection Select ISA Serial Base address could be initialized by boot loader. Default is 0x3F8 0x3F8, 0x2F8 **/ UINT16 SerialIoUartDebugIoBase; -/** Offset 0x0150 +/** Offset 0x0152 +**/ + UINT8 UnusedUpdSpace3[2]; + +/** Offset 0x0154 **/ UINT8 ReservedMemoryInitUpd[16]; } FSPM_CONFIG; @@ -733,9 +746,9 @@ **/ FSPM_CONFIG FspmConfig; -/** Offset 0x0160 +/** Offset 0x0164 **/ - UINT8 UnusedUpdSpace2[6]; + UINT8 UnusedUpdSpace4[2]; /** Offset 0x0166 **/ diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h index db39c3b..9900a12 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h @@ -209,6 +209,7 @@ uint64_t PciResourceMem64Base; uint64_t PciResourceMem64Limit; uint32_t VtdBarAddress; + uint32_t Mmio32MinSize; // Minimum required size of MMIO32 resource needed for this stack } STACK_RES; typedef struct { diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h index 1229f1b..7baa11a 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h @@ -124,7 +124,7 @@ }; typedef struct socket { - UINT8 reserved1[1110]; + UINT8 reserved1[1114]; struct ChannelDevice ChannelInfo[MAX_CH]; } MEMMAP_SOCKET; @@ -154,7 +154,7 @@ UINT32 MmiohBase; // MMIOH base in 64MB granularity - UINT8 reserved6[4]; + UINT8 reserved6[5]; } SYSTEM_MEMORY_MAP_HOB; -- To view, visit https://review.coreboot.org/c/coreboot/+/45940 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d456be62a5feecdac267c1e8be52e2a25e8aac3 Gerrit-Change-Number: 45940 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek: Add function to raise the CPU frequency of MT8192
by CK HU (Code Review) 08 Oct '20

08 Oct '20

Hello Weiyi Lu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45401 to review the following change. Change subject: soc/mediatek: Add function to raise the CPU frequency of MT8192 ...................................................................... soc/mediatek: Add function to raise the CPU frequency of MT8192 Rename all mt_pll_raise_ca53_freq() into mt_pll_raise_little_cpu_freq(). Implement mt_pll_raise_little_cpu_freq() in MT8192. Signed-off-by: Weiyi Lu <weiyi.lu(a)mediatek.com> Change-Id: I97d9a61f39f2eb27f0c6f911a9199bf0eaae4fbe --- M src/mainboard/google/kukui/romstage.c M src/mainboard/google/oak/romstage.c M src/soc/mediatek/common/include/soc/pll_common.h M src/soc/mediatek/mt8173/pll.c M src/soc/mediatek/mt8183/pll.c M src/soc/mediatek/mt8192/include/soc/pll.h M src/soc/mediatek/mt8192/pll.c 7 files changed, 32 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/45401/1 diff --git a/src/mainboard/google/kukui/romstage.c b/src/mainboard/google/kukui/romstage.c index 1a2127d..b9c0d2c 100644 --- a/src/mainboard/google/kukui/romstage.c +++ b/src/mainboard/google/kukui/romstage.c @@ -57,7 +57,7 @@ mt6358_init(); /* Adjust VSIM2 down to 2.7V because it is shared with IT6505. */ pmic_set_vsim2_cali(2700); - mt_pll_raise_ca53_freq(1989 * MHz); + mt_pll_raise_little_cpu_freq(1989 * MHz); pmic_init_scp_voltage(); rtc_boot(); mt_mem_init(&dparam_ops); diff --git a/src/mainboard/google/oak/romstage.c b/src/mainboard/google/oak/romstage.c index e1d3747..2d62980 100644 --- a/src/mainboard/google/oak/romstage.c +++ b/src/mainboard/google/oak/romstage.c @@ -28,9 +28,9 @@ /* Set to maximum frequency */ if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT < 5) - mt_pll_raise_ca53_freq(1600 * MHz); + mt_pll_raise_little_cpu_freq(1600 * MHz); else - mt_pll_raise_ca53_freq(1700 * MHz); + mt_pll_raise_little_cpu_freq(1700 * MHz); mtk_mmu_after_dram(); } diff --git a/src/soc/mediatek/common/include/soc/pll_common.h b/src/soc/mediatek/common/include/soc/pll_common.h index a1bd96d..0f8732f 100644 --- a/src/soc/mediatek/common/include/soc/pll_common.h +++ b/src/soc/mediatek/common/include/soc/pll_common.h @@ -58,6 +58,6 @@ void mux_set_sel(const struct mux *mux, u32 sel); int pll_set_rate(const struct pll *pll, u32 rate); void mt_pll_init(void); -void mt_pll_raise_ca53_freq(u32 freq); +void mt_pll_raise_little_cpu_freq(u32 freq); #endif diff --git a/src/soc/mediatek/mt8173/pll.c b/src/soc/mediatek/mt8173/pll.c index 0fe94cf..7133fde 100644 --- a/src/soc/mediatek/mt8173/pll.c +++ b/src/soc/mediatek/mt8173/pll.c @@ -417,7 +417,7 @@ } } -void mt_pll_raise_ca53_freq(u32 freq) +void mt_pll_raise_little_cpu_freq(u32 freq) { pll_set_rate(&plls[APMIXED_ARMCA7PLL], freq); /* freq in Hz */ } diff --git a/src/soc/mediatek/mt8183/pll.c b/src/soc/mediatek/mt8183/pll.c index 4570269..0e96f4c 100644 --- a/src/soc/mediatek/mt8183/pll.c +++ b/src/soc/mediatek/mt8183/pll.c @@ -362,7 +362,7 @@ setbits32(&mt8183_infracfg->module_sw_cg_2_clr, 1 << 4); } -void mt_pll_raise_ca53_freq(u32 freq) +void mt_pll_raise_little_cpu_freq(u32 freq) { /* enable [4] intermediate clock armpll_divider_pll1_ck */ setbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 4); diff --git a/src/soc/mediatek/mt8192/include/soc/pll.h b/src/soc/mediatek/mt8192/include/soc/pll.h index c83436e..177bd33 100644 --- a/src/soc/mediatek/mt8192/include/soc/pll.h +++ b/src/soc/mediatek/mt8192/include/soc/pll.h @@ -253,6 +253,7 @@ MCU_MUX_MASK = 0x3 << 9, MCU_MUX_SRC_PLL = 0x1 << 9, + MCU_MUX_SRC_DIV_PLL1 = 0x2 << 9, }; enum { diff --git a/src/soc/mediatek/mt8192/pll.c b/src/soc/mediatek/mt8192/pll.c index 40d92fd..e8849df 100644 --- a/src/soc/mediatek/mt8192/pll.c +++ b/src/soc/mediatek/mt8192/pll.c @@ -434,3 +434,28 @@ /* enable [14] dramc_pll104m_ck */ setbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 14); } + +void mt_pll_raise_little_cpu_freq(u32 freq) +{ + /* enable [4] intermediate clock armpll_divider_pll1_ck */ + setbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 4); + + /* switch ca55 clock source to intermediate clock */ + clrsetbits32(&mt8192_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_DIV_PLL1); + + /* disable armpll_ll frequency output */ + clrbits32(plls[APMIXED_ARMPLL_LL].reg, PLL_EN); + + /* raise armpll_ll frequency */ + pll_set_rate(&plls[APMIXED_ARMPLL_LL], freq); + + /* enable armpll_ll frequency output */ + setbits32(plls[APMIXED_ARMPLL_LL].reg, PLL_EN); + udelay(PLL_EN_DELAY); + + /* switch ca55 clock source back to armpll_ll */ + clrsetbits32(&mt8192_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL); + + /* disable [4] intermediate clock armpll_divider_pll1_ck */ + clrbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 4); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/45401 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97d9a61f39f2eb27f0c6f911a9199bf0eaae4fbe Gerrit-Change-Number: 45401 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Weiyi Lu <weiyi.lu(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/ocp/deltalake: Update SMBIOS type 9 information
by Angel Pons (Code Review) 08 Oct '20

08 Oct '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46125 ) Change subject: mb/ocp/deltalake: Update SMBIOS type 9 information ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/46125 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3fc03a14ff7dc43d6ddf5aa36710c99dbc648afa Gerrit-Change-Number: 46125 Gerrit-PatchSet: 2 Gerrit-Owner: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Comment-Date: Thu, 08 Oct 2020 08:02:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: lynxpoint/broadwell: Relegate IOBP printk to BIOS_SPEW
by Angel Pons (Code Review) 08 Oct '20

08 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45720 ) Change subject: lynxpoint/broadwell: Relegate IOBP printk to BIOS_SPEW ...................................................................... lynxpoint/broadwell: Relegate IOBP printk to BIOS_SPEW There's no need to make so much noise when writing IOBP registers. Change-Id: I1fbb6e409375240544b9b5e810523f9471435f2f Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/iobp.c M src/southbridge/intel/lynxpoint/iobp.c 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/45720/1 diff --git a/src/soc/intel/broadwell/iobp.c b/src/soc/intel/broadwell/iobp.c index ffa61fb..deb4156 100644 --- a/src/soc/intel/broadwell/iobp.c +++ b/src/soc/intel/broadwell/iobp.c @@ -96,7 +96,7 @@ return; } - printk(BIOS_INFO, "IOBP: set 0x%08x to 0x%08x\n", address, data); + printk(BIOS_SPEW, "IOBP: set 0x%08x to 0x%08x\n", address, data); } void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) diff --git a/src/southbridge/intel/lynxpoint/iobp.c b/src/southbridge/intel/lynxpoint/iobp.c index 3df6940..ad2527f 100644 --- a/src/southbridge/intel/lynxpoint/iobp.c +++ b/src/southbridge/intel/lynxpoint/iobp.c @@ -96,7 +96,7 @@ return; } - printk(BIOS_INFO, "IOBP: set 0x%08x to 0x%08x\n", address, data); + printk(BIOS_SPEW, "IOBP: set 0x%08x to 0x%08x\n", address, data); } void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) -- To view, visit https://review.coreboot.org/c/coreboot/+/45720 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fbb6e409375240544b9b5e810523f9471435f2f Gerrit-Change-Number: 45720 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/lynxpoint/acpi/serialio.asl: Enable DMA channels
by Angel Pons (Code Review) 08 Oct '20

08 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45719 ) Change subject: sb/intel/lynxpoint/acpi/serialio.asl: Enable DMA channels ...................................................................... sb/intel/lynxpoint/acpi/serialio.asl: Enable DMA channels Broadwell does this, so do it on Lynx Point too. Change-Id: I309f0cbf93e3f75b20cdd049d9437841ef61c03a Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/acpi/serialio.asl 1 file changed, 8 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/45719/1 diff --git a/src/southbridge/intel/lynxpoint/acpi/serialio.asl b/src/southbridge/intel/lynxpoint/acpi/serialio.asl index 7acd30d..8956563 100644 --- a/src/southbridge/intel/lynxpoint/acpi/serialio.asl +++ b/src/southbridge/intel/lynxpoint/acpi/serialio.asl @@ -162,9 +162,8 @@ // DMA channels are only used if Serial IO DMA controller is enabled Name (DBUF, ResourceTemplate () { - // TODO: Need to update IASL to support FixedDMA - //FixedDMA (0x18, 4, Width32Bit, DMA1) // Tx - //FixedDMA (0x19, 5, Width32Bit, DMA2) // Rx + FixedDMA (0x18, 4, Width32Bit, DMA1) // Tx + FixedDMA (0x19, 5, Width32Bit, DMA2) // Rx }) Method (_CRS, 0, NotSerialized) @@ -243,9 +242,8 @@ // DMA channels are only used if Serial IO DMA controller is enabled Name (DBUF, ResourceTemplate () { - // TODO: Need to update IASL to support FixedDMA - //FixedDMA (0x1A, 6, Width32Bit, DMA1) // Tx - //FixedDMA (0x1B, 7, Width32Bit, DMA2) // Rx + FixedDMA (0x1A, 6, Width32Bit, DMA1) // Tx + FixedDMA (0x1B, 7, Width32Bit, DMA2) // Rx }) Method (_CRS, 0, NotSerialized) @@ -358,9 +356,8 @@ // DMA channels are only used if Serial IO DMA controller is enabled Name (DBUF, ResourceTemplate () { - // TODO: Need to update IASL to support FixedDMA - //FixedDMA (0x10, 0, Width32Bit, DMA1) // Tx - //FixedDMA (0x11, 1, Width32Bit, DMA2) // Rx + FixedDMA (0x10, 0, Width32Bit, DMA1) // Tx + FixedDMA (0x11, 1, Width32Bit, DMA2) // Rx }) Method (_CRS, 0, NotSerialized) @@ -408,9 +405,8 @@ // DMA channels are only used if Serial IO DMA controller is enabled Name (DBUF, ResourceTemplate () { - // TODO: Need to update IASL to support FixedDMA - //FixedDMA (0x16, 2, Width32Bit, DMA1) // Tx - //FixedDMA (0x17, 3, Width32Bit, DMA2) // Rx + FixedDMA (0x16, 2, Width32Bit, DMA1) // Tx + FixedDMA (0x17, 3, Width32Bit, DMA2) // Rx }) Method (_CRS, 0, NotSerialized) -- To view, visit https://review.coreboot.org/c/coreboot/+/45719 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I309f0cbf93e3f75b20cdd049d9437841ef61c03a Gerrit-Change-Number: 45719 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/skylake: Configure L1 substates for PCH root ports
by Angel Pons (Code Review) 08 Oct '20

08 Oct '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39538 ) Change subject: soc/intel/skylake: Configure L1 substates for PCH root ports ...................................................................... Patch Set 25: Code-Review+1 > Patch Set 25: > > > Patch Set 25: > > > > Do you think that L1 substates should be guarded by that Kconfig? > > it wouldn't hurt to add 'CONFIG(PCIEXP_L1_SUB_STATE) &&' to the front of the if statement I agree. -- To view, visit https://review.coreboot.org/c/coreboot/+/39538 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36150858485715016158595c832c142b0582ddb8 Gerrit-Change-Number: 39538 Gerrit-PatchSet: 25 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 08 Oct 2020 07:59:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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