Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45940 )
Change subject: vc/intel/fsp/fsp2_0/CPX-SP: update to Intel ww40 release ......................................................................
vc/intel/fsp/fsp2_0/CPX-SP: update to Intel ww40 release
Intel CPX-SP FSP ww40 release adds MeUmaEnable FSP-M parameter, and adds some fields to HOBs.
Update FspmUpd.h and HOB header files.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Change-Id: I3d456be62a5feecdac267c1e8be52e2a25e8aac3 --- M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h 3 files changed, 21 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/45940/1
diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h index 6bd0bc8..37ff1bd 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h @@ -700,19 +700,32 @@ **/ UINT8 PchDciEn;
-/** Offset 0x014D - SerialIoUartDebugEnable +/** Offset 0x014D - MeUmaEnable + Enable or disable ME UMA feature +**/ + UINT8 MeUmaEnable; + +/** Offset 0x014E - SerialIoUartDebugEnable Enable SerialIo Uart debug library in FSP. 0:Disable, 1:Enable **/ UINT8 SerialIoUartDebugEnable;
-/** Offset 0x014E - ISA Serial Base selection +/** Offset 0x014F +**/ + UINT8 UnusedUpdSpace2; + +/** Offset 0x0150 - ISA Serial Base selection Select ISA Serial Base address could be initialized by boot loader. Default is 0x3F8 0x3F8, 0x2F8 **/ UINT16 SerialIoUartDebugIoBase;
-/** Offset 0x0150 +/** Offset 0x0152 +**/ + UINT8 UnusedUpdSpace3[2]; + +/** Offset 0x0154 **/ UINT8 ReservedMemoryInitUpd[16]; } FSPM_CONFIG; @@ -733,9 +746,9 @@ **/ FSPM_CONFIG FspmConfig;
-/** Offset 0x0160 +/** Offset 0x0164 **/ - UINT8 UnusedUpdSpace2[6]; + UINT8 UnusedUpdSpace4[2];
/** Offset 0x0166 **/ diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h index db39c3b..9900a12 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h @@ -209,6 +209,7 @@ uint64_t PciResourceMem64Base; uint64_t PciResourceMem64Limit; uint32_t VtdBarAddress; + uint32_t Mmio32MinSize; // Minimum required size of MMIO32 resource needed for this stack } STACK_RES;
typedef struct { diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h index 1229f1b..7baa11a 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h @@ -124,7 +124,7 @@ };
typedef struct socket { - UINT8 reserved1[1110]; + UINT8 reserved1[1114]; struct ChannelDevice ChannelInfo[MAX_CH]; } MEMMAP_SOCKET;
@@ -154,7 +154,7 @@
UINT32 MmiohBase; // MMIOH base in 64MB granularity
- UINT8 reserved6[4]; + UINT8 reserved6[5];
} SYSTEM_MEMORY_MAP_HOB;
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45940 )
Change subject: vc/intel/fsp/fsp2_0/CPX-SP: update to Intel ww40 release ......................................................................
Patch Set 2: Code-Review+1
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45940 )
Change subject: vc/intel/fsp/fsp2_0/CPX-SP: update to Intel ww40 release ......................................................................
Patch Set 2: Code-Review+2
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45940 )
Change subject: vc/intel/fsp/fsp2_0/CPX-SP: update to Intel ww40 release ......................................................................
vc/intel/fsp/fsp2_0/CPX-SP: update to Intel ww40 release
Intel CPX-SP FSP ww40 release adds MeUmaEnable FSP-M parameter, and adds some fields to HOBs.
Update FspmUpd.h and HOB header files.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Change-Id: I3d456be62a5feecdac267c1e8be52e2a25e8aac3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45940 Reviewed-by: Angel Pons th3fanbus@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h 3 files changed, 21 insertions(+), 7 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h index 6bd0bc8..37ff1bd 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h @@ -700,19 +700,32 @@ **/ UINT8 PchDciEn;
-/** Offset 0x014D - SerialIoUartDebugEnable +/** Offset 0x014D - MeUmaEnable + Enable or disable ME UMA feature +**/ + UINT8 MeUmaEnable; + +/** Offset 0x014E - SerialIoUartDebugEnable Enable SerialIo Uart debug library in FSP. 0:Disable, 1:Enable **/ UINT8 SerialIoUartDebugEnable;
-/** Offset 0x014E - ISA Serial Base selection +/** Offset 0x014F +**/ + UINT8 UnusedUpdSpace2; + +/** Offset 0x0150 - ISA Serial Base selection Select ISA Serial Base address could be initialized by boot loader. Default is 0x3F8 0x3F8, 0x2F8 **/ UINT16 SerialIoUartDebugIoBase;
-/** Offset 0x0150 +/** Offset 0x0152 +**/ + UINT8 UnusedUpdSpace3[2]; + +/** Offset 0x0154 **/ UINT8 ReservedMemoryInitUpd[16]; } FSPM_CONFIG; @@ -733,9 +746,9 @@ **/ FSPM_CONFIG FspmConfig;
-/** Offset 0x0160 +/** Offset 0x0164 **/ - UINT8 UnusedUpdSpace2[6]; + UINT8 UnusedUpdSpace4[2];
/** Offset 0x0166 **/ diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h index db39c3b..9900a12 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h @@ -209,6 +209,7 @@ uint64_t PciResourceMem64Base; uint64_t PciResourceMem64Limit; uint32_t VtdBarAddress; + uint32_t Mmio32MinSize; // Minimum required size of MMIO32 resource needed for this stack } STACK_RES;
typedef struct { diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h index 1229f1b..7baa11a 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h @@ -124,7 +124,7 @@ };
typedef struct socket { - UINT8 reserved1[1110]; + UINT8 reserved1[1114]; struct ChannelDevice ChannelInfo[MAX_CH]; } MEMMAP_SOCKET;
@@ -154,7 +154,7 @@
UINT32 MmiohBase; // MMIOH base in 64MB granularity
- UINT8 reserved6[4]; + UINT8 reserved6[5];
} SYSTEM_MEMORY_MAP_HOB;
-
Angel Pons (Code Review) -
Jonathan Zhang (Code Review)