coreboot-gerrit October 2020

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Change in coreboot[master]: soc/intel: Make use of common gfx.asl
by Subrata Banik (Code Review) 08 Oct '20

08 Oct '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46088 ) Change subject: soc/intel: Make use of common gfx.asl ...................................................................... soc/intel: Make use of common gfx.asl Add gfx.asl file for all IA SOCs to allow for graphics-related ACPI devices and methods. TEST=Able to build and boot TGL platform Dump and disassemble DSDT, verify GFX0 device present as below Device (GFX0) { Name (_ADR, 0x00020000) // _ADR: Address } Change-Id: I5560e900a77872552df1064dc3b7a8148e35d682 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/alderlake/acpi/southbridge.asl M src/soc/intel/apollolake/acpi/southbridge.asl M src/soc/intel/elkhartlake/acpi/southbridge.asl M src/soc/intel/icelake/acpi/southbridge.asl M src/soc/intel/jasperlake/acpi/southbridge.asl M src/soc/intel/tigerlake/acpi/southbridge.asl 6 files changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/46088/1 diff --git a/src/soc/intel/alderlake/acpi/southbridge.asl b/src/soc/intel/alderlake/acpi/southbridge.asl index 373dca5..42f3b12 100644 --- a/src/soc/intel/alderlake/acpi/southbridge.asl +++ b/src/soc/intel/alderlake/acpi/southbridge.asl @@ -17,6 +17,9 @@ /* GPIO controller */ #include "gpio.asl" +/* GFX 00:02.0 */ +#include <soc/intel/common/block/acpi/acpi/gfx.asl> + /* ESPI 0:1f.0 */ #include <soc/intel/common/block/acpi/acpi/lpc.asl> diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl index f4d1497..4a8be47 100644 --- a/src/soc/intel/apollolake/acpi/southbridge.asl +++ b/src/soc/intel/apollolake/acpi/southbridge.asl @@ -17,6 +17,9 @@ #include "xhci.asl" +/* GFX 00:02.0 */ +#include <soc/intel/common/block/acpi/acpi/gfx.asl> + /* LPC */ #include <soc/intel/common/block/acpi/acpi/lpc.asl> diff --git a/src/soc/intel/elkhartlake/acpi/southbridge.asl b/src/soc/intel/elkhartlake/acpi/southbridge.asl index d85ddac..28705b1 100644 --- a/src/soc/intel/elkhartlake/acpi/southbridge.asl +++ b/src/soc/intel/elkhartlake/acpi/southbridge.asl @@ -14,6 +14,9 @@ /* GPIO controller */ #include "gpio.asl" +/* GFX 00:02.0 */ +#include <soc/intel/common/block/acpi/acpi/gfx.asl> + /* ESPI 0:1f.0 */ #include <soc/intel/common/block/acpi/acpi/lpc.asl> diff --git a/src/soc/intel/icelake/acpi/southbridge.asl b/src/soc/intel/icelake/acpi/southbridge.asl index 4abea7c..129a88d 100644 --- a/src/soc/intel/icelake/acpi/southbridge.asl +++ b/src/soc/intel/icelake/acpi/southbridge.asl @@ -17,6 +17,9 @@ /* GPIO controller */ #include "gpio.asl" +/* GFX 00:02.0 */ +#include <soc/intel/common/block/acpi/acpi/gfx.asl> + /* ESPI 0:1f.0 */ #include <soc/intel/common/block/acpi/acpi/lpc.asl> diff --git a/src/soc/intel/jasperlake/acpi/southbridge.asl b/src/soc/intel/jasperlake/acpi/southbridge.asl index b68539a..b82cce5 100644 --- a/src/soc/intel/jasperlake/acpi/southbridge.asl +++ b/src/soc/intel/jasperlake/acpi/southbridge.asl @@ -17,6 +17,9 @@ /* GPIO controller */ #include "gpio.asl" +/* GFX 00:02.0 */ +#include <soc/intel/common/block/acpi/acpi/gfx.asl> + /* ESPI 0:1f.0 */ #include <soc/intel/common/block/acpi/acpi/lpc.asl> diff --git a/src/soc/intel/tigerlake/acpi/southbridge.asl b/src/soc/intel/tigerlake/acpi/southbridge.asl index 373dca5..42f3b12 100644 --- a/src/soc/intel/tigerlake/acpi/southbridge.asl +++ b/src/soc/intel/tigerlake/acpi/southbridge.asl @@ -17,6 +17,9 @@ /* GPIO controller */ #include "gpio.asl" +/* GFX 00:02.0 */ +#include <soc/intel/common/block/acpi/acpi/gfx.asl> + /* ESPI 0:1f.0 */ #include <soc/intel/common/block/acpi/acpi/lpc.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/46088 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5560e900a77872552df1064dc3b7a8148e35d682 Gerrit-Change-Number: 46088 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/block/acpi: Factor out common gfx.asl
by Subrata Banik (Code Review) 08 Oct '20

08 Oct '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45997 ) Change subject: soc/intel/common/block/acpi: Factor out common gfx.asl ...................................................................... soc/intel/common/block/acpi: Factor out common gfx.asl This patch moves gfx.asl into common block acpi directory to avoid duplicating the same ASL code block across SoC directory. TEST=Able to build and boot CML platform. 1) Dump and disassemble DSDT, verify GFX0 device present inside common gfx.asl is still there. 2) Verify no ACPI error seen while running 'dmesg` from console. Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Change-Id: Ie34181a6783d348265cf4299dec5c41e7f4f736f --- M src/soc/intel/cannonlake/acpi/southbridge.asl R src/soc/intel/common/block/acpi/acpi/gfx.asl 2 files changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/45997/1 diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl index 0c092e1..35dc196 100644 --- a/src/soc/intel/cannonlake/acpi/southbridge.asl +++ b/src/soc/intel/cannonlake/acpi/southbridge.asl @@ -17,7 +17,7 @@ #endif /* GFX 00:02.0 */ -#include "gfx.asl" +#include <soc/intel/common/block/acpi/acpi/gfx.asl> /* LPC 0:1f.0 */ #include <soc/intel/common/block/acpi/acpi/lpc.asl> diff --git a/src/soc/intel/cannonlake/acpi/gfx.asl b/src/soc/intel/common/block/acpi/acpi/gfx.asl similarity index 100% rename from src/soc/intel/cannonlake/acpi/gfx.asl rename to src/soc/intel/common/block/acpi/acpi/gfx.asl -- To view, visit https://review.coreboot.org/c/coreboot/+/45997 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie34181a6783d348265cf4299dec5c41e7f4f736f Gerrit-Change-Number: 45997 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/ocp/deltalake: Override cache operation mode in SMBIOS type 7
by Morgan Jang (Code Review) 08 Oct '20

08 Oct '20

Morgan Jang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46116 ) Change subject: mb/ocp/deltalake: Override cache operation mode in SMBIOS type 7 ...................................................................... mb/ocp/deltalake: Override cache operation mode in SMBIOS type 7 TEST=Execute "dmidecode -t 7" to check if the cache operation mode is correct for each cache level Change-Id: I8d8d2b1c114b9c0c740841a9121d945adaea1d6c Signed-off-by: Morgan Jang <Morgan_Jang(a)wiwynn.com> --- M src/mainboard/ocp/deltalake/ramstage.c 1 file changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/46116/1 diff --git a/src/mainboard/ocp/deltalake/ramstage.c b/src/mainboard/ocp/deltalake/ramstage.c index e00f1c3..e546bd7 100644 --- a/src/mainboard/ocp/deltalake/ramstage.c +++ b/src/mainboard/ocp/deltalake/ramstage.c @@ -247,6 +247,19 @@ return 0x8c; /* BIT2 + BIT3 + BIT7 */ } +unsigned int smbios_cache_conf_operation_mode(u8 level) +{ + switch (level) { + case 1: + return SMBIOS_CACHE_OP_MODE_WRITE_BACK; + case 2: + case 3: + return SMBIOS_CACHE_OP_MODE_VARIES_WITH_MEMORY_ADDRESS; + default: + return SMBIOS_CACHE_OP_MODE_UNKNOWN; + } +} + static void mainboard_enable(struct device *dev) { dev->ops->get_smbios_strings = dl_oem_smbios_strings, -- To view, visit https://review.coreboot.org/c/coreboot/+/46116 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d8d2b1c114b9c0c740841a9121d945adaea1d6c Gerrit-Change-Number: 46116 Gerrit-PatchSet: 1 Gerrit-Owner: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: Remove xhci0_force_gen1 from soc config
by chris wang (Code Review) 08 Oct '20

08 Oct '20

Hello Chris Wang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46041 to review the following change. Change subject: soc/amd/picasso: Remove xhci0_force_gen1 from soc config ...................................................................... soc/amd/picasso: Remove xhci0_force_gen1 from soc config To remvoe the xhci0_force_gen1 and use usb3_port_force_gen1 instead. The xhci0_force_gen1 is used for force all port on xhci0 to USB3 GEN1. Now variant can use the usb3_port_force_gen1 to custmzied which port it needs to limit. BUG=b:167651308 BRANCH=zork TEST=Build, verify the USB3 speed in gen1 Signed-off-by: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Change-Id: If5f0c1f22d8c98c4461f09d074bf082c340b14d9 --- M src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb M src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb M src/soc/amd/picasso/chip.h M src/soc/amd/picasso/fsp_params.c 4 files changed, 1 insertion(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/46041/1 diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb index 4004243..0346fd2 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb @@ -44,8 +44,6 @@ .timing = SD_EMMC_EMMC_HS400, }" - register "xhci0_force_gen1" = "0" - register "has_usb2_phy_tune_params" = "1" # Controller0 Port0 Default diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb index 8d475e9..f5cdc2f 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb @@ -44,8 +44,6 @@ .timing = SD_EMMC_EMMC_HS400, }" - register "xhci0_force_gen1" = "0" - register "has_usb2_phy_tune_params" = "1" # Controller0 Port0 Default diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index 0039479..2b85f11 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -169,8 +169,7 @@ SD_EMMC_EMMC_HS300, } timing; } emmc_config; - /* set xhci0 from gen2 to gen1 */ - uint8_t xhci0_force_gen1; + /* Force USB3 port to gen1, bit0 - controller0 Port0, bit1 - Port1 */ struct usb3_port_force_gen1 usb3_port_force_gen1; diff --git a/src/soc/amd/picasso/fsp_params.c b/src/soc/amd/picasso/fsp_params.c index bacdbb0..1473d0b 100644 --- a/src/soc/amd/picasso/fsp_params.c +++ b/src/soc/amd/picasso/fsp_params.c @@ -105,7 +105,6 @@ /* each OC mapping in xhci_oc_pin_select is 4 bit per USB port */ ASSERT(2 * sizeof(scfg->xhci_oc_pin_select) >= USB_PORT_COUNT); - scfg->xhci0_force_gen1 = cfg->xhci0_force_gen1; scfg->fch_usb_3_port_force_gen1 = cfg->usb3_port_force_gen1.usb3_port_force_gen1_en; if (cfg->has_usb2_phy_tune_params) { -- To view, visit https://review.coreboot.org/c/coreboot/+/46041 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If5f0c1f22d8c98c4461f09d074bf082c340b14d9 Gerrit-Change-Number: 46041 Gerrit-PatchSet: 1 Gerrit-Owner: chris wang <Chris.Wang(a)amd.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork:Set USB3 typeA port to force gen1 for morphius
by chris wang (Code Review) 08 Oct '20

08 Oct '20

Hello Chris Wang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45334 to review the following change. Change subject: mb/google/zork:Set USB3 typeA port to force gen1 for morphius ...................................................................... mb/google/zork:Set USB3 typeA port to force gen1 for morphius In morphius, the USBA port needs to set to gen1.So set the corresponding setting to usb3 port force gen1 to force USB3 to Gen1. BUG=b:167651308 BRANCH=zork TEST=Build,verify the USB3 speed in gen1 Signed-off-by: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Change-Id: I10419b91fe86fe3e06de36ddfe0d1769c1031f8e --- M src/mainboard/google/zork/variants/morphius/overridetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/45334/1 diff --git a/src/mainboard/google/zork/variants/morphius/overridetree.cb b/src/mainboard/google/zork/variants/morphius/overridetree.cb index ceacc70..acce883 100644 --- a/src/mainboard/google/zork/variants/morphius/overridetree.cb +++ b/src/mainboard/google/zork/variants/morphius/overridetree.cb @@ -22,6 +22,9 @@ # End : OPN Performance Configuration + # Force USB3 port to gen1, bit0 - controller0 Port0, bit1 - Port1, etc + register "usb3_port_force_gen1" = "0x6" #0110b + # Enable I2C2 for trackpad, touchscreen, pen at 400kHz register "i2c[2]" = "{ .speed = I2C_SPEED_FAST, -- To view, visit https://review.coreboot.org/c/coreboot/+/45334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I10419b91fe86fe3e06de36ddfe0d1769c1031f8e Gerrit-Change-Number: 45334 Gerrit-PatchSet: 1 Gerrit-Owner: chris wang <Chris.Wang(a)amd.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: Add Upd for support force USB3 to Gen1 by port
by chris wang (Code Review) 08 Oct '20

08 Oct '20

Hello Chris Wang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45333 to review the following change. Change subject: soc/amd/picasso: Add Upd for support force USB3 to Gen1 by port ...................................................................... soc/amd/picasso: Add Upd for support force USB3 to Gen1 by port add upd usb3_port_force_gen1 for support USB3 port to gen1 BUG=b:167651308 BRANCH=zork TEST=Build,verify the USB3 speed in gen1 Signed-off-by: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Change-Id: I896c185988c3ea5dbdd72957b363ebdaa2747cff --- M src/soc/amd/picasso/chip.h M src/soc/amd/picasso/fsp_params.c 2 files changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/45333/1 diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index e3da255..9868220 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -168,7 +168,7 @@ USB_OC_PIN_5 = 0x5, USB_OC_NONE = 0xf, } usb_port_overcurrent_pin[USB_PORT_COUNT]; - + uint32_t usb3_port_force_gen1; /* The array index is the general purpose PCIe clock output number. */ enum gpp_clk_req_setting gpp_clk_config[GPP_CLK_OUTPUT_COUNT]; }; diff --git a/src/soc/amd/picasso/fsp_params.c b/src/soc/amd/picasso/fsp_params.c index b21f237..e36ebd0 100644 --- a/src/soc/amd/picasso/fsp_params.c +++ b/src/soc/amd/picasso/fsp_params.c @@ -106,6 +106,7 @@ ASSERT(2 * sizeof(scfg->xhci_oc_pin_select) >= USB_PORT_COUNT); scfg->xhci0_force_gen1 = cfg->xhci0_force_gen1; + scfg->fch_usb_3_port_force_gen1 = cfg->usb3_port_force_gen1; if (cfg->has_usb2_phy_tune_params) { for (i = 0; i < FSPS_UPD_USB2_PORT_COUNT; i++) { -- To view, visit https://review.coreboot.org/c/coreboot/+/45333 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I896c185988c3ea5dbdd72957b363ebdaa2747cff Gerrit-Change-Number: 45333 Gerrit-PatchSet: 1 Gerrit-Owner: chris wang <Chris.Wang(a)amd.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: console: change header when vboot starts before bootblock
by Kangheui Won (Code Review) 08 Oct '20

08 Oct '20

Kangheui Won has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46060 ) Change subject: console: change header when vboot starts before bootblock ...................................................................... console: change header when vboot starts before bootblock VBOOT_STARTS_VEFORE_BOOTBLOCK indicates that verstage starts before bootblock. However "cbmem -1" will first try to match "bootblock starting" to find out the beginning of console for current boot. In case "cbmem -1" cannot find "bootblock starting", it will fall back to find "verstage starting". Replace "bootblock starting" to "bootblock-after-verstage starting" in header to let cbmem utility find for "verstage starting" for beginning of console. BUG=b:159220781 TEST=flash and boot, check `cbmem -1` BRANCH=zork Signed-off-by: Kangheui Won <khwon(a)chromium.org> Change-Id: Ica38f6bfeb05605caadac208e790fd072b352732 --- M src/console/init.c 1 file changed, 13 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/46060/1 diff --git a/src/console/init.c b/src/console/init.c index 1dba9ad..adf6239 100644 --- a/src/console/init.c +++ b/src/console/init.c @@ -74,7 +74,17 @@ console_inited = 1; - printk(BIOS_NOTICE, "\n\ncoreboot-%s%s %s " ENV_STRING " starting (log level: %i)...\n", - coreboot_version, coreboot_extra_version, coreboot_build, - get_log_level()); + printk(BIOS_NOTICE, "\n\ncoreboot-%s%s %s " ENV_STRING, + coreboot_version, coreboot_extra_version, coreboot_build); + + /* + * if verstage runs before bootblock and we're in bootblock, + * append something to ENV_STRING not to be matched against + * "bootblock starting". This will let cbmem utility to + * look for "verstage starting" for start of the log. + */ + if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) && ENV_BOOTBLOCK) + printk(BIOS_NOTICE, "-after-verstage"); + + printk(BIOS_NOTICE, " starting (log level: %i)...\n", get_log_level()); } -- To view, visit https://review.coreboot.org/c/coreboot/+/46060 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica38f6bfeb05605caadac208e790fd072b352732 Gerrit-Change-Number: 46060 Gerrit-PatchSet: 1 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: Print values from PSP transfer buffer
by Martin Roth (Code Review) 08 Oct '20

08 Oct '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46113 ) Change subject: soc/amd/picasso: Print values from PSP transfer buffer ...................................................................... soc/amd/picasso: Print values from PSP transfer buffer The PSP will now pass us data on the PSP boot mode and the production silicon level. Print these values out to save in the log. These definitions are in a vendorcode include directory that was previously only included in verstage. Add the include directory to all stages. BUG=b:170237834 TEST=Build & Boot - See values printed. BRANCH=Zork Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: Iee87413d1473786cf0e148a8088d27f8d24a47a1 --- M src/soc/amd/picasso/Makefile.inc M src/soc/amd/picasso/bootblock/bootblock.c M src/soc/amd/picasso/psp_verstage/Makefile.inc 3 files changed, 24 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/46113/1 diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 1e9ba4a..b8f35b8 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -98,6 +98,7 @@ CPPFLAGS_common += -I$(src)/soc/amd/picasso/include CPPFLAGS_common += -I$(src)/soc/amd/picasso/acpi CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/picasso +CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/picasso/include MAINBOARD_BLOBS_DIR:=$(top)/3rdparty/blobs/mainboard/$(MAINBOARDDIR) diff --git a/src/soc/amd/picasso/bootblock/bootblock.c b/src/soc/amd/picasso/bootblock/bootblock.c index 1626c55..b0f76f6 100644 --- a/src/soc/amd/picasso/bootblock/bootblock.c +++ b/src/soc/amd/picasso/bootblock/bootblock.c @@ -3,6 +3,7 @@ #include <stdint.h> #include <symbols.h> #include <amdblocks/reset.h> +#include <bl_uapp/bl_syscall_public.h> #include <bootblock_common.h> #include <console/console.h> #include <cpu/x86/cache.h> @@ -136,7 +137,28 @@ cmos_write(CMOS_RECOVERY_MAGIC_VAL, CMOS_RECOVERY_BYTE); warm_reset(); } + +static void show_psp_transfer_info(void) +{ + struct transfer_info_struct *info = (struct transfer_info_struct *) + (void *)(uintptr_t)_transfer_buffer; + + if (info->magic_val == TRANSFER_MAGIC_VAL) { + if ((info->psp_info & PSP_INFO_VALID) == 0) { + printk(BIOS_INFO,"No PSP info found in transfer buffer.\n"); + return; + } + + printk(BIOS_INFO,"PSP boot mode: %s\n", + info->psp_info & PSP_INFO_PRODUCTION_MODE ? + "Production" : "Development"); + printk(BIOS_INFO,"Silicon level: %s\n", + info->psp_info & PSP_INFO_PRODUCTION_SILICON ? + "Production" : "Pre-Production"); + } +} #else +static void show_psp_transfer_info(void) {} static void verify_workbuf(void) {} #endif @@ -161,6 +183,7 @@ if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) { verify_workbuf(); + show_psp_transfer_info(); } fch_early_init(); diff --git a/src/soc/amd/picasso/psp_verstage/Makefile.inc b/src/soc/amd/picasso/psp_verstage/Makefile.inc index 4f1642b..36e8cbe 100644 --- a/src/soc/amd/picasso/psp_verstage/Makefile.inc +++ b/src/soc/amd/picasso/psp_verstage/Makefile.inc @@ -1,7 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only verstage-generic-ccopts += -I$(src)/soc/amd/picasso/psp_verstage/include -verstage-generic-ccopts += -I$(src)/vendorcode/amd/fsp/picasso/include verstage-generic-ccopts += -D__USER_SPACE__ CPPFLAGS_common += -I$(VBOOT_SOURCE)/firmware/2lib/include/ -- To view, visit https://review.coreboot.org/c/coreboot/+/46113 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee87413d1473786cf0e148a8088d27f8d24a47a1 Gerrit-Change-Number: 46113 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: Refactor workbuf check into separate function
by Martin Roth (Code Review) 08 Oct '20

08 Oct '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46112 ) Change subject: soc/amd/picasso: Refactor workbuf check into separate function ...................................................................... soc/amd/picasso: Refactor workbuf check into separate function BUG=None TEST=Build Branch=Zork Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: Idf46f8edb6b70c63f623522e2bcd2f22d6d4790b --- M src/soc/amd/picasso/bootblock/bootblock.c 1 file changed, 29 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/46112/1 diff --git a/src/soc/amd/picasso/bootblock/bootblock.c b/src/soc/amd/picasso/bootblock/bootblock.c index 316396d..1626c55 100644 --- a/src/soc/amd/picasso/bootblock/bootblock.c +++ b/src/soc/amd/picasso/bootblock/bootblock.c @@ -113,6 +113,33 @@ wrmsr(S3_RESUME_EIP_MSR, s3_resume_entry); } +#if CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) +static void verify_workbuf(void) +{ + if (*(uint32_t *)_vboot2_work == VB2_SHARED_DATA_MAGIC) { + cmos_write(0x00, CMOS_RECOVERY_BYTE); + return; + } + + /* + * If CMOS is valid and the system has already been rebooted once, but + * still returns here, instead of rebooting to verstage again, assume + * that the system is in a reboot loop and halt. + */ + if (cmos_read(RTC_CLK_ALTCENTURY) != 0xff && + cmos_read(CMOS_RECOVERY_BYTE) == CMOS_RECOVERY_MAGIC_VAL) + die("Error: Reboot into recovery was unsuccessful. Halting."); + + printk(BIOS_ERR, "ERROR: VBOOT workbuf not valid.\n"); + printk(BIOS_DEBUG, "Signature: %#08x\n", *(uint32_t *)_vboot2_work); + cmos_init(0); + cmos_write(CMOS_RECOVERY_MAGIC_VAL, CMOS_RECOVERY_BYTE); + warm_reset(); +} +#else +static void verify_workbuf(void) {} +#endif + asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { set_caching(); @@ -132,26 +159,9 @@ u32 val = cpuid_eax(1); printk(BIOS_DEBUG, "Family_Model: %08x\n", val); -#if CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) - if (*(uint32_t *)_vboot2_work != VB2_SHARED_DATA_MAGIC) { - /* - * If the system has already been rebooted once, but still returns here, - * instead of rebooting to verstage again, assume that the system is in - * a reboot loop and halt. - */ - if (cmos_read(RTC_CLK_ALTCENTURY) != 0xff && - cmos_read(CMOS_RECOVERY_BYTE) == CMOS_RECOVERY_MAGIC_VAL) - die("Error: Reboot into recovery was unsuccessful. Halting."); - - printk(BIOS_ERR, "ERROR: VBOOT workbuf not valid.\n"); - printk(BIOS_DEBUG, "Signature: %#08x\n", *(uint32_t *)_vboot2_work); - cmos_init(0); - cmos_write(CMOS_RECOVERY_MAGIC_VAL, CMOS_RECOVERY_BYTE); - warm_reset(); - } else { - cmos_write(0x00, CMOS_RECOVERY_BYTE); + if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) { + verify_workbuf(); } -#endif fch_early_init(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/46112 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf46f8edb6b70c63f623522e2bcd2f22d6d4790b Gerrit-Change-Number: 46112 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

6 11

Change in coreboot[master]: soc/amd/picasso: Die if the workbuf is missing two boots in a row
by Martin Roth (Code Review) 08 Oct '20

08 Oct '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45964 ) Change subject: soc/amd/picasso: Die if the workbuf is missing two boots in a row ...................................................................... soc/amd/picasso: Die if the workbuf is missing two boots in a row BUG=b:169199392 TEST=Corrupt vboot signature to force an error, see that the system halts instead of rebooting forever. BRANCH=Zork Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: I949f94e78d25720f6cd7e81de8d030084e267f29 --- M src/soc/amd/picasso/bootblock/bootblock.c 1 file changed, 9 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/45964/1 diff --git a/src/soc/amd/picasso/bootblock/bootblock.c b/src/soc/amd/picasso/bootblock/bootblock.c index 4700027..a8303f5 100644 --- a/src/soc/amd/picasso/bootblock/bootblock.c +++ b/src/soc/amd/picasso/bootblock/bootblock.c @@ -134,10 +134,17 @@ #if CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) if (*(uint32_t *)_vboot2_work != VB2_SHARED_DATA_MAGIC) { + /* + * If the system has already been rebooted once, but still returns here, + * instead of rebooting to verstage again, assume that the system is in + * a reboot loop, so halt instead. + */ + if ((!vbnv_cmos_failed()) && cmos_read(CMOS_RECOVERY_BYTE) == + CMOS_RECOVERY_MAGIC_VAL) + die("Error: Reboot into recovery was unsuccessful. Halting."); + printk(BIOS_ERR, "ERROR: VBOOT workbuf not valid.\n"); - printk(BIOS_DEBUG, "Signature: %#08x\n", *(uint32_t *)_vboot2_work); - cmos_init(0); cmos_write(CMOS_RECOVERY_MAGIC_VAL, CMOS_RECOVERY_BYTE); warm_reset(); -- To view, visit https://review.coreboot.org/c/coreboot/+/45964 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I949f94e78d25720f6cd7e81de8d030084e267f29 Gerrit-Change-Number: 45964 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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