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Change in coreboot[master]: mb/intel/adlrvp: Add initial ADL-P mainboard code
by Subrata Banik (Code Review) 08 Oct '20

08 Oct '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46054 ) Change subject: mb/intel/adlrvp: Add initial ADL-P mainboard code ...................................................................... mb/intel/adlrvp: Add initial ADL-P mainboard code List of changes: 1. Initial code block to select SOC_INTEL_ALDERLAKE Kconfig 2. Add minimum code to make ADL-P RVP build successfully 3. Mainly bootblock and verstage code added to reach till verstage TEST=Able to build and boot ADL-P RVP till romstage early. Change-Id: I2b551f48a4eb4d621d9a86c5d189c517d5610069 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- A src/mainboard/intel/adlrvp/Kconfig A src/mainboard/intel/adlrvp/Kconfig.name A src/mainboard/intel/adlrvp/Makefile.inc A src/mainboard/intel/adlrvp/board_info.txt A src/mainboard/intel/adlrvp/bootblock.c A src/mainboard/intel/adlrvp/chromeos.c A src/mainboard/intel/adlrvp/chromeos.fmd A src/mainboard/intel/adlrvp/dsdt.asl A src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc A src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb A src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c A src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/ec.h A src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/gpio.h A src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h 14 files changed, 470 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/46054/1 diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig new file mode 100644 index 0000000..5183886 --- /dev/null +++ b/src/mainboard/intel/adlrvp/Kconfig @@ -0,0 +1,84 @@ +if BOARD_INTEL_ADLRVP_P + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_32768 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select MAINBOARD_HAS_CHROMEOS + select DRIVERS_I2C_HID + select DRIVERS_I2C_GENERIC + select DRIVERS_INTEL_SOUNDWIRE + select DRIVERS_USB_ACPI + select DRIVERS_SPI_ACPI + select GENERATE_SMBIOS_TABLES + select SOC_INTEL_ALDERLAKE + select MAINBOARD_USES_IFD_EC_REGION + select DRIVERS_UART_8250IO + +config CHROMEOS + bool + default y + select GBB_FLAG_FORCE_DEV_SWITCH_ON + select GBB_FLAG_FORCE_DEV_BOOT_USB + select GBB_FLAG_FORCE_MANUAL_RECOVERY + +config MAINBOARD_DIR + string + default "intel/adlrvp" + +config VARIANT_DIR + string + default "adlrvp_p" + +config GBB_HWID + string + depends on CHROMEOS + default "ADLRVPP" + +config MAINBOARD_PART_NUMBER + string + default "adlrvp" + +config MAINBOARD_FAMILY + string + default "Intel_adlrvp" + +config DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + +config DIMM_SPD_SIZE + int + default 512 + +choice ADL_EC + prompt "ON BOARD EC" + default ADL_INTEL_EC + help + This option allows you to select the on board EC to use. + Select whether the board has Intel EC or Chrome EC + +config ADL_CHROME_EC + bool "Chrome EC" + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_ESPI + select EC_GOOGLE_CHROMEEC_BOARDID + select EC_ACPI + +config ADL_INTEL_EC + bool "Intel EC" + select EC_ACPI + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC +endchoice + +config VBOOT + select VBOOT_LID_SWITCH + select VBOOT_MOCK_SECDATA + select HAS_RECOVERY_MRC_CACHE + select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN + +config UART_FOR_CONSOLE + int + default 0 +endif diff --git a/src/mainboard/intel/adlrvp/Kconfig.name b/src/mainboard/intel/adlrvp/Kconfig.name new file mode 100644 index 0000000..4bf0d89 --- /dev/null +++ b/src/mainboard/intel/adlrvp/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_INTEL_ADLRVP_P + bool "Alderlake-P RVP" diff --git a/src/mainboard/intel/adlrvp/Makefile.inc b/src/mainboard/intel/adlrvp/Makefile.inc new file mode 100644 index 0000000..7422a7a --- /dev/null +++ b/src/mainboard/intel/adlrvp/Makefile.inc @@ -0,0 +1,14 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c +bootblock-$(CONFIG_CHROMEOS) += chromeos.c + +verstage-$(CONFIG_CHROMEOS) += chromeos.c + +romstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c +subdirs-y += ../common +subdirs-y += variants/baseboard +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include + +subdirs-y += variants/$(VARIANT_DIR) diff --git a/src/mainboard/intel/adlrvp/board_info.txt b/src/mainboard/intel/adlrvp/board_info.txt new file mode 100644 index 0000000..be99df8 --- /dev/null +++ b/src/mainboard/intel/adlrvp/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Intel +Board name: Alderlake rvp +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/intel/adlrvp/bootblock.c b/src/mainboard/intel/adlrvp/bootblock.c new file mode 100644 index 0000000..a8f7e41 --- /dev/null +++ b/src/mainboard/intel/adlrvp/bootblock.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <bootblock_common.h> +#include <soc/gpio.h> + +void bootblock_mainboard_init(void) +{ + const struct pad_config *pads; + size_t num; + + pads = variant_early_gpio_table(&num); + gpio_configure_pads(pads, num); +} diff --git a/src/mainboard/intel/adlrvp/chromeos.c b/src/mainboard/intel/adlrvp/chromeos.c new file mode 100644 index 0000000..d963c73 --- /dev/null +++ b/src/mainboard/intel/adlrvp/chromeos.c @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <boot/coreboot_tables.h> +#include <gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio chromeos_gpios[] = { + {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, + {-1, ACTIVE_HIGH, 0, "power"}, + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + {-1, ACTIVE_HIGH, 0, "EC in RW"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); +} + +#if !CONFIG(EC_GOOGLE_CHROMEEC_SWITCHES) +int get_lid_switch(void) +{ + /* Lid always open */ + return 1; +} + +int get_recovery_mode_switch(void) +{ + return 0; +} +#endif /*!CONFIG(EC_GOOGLE_CHROMEEC_SWITCHES) */ + +int get_write_protect_state(void) +{ + /* No write protect */ + return 0; +} + +void mainboard_chromeos_acpi_generate(void) +{ + const struct cros_gpio *gpios; + size_t num; + + gpios = variant_cros_gpios(&num); + chromeos_acpi_gpio_generate(gpios, num); +} diff --git a/src/mainboard/intel/adlrvp/chromeos.fmd b/src/mainboard/intel/adlrvp/chromeos.fmd new file mode 100644 index 0000000..183f1c1 --- /dev/null +++ b/src/mainboard/intel/adlrvp/chromeos.fmd @@ -0,0 +1,44 @@ +FLASH@0xfe000000 0x2000000 { + SI_ALL@0x0 0x1081000 { + SI_DESC@0x0 0x1000 + SI_EC@0x1000 0x80000 + SI_ME@0x81000 0x1000000 + } + SI_BIOS@0x1400000 0xc00000 { + RW_SECTION_A@0x0 0x368000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x357fc0 + RW_FWID_A@0x367fc0 0x40 + } + RW_SECTION_B@0x368000 0x368000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x357fc0 + RW_FWID_B@0x367fc0 0x40 + } + RW_MISC@0x6D0000 0x30000 { + UNIFIED_MRC_CACHE@0x0 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_ELOG(PRESERVE)@0x20000 0x4000 + RW_SHARED@0x24000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD(PRESERVE)@0x28000 0x2000 + RW_NVRAM(PRESERVE)@0x2a000 0x6000 + } + # RW_LEGACY needs to be minimum of 1MB + RW_LEGACY(CBFS)@0x700000 0x100000 + WP_RO@0x800000 0x400000 { + RO_VPD(PRESERVE)@0x0 0x4000 + RO_SECTION@0x4000 0x3fc000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0x3000 + COREBOOT(CBFS)@0x4000 0x3f8000 + } + } + } +} diff --git a/src/mainboard/intel/adlrvp/dsdt.asl b/src/mainboard/intel/adlrvp/dsdt.asl new file mode 100644 index 0000000..b758973 --- /dev/null +++ b/src/mainboard/intel/adlrvp/dsdt.asl @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <baseboard/ec.h> +#include <baseboard/gpio.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI v2.0 and up */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 /* OEM revision */ +) +{ + +} diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc b/src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc new file mode 100644 index 0000000..756de4d --- /dev/null +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c + + diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb new file mode 100644 index 0000000..16f97bf --- /dev/null +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb @@ -0,0 +1,111 @@ +chip soc/intel/alderlake + + device cpu_cluster 0 on + device lapic 0 on end + end + + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + register "gen4_dec" = "0x000c0081" + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Graphics + device pci 04.0 on end # DPTF + device pci 05.0 on end # IPU + device pci 06.0 on end # PEG60 + device pci 07.0 off end # TBT_PCIe0 + device pci 07.1 off end # TBT_PCIe1 + device pci 07.2 off end # TBT_PCIe2 + device pci 07.3 off end # TBT_PCIe3 + device pci 08.0 off end # GNA + device pci 09.0 off end # NPK + device pci 0a.0 off end # Crash-log SRAM + device pci 0d.0 on end # USB xHCI + device pci 0d.1 off end # USB xDCI (OTG) + device pci 0d.2 off end # TBT DMA0 + device pci 0d.3 off end # TBT DMA1 + device pci 0e.0 off end # VMD + device pci 10.0 off end + device pci 10.1 off end + device pci 10.2 on end # CNVi: BT + device pci 10.6 off end # THC0 + device pci 10.7 off end # THC1 + device pci 11.0 off end + device pci 11.1 off end + device pci 11.2 off end + device pci 11.3 off end + device pci 11.4 off end + device pci 11.5 off end + device pci 12.0 off end # SensorHUB + device pci 12.5 off end + device pci 12.6 off end # GSPI2 + device pci 13.0 off end # GSPI3 + device pci 13.1 off end + device pci 14.0 on + chip drivers/usb/acpi + register "desc" = ""Root Hub"" + register "type" = "UPC_TYPE_HUB" + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.9 on end + end + end + end + end # USB3.1 xHCI + device pci 14.1 off end # USB3.1 xDCI + device pci 14.2 off end # Shared RAM + chip drivers/intel/wifi + register "wake" = "GPE0_PME_B0" + device pci 14.3 on end # CNVi: WiFi + end + device pci 15.0 on end # I2C0 + device pci 15.1 on end # I2C1 + device pci 15.2 on end # I2C2 + device pci 15.3 on end # I2C3 + device pci 16.0 on end # HECI1 + device pci 16.1 off end # HECI2 + device pci 16.2 off end # CSME + device pci 16.3 off end # CSME + device pci 16.4 off end # HECI3 + device pci 16.5 off end # HECI4 + device pci 17.0 on end # SATA + device pci 19.0 off end # I2C4 + device pci 19.1 on end # I2C5 + device pci 19.2 on end # UART2 + device pci 1c.0 on end # RP1 + device pci 1c.1 on end # RP2 + device pci 1c.2 on end # RP3 + device pci 1c.3 on end # RP4 + device pci 1c.4 on end # RP5 + device pci 1c.5 on end # RP6 + device pci 1c.6 on end # RP7 + device pci 1c.7 on end # RP8 + device pci 1d.0 on end # RP9 + device pci 1d.1 on end # RP10 + device pci 1d.2 on end # RP11 + device pci 1d.3 on end # RP12 + device pci 1e.0 off end # UART0 + device pci 1e.1 off end # UART1 + device pci 1e.2 off end # GSPI0 + device pci 1e.3 off end # GSPI1 + device pci 1f.0 on end # eSPI + device pci 1f.1 on end # P2SB + device pci 1f.2 hidden end # PMC + device pci 1f.3 on + chip drivers/intel/soundwire + device generic 0 on + end + end + end # Intel Audio SNDW + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # SPI + device pci 1f.6 off end # GbE + device pci 1f.7 off end # TH + end +end diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c b/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c new file mode 100644 index 0000000..4e3ff8d --- /dev/null +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* WWAN_RST# */ + PAD_CFG_GPO(GPP_E10, 0, PLTRST), + /* WWAN_PWR_EN */ + PAD_CFG_GPO(GPP_E13, 1, DEEP), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/ec.h b/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/ec.h new file mode 100644 index 0000000..4303faf --- /dev/null +++ b/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/ec.h @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __BASEBOARD_EC_H__ +#define __BASEBOARD_EC_H__ + +#include <ec/ec.h> +#include <ec/google/chromeec/ec_commands.h> +#include <baseboard/gpio.h> + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX)) + +#define MAINBOARD_EC_SMI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) + +/* EC can wake from S5 with lid or power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) + +/* + * EC can wake from S3 with lid or power button or key press or + * mode change event. + */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) + +#define MAINBOARD_EC_S0IX_WAKE_EVENTS (MAINBOARD_EC_S3_WAKE_EVENTS) + +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) + +/* + * ACPI related definitions for ASL code. + */ + +/* Enable EC backed ALS device in ACPI */ +#define EC_ENABLE_ALS_DEVICE + +/* Enable EC sync interrupt, EC_SYNC_IRQ is defined in baseboard/gpio.h */ +#define EC_ENABLE_SYNC_IRQ + +/* Enable EC backed PD MCU device in ACPI */ +#define EC_ENABLE_PD_MCU_DEVICE + +/* Enable LID switch and provide wake pin for EC */ +#define EC_ENABLE_LID_SWITCH +#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE + +#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ +#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ +#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ + +#endif /* __BASEBOARD_EC_H__ */ diff --git a/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/gpio.h new file mode 100644 index 0000000..b61276c --- /dev/null +++ b/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/gpio.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __BASEBOARD_GPIO_H__ +#define __BASEBOARD_GPIO_H__ + +#include <soc/gpe.h> +#include <soc/gpio.h> + +/* eSPI virtual wire reporting */ +#define EC_SCI_GPI GPE0_ESPI + +/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ +#define GPE_EC_WAKE GPE0_LAN_WAK + +/* EC sync IRQ */ +#define EC_SYNC_IRQ GPP_A15_IRQ + +#endif /* __BASEBOARD_GPIO_H__ */ diff --git a/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h new file mode 100644 index 0000000..4e6001d --- /dev/null +++ b/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __BASEBOARD_VARIANTS_H__ +#define __BASEBOARD_VARIANTS_H__ + +#include <soc/gpio.h> +#include <stdint.h> +#include <vendorcode/google/chromeos/chromeos.h> + +/* The next set of functions return the gpio table and fill in the number of + * entries for each table. */ + +const struct pad_config *variant_early_gpio_table(size_t *num); +const struct cros_gpio *variant_cros_gpios(size_t *num); + +#endif /*__BASEBOARD_VARIANTS_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/46054 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b551f48a4eb4d621d9a86c5d189c517d5610069 Gerrit-Change-Number: 46054 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

3 23

Change in coreboot[master]: mb/intel/{jslrvp,tglrvp}: Remove non-existent 'subdirs-y += ../common'
by Subrata Banik (Code Review) 08 Oct '20

08 Oct '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46123 ) Change subject: mb/intel/{jslrvp,tglrvp}: Remove non-existent 'subdirs-y += ../common' ...................................................................... mb/intel/{jslrvp,tglrvp}: Remove non-existent 'subdirs-y += ../common' TEST=Able to build TGLRVP and JSLRVP. Change-Id: Ie07df9f59015092a4c2a27b1451f0d556c70f0d8 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/mainboard/intel/jasperlake_rvp/Makefile.inc M src/mainboard/intel/tglrvp/Makefile.inc 2 files changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/46123/1 diff --git a/src/mainboard/intel/jasperlake_rvp/Makefile.inc b/src/mainboard/intel/jasperlake_rvp/Makefile.inc index a1cd12c..2ac1b07 100644 --- a/src/mainboard/intel/jasperlake_rvp/Makefile.inc +++ b/src/mainboard/intel/jasperlake_rvp/Makefile.inc @@ -17,7 +17,6 @@ smm-y += smihandler.c -subdirs-y += ../common subdirs-y += variants/baseboard CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include diff --git a/src/mainboard/intel/tglrvp/Makefile.inc b/src/mainboard/intel/tglrvp/Makefile.inc index cba1909..2ca32f3 100644 --- a/src/mainboard/intel/tglrvp/Makefile.inc +++ b/src/mainboard/intel/tglrvp/Makefile.inc @@ -18,7 +18,6 @@ ramstage-y += mainboard.c ramstage-y += board_id.c -subdirs-y += ../common subdirs-y += variants/baseboard CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include -- To view, visit https://review.coreboot.org/c/coreboot/+/46123 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie07df9f59015092a4c2a27b1451f0d556c70f0d8 Gerrit-Change-Number: 46123 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: soc/intel: Make use of common gfx.asl
by Subrata Banik (Code Review) 08 Oct '20

08 Oct '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46088 ) Change subject: soc/intel: Make use of common gfx.asl ...................................................................... soc/intel: Make use of common gfx.asl Add gfx.asl file for all IA SOCs to allow for graphics-related ACPI devices and methods. TEST=Able to build and boot TGL platform Dump and disassemble DSDT, verify GFX0 device present as below Device (GFX0) { Name (_ADR, 0x00020000) // _ADR: Address } Change-Id: I5560e900a77872552df1064dc3b7a8148e35d682 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/alderlake/acpi/southbridge.asl M src/soc/intel/apollolake/acpi/southbridge.asl M src/soc/intel/elkhartlake/acpi/southbridge.asl M src/soc/intel/icelake/acpi/southbridge.asl M src/soc/intel/jasperlake/acpi/southbridge.asl M src/soc/intel/tigerlake/acpi/southbridge.asl 6 files changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/46088/1 diff --git a/src/soc/intel/alderlake/acpi/southbridge.asl b/src/soc/intel/alderlake/acpi/southbridge.asl index 373dca5..42f3b12 100644 --- a/src/soc/intel/alderlake/acpi/southbridge.asl +++ b/src/soc/intel/alderlake/acpi/southbridge.asl @@ -17,6 +17,9 @@ /* GPIO controller */ #include "gpio.asl" +/* GFX 00:02.0 */ +#include <soc/intel/common/block/acpi/acpi/gfx.asl> + /* ESPI 0:1f.0 */ #include <soc/intel/common/block/acpi/acpi/lpc.asl> diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl index f4d1497..4a8be47 100644 --- a/src/soc/intel/apollolake/acpi/southbridge.asl +++ b/src/soc/intel/apollolake/acpi/southbridge.asl @@ -17,6 +17,9 @@ #include "xhci.asl" +/* GFX 00:02.0 */ +#include <soc/intel/common/block/acpi/acpi/gfx.asl> + /* LPC */ #include <soc/intel/common/block/acpi/acpi/lpc.asl> diff --git a/src/soc/intel/elkhartlake/acpi/southbridge.asl b/src/soc/intel/elkhartlake/acpi/southbridge.asl index d85ddac..28705b1 100644 --- a/src/soc/intel/elkhartlake/acpi/southbridge.asl +++ b/src/soc/intel/elkhartlake/acpi/southbridge.asl @@ -14,6 +14,9 @@ /* GPIO controller */ #include "gpio.asl" +/* GFX 00:02.0 */ +#include <soc/intel/common/block/acpi/acpi/gfx.asl> + /* ESPI 0:1f.0 */ #include <soc/intel/common/block/acpi/acpi/lpc.asl> diff --git a/src/soc/intel/icelake/acpi/southbridge.asl b/src/soc/intel/icelake/acpi/southbridge.asl index 4abea7c..129a88d 100644 --- a/src/soc/intel/icelake/acpi/southbridge.asl +++ b/src/soc/intel/icelake/acpi/southbridge.asl @@ -17,6 +17,9 @@ /* GPIO controller */ #include "gpio.asl" +/* GFX 00:02.0 */ +#include <soc/intel/common/block/acpi/acpi/gfx.asl> + /* ESPI 0:1f.0 */ #include <soc/intel/common/block/acpi/acpi/lpc.asl> diff --git a/src/soc/intel/jasperlake/acpi/southbridge.asl b/src/soc/intel/jasperlake/acpi/southbridge.asl index b68539a..b82cce5 100644 --- a/src/soc/intel/jasperlake/acpi/southbridge.asl +++ b/src/soc/intel/jasperlake/acpi/southbridge.asl @@ -17,6 +17,9 @@ /* GPIO controller */ #include "gpio.asl" +/* GFX 00:02.0 */ +#include <soc/intel/common/block/acpi/acpi/gfx.asl> + /* ESPI 0:1f.0 */ #include <soc/intel/common/block/acpi/acpi/lpc.asl> diff --git a/src/soc/intel/tigerlake/acpi/southbridge.asl b/src/soc/intel/tigerlake/acpi/southbridge.asl index 373dca5..42f3b12 100644 --- a/src/soc/intel/tigerlake/acpi/southbridge.asl +++ b/src/soc/intel/tigerlake/acpi/southbridge.asl @@ -17,6 +17,9 @@ /* GPIO controller */ #include "gpio.asl" +/* GFX 00:02.0 */ +#include <soc/intel/common/block/acpi/acpi/gfx.asl> + /* ESPI 0:1f.0 */ #include <soc/intel/common/block/acpi/acpi/lpc.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/46088 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5560e900a77872552df1064dc3b7a8148e35d682 Gerrit-Change-Number: 46088 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: soc/intel/common/block/acpi: Factor out common gfx.asl
by Subrata Banik (Code Review) 08 Oct '20

08 Oct '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45997 ) Change subject: soc/intel/common/block/acpi: Factor out common gfx.asl ...................................................................... soc/intel/common/block/acpi: Factor out common gfx.asl This patch moves gfx.asl into common block acpi directory to avoid duplicating the same ASL code block across SoC directory. TEST=Able to build and boot CML platform. 1) Dump and disassemble DSDT, verify GFX0 device present inside common gfx.asl is still there. 2) Verify no ACPI error seen while running 'dmesg` from console. Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Change-Id: Ie34181a6783d348265cf4299dec5c41e7f4f736f --- M src/soc/intel/cannonlake/acpi/southbridge.asl R src/soc/intel/common/block/acpi/acpi/gfx.asl 2 files changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/45997/1 diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl index 0c092e1..35dc196 100644 --- a/src/soc/intel/cannonlake/acpi/southbridge.asl +++ b/src/soc/intel/cannonlake/acpi/southbridge.asl @@ -17,7 +17,7 @@ #endif /* GFX 00:02.0 */ -#include "gfx.asl" +#include <soc/intel/common/block/acpi/acpi/gfx.asl> /* LPC 0:1f.0 */ #include <soc/intel/common/block/acpi/acpi/lpc.asl> diff --git a/src/soc/intel/cannonlake/acpi/gfx.asl b/src/soc/intel/common/block/acpi/acpi/gfx.asl similarity index 100% rename from src/soc/intel/cannonlake/acpi/gfx.asl rename to src/soc/intel/common/block/acpi/acpi/gfx.asl -- To view, visit https://review.coreboot.org/c/coreboot/+/45997 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie34181a6783d348265cf4299dec5c41e7f4f736f Gerrit-Change-Number: 45997 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

3 10

Change in coreboot[master]: mb/ocp/deltalake: Override cache operation mode in SMBIOS type 7
by Morgan Jang (Code Review) 08 Oct '20

08 Oct '20

Morgan Jang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46116 ) Change subject: mb/ocp/deltalake: Override cache operation mode in SMBIOS type 7 ...................................................................... mb/ocp/deltalake: Override cache operation mode in SMBIOS type 7 TEST=Execute "dmidecode -t 7" to check if the cache operation mode is correct for each cache level Change-Id: I8d8d2b1c114b9c0c740841a9121d945adaea1d6c Signed-off-by: Morgan Jang <Morgan_Jang(a)wiwynn.com> --- M src/mainboard/ocp/deltalake/ramstage.c 1 file changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/46116/1 diff --git a/src/mainboard/ocp/deltalake/ramstage.c b/src/mainboard/ocp/deltalake/ramstage.c index e00f1c3..e546bd7 100644 --- a/src/mainboard/ocp/deltalake/ramstage.c +++ b/src/mainboard/ocp/deltalake/ramstage.c @@ -247,6 +247,19 @@ return 0x8c; /* BIT2 + BIT3 + BIT7 */ } +unsigned int smbios_cache_conf_operation_mode(u8 level) +{ + switch (level) { + case 1: + return SMBIOS_CACHE_OP_MODE_WRITE_BACK; + case 2: + case 3: + return SMBIOS_CACHE_OP_MODE_VARIES_WITH_MEMORY_ADDRESS; + default: + return SMBIOS_CACHE_OP_MODE_UNKNOWN; + } +} + static void mainboard_enable(struct device *dev) { dev->ops->get_smbios_strings = dl_oem_smbios_strings, -- To view, visit https://review.coreboot.org/c/coreboot/+/46116 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d8d2b1c114b9c0c740841a9121d945adaea1d6c Gerrit-Change-Number: 46116 Gerrit-PatchSet: 1 Gerrit-Owner: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: soc/amd/picasso: Remove xhci0_force_gen1 from soc config
by chris wang (Code Review) 08 Oct '20

08 Oct '20

Hello Chris Wang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46041 to review the following change. Change subject: soc/amd/picasso: Remove xhci0_force_gen1 from soc config ...................................................................... soc/amd/picasso: Remove xhci0_force_gen1 from soc config To remvoe the xhci0_force_gen1 and use usb3_port_force_gen1 instead. The xhci0_force_gen1 is used for force all port on xhci0 to USB3 GEN1. Now variant can use the usb3_port_force_gen1 to custmzied which port it needs to limit. BUG=b:167651308 BRANCH=zork TEST=Build, verify the USB3 speed in gen1 Signed-off-by: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Change-Id: If5f0c1f22d8c98c4461f09d074bf082c340b14d9 --- M src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb M src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb M src/soc/amd/picasso/chip.h M src/soc/amd/picasso/fsp_params.c 4 files changed, 1 insertion(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/46041/1 diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb index 4004243..0346fd2 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb @@ -44,8 +44,6 @@ .timing = SD_EMMC_EMMC_HS400, }" - register "xhci0_force_gen1" = "0" - register "has_usb2_phy_tune_params" = "1" # Controller0 Port0 Default diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb index 8d475e9..f5cdc2f 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb @@ -44,8 +44,6 @@ .timing = SD_EMMC_EMMC_HS400, }" - register "xhci0_force_gen1" = "0" - register "has_usb2_phy_tune_params" = "1" # Controller0 Port0 Default diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index 0039479..2b85f11 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -169,8 +169,7 @@ SD_EMMC_EMMC_HS300, } timing; } emmc_config; - /* set xhci0 from gen2 to gen1 */ - uint8_t xhci0_force_gen1; + /* Force USB3 port to gen1, bit0 - controller0 Port0, bit1 - Port1 */ struct usb3_port_force_gen1 usb3_port_force_gen1; diff --git a/src/soc/amd/picasso/fsp_params.c b/src/soc/amd/picasso/fsp_params.c index bacdbb0..1473d0b 100644 --- a/src/soc/amd/picasso/fsp_params.c +++ b/src/soc/amd/picasso/fsp_params.c @@ -105,7 +105,6 @@ /* each OC mapping in xhci_oc_pin_select is 4 bit per USB port */ ASSERT(2 * sizeof(scfg->xhci_oc_pin_select) >= USB_PORT_COUNT); - scfg->xhci0_force_gen1 = cfg->xhci0_force_gen1; scfg->fch_usb_3_port_force_gen1 = cfg->usb3_port_force_gen1.usb3_port_force_gen1_en; if (cfg->has_usb2_phy_tune_params) { -- To view, visit https://review.coreboot.org/c/coreboot/+/46041 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If5f0c1f22d8c98c4461f09d074bf082c340b14d9 Gerrit-Change-Number: 46041 Gerrit-PatchSet: 1 Gerrit-Owner: chris wang <Chris.Wang(a)amd.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

5 7

Change in coreboot[master]: mb/google/zork:Set USB3 typeA port to force gen1 for morphius
by chris wang (Code Review) 08 Oct '20

08 Oct '20

Hello Chris Wang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45334 to review the following change. Change subject: mb/google/zork:Set USB3 typeA port to force gen1 for morphius ...................................................................... mb/google/zork:Set USB3 typeA port to force gen1 for morphius In morphius, the USBA port needs to set to gen1.So set the corresponding setting to usb3 port force gen1 to force USB3 to Gen1. BUG=b:167651308 BRANCH=zork TEST=Build,verify the USB3 speed in gen1 Signed-off-by: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Change-Id: I10419b91fe86fe3e06de36ddfe0d1769c1031f8e --- M src/mainboard/google/zork/variants/morphius/overridetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/45334/1 diff --git a/src/mainboard/google/zork/variants/morphius/overridetree.cb b/src/mainboard/google/zork/variants/morphius/overridetree.cb index ceacc70..acce883 100644 --- a/src/mainboard/google/zork/variants/morphius/overridetree.cb +++ b/src/mainboard/google/zork/variants/morphius/overridetree.cb @@ -22,6 +22,9 @@ # End : OPN Performance Configuration + # Force USB3 port to gen1, bit0 - controller0 Port0, bit1 - Port1, etc + register "usb3_port_force_gen1" = "0x6" #0110b + # Enable I2C2 for trackpad, touchscreen, pen at 400kHz register "i2c[2]" = "{ .speed = I2C_SPEED_FAST, -- To view, visit https://review.coreboot.org/c/coreboot/+/45334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I10419b91fe86fe3e06de36ddfe0d1769c1031f8e Gerrit-Change-Number: 45334 Gerrit-PatchSet: 1 Gerrit-Owner: chris wang <Chris.Wang(a)amd.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

8 25

Change in coreboot[master]: soc/amd/picasso: Add Upd for support force USB3 to Gen1 by port
by chris wang (Code Review) 08 Oct '20

08 Oct '20

Hello Chris Wang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45333 to review the following change. Change subject: soc/amd/picasso: Add Upd for support force USB3 to Gen1 by port ...................................................................... soc/amd/picasso: Add Upd for support force USB3 to Gen1 by port add upd usb3_port_force_gen1 for support USB3 port to gen1 BUG=b:167651308 BRANCH=zork TEST=Build,verify the USB3 speed in gen1 Signed-off-by: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Change-Id: I896c185988c3ea5dbdd72957b363ebdaa2747cff --- M src/soc/amd/picasso/chip.h M src/soc/amd/picasso/fsp_params.c 2 files changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/45333/1 diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index e3da255..9868220 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -168,7 +168,7 @@ USB_OC_PIN_5 = 0x5, USB_OC_NONE = 0xf, } usb_port_overcurrent_pin[USB_PORT_COUNT]; - + uint32_t usb3_port_force_gen1; /* The array index is the general purpose PCIe clock output number. */ enum gpp_clk_req_setting gpp_clk_config[GPP_CLK_OUTPUT_COUNT]; }; diff --git a/src/soc/amd/picasso/fsp_params.c b/src/soc/amd/picasso/fsp_params.c index b21f237..e36ebd0 100644 --- a/src/soc/amd/picasso/fsp_params.c +++ b/src/soc/amd/picasso/fsp_params.c @@ -106,6 +106,7 @@ ASSERT(2 * sizeof(scfg->xhci_oc_pin_select) >= USB_PORT_COUNT); scfg->xhci0_force_gen1 = cfg->xhci0_force_gen1; + scfg->fch_usb_3_port_force_gen1 = cfg->usb3_port_force_gen1; if (cfg->has_usb2_phy_tune_params) { for (i = 0; i < FSPS_UPD_USB2_PORT_COUNT; i++) { -- To view, visit https://review.coreboot.org/c/coreboot/+/45333 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I896c185988c3ea5dbdd72957b363ebdaa2747cff Gerrit-Change-Number: 45333 Gerrit-PatchSet: 1 Gerrit-Owner: chris wang <Chris.Wang(a)amd.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: console: change header when vboot starts before bootblock
by Kangheui Won (Code Review) 08 Oct '20

08 Oct '20

Kangheui Won has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46060 ) Change subject: console: change header when vboot starts before bootblock ...................................................................... console: change header when vboot starts before bootblock VBOOT_STARTS_VEFORE_BOOTBLOCK indicates that verstage starts before bootblock. However "cbmem -1" will first try to match "bootblock starting" to find out the beginning of console for current boot. In case "cbmem -1" cannot find "bootblock starting", it will fall back to find "verstage starting". Replace "bootblock starting" to "bootblock-after-verstage starting" in header to let cbmem utility find for "verstage starting" for beginning of console. BUG=b:159220781 TEST=flash and boot, check `cbmem -1` BRANCH=zork Signed-off-by: Kangheui Won <khwon(a)chromium.org> Change-Id: Ica38f6bfeb05605caadac208e790fd072b352732 --- M src/console/init.c 1 file changed, 13 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/46060/1 diff --git a/src/console/init.c b/src/console/init.c index 1dba9ad..adf6239 100644 --- a/src/console/init.c +++ b/src/console/init.c @@ -74,7 +74,17 @@ console_inited = 1; - printk(BIOS_NOTICE, "\n\ncoreboot-%s%s %s " ENV_STRING " starting (log level: %i)...\n", - coreboot_version, coreboot_extra_version, coreboot_build, - get_log_level()); + printk(BIOS_NOTICE, "\n\ncoreboot-%s%s %s " ENV_STRING, + coreboot_version, coreboot_extra_version, coreboot_build); + + /* + * if verstage runs before bootblock and we're in bootblock, + * append something to ENV_STRING not to be matched against + * "bootblock starting". This will let cbmem utility to + * look for "verstage starting" for start of the log. + */ + if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) && ENV_BOOTBLOCK) + printk(BIOS_NOTICE, "-after-verstage"); + + printk(BIOS_NOTICE, " starting (log level: %i)...\n", get_log_level()); } -- To view, visit https://review.coreboot.org/c/coreboot/+/46060 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica38f6bfeb05605caadac208e790fd072b352732 Gerrit-Change-Number: 46060 Gerrit-PatchSet: 1 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: Print values from PSP transfer buffer
by Martin Roth (Code Review) 08 Oct '20

08 Oct '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46113 ) Change subject: soc/amd/picasso: Print values from PSP transfer buffer ...................................................................... soc/amd/picasso: Print values from PSP transfer buffer The PSP will now pass us data on the PSP boot mode and the production silicon level. Print these values out to save in the log. These definitions are in a vendorcode include directory that was previously only included in verstage. Add the include directory to all stages. BUG=b:170237834 TEST=Build & Boot - See values printed. BRANCH=Zork Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: Iee87413d1473786cf0e148a8088d27f8d24a47a1 --- M src/soc/amd/picasso/Makefile.inc M src/soc/amd/picasso/bootblock/bootblock.c M src/soc/amd/picasso/psp_verstage/Makefile.inc 3 files changed, 24 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/46113/1 diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 1e9ba4a..b8f35b8 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -98,6 +98,7 @@ CPPFLAGS_common += -I$(src)/soc/amd/picasso/include CPPFLAGS_common += -I$(src)/soc/amd/picasso/acpi CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/picasso +CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/picasso/include MAINBOARD_BLOBS_DIR:=$(top)/3rdparty/blobs/mainboard/$(MAINBOARDDIR) diff --git a/src/soc/amd/picasso/bootblock/bootblock.c b/src/soc/amd/picasso/bootblock/bootblock.c index 1626c55..b0f76f6 100644 --- a/src/soc/amd/picasso/bootblock/bootblock.c +++ b/src/soc/amd/picasso/bootblock/bootblock.c @@ -3,6 +3,7 @@ #include <stdint.h> #include <symbols.h> #include <amdblocks/reset.h> +#include <bl_uapp/bl_syscall_public.h> #include <bootblock_common.h> #include <console/console.h> #include <cpu/x86/cache.h> @@ -136,7 +137,28 @@ cmos_write(CMOS_RECOVERY_MAGIC_VAL, CMOS_RECOVERY_BYTE); warm_reset(); } + +static void show_psp_transfer_info(void) +{ + struct transfer_info_struct *info = (struct transfer_info_struct *) + (void *)(uintptr_t)_transfer_buffer; + + if (info->magic_val == TRANSFER_MAGIC_VAL) { + if ((info->psp_info & PSP_INFO_VALID) == 0) { + printk(BIOS_INFO,"No PSP info found in transfer buffer.\n"); + return; + } + + printk(BIOS_INFO,"PSP boot mode: %s\n", + info->psp_info & PSP_INFO_PRODUCTION_MODE ? + "Production" : "Development"); + printk(BIOS_INFO,"Silicon level: %s\n", + info->psp_info & PSP_INFO_PRODUCTION_SILICON ? + "Production" : "Pre-Production"); + } +} #else +static void show_psp_transfer_info(void) {} static void verify_workbuf(void) {} #endif @@ -161,6 +183,7 @@ if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) { verify_workbuf(); + show_psp_transfer_info(); } fch_early_init(); diff --git a/src/soc/amd/picasso/psp_verstage/Makefile.inc b/src/soc/amd/picasso/psp_verstage/Makefile.inc index 4f1642b..36e8cbe 100644 --- a/src/soc/amd/picasso/psp_verstage/Makefile.inc +++ b/src/soc/amd/picasso/psp_verstage/Makefile.inc @@ -1,7 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only verstage-generic-ccopts += -I$(src)/soc/amd/picasso/psp_verstage/include -verstage-generic-ccopts += -I$(src)/vendorcode/amd/fsp/picasso/include verstage-generic-ccopts += -D__USER_SPACE__ CPPFLAGS_common += -I$(VBOOT_SOURCE)/firmware/2lib/include/ -- To view, visit https://review.coreboot.org/c/coreboot/+/46113 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee87413d1473786cf0e148a8088d27f8d24a47a1 Gerrit-Change-Number: 46113 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit October 2020