coreboot-gerrit October 2020

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Change in coreboot[master]: soc/amd/picasso: Refactor workbuf check into separate function
by Martin Roth (Code Review) 08 Oct '20

08 Oct '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46112 ) Change subject: soc/amd/picasso: Refactor workbuf check into separate function ...................................................................... soc/amd/picasso: Refactor workbuf check into separate function BUG=None TEST=Build Branch=Zork Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: Idf46f8edb6b70c63f623522e2bcd2f22d6d4790b --- M src/soc/amd/picasso/bootblock/bootblock.c 1 file changed, 29 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/46112/1 diff --git a/src/soc/amd/picasso/bootblock/bootblock.c b/src/soc/amd/picasso/bootblock/bootblock.c index 316396d..1626c55 100644 --- a/src/soc/amd/picasso/bootblock/bootblock.c +++ b/src/soc/amd/picasso/bootblock/bootblock.c @@ -113,6 +113,33 @@ wrmsr(S3_RESUME_EIP_MSR, s3_resume_entry); } +#if CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) +static void verify_workbuf(void) +{ + if (*(uint32_t *)_vboot2_work == VB2_SHARED_DATA_MAGIC) { + cmos_write(0x00, CMOS_RECOVERY_BYTE); + return; + } + + /* + * If CMOS is valid and the system has already been rebooted once, but + * still returns here, instead of rebooting to verstage again, assume + * that the system is in a reboot loop and halt. + */ + if (cmos_read(RTC_CLK_ALTCENTURY) != 0xff && + cmos_read(CMOS_RECOVERY_BYTE) == CMOS_RECOVERY_MAGIC_VAL) + die("Error: Reboot into recovery was unsuccessful. Halting."); + + printk(BIOS_ERR, "ERROR: VBOOT workbuf not valid.\n"); + printk(BIOS_DEBUG, "Signature: %#08x\n", *(uint32_t *)_vboot2_work); + cmos_init(0); + cmos_write(CMOS_RECOVERY_MAGIC_VAL, CMOS_RECOVERY_BYTE); + warm_reset(); +} +#else +static void verify_workbuf(void) {} +#endif + asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { set_caching(); @@ -132,26 +159,9 @@ u32 val = cpuid_eax(1); printk(BIOS_DEBUG, "Family_Model: %08x\n", val); -#if CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) - if (*(uint32_t *)_vboot2_work != VB2_SHARED_DATA_MAGIC) { - /* - * If the system has already been rebooted once, but still returns here, - * instead of rebooting to verstage again, assume that the system is in - * a reboot loop and halt. - */ - if (cmos_read(RTC_CLK_ALTCENTURY) != 0xff && - cmos_read(CMOS_RECOVERY_BYTE) == CMOS_RECOVERY_MAGIC_VAL) - die("Error: Reboot into recovery was unsuccessful. Halting."); - - printk(BIOS_ERR, "ERROR: VBOOT workbuf not valid.\n"); - printk(BIOS_DEBUG, "Signature: %#08x\n", *(uint32_t *)_vboot2_work); - cmos_init(0); - cmos_write(CMOS_RECOVERY_MAGIC_VAL, CMOS_RECOVERY_BYTE); - warm_reset(); - } else { - cmos_write(0x00, CMOS_RECOVERY_BYTE); + if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) { + verify_workbuf(); } -#endif fch_early_init(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/46112 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf46f8edb6b70c63f623522e2bcd2f22d6d4790b Gerrit-Change-Number: 46112 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: Die if the workbuf is missing two boots in a row
by Martin Roth (Code Review) 08 Oct '20

08 Oct '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45964 ) Change subject: soc/amd/picasso: Die if the workbuf is missing two boots in a row ...................................................................... soc/amd/picasso: Die if the workbuf is missing two boots in a row BUG=b:169199392 TEST=Corrupt vboot signature to force an error, see that the system halts instead of rebooting forever. BRANCH=Zork Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: I949f94e78d25720f6cd7e81de8d030084e267f29 --- M src/soc/amd/picasso/bootblock/bootblock.c 1 file changed, 9 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/45964/1 diff --git a/src/soc/amd/picasso/bootblock/bootblock.c b/src/soc/amd/picasso/bootblock/bootblock.c index 4700027..a8303f5 100644 --- a/src/soc/amd/picasso/bootblock/bootblock.c +++ b/src/soc/amd/picasso/bootblock/bootblock.c @@ -134,10 +134,17 @@ #if CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) if (*(uint32_t *)_vboot2_work != VB2_SHARED_DATA_MAGIC) { + /* + * If the system has already been rebooted once, but still returns here, + * instead of rebooting to verstage again, assume that the system is in + * a reboot loop, so halt instead. + */ + if ((!vbnv_cmos_failed()) && cmos_read(CMOS_RECOVERY_BYTE) == + CMOS_RECOVERY_MAGIC_VAL) + die("Error: Reboot into recovery was unsuccessful. Halting."); + printk(BIOS_ERR, "ERROR: VBOOT workbuf not valid.\n"); - printk(BIOS_DEBUG, "Signature: %#08x\n", *(uint32_t *)_vboot2_work); - cmos_init(0); cmos_write(CMOS_RECOVERY_MAGIC_VAL, CMOS_RECOVERY_BYTE); warm_reset(); -- To view, visit https://review.coreboot.org/c/coreboot/+/45964 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I949f94e78d25720f6cd7e81de8d030084e267f29 Gerrit-Change-Number: 45964 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer/variant/volteer: Turn I2C3 bus freq closer to 400 k...
by Johnny Li (Code Review) 08 Oct '20

08 Oct '20

Johnny Li has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43048 ) Change subject: mb/google/volteer/variant/volteer: Turn I2C3 bus freq closer to 400 kHz for camera ...................................................................... mb/google/volteer/variant/volteer: Turn I2C3 bus freq closer to 400 kHz for camera The current I2C3 bus frequency is 341 kHZ, which does not meet the spec. This change updates scl_lcnt, scl_hcnt, sda_hold value for I2C3 to bring the bus frequency closer to 400kHz. BUG=b:153588771 TEST=Verified that I2C3 frequency is 394kHz. Signed-off-by: Johnny Li <johnny_li(a)wistron.corp-partner.google.com> Change-Id: Ie3edb04303701460932fb6cd92cc8d8fcf0a4b9b --- M src/mainboard/google/volteer/variants/volteer/overridetree.cb 1 file changed, 44 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/43048/1 diff --git a/src/mainboard/google/volteer/variants/volteer/overridetree.cb b/src/mainboard/google/volteer/variants/volteer/overridetree.cb index 24b869c..3effc6d 100644 --- a/src/mainboard/google/volteer/variants/volteer/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer/overridetree.cb @@ -161,5 +161,49 @@ end end end # PMC + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| GSPI1 | Fingerprint MCU | + #| I2C0 | Audio | + #| I2C1 | Touchscreen | + #| I2C2 | WLAN, SAR0 | + #| I2C3 | Camera, SAR1 | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 153, + .scl_hcnt = 75, + .sda_hold = 36, + }, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" end end -- To view, visit https://review.coreboot.org/c/coreboot/+/43048 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3edb04303701460932fb6cd92cc8d8fcf0a4b9b Gerrit-Change-Number: 43048 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Li <johnny_li(a)wistron.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: Replace soc_get_pmc_mux_device with device pointers
by Tim Wawrzynczak (Code Review) 08 Oct '20

08 Oct '20

Hello build bot (Jenkins), Furquan Shaikh, Caveh Jalali, Duncan Laurie, Nick Vaccaro, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45747 to look at the new patch set (#4). Change subject: soc/intel/tigerlake: Replace soc_get_pmc_mux_device with device pointers ...................................................................... soc/intel/tigerlake: Replace soc_get_pmc_mux_device with device pointers Now that device aliases can be used in the devicetree, the hacky function 'soc_get_pmc_mux_device' can be removed and replaced with pointers to the devices the function was supposed to return (1 for each port). Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: Ie00834c79bd5304998adaccb388ae74a108192b1 --- M src/ec/google/chromeec/chip.h M src/ec/google/chromeec/ec_acpi.c M src/soc/intel/common/block/include/intelblocks/pmc.h M src/soc/intel/tigerlake/pmc.c 4 files changed, 14 insertions(+), 73 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/45747/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/45747 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie00834c79bd5304998adaccb388ae74a108192b1 Gerrit-Change-Number: 45747 Gerrit-PatchSet: 4 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: trogdor: Remove Limits config entry.
by Ravi kumar (Code Review) 08 Oct '20

08 Oct '20

Ravi kumar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45705 ) Change subject: trogdor: Remove Limits config entry. ...................................................................... trogdor: Remove Limits config entry. Change-Id: Id913fc4a89ad5eff6b3487354ff8be7661539fe5 --- M src/mainboard/google/trogdor/chromeos.fmd 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/45705/1 diff --git a/src/mainboard/google/trogdor/chromeos.fmd b/src/mainboard/google/trogdor/chromeos.fmd index 3aa0473..2783496 100644 --- a/src/mainboard/google/trogdor/chromeos.fmd +++ b/src/mainboard/google/trogdor/chromeos.fmd @@ -11,13 +11,11 @@ } RO_VPD(PRESERVE) 228K RO_DDR_TRAINING(PRESERVE) 8K - RO_LIMITS_CFG(PRESERVE) 4K } RW_VPD(PRESERVE) 32K RW_NVRAM(PRESERVE) 16K RW_DDR_TRAINING(PRESERVE) 8K - RW_LIMITS_CFG(PRESERVE) 4K RW_ELOG(PRESERVE) 4K RW_SHARED 4K { SHARED_DATA -- To view, visit https://review.coreboot.org/c/coreboot/+/45705 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id913fc4a89ad5eff6b3487354ff8be7661539fe5 Gerrit-Change-Number: 45705 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sc7180: Remove LIMITS_CFG loading in romstage.
by Ravi kumar (Code Review) 08 Oct '20

08 Oct '20

Ravi kumar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45704 ) Change subject: sc7180: Remove LIMITS_CFG loading in romstage. ...................................................................... sc7180: Remove LIMITS_CFG loading in romstage. Change-Id: I9f57f5b520599ba6d708c91df9851e0e86b4b6c0 --- M src/soc/qualcomm/sc7180/qclib.c 1 file changed, 0 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/45704/1 diff --git a/src/soc/qualcomm/sc7180/qclib.c b/src/soc/qualcomm/sc7180/qclib.c index 6affc63..274d906 100644 --- a/src/soc/qualcomm/sc7180/qclib.c +++ b/src/soc/qualcomm/sc7180/qclib.c @@ -9,7 +9,6 @@ int qclib_soc_blob_load(void) { size_t size; - ssize_t ssize; /* Attempt to load PMICCFG Blob */ size = cbfs_boot_load_file(CONFIG_CBFS_PREFIX "/pmiccfg", @@ -25,13 +24,5 @@ return -1; qclib_add_if_table_entry(QCLIB_TE_DCB_SETTINGS, _dcb, size, 0); - /* Attempt to load Limits Config Blob */ - ssize = fmap_read_area(QCLIB_FR_LIMITS_CFG_DATA, _limits_cfg, - REGION_SIZE(limits_cfg)); - if (ssize < 0) - return -1; - qclib_add_if_table_entry(QCLIB_TE_LIMITS_CFG_DATA, - _limits_cfg, ssize, 0); - return 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/45704 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f57f5b520599ba6d708c91df9851e0e86b4b6c0 Gerrit-Change-Number: 45704 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork: Add EC device wakeup for morphius
by Josie Nordrum (Code Review) 07 Oct '20

07 Oct '20

Josie Nordrum has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45965 ) Change subject: mb/google/zork: Add EC device wakeup for morphius ...................................................................... mb/google/zork: Add EC device wakeup for morphius Add support for trackpoint wakeup from S3 by adding device events to mainboard and defining for morphius. BUG=b:160345665 BRANCH=None TEST=None Signed-off-by: Josie Nordrum <josienordrum(a)google.com> Change-Id: I982f0f4b60fbaeb389774531e1dee83da77cb8a1 --- M src/mainboard/google/zork/ec.c M src/mainboard/google/zork/variants/baseboard/include/baseboard/ec.h M src/mainboard/google/zork/variants/morphius/include/variant/ec.h 3 files changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/45965/1 diff --git a/src/mainboard/google/zork/ec.c b/src/mainboard/google/zork/ec.c index d770d27..f4f441c 100644 --- a/src/mainboard/google/zork/ec.c +++ b/src/mainboard/google/zork/ec.c @@ -11,6 +11,7 @@ .log_events = MAINBOARD_EC_LOG_EVENTS, .sci_events = MAINBOARD_EC_SCI_EVENTS, .s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS, + .s3_device_events = MAINBOARD_EC_S3_DEVICE_EVENTS, .s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS, }; diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/zork/variants/baseboard/include/baseboard/ec.h index ff42989..1bb6811 100644 --- a/src/mainboard/google/zork/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/ec.h @@ -38,6 +38,7 @@ #define MAINBOARD_EC_S3_WAKE_EVENTS \ (MAINBOARD_EC_S5_WAKE_EVENTS |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_DEVICE) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) /* Log EC wake events plus EC shutdown events */ @@ -46,6 +47,9 @@ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) +/* EC device events to enable and log in S3 */ +#define MAINBOARD_EC_S3_DEVICE_EVENTS 0 + /* Enable LID switch */ #define EC_ENABLE_LID_SWITCH #define EC_ENABLE_WAKE_PIN EC_WAKE_GPI diff --git a/src/mainboard/google/zork/variants/morphius/include/variant/ec.h b/src/mainboard/google/zork/variants/morphius/include/variant/ec.h index 04dfba4..a80e22c 100644 --- a/src/mainboard/google/zork/variants/morphius/include/variant/ec.h +++ b/src/mainboard/google/zork/variants/morphius/include/variant/ec.h @@ -7,3 +7,14 @@ /* Enable DPTC support */ #define EC_ENABLE_AMD_DPTC_SUPPORT + +/* Enable trackpoint S3 wakeups */ +#undef MAINBOARD_EC_S3_WAKE_EVENTS +#undef MAINBOARD_EC_S3_DEVICE_EVENTS +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_DEVICE) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) +#define MAINBOARD_EC_S3_DEVICE_EVENTS \ + (EC_DEVICE_EVENT_MASK(EC_DEVICE_EVENT_TRACKPAD)) -- To view, visit https://review.coreboot.org/c/coreboot/+/45965 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I982f0f4b60fbaeb389774531e1dee83da77cb8a1 Gerrit-Change-Number: 45965 Gerrit-PatchSet: 1 Gerrit-Owner: Josie Nordrum <josienordrum(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: commonlib/storage/mmc: Add DS and DDR50 speed modes
by Angel Pons (Code Review) 07 Oct '20

07 Oct '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44493 ) Change subject: commonlib/storage/mmc: Add DS and DDR50 speed modes ...................................................................... Patch Set 4: Code-Review+1 (1 comment) https://review.coreboot.org/c/coreboot/+/44493/2/src/commonlib/storage/mmc.c File src/commonlib/storage/mmc.c: https://review.coreboot.org/c/coreboot/+/44493/2/src/commonlib/storage/mmc.… PS2, Line 197: Increase > Yes, initially "SDHCI bus clock: 0. […] Ah, it increases from reset default speed. Is this reset speed what `mmc_select_ds` would program? -- To view, visit https://review.coreboot.org/c/coreboot/+/44493 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic75a3815a47e99e054d2cea2e82757740caffd1a Gerrit-Change-Number: 44493 Gerrit-PatchSet: 4 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.corp-partner.google.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 07 Oct 2020 16:55:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Bora Guvendik <bora.guvendik(a)intel.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/xeon_sp/cpx: Add save_dimm_info for SMBIOS type 17
by Angel Pons (Code Review) 07 Oct '20

07 Oct '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45798 ) Change subject: soc/intel/xeon_sp/cpx: Add save_dimm_info for SMBIOS type 17 ...................................................................... Patch Set 11: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/45798 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3cb72d18027d972140828970206834ff55b72022 Gerrit-Change-Number: 45798 Gerrit-PatchSet: 11 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: John Looney <john.looney(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 07 Oct 2020 16:46:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/xeon_sp/cpx: Add save_dimm_info for SMBIOS type 17
by Jonathan Zhang (Code Review) 07 Oct '20

07 Oct '20

Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45798 ) Change subject: soc/intel/xeon_sp/cpx: Add save_dimm_info for SMBIOS type 17 ...................................................................... Patch Set 11: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/45798 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3cb72d18027d972140828970206834ff55b72022 Gerrit-Change-Number: 45798 Gerrit-PatchSet: 11 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: John Looney <john.looney(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 07 Oct 2020 16:36:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit October 2020