coreboot-gerrit October 2020

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Change in coreboot[master]: [UNTESTED] soc/intel/{icl,tgl,jsl,ehl}: set PM ACPI timer state from ...
by Nico Huber (Code Review) 06 Oct '20

06 Oct '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45957 ) Change subject: [UNTESTED] soc/intel/{icl,tgl,jsl,ehl}: set PM ACPI timer state from Kconfig ...................................................................... Patch Set 22: (1 comment) https://review.coreboot.org/c/coreboot/+/45957/21/src/soc/intel/elkhartlake… File src/soc/intel/elkhartlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/45957/21/src/soc/intel/elkhartlake… PS21, Line 64: /* PM ACPI timer */ > hmm, isn't "Override/Fill FSP Silicon Param for mainboard" for `mainboard_silicon_init_params` redun […] Absolutely, yes. -- To view, visit https://review.coreboot.org/c/coreboot/+/45957 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf1eee9297034b29b7250f6c752e6f7f52b4b908 Gerrit-Change-Number: 45957 Gerrit-PatchSet: 22 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 06 Oct 2020 21:06:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: northbridge/intel: Use common 'MCHBARx()'
by HAOUAS Elyes (Code Review) 06 Oct '20

06 Oct '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45639 ) Change subject: northbridge/intel: Use common 'MCHBARx()' ...................................................................... northbridge/intel: Use common 'MCHBARx()' Change-Id: I67cb587c51f706eeb1e47dda83ece8b403ef7738 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/gm45/gm45.h M src/northbridge/intel/haswell/haswell.h M src/northbridge/intel/i945/i945.h M src/northbridge/intel/ironlake/ironlake.h M src/northbridge/intel/pineview/pineview.h M src/northbridge/intel/sandybridge/sandybridge.h M src/northbridge/intel/x4x/x4x.h 7 files changed, 9 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/45639/1 diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index 8196e90..4f9d82f 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -3,6 +3,7 @@ #ifndef __NORTHBRIDGE_INTEL_GM45_GM45_H__ #define __NORTHBRIDGE_INTEL_GM45_GM45_H__ +#include <northbridge/intel/common/mchbar_ops.h> #include <southbridge/intel/i82801ix/i82801ix.h> #ifndef __ACPI__ @@ -237,10 +238,6 @@ * MCHBAR */ -#define MCHBAR8(x) *((volatile u8 *)(DEFAULT_MCHBAR + x)) -#define MCHBAR16(x) *((volatile u16 *)(DEFAULT_MCHBAR + x)) -#define MCHBAR32(x) *((volatile u32 *)(DEFAULT_MCHBAR + x)) - #define HPLLVCO_MCHBAR 0x0c0f #define PMSTS_MCHBAR 0x0f14 /* Self refresh channel status */ diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index 4bcaaa7..b7328e7 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -10,6 +10,7 @@ #include "memmap.h" +#include <northbridge/intel/common/mchbar_ops.h> #include <southbridge/intel/lynxpoint/pch.h> /* Everything below this line is ignored in the DSDT */ @@ -28,9 +29,6 @@ * MCHBAR */ -#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x)))) #define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) #define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) #define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h index 26fc931..365c7b9 100644 --- a/src/northbridge/intel/i945/i945.h +++ b/src/northbridge/intel/i945/i945.h @@ -14,6 +14,7 @@ #endif #define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ +#include <northbridge/intel/common/mchbar_ops.h> #include <southbridge/intel/i82801gx/i82801gx.h> /* Everything below this line is ignored in the DSDT */ @@ -99,10 +100,6 @@ * MCHBAR */ -#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x)))) - /* Chipset Control Registers */ #define FSBPMC3 0x40 /* 32bit */ #define FSBPMC4 0x44 /* 32bit */ diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h index 97a9391..4da9854 100644 --- a/src/northbridge/intel/ironlake/ironlake.h +++ b/src/northbridge/intel/ironlake/ironlake.h @@ -3,6 +3,8 @@ #ifndef __NORTHBRIDGE_INTEL_IRONLAKE_IRONLAKE_H__ #define __NORTHBRIDGE_INTEL_IRONLAKE_IRONLAKE_H__ +#include <northbridge/intel/common/mchbar_ops.h> + #define DEFAULT_HECIBAR ((u8 *)0xfed17000) #define IOMMU_BASE1 0xfed90000 @@ -100,9 +102,6 @@ * MCHBAR */ -#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x)))) #define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) #define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) #define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) diff --git a/src/northbridge/intel/pineview/pineview.h b/src/northbridge/intel/pineview/pineview.h index 03fa318..aecf2ac 100644 --- a/src/northbridge/intel/pineview/pineview.h +++ b/src/northbridge/intel/pineview/pineview.h @@ -3,6 +3,7 @@ #ifndef NORTHBRIDGE_INTEL_PINEVIEW_H #define NORTHBRIDGE_INTEL_PINEVIEW_H +#include <northbridge/intel/common/mchbar_ops.h> #include <northbridge/intel/pineview/memmap.h> #include <southbridge/intel/i82801gx/i82801gx.h> @@ -38,9 +39,6 @@ * MCHBAR */ -#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + x))) /* FIXME: causes changes */ #define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) #define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) #define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 8f9d118..853c8f8 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -3,6 +3,8 @@ #ifndef __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__ #define __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__ +#include <northbridge/intel/common/mchbar_ops.h> + /* Device ID for SandyBridge and IvyBridge */ #define BASE_REV_SNB 0x00 #define BASE_REV_IVB 0x50 @@ -49,9 +51,6 @@ * MCHBAR */ -#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x)))) #define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) #define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) #define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index 45785a0..84ee6bb 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -3,6 +3,7 @@ #ifndef __NORTHBRIDGE_INTEL_X4X_H__ #define __NORTHBRIDGE_INTEL_X4X_H__ +#include <northbridge/intel/common/mchbar_ops.h> #include <stdint.h> #include "iomap.h" @@ -40,9 +41,6 @@ * MCHBAR */ -#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x)))) #define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) #define MCHBAR8_OR(x, or) (MCHBAR8(x) = MCHBAR8(x) | (or)) #define MCHBAR8_AND_OR(x, and, or) \ -- To view, visit https://review.coreboot.org/c/coreboot/+/45639 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67cb587c51f706eeb1e47dda83ece8b403ef7738 Gerrit-Change-Number: 45639 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 6

Change in coreboot[master]: nb/i945: Move DEFAULT_MCHBAR to Kconfig
by HAOUAS Elyes (Code Review) 06 Oct '20

06 Oct '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45613 ) Change subject: nb/i945: Move DEFAULT_MCHBAR to Kconfig ...................................................................... nb/i945: Move DEFAULT_MCHBAR to Kconfig Change-Id: If7aab904a92ddf741e7032fd111c945633d7c1d6 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/Kconfig M src/northbridge/intel/i945/acpi/i945.asl M src/northbridge/intel/i945/early_init.c M src/northbridge/intel/i945/i945.h 4 files changed, 9 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/45613/1 diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index d6498f1..0499a7c 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -15,6 +15,10 @@ select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT select PARALLEL_MP +config DEFAULT_MCHBAR + hex + default 0xfed14000 + config VBOOT select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_SEPARATE_VERSTAGE diff --git a/src/northbridge/intel/i945/acpi/i945.asl b/src/northbridge/intel/i945/acpi/i945.asl index 789225c..76a50f0 100644 --- a/src/northbridge/intel/i945/acpi/i945.asl +++ b/src/northbridge/intel/i945/acpi/i945.asl @@ -39,7 +39,7 @@ Name (PDRS, ResourceTemplate() { Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) - Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) + Memory32Fixed(ReadWrite, CONFIG_DEFAULT_MCHBAR, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000) diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index b04a2f594..0bdcd17 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -145,7 +145,7 @@ printk(BIOS_DEBUG, "Setting up static northbridge registers..."); /* Set up all hardcoded northbridge BARs */ pci_write_config32(HOST_BRIDGE, EPBAR, DEFAULT_EPBAR | 1); - pci_write_config32(HOST_BRIDGE, MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1); + pci_write_config32(HOST_BRIDGE, MCHBAR, (uintptr_t)CONFIG_DEFAULT_MCHBAR | 1); pci_write_config32(HOST_BRIDGE, DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1); pci_write_config32(HOST_BRIDGE, X60BAR, DEFAULT_X60BAR | 1); diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h index 4b79b2b..96623be 100644 --- a/src/northbridge/intel/i945/i945.h +++ b/src/northbridge/intel/i945/i945.h @@ -6,10 +6,8 @@ /* Northbridge BARs */ #define DEFAULT_X60BAR 0xfed13000 #ifndef __ACPI__ -#define DEFAULT_MCHBAR ((u8 *)0xfed14000) /* 16 KB */ #define DEFAULT_DMIBAR ((u8 *)0xfed18000) /* 4 KB */ #else -#define DEFAULT_MCHBAR 0xfed14000 /* 16 KB */ #define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ #endif #define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ @@ -99,9 +97,9 @@ * MCHBAR */ -#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x)))) +#define MCHBAR8(x) (*((volatile u8 *)(CONFIG_DEFAULT_MCHBAR + (x)))) +#define MCHBAR16(x) (*((volatile u16 *)(CONFIG_DEFAULT_MCHBAR + (x)))) +#define MCHBAR32(x) (*((volatile u32 *)(CONFIG_DEFAULT_MCHBAR + (x)))) /* Chipset Control Registers */ #define FSBPMC3 0x40 /* 32bit */ -- To view, visit https://review.coreboot.org/c/coreboot/+/45613 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7aab904a92ddf741e7032fd111c945633d7c1d6 Gerrit-Change-Number: 45613 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 19

Change in coreboot[master]: mb/{asus/p2b,supermicro/x10slm-f}/dsdt.asl: Reformat DefinitionBlock(...
by HAOUAS Elyes (Code Review) 06 Oct '20

06 Oct '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45791 ) Change subject: mb/{asus/p2b,supermicro/x10slm-f}/dsdt.asl: Reformat DefinitionBlock() and use macro ...................................................................... mb/{asus/p2b,supermicro/x10slm-f}/dsdt.asl: Reformat DefinitionBlock() and use macro Change-Id: I28655280e6caebeae82ed881b7871f48699e4155 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/asus/p2b/dsdt.asl M src/mainboard/supermicro/x10slm-f/dsdt.asl 2 files changed, 16 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/45791/1 diff --git a/src/mainboard/asus/p2b/dsdt.asl b/src/mainboard/asus/p2b/dsdt.asl index e1bda17..19bdb61 100644 --- a/src/mainboard/asus/p2b/dsdt.asl +++ b/src/mainboard/asus/p2b/dsdt.asl @@ -9,7 +9,14 @@ #define SUPERIO_SHOW_LPT #include <acpi/acpi.h> -DefinitionBlock ("DSDT.aml", "DSDT", 2, OEM_ID, ACPI_TABLE_CREATOR, 1) +DefinitionBlock ( + "DSDT.aml", + "DSDT", + CURRENT_DSDT_REV, + OEM_ID, + ACPI_TABLE_CREATOR, + 1 + ) { /* \_SB scope defining the main processor is generated in SSDT. */ diff --git a/src/mainboard/supermicro/x10slm-f/dsdt.asl b/src/mainboard/supermicro/x10slm-f/dsdt.asl index fc0ca02..92d72a9 100644 --- a/src/mainboard/supermicro/x10slm-f/dsdt.asl +++ b/src/mainboard/supermicro/x10slm-f/dsdt.asl @@ -2,7 +2,14 @@ #include <acpi/acpi.h> -DefinitionBlock("dsdt.aml", "DSDT", 2, OEM_ID, ACPI_TABLE_CREATOR, 0x20181220) +DefinitionBlock( + "dsdt.aml", + "DSDT", + CURRENT_DSDT_REV, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20181220 + ) { #include "acpi/platform.asl" #include <southbridge/intel/common/acpi/platform.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/45791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28655280e6caebeae82ed881b7871f48699e4155 Gerrit-Change-Number: 45791 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: drivers/i2c: Add chip driver for GPIO based I2C multiplexer
by Tim Wawrzynczak (Code Review) 06 Oct '20

06 Oct '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45911 ) Change subject: drivers/i2c: Add chip driver for GPIO based I2C multiplexer ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/c/coreboot/+/45911/4/src/drivers/i2c/gpio_mux/g… File src/drivers/i2c/gpio_mux/gpio_mux.c: PS4: > I proposed that just to keep the support for the mux and the bus closer in coreboot. […] Exactly what I was thinking -- To view, visit https://review.coreboot.org/c/coreboot/+/45911 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib371108cc6043c133681066bf7bf4b2e00771e8b Gerrit-Change-Number: 45911 Gerrit-PatchSet: 5 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 06 Oct 2020 18:52:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: templates: add an empty SPD to SPD_SOURCES
by Paul Fagerburg (Code Review) 06 Oct '20

06 Oct '20

Paul Fagerburg has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45746 ) Change subject: templates: add an empty SPD to SPD_SOURCES ...................................................................... templates: add an empty SPD to SPD_SOURCES Add an empty SPD in SPD_SOURCES when creating a new variant of hatch, volteer, waddledee, or waddledoo, so that coreboot can build successfully. For variants that use spd_tools, add an empty mem_parts_used.txt so that the developer can add the supported memory parts and regenerate the Makefile.inc with the correct SPD references. BUG=b:169422833 TEST=create a new variant of hatch, volteer, waddledee, and waddledoo, and observe that each one succeeds. Signed-off-by: Paul Fagerburg <pfagerburg(a)google.com> Change-Id: I06dfb6103701bf8949180595f1e98fac48bcc585 --- M util/mainboard/google/hatch/template/Makefile.inc A util/mainboard/google/volteer/template/memory/Makefile.inc A util/mainboard/google/volteer/template/memory/dram_id.generated.txt A util/mainboard/google/volteer/template/memory/mem_parts_used.txt A util/mainboard/google/waddledee/template/memory/Makefile.inc A util/mainboard/google/waddledee/template/memory/dram_id.generated.txt A util/mainboard/google/waddledee/template/memory/mem_parts_used.txt A util/mainboard/google/waddledoo/template/memory/Makefile.inc A util/mainboard/google/waddledoo/template/memory/dram_id.generated.txt A util/mainboard/google/waddledoo/template/memory/mem_parts_used.txt 10 files changed, 48 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/45746/1 diff --git a/util/mainboard/google/hatch/template/Makefile.inc b/util/mainboard/google/hatch/template/Makefile.inc index 61b23ed..599cfcc 100644 --- a/util/mainboard/google/hatch/template/Makefile.inc +++ b/util/mainboard/google/hatch/template/Makefile.inc @@ -1,4 +1,6 @@ ## ## SPDX-License-Identifier: GPL-2.0-only -SPD_SOURCES = +## TODO engineer creating a new variant needs to add SPDs for memory parts + +SPD_SOURCES = empty_ddr4 diff --git a/util/mainboard/google/volteer/template/memory/Makefile.inc b/util/mainboard/google/volteer/template/memory/Makefile.inc new file mode 100644 index 0000000..3edeb96 --- /dev/null +++ b/util/mainboard/google/volteer/template/memory/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! +## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. + +SPD_SOURCES = ddr4-spd-empty.hex diff --git a/util/mainboard/google/volteer/template/memory/dram_id.generated.txt b/util/mainboard/google/volteer/template/memory/dram_id.generated.txt new file mode 100644 index 0000000..fa24790 --- /dev/null +++ b/util/mainboard/google/volteer/template/memory/dram_id.generated.txt @@ -0,0 +1 @@ +DRAM Part Name ID to assign diff --git a/util/mainboard/google/volteer/template/memory/mem_parts_used.txt b/util/mainboard/google/volteer/template/memory/mem_parts_used.txt new file mode 100644 index 0000000..106a705 --- /dev/null +++ b/util/mainboard/google/volteer/template/memory/mem_parts_used.txt @@ -0,0 +1,9 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Each part must also be listed in util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt. +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/ddr4. +# See util/spd_tools/ddr4/README.md for more details and instructions. + +# Part Name, Fixed ID (optional) diff --git a/util/mainboard/google/waddledee/template/memory/Makefile.inc b/util/mainboard/google/waddledee/template/memory/Makefile.inc new file mode 100644 index 0000000..3edeb96 --- /dev/null +++ b/util/mainboard/google/waddledee/template/memory/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! +## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. + +SPD_SOURCES = ddr4-spd-empty.hex diff --git a/util/mainboard/google/waddledee/template/memory/dram_id.generated.txt b/util/mainboard/google/waddledee/template/memory/dram_id.generated.txt new file mode 100644 index 0000000..fa24790 --- /dev/null +++ b/util/mainboard/google/waddledee/template/memory/dram_id.generated.txt @@ -0,0 +1 @@ +DRAM Part Name ID to assign diff --git a/util/mainboard/google/waddledee/template/memory/mem_parts_used.txt b/util/mainboard/google/waddledee/template/memory/mem_parts_used.txt new file mode 100644 index 0000000..106a705 --- /dev/null +++ b/util/mainboard/google/waddledee/template/memory/mem_parts_used.txt @@ -0,0 +1,9 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Each part must also be listed in util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt. +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/ddr4. +# See util/spd_tools/ddr4/README.md for more details and instructions. + +# Part Name, Fixed ID (optional) diff --git a/util/mainboard/google/waddledoo/template/memory/Makefile.inc b/util/mainboard/google/waddledoo/template/memory/Makefile.inc new file mode 100644 index 0000000..3edeb96 --- /dev/null +++ b/util/mainboard/google/waddledoo/template/memory/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! +## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. + +SPD_SOURCES = ddr4-spd-empty.hex diff --git a/util/mainboard/google/waddledoo/template/memory/dram_id.generated.txt b/util/mainboard/google/waddledoo/template/memory/dram_id.generated.txt new file mode 100644 index 0000000..fa24790 --- /dev/null +++ b/util/mainboard/google/waddledoo/template/memory/dram_id.generated.txt @@ -0,0 +1 @@ +DRAM Part Name ID to assign diff --git a/util/mainboard/google/waddledoo/template/memory/mem_parts_used.txt b/util/mainboard/google/waddledoo/template/memory/mem_parts_used.txt new file mode 100644 index 0000000..106a705 --- /dev/null +++ b/util/mainboard/google/waddledoo/template/memory/mem_parts_used.txt @@ -0,0 +1,9 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Each part must also be listed in util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt. +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/ddr4. +# See util/spd_tools/ddr4/README.md for more details and instructions. + +# Part Name, Fixed ID (optional) -- To view, visit https://review.coreboot.org/c/coreboot/+/45746 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06dfb6103701bf8949180595f1e98fac48bcc585 Gerrit-Change-Number: 45746 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-MessageType: newchange

5 35

Change in coreboot[master]: commonlib/storage/mmc: Add DS and DDR50 speed modes
by Bora Guvendik (Code Review) 06 Oct '20

06 Oct '20

Bora Guvendik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44493 ) Change subject: commonlib/storage/mmc: Add DS and DDR50 speed modes ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/44493/2/src/commonlib/storage/mmc.c File src/commonlib/storage/mmc.c: https://review.coreboot.org/c/coreboot/+/44493/2/src/commonlib/storage/mmc.… PS2, Line 197: Increase > Is it increasing, though? Yes, initially "SDHCI bus clock: 0.097 MHz", then this changes to 25,50 or 200Mhz depending on the speed. I can change it to "Configure" if you think it is needed. -- To view, visit https://review.coreboot.org/c/coreboot/+/44493 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic75a3815a47e99e054d2cea2e82757740caffd1a Gerrit-Change-Number: 44493 Gerrit-PatchSet: 4 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.corp-partner.google.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 06 Oct 2020 17:51:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: drivers/ipmi/ocp/ipmii_ocp.c: Clean up includes
by Marc Jones (Code Review) 06 Oct '20

06 Oct '20

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45968 ) Change subject: drivers/ipmi/ocp/ipmii_ocp.c: Clean up includes ...................................................................... drivers/ipmi/ocp/ipmii_ocp.c: Clean up includes Remove #include "chip.h", which is not needed and causes a build problem in a later change. Alphabetise the #includes. Change-Id: If19ccd144bd352a196adccd75f9f6f139eae4e4a Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com> --- M src/drivers/ipmi/ocp/ipmi_ocp.c R src/soc/intel/xeon_sp/cpx/cpx.h R src/soc/intel/xeon_sp/skx/skx.h 3 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/45968/1 diff --git a/src/drivers/ipmi/ocp/ipmi_ocp.c b/src/drivers/ipmi/ocp/ipmi_ocp.c index f96ce24..459b8e2 100644 --- a/src/drivers/ipmi/ocp/ipmi_ocp.c +++ b/src/drivers/ipmi/ocp/ipmi_ocp.c @@ -7,14 +7,14 @@ * end */ +#include <arch/cpu.h> #include <console/console.h> #include <device/device.h> #include <device/pnp.h> -#include <string.h> +#include <drivers/ipmi/ipmi_kcs.h> #include <intelblocks/cpulib.h> -#include <arch/cpu.h> -#include "chip.h" -#include "drivers/ipmi/ipmi_kcs.h" +#include <string.h> + #include "ipmi_ocp.h" static int ipmi_set_processor_information_param1(struct device *dev) diff --git a/src/soc/intel/xeon_sp/cpx/chip.h b/src/soc/intel/xeon_sp/cpx/cpx.h similarity index 100% rename from src/soc/intel/xeon_sp/cpx/chip.h rename to src/soc/intel/xeon_sp/cpx/cpx.h diff --git a/src/soc/intel/xeon_sp/skx/chip.h b/src/soc/intel/xeon_sp/skx/skx.h similarity index 100% rename from src/soc/intel/xeon_sp/skx/chip.h rename to src/soc/intel/xeon_sp/skx/skx.h -- To view, visit https://review.coreboot.org/c/coreboot/+/45968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If19ccd144bd352a196adccd75f9f6f139eae4e4a Gerrit-Change-Number: 45968 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 6

Change in coreboot[master]: soc/intel/tigerlake: Replace soc_get_pmc_mux_device with device pointers
by Duncan Laurie (Code Review) 06 Oct '20

06 Oct '20

Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45747 ) Change subject: soc/intel/tigerlake: Replace soc_get_pmc_mux_device with device pointers ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/45747 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie00834c79bd5304998adaccb388ae74a108192b1 Gerrit-Change-Number: 45747 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 06 Oct 2020 16:38:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/tigerlake: Replace soc_get_pmc_mux_device with device pointers
by Tim Wawrzynczak (Code Review) 06 Oct '20

06 Oct '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45747 ) Change subject: soc/intel/tigerlake: Replace soc_get_pmc_mux_device with device pointers ...................................................................... Patch Set 3: ping 😎 -- To view, visit https://review.coreboot.org/c/coreboot/+/45747 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie00834c79bd5304998adaccb388ae74a108192b1 Gerrit-Change-Number: 45747 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 06 Oct 2020 16:35:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit October 2020