coreboot-gerrit October 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/inte/tgl: Reflow long lines
by Subrata Banik (Code Review) 07 Oct '20

07 Oct '20

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46072 ) Change subject: soc/inte/tgl: Reflow long lines ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/46072 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43d77db1f81d72aa13f3a702abff490a68a52bd7 Gerrit-Change-Number: 46072 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Wed, 07 Oct 2020 05:48:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/xeon_sp/cpx: Add save_dimm_info for SMBIOS type 17
by Johnny Lin (Code Review) 07 Oct '20

07 Oct '20

Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45798 ) Change subject: soc/intel/xeon_sp/cpx: Add save_dimm_info for SMBIOS type 17 ...................................................................... Patch Set 11: (1 comment) https://review.coreboot.org/c/coreboot/+/45798/4/src/soc/intel/xeon_sp/cpx/… File src/soc/intel/xeon_sp/cpx/romstage.c: https://review.coreboot.org/c/coreboot/+/45798/4/src/soc/intel/xeon_sp/cpx/… PS4, Line 41: save_dimm_info > The save_dimm_info() and the SystemMemoryMapHob struct are both Cooper Lake specific, they cannot be […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/45798 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3cb72d18027d972140828970206834ff55b72022 Gerrit-Change-Number: 45798 Gerrit-PatchSet: 11 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: John Looney <john.looney(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 07 Oct 2020 05:16:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Johnny Lin <Johnny_Lin(a)wiwynn.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: amd/picasso/psp_verstage: use cbmem console
by Kangheui Won (Code Review) 07 Oct '20

07 Oct '20

Kangheui Won has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46059 ) Change subject: amd/picasso/psp_verstage: use cbmem console ...................................................................... amd/picasso/psp_verstage: use cbmem console psp_verstage uses separate pritnk implementation, which does not include code to add console output to cbmem. Add cbmemc_init and cbmemc_tx_byte to add console output to cbmem. BUG=b:159220781 TEST=build BRANCH=zork Change-Id: I63ba5814903565c372dbeb50004565a371dad730 Signed-off-by: Kangheui Won <khwon(a)chromium.org> --- M src/soc/amd/picasso/psp_verstage/printk.c 1 file changed, 7 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/46059/1 diff --git a/src/soc/amd/picasso/psp_verstage/printk.c b/src/soc/amd/picasso/psp_verstage/printk.c index 2f9d30a..1fe2dc7 100644 --- a/src/soc/amd/picasso/psp_verstage/printk.c +++ b/src/soc/amd/picasso/psp_verstage/printk.c @@ -2,12 +2,13 @@ #include <bl_uapp/bl_syscall_public.h> #include <console/console.h> +#include <console/cbmem_console.h> #include <console/streams.h> #include <stdarg.h> void console_hw_init(void) { - // Nothing to init for svc_debug_print + __cbmemc_init(); } int do_printk(int msg_level, const char *fmt, ...) @@ -24,14 +25,17 @@ int do_vprintk(int msg_level, const char *fmt, va_list args) { - int i, log_this; + int i, cnt, log_this; char buf[256]; log_this = console_log_level(msg_level); if (log_this < CONSOLE_LOG_FAST) return 0; - i = vsnprintf(buf, sizeof(buf), fmt, args); + cnt = vsnprintf(buf, sizeof(buf), fmt, args); + for(i = 0; i < cnt; i++) { + __cbmemc_tx_byte(buf[i]); + } svc_debug_print(buf); return i; } -- To view, visit https://review.coreboot.org/c/coreboot/+/46059 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I63ba5814903565c372dbeb50004565a371dad730 Gerrit-Change-Number: 46059 Gerrit-PatchSet: 1 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: Update vboot submodule to upstream master
by Kangheui Won (Code Review) 07 Oct '20

07 Oct '20

Kangheui Won has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45986 ) Change subject: Update vboot submodule to upstream master ...................................................................... Update vboot submodule to upstream master Updating from commit id 4bb06cc1: COIL: Change denylist to blocklist to commit id 4c523ed1: vboot2: Add support for modexp acceleration This brings in 10 new commmits. Change-Id: Iff6eb99c8ed3046b6fdb6c1e2892aab956f3b562 --- M 3rdparty/vboot 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/45986/1 diff --git a/3rdparty/vboot b/3rdparty/vboot index 4bb06cc..4c523ed 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit 4bb06cc1b73c738acf056d7fc0a96c4690e8ef8a +Subproject commit 4c523ed10f25de872ac0513ebd6ca53d3970b9de -- To view, visit https://review.coreboot.org/c/coreboot/+/45986 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff6eb99c8ed3046b6fdb6c1e2892aab956f3b562 Gerrit-Change-Number: 45986 Gerrit-PatchSet: 1 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: amd/picasso/psp_verstage: Add modexp svc wrapper
by Kangheui Won (Code Review) 07 Oct '20

07 Oct '20

Kangheui Won has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45985 ) Change subject: amd/picasso/psp_verstage: Add modexp svc wrapper ...................................................................... amd/picasso/psp_verstage: Add modexp svc wrapper The PSP bootloader version 0.08.0B.7B added support for the Mod Exp svc call. BUG=b:169157796 BRANCH=zork TEST=build verstage for zork Signed-off-by: Kangheui Won <khwon(a)chromium.org> Change-Id: Ifdbf20544b21b7fa90a49c5497ff4a5da61bebb1 --- M src/soc/amd/picasso/psp_verstage/svc.c 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/45985/1 diff --git a/src/soc/amd/picasso/psp_verstage/svc.c b/src/soc/amd/picasso/psp_verstage/svc.c index eff0261..b847276 100644 --- a/src/soc/amd/picasso/psp_verstage/svc.c +++ b/src/soc/amd/picasso/psp_verstage/svc.c @@ -157,3 +157,10 @@ SVC_CALL1(SVC_RSAPKCS_VERIFY, rsa_params, retval); return retval; } + +uint32_t svc_modexp(MOD_EXP_PARAMS *mod_exp_param) +{ + uint32_t retval = 0; + SVC_CALL1(SVC_MODEXP, mod_exp_param, retval); + return retval; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/45985 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifdbf20544b21b7fa90a49c5497ff4a5da61bebb1 Gerrit-Change-Number: 45985 Gerrit-PatchSet: 1 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: vc/amd/fsp: Update the svc call header for the Mod Exp SVC
by Martin Roth (Code Review) 07 Oct '20

07 Oct '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45942 ) Change subject: vc/amd/fsp: Update the svc call header for the Mod Exp SVC ...................................................................... vc/amd/fsp: Update the svc call header for the Mod Exp SVC The PSP bootloader version 0.08.0B.7B added support for the Mod Exp svc call. BUG=b:169157796 TEST=Build BRANCH=Zork Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: I1ce69c80cec77e1692cf9713a739cc4da4677da6 --- M src/vendorcode/amd/fsp/picasso/include/bl_uapp/bl_syscall_public.h 1 file changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/45942/1 diff --git a/src/vendorcode/amd/fsp/picasso/include/bl_uapp/bl_syscall_public.h b/src/vendorcode/amd/fsp/picasso/include/bl_uapp/bl_syscall_public.h index 7cc9fd4..09100a3 100644 --- a/src/vendorcode/amd/fsp/picasso/include/bl_uapp/bl_syscall_public.h +++ b/src/vendorcode/amd/fsp/picasso/include/bl_uapp/bl_syscall_public.h @@ -35,6 +35,7 @@ #define SVC_EXIT 0x00 #define SVC_MAP_USER_STACK 0x01 #define SVC_DEBUG_PRINT 0x06 +#define SVC_MODEXP 0x0C #define SVC_RSAPSS_VERIFY 0x0D #define SVC_DEBUG_PRINT_EX 0x1A #define SVC_WAIT_10NS_MULTIPLE 0x1B @@ -59,6 +60,17 @@ #define PSP_INFO_PRODUCTION_SILICON 0x00000002UL #define PSP_INFO_VALID 0x80000000UL +typedef struct MOD_EXP_PARAMS_T +{ + char *pExponent; // Exponent address + unsigned int ExpSize; // Exponent size in bytes + char *pModulus; // Modulus address + unsigned int ModulusSize; // Modulus size in bytes + char *pMessage; // Message address, same size as ModulusSize + char *pOuput; // Output address; Must be big enough to hold the + // data of ModulusSize +} MOD_EXP_PARAMS; + typedef struct _RSAPSS_VERIFY_PARAMS_T { char *pHash; // Message digest to verify the RSA signature @@ -384,6 +396,15 @@ */ uint32_t svc_rsa_pkcs_verify(const RSAPKCS_VERIFY_PARAMS *params); +/* Calculate ModEx + * + * Parameters: + * mod_exp_param - ModExp parameters + * + * Return value: BL_OK or error code + */ +unsigned int svc_modexp(MOD_EXP_PARAMS *mod_exp_param); + /* C entry point for the Bootloader Userspace Application */ void Main(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/45942 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ce69c80cec77e1692cf9713a739cc4da4677da6 Gerrit-Change-Number: 45942 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/ocp/tiogapass: Implement set POST start/end command
by Tim Chu (Code Review) 07 Oct '20

07 Oct '20

Tim Chu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41604 ) Change subject: mb/ocp/tiogapass: Implement set POST start/end command ...................................................................... mb/ocp/tiogapass: Implement set POST start/end command Implemented sending POST start and POST end command to BMC in ramstage. Tested=Read POST command in OpenBMC, if success message may show as below, root@bmc:~# cat /var/log/messages |grep -i "POST" Aug 10 00:11:24 bmc user.info ipmid: POST Start Event for Payload#1 Aug 10 00:11:28 bmc user.info ipmid: POST End Event for Payload#1 root@bmc:~# Signed-off-by: TimChu <Tim.Chu(a)quantatw.com> Change-Id: Ia283c5e8d539bfeb47a73d32d8bfb5e666f27170 --- M src/mainboard/ocp/tiogapass/Kconfig M src/mainboard/ocp/tiogapass/devicetree.cb 2 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/41604/1 diff --git a/src/mainboard/ocp/tiogapass/Kconfig b/src/mainboard/ocp/tiogapass/Kconfig index 5cb2421..2ec47ed 100644 --- a/src/mainboard/ocp/tiogapass/Kconfig +++ b/src/mainboard/ocp/tiogapass/Kconfig @@ -9,6 +9,7 @@ select HAVE_ACPI_TABLES select MAINBOARD_USES_FSP2_0 select IPMI_KCS + select IPMI_OCP select SOC_INTEL_SKYLAKE_SP select SUPERIO_ASPEED_AST2400 diff --git a/src/mainboard/ocp/tiogapass/devicetree.cb b/src/mainboard/ocp/tiogapass/devicetree.cb index 19dba55..35e74b0 100644 --- a/src/mainboard/ocp/tiogapass/devicetree.cb +++ b/src/mainboard/ocp/tiogapass/devicetree.cb @@ -77,6 +77,9 @@ register "bmc_i2c_address" = "0x20" register "bmc_boot_timeout" = "60" end + chip drivers/ocp/ipmi # OCP specific IPMI porting + device pnp ca2.1 on end + end end # Intel Corporation C621 Series Chipset LPC/eSPI Controller device pci 1f.2 on end # Intel Corporation C620 Series Chipset Family Power Management Controller device pci 1f.4 on end # Intel Corporation C620 Series Chipset Family SMBus -- To view, visit https://review.coreboot.org/c/coreboot/+/41604 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia283c5e8d539bfeb47a73d32d8bfb5e666f27170 Gerrit-Change-Number: 41604 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/amd/pi/hudson: Add SPI controller support
by Marshall Dawson (Code Review) 07 Oct '20

07 Oct '20

Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28719 ) Change subject: sb/amd/pi/hudson: Add SPI controller support ...................................................................... Patch Set 5: (3 comments) https://review.coreboot.org/c/coreboot/+/28719/5/src/southbridge/amd/pi/hud… File src/southbridge/amd/pi/hudson/Makefile.inc: https://review.coreboot.org/c/coreboot/+/28719/5/src/southbridge/amd/pi/hud… PS5, Line 31: bootblock Did you consider all-$()? For any system with elog support, then it can also be good to have spi in smm as well. Or, it looks like in soc/amd/common/block/spi, it looks like we've qualified it with CONFIG_SPI_FLASH_SMM. https://review.coreboot.org/c/coreboot/+/28719/5/src/southbridge/amd/pi/hud… File src/southbridge/amd/pi/hudson/pci_devs.h: https://review.coreboot.org/c/coreboot/+/28719/5/src/southbridge/amd/pi/hud… PS5, Line 18: Was this file added to the commit by accident? It doesn't seem to fit with adding SPI. https://review.coreboot.org/c/coreboot/+/28719/5/src/southbridge/amd/pi/hud… File src/southbridge/amd/pi/hudson/spi.c: https://review.coreboot.org/c/coreboot/+/28719/5/src/southbridge/amd/pi/hud… PS5, Line 158: spi_write8(SPI_EXT_REG_INDX, SPI_EXT_REG_TXCOUNT); : spi_write8(SPI_EXT_REG_DATA, bytesout); Hmm, which device did you write this for? It looks like, for example, that Hudson 1 is completely different than Kabini. As a result, I think a lot of the definitions should be looked at more closely. Maybe break the steps out into their own functions? -- To view, visit https://review.coreboot.org/c/coreboot/+/28719 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc6feb433a19337e09fc394cbf30288f53b195dd Gerrit-Change-Number: 28719 Gerrit-PatchSet: 5 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Comment-Date: Wed, 07 Oct 2020 01:21:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/wifi: Drop call to pci_dev_init
by Furquan Shaikh (Code Review) 07 Oct '20

07 Oct '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46029 ) Change subject: drivers/intel/wifi: Drop call to pci_dev_init ...................................................................... drivers/intel/wifi: Drop call to pci_dev_init `pci_dev_init()` is used to load and run option ROM on VGA class devices (PCI_CLASS_DISPLAY_VGA). WiFi device is not a VGA class device and hence the call to `pci_dev_init()` is not required. This change drops the call to `pci_dev_init()` from `wifi_pci_dev_init()` in Intel WiFi driver. BUG=b:169802515 BRANCH=zork Change-Id: I6588ea0a5c848904088d05fd1cbdf677b2dc8ea9 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/drivers/intel/wifi/wifi.c 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/46029/1 diff --git a/src/drivers/intel/wifi/wifi.c b/src/drivers/intel/wifi/wifi.c index 0ad0e1c..e117ec0 100644 --- a/src/drivers/intel/wifi/wifi.c +++ b/src/drivers/intel/wifi/wifi.c @@ -63,8 +63,6 @@ static void wifi_pci_dev_init(struct device *dev) { - pci_dev_init(dev); - if (CONFIG(ELOG)) { uint32_t val; val = pci_read_config16(dev, PMCS_DR); -- To view, visit https://review.coreboot.org/c/coreboot/+/46029 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6588ea0a5c848904088d05fd1cbdf677b2dc8ea9 Gerrit-Change-Number: 46029 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/wifi/generic: Use pci_dev_* operations for device ops
by Furquan Shaikh (Code Review) 07 Oct '20

07 Oct '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46028 ) Change subject: drivers/wifi/generic: Use pci_dev_* operations for device ops ...................................................................... drivers/wifi/generic: Use pci_dev_* operations for device ops WiFi devices supported by the generic WiFi driver are PCIe devices which need to be managed using the standard pci_dev_* operations to read, set and enable resources. This change updates the device_operations structure `wifi_generic_ops` to use the standard pci_dev_* operations for these devices. BUG=b:169802515 BRANCH=zork Change-Id: I8b306259e205ecb963c0563000bd96ec6b978b8b Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/drivers/wifi/generic/generic.c 1 file changed, 6 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/46028/1 diff --git a/src/drivers/wifi/generic/generic.c b/src/drivers/wifi/generic/generic.c index dd53da3..b175f23 100644 --- a/src/drivers/wifi/generic/generic.c +++ b/src/drivers/wifi/generic/generic.c @@ -4,6 +4,7 @@ #include <acpi/acpigen.h> #include <console/console.h> #include <device/device.h> +#include <device/pci.h> #include <device/pci_def.h> #include <sar.h> #include <string.h> @@ -236,9 +237,11 @@ wifi_generic_fill_ssdt(dev, dev->chip_info); } -static struct device_operations wifi_generic_ops = { - .read_resources = noop_read_resources, - .set_resources = noop_set_resources, +struct device_operations wifi_generic_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .ops_pci = &pci_dev_ops_pci, .acpi_name = wifi_generic_acpi_name, .acpi_fill_ssdt = wifi_generic_fill_ssdt_generator, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/46028 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b306259e205ecb963c0563000bd96ec6b978b8b Gerrit-Change-Number: 46028 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit October 2020