coreboot-gerrit October 2020

coreboot-gerrit@coreboot.org

1 participants
3473 discussions

Change in coreboot[master]: mb/google/rambi: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 08 Oct '20

08 Oct '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46178 ) Change subject: mb/google/rambi: Convert to ASL 2.0 syntax ...................................................................... mb/google/rambi: Convert to ASL 2.0 syntax Change-Id: I0a86b2f55338eb8e7195e847c0052e0352f4e650 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/google/rambi/acpi/mainboard.asl 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/46178/1 diff --git a/src/mainboard/google/rambi/acpi/mainboard.asl b/src/mainboard/google/rambi/acpi/mainboard.asl index 1d0c71e..bfbb66b 100644 --- a/src/mainboard/google/rambi/acpi/mainboard.asl +++ b/src/mainboard/google/rambi/acpi/mainboard.asl @@ -23,7 +23,7 @@ Method (_CRS) { /* Only return interrupt if I2C1 is PCI mode */ - If (LEqual (\S1EN, 0)) { + If (\S1EN == 0) { Return (^RBUF) } @@ -51,7 +51,7 @@ Method (_CRS) { /* Return interrupt if I2C6 is PCI mode */ - If (LEqual (\S6EN, 0)) { + If (\S6EN == 0) { Return (^RBUF) } @@ -93,7 +93,7 @@ Method (_STA) { - If (LEqual (\S2EN, 1)) { + If (\S2EN == 1) { Return (0xF) } Else { Return (0x0) -- To view, visit https://review.coreboot.org/c/coreboot/+/46178 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a86b2f55338eb8e7195e847c0052e0352f4e650 Gerrit-Change-Number: 46178 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: mb/google/glados: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 08 Oct '20

08 Oct '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46173 ) Change subject: mb/google/glados: Convert to ASL 2.0 syntax ...................................................................... mb/google/glados: Convert to ASL 2.0 syntax Change-Id: I7e9f9e9f724efe6db5199a36f01452ac93d4293a Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/google/glados/variants/caroline/include/variant/acpi/mainboard.asl 1 file changed, 4 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/46173/1 diff --git a/src/mainboard/google/glados/variants/caroline/include/variant/acpi/mainboard.asl b/src/mainboard/google/glados/variants/caroline/include/variant/acpi/mainboard.asl index f382e08..2cc694b 100644 --- a/src/mainboard/google/glados/variants/caroline/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/glados/variants/caroline/include/variant/acpi/mainboard.asl @@ -87,18 +87,17 @@ */ Method (_DSM, 4, NotSerialized) { - If (LEqual (Arg0, ToUUID - ("3cdff6f7-4267-4555-ad05-b30a3d8938de"))) { - If (LEqual (Arg2, Zero)) { + If (Arg0 == ToUUID("3cdff6f7-4267-4555-ad05-b30a3d8938de")) { + If (Arg2 == 0) { /* Function 0 - Query */ - If (LEqual (Arg1, One)) { + If (Arg1 == 1) { /* Revision 1 Function 1 */ Return (Buffer (One) { 0x03 }) } Else { /* Revision 2+ not supported */ Return (Buffer (One) { 0x00 }) } - } ElseIf (LEqual (Arg2, One)) { + } ElseIf (Arg2 == 1) { /* Function 1 - HID Descriptor Addr */ Return (0x0001) } Else { -- To view, visit https://review.coreboot.org/c/coreboot/+/46173 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e9f9e9f724efe6db5199a36f01452ac93d4293a Gerrit-Change-Number: 46173 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: mb/google/cyan: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 08 Oct '20

08 Oct '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46172 ) Change subject: mb/google/cyan: Convert to ASL 2.0 syntax ...................................................................... mb/google/cyan: Convert to ASL 2.0 syntax Change-Id: Ic655b26730a9118ecd6c7af0adfead5da2490e0f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/google/cyan/variants/terra/include/variant/acpi/mainboard.asl M src/mainboard/google/cyan/variants/terra/include/variant/acpi/thermal.asl 2 files changed, 15 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/46172/1 diff --git a/src/mainboard/google/cyan/variants/terra/include/variant/acpi/mainboard.asl b/src/mainboard/google/cyan/variants/terra/include/variant/acpi/mainboard.asl index 0bee309..a2a7640 100644 --- a/src/mainboard/google/cyan/variants/terra/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/cyan/variants/terra/include/variant/acpi/mainboard.asl @@ -10,7 +10,8 @@ { Method (GPID, 0, Serialized) // GPID: Get Project ID for Terra2/Terra3 { - And( ShiftRight (\BDID, 3, Local0), 0x01, Local0) + Local0 = \BDID >> 3 + Local0 &= 0x01 Return (Local0) } } diff --git a/src/mainboard/google/cyan/variants/terra/include/variant/acpi/thermal.asl b/src/mainboard/google/cyan/variants/terra/include/variant/acpi/thermal.asl index 1e2d286..94c80da 100644 --- a/src/mainboard/google/cyan/variants/terra/include/variant/acpi/thermal.asl +++ b/src/mainboard/google/cyan/variants/terra/include/variant/acpi/thermal.asl @@ -6,20 +6,20 @@ #if CONFIG(EC_SUPPORTS_DPTF_TEVT) Method (TEVT, 1, NotSerialized) { - Store (ToInteger (Arg0), Local0) + Local0 = ToInteger (Arg0) #ifdef DPTF_TSR0_SENSOR_ID - If (LEqual (Local0, DPTF_TSR0_SENSOR_ID)) { + If (Local0 == DPTF_TSR0_SENSOR_ID) { Notify (^TSR0, 0x90) } #endif #ifdef DPTF_TSR1_SENSOR_ID - If (LEqual (Local0, DPTF_TSR1_SENSOR_ID)) { + If (Local0 == DPTF_TSR1_SENSOR_ID) { Notify (^TSR1, 0x90) } #endif #ifdef DPTF_TSR2_SENSOR_ID - If (LEqual (Local0, DPTF_TSR2_SENSOR_ID)) { + If (Local0 == DPTF_TSR2_SENSOR_ID) { Notify (^TSR2, 0x90) } #endif @@ -52,7 +52,7 @@ Method (_STA) { - If (LEqual (\DPTE, One)) { + If (\DPTE == 1) { Return (0xF) } Else { Return (0x0) @@ -67,7 +67,7 @@ /* Return passive thermal point defined by Terra2 or Terra3 mainboard */ Method (_PSV) { - If (LEqual (\_SB.GPID, TERRA2_PROJECT_ID)) + If (\_SB.GPID == TERRA2_PROJECT_ID) { Return (CTOK (DPTF_TERRA2_TSR0_PASSIVE)) } Else { @@ -78,7 +78,7 @@ /* Return critical thermal point defined by Terra2 or Terra3 mainboard */ Method (_CRT) { - If (LEqual (\_SB.GPID, TERRA2_PROJECT_ID)) + If (\_SB.GPID == TERRA2_PROJECT_ID) { Return (CTOK (DPTF_TERRA2_TSR0_CRITICAL)) } Else { @@ -120,7 +120,7 @@ Method (_STA) { - If (LEqual (\DPTE, One)) { + If (\DPTE == 1) { Return (0xF) } Else { Return (0x0) @@ -135,7 +135,7 @@ /* Return passive thermal point defined by Terra2 or Terra3 mainboard */ Method (_PSV) { - If (LEqual (\_SB.GPID, TERRA2_PROJECT_ID)) + If (\_SB.GPID == TERRA2_PROJECT_ID) { Return (CTOK (DPTF_TERRA2_TSR1_PASSIVE)) } Else { @@ -146,7 +146,7 @@ /* Return critical thermal point defined by Terra2 or Terra3 mainboard */ Method (_CRT) { - If (LEqual (\_SB.GPID, TERRA2_PROJECT_ID)) + If (\_SB.GPID == TERRA2_PROJECT_ID) { Return (CTOK (DPTF_TERRA2_TSR1_CRITICAL)) } Else { @@ -188,7 +188,7 @@ Method (_STA) { - If (LEqual (\DPTE, One)) { + If (\DPTE == 1) { Return (0xF) } Else { Return (0x0) @@ -203,7 +203,7 @@ /* Return passive thermal point defined by Terra2 or Terra3 mainboard */ Method (_PSV) { - If (LEqual (\_SB.GPID, TERRA2_PROJECT_ID)) + If (\_SB.GPID == TERRA2_PROJECT_ID) { Return (CTOK (DPTF_TERRA2_TSR2_PASSIVE)) } Else { @@ -214,7 +214,7 @@ /* Return critical thermal point defined by Terra2 or Terra3 mainboard */ Method (_CRT) { - If (LEqual (\_SB.GPID, TERRA2_PROJECT_ID)) + If (\_SB.GPID == TERRA2_PROJECT_ID) { Return (CTOK (DPTF_TERRA2_TSR2_CRITICAL)) } Else { -- To view, visit https://review.coreboot.org/c/coreboot/+/46172 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic655b26730a9118ecd6c7af0adfead5da2490e0f Gerrit-Change-Number: 46172 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: mb/google/dedede/var/waddledee: Enable GPIO based I2C Multiplexer
by Karthik Ramasubramanian (Code Review) 08 Oct '20

08 Oct '20

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45912 ) Change subject: mb/google/dedede/var/waddledee: Enable GPIO based I2C Multiplexer ...................................................................... Patch Set 6: (1 comment) https://review.coreboot.org/c/coreboot/+/45912/5/src/mainboard/google/deded… File src/mainboard/google/dedede/Kconfig.name: https://review.coreboot.org/c/coreboot/+/45912/5/src/mainboard/google/deded… PS5, Line 54: select DRIVERS_I2C_GPIO_MUX > It should be fine to do this in Kconfig under BOARD_GOOGLE_BASEBOARD_DEDEDE. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/45912 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b09e063b4377587019ade9e6e194f4aadcdd312 Gerrit-Change-Number: 45912 Gerrit-PatchSet: 6 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 08 Oct 2020 07:23:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: drivers/i2c: Add chip driver for GPIO based I2C multiplexer
by Karthik Ramasubramanian (Code Review) 08 Oct '20

08 Oct '20

Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Justin TerAvest, Evan Green, Tim Wawrzynczak, Duncan Laurie, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45911 to look at the new patch set (#6). Change subject: drivers/i2c: Add chip driver for GPIO based I2C multiplexer ...................................................................... drivers/i2c: Add chip driver for GPIO based I2C multiplexer Add identifiers in ACPI tables for GPIO based I2C multiplexer. The multiplexer device defines the GPIO resource used to select the adapter/bus lines. The multiplexer adapter device defines the address to select the adapter/client lines. BUG=b:169444894 TEST=Build and boot waddledee to OS. Ensure that the ACPI identifiers are added for I2C devices multiplexed using I2C MUX under the appropriate scope. Here is the output SSDT: Scope (\_SB.PCI0.I2C3) { Device (MUX0) { Name (_HID, "PRP0001") // _HID: Hardware ID Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly, "\\_SB.PCI0.GPIO", 0x00, ResourceConsumer, , ) { // Pin list 0x0125 } }) Name (_DSD, Package (0x02) // _DSD: Device-Specific Data { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */, Package (0x02) { Package (0x02) { "compatible", "i2c-mux-gpio" }, Package (0x02) { "mux-gpios", Package (0x04) { \_SB.PCI0.I2C3.MUX0, Zero, Zero, Zero } } } }) } } Change-Id: Ib371108cc6043c133681066bf7bf4b2e00771e8b Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- A src/drivers/i2c/gpiomux/Kconfig A src/drivers/i2c/gpiomux/Makefile.inc A src/drivers/i2c/gpiomux/mux/Makefile.inc A src/drivers/i2c/gpiomux/mux/chip.h A src/drivers/i2c/gpiomux/mux/mux.c 5 files changed, 109 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/45911/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/45911 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib371108cc6043c133681066bf7bf4b2e00771e8b Gerrit-Change-Number: 45911 Gerrit-PatchSet: 6 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/google/dedede/var/waddledee: Enable GPIO based I2C Multiplexer
by Karthik Ramasubramanian (Code Review) 08 Oct '20

08 Oct '20

Hello build bot (Jenkins), Furquan Shaikh, Justin TerAvest, Evan Green, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45912 to look at the new patch set (#6). Change subject: mb/google/dedede/var/waddledee: Enable GPIO based I2C Multiplexer ...................................................................... mb/google/dedede/var/waddledee: Enable GPIO based I2C Multiplexer The camera sensor component chosen for UFC and WFC have address conflict. Resolve it by enabling GPIO based I2C Multiplexer BUG=b:169444894 TEST=Build and boot waddledee to OS. Ensure that the ACPI identifiers are added for I2C devices multiplexed using I2C MUX under the appropriate scope. Change-Id: I9b09e063b4377587019ade9e6e194f4aadcdd312 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/dedede/Kconfig M src/mainboard/google/dedede/variants/waddledee/overridetree.cb 2 files changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/45912/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/45912 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b09e063b4377587019ade9e6e194f4aadcdd312 Gerrit-Change-Number: 45912 Gerrit-PatchSet: 6 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/skylake: Configure L1 substates for PCH root ports
by Matt DeVillier (Code Review) 08 Oct '20

08 Oct '20

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39538 ) Change subject: soc/intel/skylake: Configure L1 substates for PCH root ports ...................................................................... Patch Set 25: > Patch Set 25: > > Do you think that L1 substates should be guarded by that Kconfig? it wouldn't hurt to add 'CONFIG(PCIEXP_L1_SUB_STATE) &&' to the front of the if statement -- To view, visit https://review.coreboot.org/c/coreboot/+/39538 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36150858485715016158595c832c142b0582ddb8 Gerrit-Change-Number: 39538 Gerrit-PatchSet: 25 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 08 Oct 2020 06:45:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: util/intelp2m: Add output files to .gitignore
by Maxim Polyakov (Code Review) 08 Oct '20

08 Oct '20

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45870 ) Change subject: util/intelp2m: Add output files to .gitignore ...................................................................... util/intelp2m: Add output files to .gitignore Change-Id: I50a783424b0d244eb824db9cd73738108f800003 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M .gitignore 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/45870/1 diff --git a/.gitignore b/.gitignore index 190d3717..2fabfee 100644 --- a/.gitignore +++ b/.gitignore @@ -105,6 +105,8 @@ util/intelmetool/intelmetool util/inteltool/.dependencies util/inteltool/inteltool +util/intelp2m/intelp2m +util/intelp2m/generate/gpio.h util/intelvbttool/intelvbttool util/msrtool/Makefile util/msrtool/Makefile.deps -- To view, visit https://review.coreboot.org/c/coreboot/+/45870 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50a783424b0d244eb824db9cd73738108f800003 Gerrit-Change-Number: 45870 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: mb/intel/adlrvp: Add initial ADL-P mainboard code
by Subrata Banik (Code Review) 08 Oct '20

08 Oct '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46054 ) Change subject: mb/intel/adlrvp: Add initial ADL-P mainboard code ...................................................................... mb/intel/adlrvp: Add initial ADL-P mainboard code List of changes: 1. Initial code block to select SOC_INTEL_ALDERLAKE Kconfig 2. Add minimum code to make ADL-P RVP build successfully 3. Mainly bootblock and verstage code added to reach till verstage TEST=Able to build and boot ADL-P RVP till romstage early. Change-Id: I2b551f48a4eb4d621d9a86c5d189c517d5610069 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- A src/mainboard/intel/adlrvp/Kconfig A src/mainboard/intel/adlrvp/Kconfig.name A src/mainboard/intel/adlrvp/Makefile.inc A src/mainboard/intel/adlrvp/board_info.txt A src/mainboard/intel/adlrvp/bootblock.c A src/mainboard/intel/adlrvp/chromeos.c A src/mainboard/intel/adlrvp/chromeos.fmd A src/mainboard/intel/adlrvp/dsdt.asl A src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc A src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb A src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c A src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/ec.h A src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/gpio.h A src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h 14 files changed, 470 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/46054/1 diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig new file mode 100644 index 0000000..5183886 --- /dev/null +++ b/src/mainboard/intel/adlrvp/Kconfig @@ -0,0 +1,84 @@ +if BOARD_INTEL_ADLRVP_P + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_32768 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select MAINBOARD_HAS_CHROMEOS + select DRIVERS_I2C_HID + select DRIVERS_I2C_GENERIC + select DRIVERS_INTEL_SOUNDWIRE + select DRIVERS_USB_ACPI + select DRIVERS_SPI_ACPI + select GENERATE_SMBIOS_TABLES + select SOC_INTEL_ALDERLAKE + select MAINBOARD_USES_IFD_EC_REGION + select DRIVERS_UART_8250IO + +config CHROMEOS + bool + default y + select GBB_FLAG_FORCE_DEV_SWITCH_ON + select GBB_FLAG_FORCE_DEV_BOOT_USB + select GBB_FLAG_FORCE_MANUAL_RECOVERY + +config MAINBOARD_DIR + string + default "intel/adlrvp" + +config VARIANT_DIR + string + default "adlrvp_p" + +config GBB_HWID + string + depends on CHROMEOS + default "ADLRVPP" + +config MAINBOARD_PART_NUMBER + string + default "adlrvp" + +config MAINBOARD_FAMILY + string + default "Intel_adlrvp" + +config DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + +config DIMM_SPD_SIZE + int + default 512 + +choice ADL_EC + prompt "ON BOARD EC" + default ADL_INTEL_EC + help + This option allows you to select the on board EC to use. + Select whether the board has Intel EC or Chrome EC + +config ADL_CHROME_EC + bool "Chrome EC" + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_ESPI + select EC_GOOGLE_CHROMEEC_BOARDID + select EC_ACPI + +config ADL_INTEL_EC + bool "Intel EC" + select EC_ACPI + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC +endchoice + +config VBOOT + select VBOOT_LID_SWITCH + select VBOOT_MOCK_SECDATA + select HAS_RECOVERY_MRC_CACHE + select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN + +config UART_FOR_CONSOLE + int + default 0 +endif diff --git a/src/mainboard/intel/adlrvp/Kconfig.name b/src/mainboard/intel/adlrvp/Kconfig.name new file mode 100644 index 0000000..4bf0d89 --- /dev/null +++ b/src/mainboard/intel/adlrvp/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_INTEL_ADLRVP_P + bool "Alderlake-P RVP" diff --git a/src/mainboard/intel/adlrvp/Makefile.inc b/src/mainboard/intel/adlrvp/Makefile.inc new file mode 100644 index 0000000..7422a7a --- /dev/null +++ b/src/mainboard/intel/adlrvp/Makefile.inc @@ -0,0 +1,14 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c +bootblock-$(CONFIG_CHROMEOS) += chromeos.c + +verstage-$(CONFIG_CHROMEOS) += chromeos.c + +romstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c +subdirs-y += ../common +subdirs-y += variants/baseboard +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include + +subdirs-y += variants/$(VARIANT_DIR) diff --git a/src/mainboard/intel/adlrvp/board_info.txt b/src/mainboard/intel/adlrvp/board_info.txt new file mode 100644 index 0000000..be99df8 --- /dev/null +++ b/src/mainboard/intel/adlrvp/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Intel +Board name: Alderlake rvp +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/intel/adlrvp/bootblock.c b/src/mainboard/intel/adlrvp/bootblock.c new file mode 100644 index 0000000..a8f7e41 --- /dev/null +++ b/src/mainboard/intel/adlrvp/bootblock.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <bootblock_common.h> +#include <soc/gpio.h> + +void bootblock_mainboard_init(void) +{ + const struct pad_config *pads; + size_t num; + + pads = variant_early_gpio_table(&num); + gpio_configure_pads(pads, num); +} diff --git a/src/mainboard/intel/adlrvp/chromeos.c b/src/mainboard/intel/adlrvp/chromeos.c new file mode 100644 index 0000000..d963c73 --- /dev/null +++ b/src/mainboard/intel/adlrvp/chromeos.c @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <boot/coreboot_tables.h> +#include <gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio chromeos_gpios[] = { + {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, + {-1, ACTIVE_HIGH, 0, "power"}, + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + {-1, ACTIVE_HIGH, 0, "EC in RW"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); +} + +#if !CONFIG(EC_GOOGLE_CHROMEEC_SWITCHES) +int get_lid_switch(void) +{ + /* Lid always open */ + return 1; +} + +int get_recovery_mode_switch(void) +{ + return 0; +} +#endif /*!CONFIG(EC_GOOGLE_CHROMEEC_SWITCHES) */ + +int get_write_protect_state(void) +{ + /* No write protect */ + return 0; +} + +void mainboard_chromeos_acpi_generate(void) +{ + const struct cros_gpio *gpios; + size_t num; + + gpios = variant_cros_gpios(&num); + chromeos_acpi_gpio_generate(gpios, num); +} diff --git a/src/mainboard/intel/adlrvp/chromeos.fmd b/src/mainboard/intel/adlrvp/chromeos.fmd new file mode 100644 index 0000000..183f1c1 --- /dev/null +++ b/src/mainboard/intel/adlrvp/chromeos.fmd @@ -0,0 +1,44 @@ +FLASH@0xfe000000 0x2000000 { + SI_ALL@0x0 0x1081000 { + SI_DESC@0x0 0x1000 + SI_EC@0x1000 0x80000 + SI_ME@0x81000 0x1000000 + } + SI_BIOS@0x1400000 0xc00000 { + RW_SECTION_A@0x0 0x368000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x357fc0 + RW_FWID_A@0x367fc0 0x40 + } + RW_SECTION_B@0x368000 0x368000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x357fc0 + RW_FWID_B@0x367fc0 0x40 + } + RW_MISC@0x6D0000 0x30000 { + UNIFIED_MRC_CACHE@0x0 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_ELOG(PRESERVE)@0x20000 0x4000 + RW_SHARED@0x24000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD(PRESERVE)@0x28000 0x2000 + RW_NVRAM(PRESERVE)@0x2a000 0x6000 + } + # RW_LEGACY needs to be minimum of 1MB + RW_LEGACY(CBFS)@0x700000 0x100000 + WP_RO@0x800000 0x400000 { + RO_VPD(PRESERVE)@0x0 0x4000 + RO_SECTION@0x4000 0x3fc000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0x3000 + COREBOOT(CBFS)@0x4000 0x3f8000 + } + } + } +} diff --git a/src/mainboard/intel/adlrvp/dsdt.asl b/src/mainboard/intel/adlrvp/dsdt.asl new file mode 100644 index 0000000..b758973 --- /dev/null +++ b/src/mainboard/intel/adlrvp/dsdt.asl @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <baseboard/ec.h> +#include <baseboard/gpio.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI v2.0 and up */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 /* OEM revision */ +) +{ + +} diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc b/src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc new file mode 100644 index 0000000..756de4d --- /dev/null +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c + + diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb new file mode 100644 index 0000000..16f97bf --- /dev/null +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb @@ -0,0 +1,111 @@ +chip soc/intel/alderlake + + device cpu_cluster 0 on + device lapic 0 on end + end + + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + register "gen4_dec" = "0x000c0081" + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Graphics + device pci 04.0 on end # DPTF + device pci 05.0 on end # IPU + device pci 06.0 on end # PEG60 + device pci 07.0 off end # TBT_PCIe0 + device pci 07.1 off end # TBT_PCIe1 + device pci 07.2 off end # TBT_PCIe2 + device pci 07.3 off end # TBT_PCIe3 + device pci 08.0 off end # GNA + device pci 09.0 off end # NPK + device pci 0a.0 off end # Crash-log SRAM + device pci 0d.0 on end # USB xHCI + device pci 0d.1 off end # USB xDCI (OTG) + device pci 0d.2 off end # TBT DMA0 + device pci 0d.3 off end # TBT DMA1 + device pci 0e.0 off end # VMD + device pci 10.0 off end + device pci 10.1 off end + device pci 10.2 on end # CNVi: BT + device pci 10.6 off end # THC0 + device pci 10.7 off end # THC1 + device pci 11.0 off end + device pci 11.1 off end + device pci 11.2 off end + device pci 11.3 off end + device pci 11.4 off end + device pci 11.5 off end + device pci 12.0 off end # SensorHUB + device pci 12.5 off end + device pci 12.6 off end # GSPI2 + device pci 13.0 off end # GSPI3 + device pci 13.1 off end + device pci 14.0 on + chip drivers/usb/acpi + register "desc" = ""Root Hub"" + register "type" = "UPC_TYPE_HUB" + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.9 on end + end + end + end + end # USB3.1 xHCI + device pci 14.1 off end # USB3.1 xDCI + device pci 14.2 off end # Shared RAM + chip drivers/intel/wifi + register "wake" = "GPE0_PME_B0" + device pci 14.3 on end # CNVi: WiFi + end + device pci 15.0 on end # I2C0 + device pci 15.1 on end # I2C1 + device pci 15.2 on end # I2C2 + device pci 15.3 on end # I2C3 + device pci 16.0 on end # HECI1 + device pci 16.1 off end # HECI2 + device pci 16.2 off end # CSME + device pci 16.3 off end # CSME + device pci 16.4 off end # HECI3 + device pci 16.5 off end # HECI4 + device pci 17.0 on end # SATA + device pci 19.0 off end # I2C4 + device pci 19.1 on end # I2C5 + device pci 19.2 on end # UART2 + device pci 1c.0 on end # RP1 + device pci 1c.1 on end # RP2 + device pci 1c.2 on end # RP3 + device pci 1c.3 on end # RP4 + device pci 1c.4 on end # RP5 + device pci 1c.5 on end # RP6 + device pci 1c.6 on end # RP7 + device pci 1c.7 on end # RP8 + device pci 1d.0 on end # RP9 + device pci 1d.1 on end # RP10 + device pci 1d.2 on end # RP11 + device pci 1d.3 on end # RP12 + device pci 1e.0 off end # UART0 + device pci 1e.1 off end # UART1 + device pci 1e.2 off end # GSPI0 + device pci 1e.3 off end # GSPI1 + device pci 1f.0 on end # eSPI + device pci 1f.1 on end # P2SB + device pci 1f.2 hidden end # PMC + device pci 1f.3 on + chip drivers/intel/soundwire + device generic 0 on + end + end + end # Intel Audio SNDW + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # SPI + device pci 1f.6 off end # GbE + device pci 1f.7 off end # TH + end +end diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c b/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c new file mode 100644 index 0000000..4e3ff8d --- /dev/null +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* WWAN_RST# */ + PAD_CFG_GPO(GPP_E10, 0, PLTRST), + /* WWAN_PWR_EN */ + PAD_CFG_GPO(GPP_E13, 1, DEEP), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/ec.h b/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/ec.h new file mode 100644 index 0000000..4303faf --- /dev/null +++ b/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/ec.h @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __BASEBOARD_EC_H__ +#define __BASEBOARD_EC_H__ + +#include <ec/ec.h> +#include <ec/google/chromeec/ec_commands.h> +#include <baseboard/gpio.h> + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX)) + +#define MAINBOARD_EC_SMI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) + +/* EC can wake from S5 with lid or power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) + +/* + * EC can wake from S3 with lid or power button or key press or + * mode change event. + */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) + +#define MAINBOARD_EC_S0IX_WAKE_EVENTS (MAINBOARD_EC_S3_WAKE_EVENTS) + +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) + +/* + * ACPI related definitions for ASL code. + */ + +/* Enable EC backed ALS device in ACPI */ +#define EC_ENABLE_ALS_DEVICE + +/* Enable EC sync interrupt, EC_SYNC_IRQ is defined in baseboard/gpio.h */ +#define EC_ENABLE_SYNC_IRQ + +/* Enable EC backed PD MCU device in ACPI */ +#define EC_ENABLE_PD_MCU_DEVICE + +/* Enable LID switch and provide wake pin for EC */ +#define EC_ENABLE_LID_SWITCH +#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE + +#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ +#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ +#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ + +#endif /* __BASEBOARD_EC_H__ */ diff --git a/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/gpio.h new file mode 100644 index 0000000..b61276c --- /dev/null +++ b/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/gpio.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __BASEBOARD_GPIO_H__ +#define __BASEBOARD_GPIO_H__ + +#include <soc/gpe.h> +#include <soc/gpio.h> + +/* eSPI virtual wire reporting */ +#define EC_SCI_GPI GPE0_ESPI + +/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ +#define GPE_EC_WAKE GPE0_LAN_WAK + +/* EC sync IRQ */ +#define EC_SYNC_IRQ GPP_A15_IRQ + +#endif /* __BASEBOARD_GPIO_H__ */ diff --git a/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h new file mode 100644 index 0000000..4e6001d --- /dev/null +++ b/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __BASEBOARD_VARIANTS_H__ +#define __BASEBOARD_VARIANTS_H__ + +#include <soc/gpio.h> +#include <stdint.h> +#include <vendorcode/google/chromeos/chromeos.h> + +/* The next set of functions return the gpio table and fill in the number of + * entries for each table. */ + +const struct pad_config *variant_early_gpio_table(size_t *num); +const struct cros_gpio *variant_cros_gpios(size_t *num); + +#endif /*__BASEBOARD_VARIANTS_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/46054 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b551f48a4eb4d621d9a86c5d189c517d5610069 Gerrit-Change-Number: 46054 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

3 23

Change in coreboot[master]: mb/intel/{jslrvp,tglrvp}: Remove non-existent 'subdirs-y += ../common'
by Subrata Banik (Code Review) 08 Oct '20

08 Oct '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46123 ) Change subject: mb/intel/{jslrvp,tglrvp}: Remove non-existent 'subdirs-y += ../common' ...................................................................... mb/intel/{jslrvp,tglrvp}: Remove non-existent 'subdirs-y += ../common' TEST=Able to build TGLRVP and JSLRVP. Change-Id: Ie07df9f59015092a4c2a27b1451f0d556c70f0d8 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/mainboard/intel/jasperlake_rvp/Makefile.inc M src/mainboard/intel/tglrvp/Makefile.inc 2 files changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/46123/1 diff --git a/src/mainboard/intel/jasperlake_rvp/Makefile.inc b/src/mainboard/intel/jasperlake_rvp/Makefile.inc index a1cd12c..2ac1b07 100644 --- a/src/mainboard/intel/jasperlake_rvp/Makefile.inc +++ b/src/mainboard/intel/jasperlake_rvp/Makefile.inc @@ -17,7 +17,6 @@ smm-y += smihandler.c -subdirs-y += ../common subdirs-y += variants/baseboard CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include diff --git a/src/mainboard/intel/tglrvp/Makefile.inc b/src/mainboard/intel/tglrvp/Makefile.inc index cba1909..2ca32f3 100644 --- a/src/mainboard/intel/tglrvp/Makefile.inc +++ b/src/mainboard/intel/tglrvp/Makefile.inc @@ -18,7 +18,6 @@ ramstage-y += mainboard.c ramstage-y += board_id.c -subdirs-y += ../common subdirs-y += variants/baseboard CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include -- To view, visit https://review.coreboot.org/c/coreboot/+/46123 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie07df9f59015092a4c2a27b1451f0d556c70f0d8 Gerrit-Change-Number: 46123 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

3 3

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit October 2020