coreboot-gerrit October 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/jasperlake: Correct SaGv mapping
by Tim Wawrzynczak (Code Review) 08 Oct '20

08 Oct '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45195 ) Change subject: soc/intel/jasperlake: Correct SaGv mapping ...................................................................... Patch Set 2: Code-Review+2 Was this just missed when the TGL/JSL split happened? -- To view, visit https://review.coreboot.org/c/coreboot/+/45195 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I366de1ea7cf41c56b2954b8032c69bfba81058e2 Gerrit-Change-Number: 45195 Gerrit-PatchSet: 2 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Comment-Date: Thu, 08 Oct 2020 16:34:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/i2c: Add chip driver for GPIO based I2C multiplexer
by Evan Green (Code Review) 08 Oct '20

08 Oct '20

Evan Green has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45911 ) Change subject: drivers/i2c: Add chip driver for GPIO based I2C multiplexer ...................................................................... Patch Set 6: (1 comment) https://review.coreboot.org/c/coreboot/+/45911/6/src/drivers/i2c/gpiomux/mu… File src/drivers/i2c/gpiomux/mux/mux.c: https://review.coreboot.org/c/coreboot/+/45911/6/src/drivers/i2c/gpiomux/mu… PS6, Line 37: "_HID", ACPI_DT_NAMESPACE_HID) Wait but if you do this and use PRP0001, aren't you deferring into the DT world entirely, including its bindings? We're not following the DT-based bindings exactly (around i2c-parent). Don't we need an ACPI-based _HID so we can say "this is the ACPI version"? -- To view, visit https://review.coreboot.org/c/coreboot/+/45911 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib371108cc6043c133681066bf7bf4b2e00771e8b Gerrit-Change-Number: 45911 Gerrit-PatchSet: 6 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 08 Oct 2020 16:16:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Replace soc_get_pmc_mux_device with device pointers
by Tim Wawrzynczak (Code Review) 08 Oct '20

08 Oct '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45747 ) Change subject: soc/intel/tigerlake: Replace soc_get_pmc_mux_device with device pointers ...................................................................... Patch Set 4: (2 comments) https://review.coreboot.org/c/coreboot/+/45747/1/src/mainboard/google/volte… File src/mainboard/google/volteer/variants/baseboard/devicetree.cb: https://review.coreboot.org/c/coreboot/+/45747/1/src/mainboard/google/volte… PS1, Line 403: device ref south_xhci on end > note to self: oops, this should stay Done https://review.coreboot.org/c/coreboot/+/45747/1/src/mainboard/google/volte… File src/mainboard/google/volteer/variants/volteer/overridetree.cb: https://review.coreboot.org/c/coreboot/+/45747/1/src/mainboard/google/volte… PS1, Line 183: : use dev1 as conn1; > C makes it hard not to end lines with semicolons sometimes... Done -- To view, visit https://review.coreboot.org/c/coreboot/+/45747 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie00834c79bd5304998adaccb388ae74a108192b1 Gerrit-Change-Number: 45747 Gerrit-PatchSet: 4 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 08 Oct 2020 15:42:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/xeon_sp/cpx: Add locking of IA32_FEATURE_CONTROL and VMX
by Christian Walter (Code Review) 08 Oct '20

08 Oct '20

Christian Walter has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45869 ) Change subject: soc/intel/xeon_sp/cpx: Add locking of IA32_FEATURE_CONTROL and VMX ...................................................................... soc/intel/xeon_sp/cpx: Add locking of IA32_FEATURE_CONTROL and VMX Change-Id: Ib329648f77acecccb0ced1806f61be252d03f2f4 Signed-off-by: Christian Walter <christian.walter(a)9elements.com> --- M src/soc/intel/xeon_sp/cpx/cpu.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/45869/1 diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c index eb8c0eb..0999f6d 100644 --- a/src/soc/intel/xeon_sp/cpx/cpu.c +++ b/src/soc/intel/xeon_sp/cpx/cpu.c @@ -16,6 +16,7 @@ #include <soc/msr.h> #include <soc/soc_util.h> #include "chip.h" +#include <cpu/intel/common/common.h> static const void *microcode_patch; @@ -91,6 +92,9 @@ /* Clear out pending MCEs */ xeon_configure_mca(); + + /* Enable Vmx */ + set_vmx_and_lock(); } static struct device_operations cpu_dev_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/45869 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib329648f77acecccb0ced1806f61be252d03f2f4 Gerrit-Change-Number: 45869 Gerrit-PatchSet: 1 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: security/intel/txt: Style fixes
by Christian Walter (Code Review) 08 Oct '20

08 Oct '20

Christian Walter has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45867 ) Change subject: security/intel/txt: Style fixes ...................................................................... security/intel/txt: Style fixes Fix two style issues. First one is to align the #define in txt_registers.h, the second one prints the chipset as hex to make it more readable. Change-Id: Ifafbe0a1161e9fe6e790692002375f45d813b723 Signed-off-by: Christian Walter <christian.walter(a)9elements.com> --- M src/security/intel/txt/logging.c M src/security/intel/txt/txt_register.h 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/45867/1 diff --git a/src/security/intel/txt/logging.c b/src/security/intel/txt/logging.c index cf14b55..f329cf9 100644 --- a/src/security/intel/txt/logging.c +++ b/src/security/intel/txt/logging.c @@ -141,7 +141,7 @@ printk(BIOS_INFO, " Header: v%u.%u\n", acm_header->header_version[0], acm_header->header_version[1]); - printk(BIOS_INFO, " Chipset: %u\n", acm_header->chipset_id); + printk(BIOS_INFO, " Chipset: %x\n", acm_header->chipset_id); printk(BIOS_INFO, " Size: %zu\n", acm_size); switch (acm_header->flags) { diff --git a/src/security/intel/txt/txt_register.h b/src/security/intel/txt/txt_register.h index c7f1575..bf087de 100644 --- a/src/security/intel/txt/txt_register.h +++ b/src/security/intel/txt/txt_register.h @@ -23,7 +23,7 @@ */ #define TXT_ESTS_WAKE_ERROR_STS (1 << 6) -#define TXT_ERROR (TXT_BASE + 0x30) +#define TXT_ERROR (TXT_BASE + 0x30) #define ACMERROR_TXT_VALID (1ul << 31) #define ACMERROR_TXT_EXTERNAL (1ul << 30) -- To view, visit https://review.coreboot.org/c/coreboot/+/45867 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifafbe0a1161e9fe6e790692002375f45d813b723 Gerrit-Change-Number: 45867 Gerrit-PatchSet: 1 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer: add mainboard_supports_usb4()
by Nick Vaccaro (Code Review) 08 Oct '20

08 Oct '20

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45946 ) Change subject: mb/google/volteer: add mainboard_supports_usb4() ...................................................................... mb/google/volteer: add mainboard_supports_usb4() Implement mainboard_supports_usb4() to allow soc code to disable the USB4/TBT in the cases where we're on SKUs without USB4 hardware. BUG=b:167983038 TEST=none Change-Id: Iab23c07e15f754ca807f128b9edad7fdc9a44b9d Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/volteer/Makefile.inc A src/mainboard/google/volteer/mainboard_support.c 2 files changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/45946/1 diff --git a/src/mainboard/google/volteer/Makefile.inc b/src/mainboard/google/volteer/Makefile.inc index c01f993..d07588b 100644 --- a/src/mainboard/google/volteer/Makefile.inc +++ b/src/mainboard/google/volteer/Makefile.inc @@ -4,12 +4,14 @@ bootblock-y += bootblock.c romstage-$(CONFIG_CHROMEOS) += chromeos.c +romstage-y += mainboard_support.c romstage-y += romstage.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += ec.c ramstage-$(CONFIG_FW_CONFIG) += fw_config.c ramstage-y += mainboard.c +ramstage-y += mainboard_support.c smm-y += smihandler.c diff --git a/src/mainboard/google/volteer/mainboard_support.c b/src/mainboard/google/volteer/mainboard_support.c new file mode 100644 index 0000000..9be2e51 --- /dev/null +++ b/src/mainboard/google/volteer/mainboard_support.c @@ -0,0 +1,8 @@ +#include <soc/mainboard_support.h> +#include <fw_config.h> + +bool mainboard_supports_usb4(void) +{ + return (fw_config_probe(FW_CONFIG(DB_USB, USB4_GEN2)) || + fw_config_probe(FW_CONFIG(DB_USB, USB4_GEN3))); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/45946 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab23c07e15f754ca807f128b9edad7fdc9a44b9d Gerrit-Change-Number: 45946 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: lib/fw_config: change BOOT_STATE_INIT_ENTRY to be BS_DEV_INIT_CHIPS
by Nick Vaccaro (Code Review) 08 Oct '20

08 Oct '20

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45961 ) Change subject: lib/fw_config: change BOOT_STATE_INIT_ENTRY to be BS_DEV_INIT_CHIPS ...................................................................... lib/fw_config: change BOOT_STATE_INIT_ENTRY to be BS_DEV_INIT_CHIPS Make boot state init run before the init_chips code. This allows for correcting tbt settings at a stage earlier than devicetree parsing. BUG=b:167983038 TEST=none Change-Id: I8364746ba311575e7de93fa25241ffef7faf35b4 Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/lib/fw_config.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/45961/1 diff --git a/src/lib/fw_config.c b/src/lib/fw_config.c index fdfab0a..ec32059 100644 --- a/src/lib/fw_config.c +++ b/src/lib/fw_config.c @@ -127,5 +127,5 @@ } } } -BOOT_STATE_INIT_ENTRY(BS_DEV_ENUMERATE, BS_ON_ENTRY, fw_config_init, NULL); +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_ENTRY, fw_config_init, NULL); #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/45961 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8364746ba311575e7de93fa25241ffef7faf35b4 Gerrit-Change-Number: 45961 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/ocp/deltalake: Override smbios_fill_dimm_locator for type 17
by Angel Pons (Code Review) 08 Oct '20

08 Oct '20

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45799 ) Change subject: mb/ocp/deltalake: Override smbios_fill_dimm_locator for type 17 ...................................................................... mb/ocp/deltalake: Override smbios_fill_dimm_locator for type 17 Override smbios_fill_dimm_locator for type 17 Locator and Bank Locator. Also remove CONFIG(GENERATE_SMBIOS_TABLES) compile option because SMBIOS is always enabled and it makes the code cleaner. One sample type 17 table displayed as below: Handle 0x0010, DMI type 17, 40 bytes Memory Device ... Locator: DIMM F0 Bank Locator: _Node0_Channel5_Dimm0 Tested=On OCP Delta Lake, the Locator and Bank Locator strings are expected. Change-Id: I84531f9ee8bc76d9529aa983bc13e64f40c93138 Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45799 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/ocp/deltalake/ramstage.c 1 file changed, 11 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/ocp/deltalake/ramstage.c b/src/mainboard/ocp/deltalake/ramstage.c index e00f1c3..c03ad68 100644 --- a/src/mainboard/ocp/deltalake/ramstage.c +++ b/src/mainboard/ocp/deltalake/ramstage.c @@ -128,7 +128,6 @@ } } -#if CONFIG(GENERATE_SMBIOS_TABLES) static int create_smbios_type9(int *handle, unsigned long *current) { int index; @@ -234,7 +233,17 @@ return len; } -#endif + +void smbios_fill_dimm_locator(const struct dimm_info *dimm, struct smbios_type17 *t) +{ + char buf[40]; + + snprintf(buf, sizeof(buf), "DIMM %c0", 'A' + dimm->channel_num); + t->device_locator = smbios_add_string(t->eos, buf); + + snprintf(buf, sizeof(buf), "_Node0_Channel%d_Dimm0", dimm->channel_num); + t->bank_locator = smbios_add_string(t->eos, buf); +} unsigned int smbios_processor_family(struct cpuid_result res) { @@ -251,9 +260,7 @@ { dev->ops->get_smbios_strings = dl_oem_smbios_strings, read_fru_areas(CONFIG_BMC_KCS_BASE, CONFIG_FRU_DEVICE_ID, 0, &fru_strings); -#if (CONFIG(GENERATE_SMBIOS_TABLES)) dev->ops->get_smbios_data = mainboard_smbios_data; -#endif } void mainboard_silicon_init_params(FSPS_UPD *params) -- To view, visit https://review.coreboot.org/c/coreboot/+/45799 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I84531f9ee8bc76d9529aa983bc13e64f40c93138 Gerrit-Change-Number: 45799 Gerrit-PatchSet: 13 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: John Looney <john.looney(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/xeon_sp/cpx: Add save_dimm_info for SMBIOS type 17
by Angel Pons (Code Review) 08 Oct '20

08 Oct '20

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45798 ) Change subject: soc/intel/xeon_sp/cpx: Add save_dimm_info for SMBIOS type 17 ...................................................................... soc/intel/xeon_sp/cpx: Add save_dimm_info for SMBIOS type 17 For now only implement for one socket and some of the fields are hard-coded for DDR4 including memory device type, data width and ECC support. Change-Id: I3cb72d18027d972140828970206834ff55b72022 Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45798 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang(a)fb.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/xeon_sp/cpx/Makefile.inc A src/soc/intel/xeon_sp/cpx/ddr.c A src/soc/intel/xeon_sp/cpx/include/soc/ddr.h M src/soc/intel/xeon_sp/cpx/romstage.c M src/soc/intel/xeon_sp/include/soc/romstage.h M src/soc/intel/xeon_sp/romstage.c 6 files changed, 229 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Jonathan Zhang: Looks good to me, but someone else must approve diff --git a/src/soc/intel/xeon_sp/cpx/Makefile.inc b/src/soc/intel/xeon_sp/cpx/Makefile.inc index b1fcd04..79a83b5 100644 --- a/src/soc/intel/xeon_sp/cpx/Makefile.inc +++ b/src/soc/intel/xeon_sp/cpx/Makefile.inc @@ -8,7 +8,7 @@ subdirs-y += ../../../../cpu/x86/tsc subdirs-y += ../../../../cpu/intel/microcode -romstage-y += romstage.c +romstage-y += romstage.c ddr.c romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c diff --git a/src/soc/intel/xeon_sp/cpx/ddr.c b/src/soc/intel/xeon_sp/cpx/ddr.c new file mode 100644 index 0000000..0fa36ab --- /dev/null +++ b/src/soc/intel/xeon_sp/cpx/ddr.c @@ -0,0 +1,84 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <soc/ddr.h> + +uint32_t get_ddr_voltage(uint8_t DdrVoltage) +{ + /* SPD Byte 11: Module Nominal Voltage, currently DDR4 only supports 1.2V. + Either Bit 0 or Bit 1 is set, return 1.2V */ + if (DdrVoltage & 0x3) + return 1200; + return 0; +} + +uint16_t get_max_memory_speed(uint32_t commonTck) +{ + if (commonTck <= DDR_8400_TCK_MIN) + return 8400; + else if (commonTck <= DDR_6400_TCK_MIN) + return 6400; + else if (commonTck <= DDR_6000_TCK_MIN) + return 6000; + else if (commonTck <= DDR_5600_TCK_MIN) + return 5600; + else if (commonTck <= DDR_5200_TCK_MIN) + return 5200; + else if (commonTck <= DDR_4800_TCK_MIN) + return 4800; + else if (commonTck <= DDR_4400_TCK_MIN) + return 4400; + else if (commonTck <= DDR_4266_TCK_MIN) + return 4266; + else if (commonTck <= DDR_4200_TCK_MIN) + return 4200; + else if (commonTck <= DDR_4000_TCK_MIN) + return 4000; + else if (commonTck <= DDR_3800_TCK_MIN) + return 3800; + else if (commonTck <= DDR_3733_TCK_MIN) + return 3733; + else if (commonTck <= DDR_3600_TCK_MIN) + return 3600; + else if (commonTck <= DDR_3466_TCK_MIN) + return 3466; + else if (commonTck <= DDR_3400_TCK_MIN) + return 3400; + else if (commonTck <= DDR_3200_TCK_MIN) + return 3200; + else if (commonTck <= DDR_3000_TCK_MIN) + return 3000; + else if (commonTck <= DDR_2933_TCK_MIN) + return 2933; + else if (commonTck <= DDR_2800_TCK_MIN) + return 2800; + else if (commonTck <= DDR_2666_TCK_MIN) + return 2666; + else if (commonTck <= DDR_2600_TCK_MIN) + return 2600; + else if (commonTck <= DDR_2400_TCK_MIN) + return 2400; + else if (commonTck <= DDR_2200_TCK_MIN) + return 2200; + else if (commonTck <= DDR_2133_TCK_MIN) + return 2133; + else if (commonTck <= DDR_2000_TCK_MIN) + return 2000; + else if (commonTck <= DDR_1866_TCK_MIN) + return 1866; + else if (commonTck <= DDR_1800_TCK_MIN) + return 1800; + else if (commonTck <= DDR_1600_TCK_MIN) + return 1600; + else if (commonTck <= DDR_1400_TCK_MIN) + return 1400; + else if (commonTck <= DDR_1333_TCK_MIN) + return 1333; + else if (commonTck <= DDR_1200_TCK_MIN) + return 1200; + else if (commonTck <= DDR_1066_TCK_MIN) + return 1066; + else if (commonTck <= DDR_1000_TCK_MIN) + return 1000; + else + return 800; +} diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/ddr.h b/src/soc/intel/xeon_sp/cpx/include/soc/ddr.h new file mode 100644 index 0000000..61a5ebe --- /dev/null +++ b/src/soc/intel/xeon_sp/cpx/include/soc/ddr.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef _CPX_DDR_H_ +#define _CPX_DDR_H_ + +#include <stdint.h> + +/* DDR_*_TCK_MIN are in picoseconds */ +#define DDR_800_TCK_MIN 2500 +#define DDR_1000_TCK_MIN 2000 +#define DDR_1066_TCK_MIN 1875 +#define DDR_1200_TCK_MIN 1667 +#define DDR_1333_TCK_MIN 1500 +#define DDR_1400_TCK_MIN 1429 +#define DDR_1600_TCK_MIN 1250 +#define DDR_1800_TCK_MIN 1110 +#define DDR_1866_TCK_MIN 1071 +#define DDR_2000_TCK_MIN 1000 +#define DDR_2133_TCK_MIN 938 +#define DDR_2200_TCK_MIN 909 +#define DDR_2400_TCK_MIN 833 +#define DDR_2600_TCK_MIN 769 +#define DDR_2666_TCK_MIN 750 +#define DDR_2800_TCK_MIN 714 +#define DDR_2933_TCK_MIN 682 +#define DDR_3000_TCK_MIN 667 +#define DDR_3200_TCK_MIN 625 +#define DDR_3400_TCK_MIN 589 +#define DDR_3466_TCK_MIN 577 +#define DDR_3600_TCK_MIN 556 +#define DDR_3733_TCK_MIN 536 +#define DDR_3800_TCK_MIN 527 +#define DDR_4000_TCK_MIN 500 +#define DDR_4200_TCK_MIN 477 +#define DDR_4266_TCK_MIN 469 +#define DDR_4400_TCK_MIN 455 +#define DDR_4800_TCK_MIN 417 +#define DDR_5200_TCK_MIN 385 +#define DDR_5600_TCK_MIN 358 +#define DDR_6000_TCK_MIN 334 +#define DDR_6400_TCK_MIN 313 +#define DDR_6800_TCK_MIN 295 +#define DDR_7200_TCK_MIN 278 +#define DDR_7600_TCK_MIN 264 +#define DDR_8000_TCK_MIN 250 +#define DDR_8400_TCK_MIN 239 + +uint16_t get_max_memory_speed(uint32_t commonTck); +uint32_t get_ddr_voltage(uint8_t DdrVoltage); + +#endif /* _CPX_DDR_H_ */ diff --git a/src/soc/intel/xeon_sp/cpx/romstage.c b/src/soc/intel/xeon_sp/cpx/romstage.c index a198c99..6f47a30 100644 --- a/src/soc/intel/xeon_sp/cpx/romstage.c +++ b/src/soc/intel/xeon_sp/cpx/romstage.c @@ -1,9 +1,19 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <assert.h> #include <arch/romstage.h> +#include <console/console.h> +#include <cbmem.h> #include <fsp/api.h> +#include <fsp/util.h> +#include <hob_iiouds.h> +#include <hob_memmap.h> +#include <soc/ddr.h> #include <soc/romstage.h> #include <soc/pci_devs.h> +#include <soc/intel/common/smbios.h> +#include <string.h> + #include "chip.h" void __weak mainboard_memory_init_params(FSPM_UPD *mupd) @@ -11,6 +21,86 @@ /* Default weak implementation */ } +static const struct SystemMemoryMapHob *get_system_memory_map(void) +{ + size_t hob_size; + const uint8_t mem_hob_guid[16] = FSP_SYSTEM_MEMORYMAP_HOB_GUID; + const struct SystemMemoryMapHob **memmap_addr; + + memmap_addr = (const struct SystemMemoryMapHob **) + fsp_find_extension_hob_by_guid(mem_hob_guid, &hob_size); + /* hob_size is the size of the 8-byte address not the hob data */ + assert(memmap_addr != NULL && hob_size != 0); + /* assert the pointer to the hob is not NULL */ + assert(*memmap_addr != NULL); + + return *memmap_addr; +} + +/* Save the DIMM information for SMBIOS table 17 */ +void save_dimm_info(void) +{ + struct dimm_info *dest_dimm; + struct memory_info *mem_info; + const struct SystemMemoryMapHob *hob; + MEMMAP_DIMM_DEVICE_INFO_STRUCT src_dimm; + int dimm_max, index = 0; + uint32_t vdd_voltage; + + hob = get_system_memory_map(); + assert(hob != NULL); + + /* + * Allocate CBMEM area for DIMM information used to populate SMBIOS + * table 17 + */ + mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); + if (mem_info == NULL) { + printk(BIOS_ERR, "CBMEM entry for DIMM info missing\n"); + return; + } + memset(mem_info, 0, sizeof(*mem_info)); + dimm_max = ARRAY_SIZE(mem_info->dimm); + vdd_voltage = get_ddr_voltage(hob->DdrVoltage); + /* For now only implement for one socket and hard-coded for DDR4 */ + for (int ch = 0; ch < MAX_CH; ch++) { + for (int dimm = 0; dimm < MAX_IMC; dimm++) { + src_dimm = hob->Socket[0].ChannelInfo[ch].DimmInfo[dimm]; + if (src_dimm.Present) { + if (index >= dimm_max) { + printk(BIOS_WARNING, "Too many DIMMs info for %s.\n", + __func__); + return; + } + dest_dimm = &mem_info->dimm[index]; + dest_dimm->max_speed_mts = + get_max_memory_speed(src_dimm.commonTck); + dest_dimm->configured_speed_mts = hob->memFreq; + dimm_info_fill(dest_dimm, + src_dimm.DimmSize << 6, + 0x1a, /* hard-coded memory device type as DDR4 */ + hob->memFreq, /* replaced by configured_speed_mts */ + src_dimm.NumRanks, + ch, /* for mainboard locator string override */ + dimm, /* for mainboard locator string override */ + (const char *)&src_dimm.PartNumber[0], + sizeof(src_dimm.PartNumber), + (const uint8_t *)&src_dimm.serialNumber[0], + 64, /* hard-coded for DDR4 data width */ + vdd_voltage, + true, /* hard-coded as ECC supported */ + src_dimm.VendorID, + src_dimm.actKeyByte2); + index++; + } + } + } + + /* Save available DIMM information */ + mem_info->dimm_cnt = index; + printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt); +} + void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { FSPM_CONFIG *m_cfg = &mupd->FspmConfig; diff --git a/src/soc/intel/xeon_sp/include/soc/romstage.h b/src/soc/intel/xeon_sp/include/soc/romstage.h index aa46067..90689af 100644 --- a/src/soc/intel/xeon_sp/include/soc/romstage.h +++ b/src/soc/intel/xeon_sp/include/soc/romstage.h @@ -8,5 +8,5 @@ /* These functions are weak and can be overridden by a mainboard functions. */ void mainboard_memory_init_params(FSPM_UPD * mupd); void mainboard_rtc_failed(void); - +void save_dimm_info(void); #endif /* _SOC_ROMSTAGE_H_ */ diff --git a/src/soc/intel/xeon_sp/romstage.c b/src/soc/intel/xeon_sp/romstage.c index a4853c0..f3e32fd 100644 --- a/src/soc/intel/xeon_sp/romstage.c +++ b/src/soc/intel/xeon_sp/romstage.c @@ -41,7 +41,7 @@ /* Cache the memory-mapped boot media. */ postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); - + save_dimm_info(); run_postcar_phase(&pcf); } @@ -54,3 +54,4 @@ { } +__weak void save_dimm_info(void) { } -- To view, visit https://review.coreboot.org/c/coreboot/+/45798 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3cb72d18027d972140828970206834ff55b72022 Gerrit-Change-Number: 45798 Gerrit-PatchSet: 12 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: John Looney <john.looney(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: vc/intel/fsp/fsp2_0/cpx_sp: Expose DIMM Present and DdrVoltage fields
by Angel Pons (Code Review) 08 Oct '20

08 Oct '20

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45797 ) Change subject: vc/intel/fsp/fsp2_0/cpx_sp: Expose DIMM Present and DdrVoltage fields ...................................................................... vc/intel/fsp/fsp2_0/cpx_sp: Expose DIMM Present and DdrVoltage fields The fields from SystemMemoryMapHob can be used to generate SMBIOS type 17. Tested=On OCP Delta Lake, verify the values are expected. Change-Id: I988e7341ddd3b701c698b41451a87890f21cc928 Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45797 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h 1 file changed, 9 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h index 7baa11a..dc870f1 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h @@ -89,7 +89,8 @@ } SYSTEM_MEMORY_MAP_ELEMENT; typedef struct DimmDevice { - UINT8 reserved1[2]; + UINT8 Present; + UINT8 reserved1[1]; UINT8 DcpmmPresent; UINT8 reserved2[1]; UINT8 NumRanks; @@ -139,22 +140,24 @@ UINT32 memSize; // Total physical memory size UINT16 memFreq; // Mem Frequency - UINT8 reserved2[61]; + UINT8 reserved2[22]; + UINT8 DdrVoltage; + UINT8 reserved3[38]; UINT8 NumChPerMC; UINT8 numberEntries; // Number of Memory Map Elements SYSTEM_MEMORY_MAP_ELEMENT Element[(MAX_SOCKET * MAX_DRAM_CLUSTERS * MAX_SAD_RULES) + MAX_FPGA_REMOTE_SAD_RULES]; - UINT8 reserved3[2213]; + UINT8 reserved4[2213]; MEMMAP_SOCKET Socket[MAX_SOCKET]; - UINT8 reserved4[1603]; + UINT8 reserved5[1603]; UINT16 BiosFisVersion; // Firmware Interface Specification version currently supported by BIOS - UINT8 reserved5[24]; + UINT8 reserved6[24]; UINT32 MmiohBase; // MMIOH base in 64MB granularity - UINT8 reserved6[5]; + UINT8 reserved7[5]; } SYSTEM_MEMORY_MAP_HOB; -- To view, visit https://review.coreboot.org/c/coreboot/+/45797 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I988e7341ddd3b701c698b41451a87890f21cc928 Gerrit-Change-Number: 45797 Gerrit-PatchSet: 9 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Isaac W Oram <isaac.w.oram(a)intel.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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coreboot-gerrit October 2020