coreboot-gerrit October 2020

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Change in coreboot[master]: soc/intel/jasperlake: Update VR Configuration Values
by Meera Ravindranath (Code Review) 08 Oct '20

08 Oct '20

Meera Ravindranath has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45645 ) Change subject: soc/intel/jasperlake: Update VR Configuration Values ...................................................................... soc/intel/jasperlake: Update VR Configuration Values This patch fixes the CPU Throttling issue observed on Drawlat BRANCH=None BUG=b:167472333 Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> Change-Id: I3fa32218040263f0abef8b9dd4c52efb31289fd7 --- M src/soc/intel/jasperlake/fsp_params.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/45645/1 diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c index cdd088e..6c83503 100644 --- a/src/soc/intel/jasperlake/fsp_params.c +++ b/src/soc/intel/jasperlake/fsp_params.c @@ -177,6 +177,10 @@ sizeof(params->SataPortsDevSlp)); } + /* VR Configuration */ + params->IccMax[0] = 140; + params->TdcCurrentLimit[0] = 80; + /* SDCard related configuration */ dev = pcidev_path_on_root(PCH_DEVFN_SDCARD); params->ScsSdCardEnabled = is_dev_enabled(dev); -- To view, visit https://review.coreboot.org/c/coreboot/+/45645 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3fa32218040263f0abef8b9dd4c52efb31289fd7 Gerrit-Change-Number: 45645 Gerrit-PatchSet: 1 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel: Configure PAVP at compile-time
by Nico Huber (Code Review) 08 Oct '20

08 Oct '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42745 ) Change subject: soc/intel: Configure PAVP at compile-time ...................................................................... Patch Set 9: Code-Review+2 (2 comments) Looks good, but please remove the Jasper Lake special treatment after rebase. https://review.coreboot.org/c/coreboot/+/42745/9//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/42745/9//COMMIT_MSG@9 PS9, Line 9: Expose configuration of Intel PAVP (Protected Audio-Video Path, a digital Please break lines before 72 chars. https://review.coreboot.org/c/coreboot/+/42745/9//COMMIT_MSG@14 PS9, Line 14: Also add a period at the end of Kconfig help for MMA while editing the file. Not a good idea generally, it makes individual changes harder to track (and to revert). -- To view, visit https://review.coreboot.org/c/coreboot/+/42745 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2aae741bb30e3be3c64324cd6334778bd271a903 Gerrit-Change-Number: 42745 Gerrit-PatchSet: 9 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 08 Oct 2020 19:10:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: Revert "soc/intel/jasperlake: Disable PAVP UPD"
by Nico Huber (Code Review) 08 Oct '20

08 Oct '20

Hello Benjamin Doron, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46044 to review the following change. Change subject: Revert "soc/intel/jasperlake: Disable PAVP UPD" ...................................................................... Revert "soc/intel/jasperlake: Disable PAVP UPD" This reverts commit 69589294c205b616e80cafbbfb0b33e105a75386. No reason was given why this should deviate from the other platforms and the author can't explain it. Change-Id: I2e8d6f9bd4ebba69b6f7cdd9a1c5d08aaf2e798f Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/soc/intel/jasperlake/fsp_params.c 1 file changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/46044/1 diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c index cdd088e..d2e07e9 100644 --- a/src/soc/intel/jasperlake/fsp_params.c +++ b/src/soc/intel/jasperlake/fsp_params.c @@ -207,9 +207,6 @@ params->XdciEnable = 0; } - /* Disable Pavp */ - params->PavpEnable = 0; - /* Provide correct UART number for FSP debug logs */ params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE; -- To view, visit https://review.coreboot.org/c/coreboot/+/46044 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e8d6f9bd4ebba69b6f7cdd9a1c5d08aaf2e798f Gerrit-Change-Number: 46044 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/i2c: Add chip driver for GPIO based I2C multiplexer
by Tim Wawrzynczak (Code Review) 08 Oct '20

08 Oct '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45911 ) Change subject: drivers/i2c: Add chip driver for GPIO based I2C multiplexer ...................................................................... Patch Set 6: (1 comment) https://review.coreboot.org/c/coreboot/+/45911/6//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/45911/6//COMMIT_MSG@48 PS6, Line 48: Package (0x02) : { : "mux-gpios", : Package (0x04) : { : \_SB.PCI0.I2C3.MUX0, : Zero, : Zero, : Zero : } : } : } Where is this used? -- To view, visit https://review.coreboot.org/c/coreboot/+/45911 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib371108cc6043c133681066bf7bf4b2e00771e8b Gerrit-Change-Number: 45911 Gerrit-PatchSet: 6 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 08 Oct 2020 18:35:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [UNTESTED] soc/intel/{icl,tgl,jsl,ehl}: set PM ACPI timer state from ...
by Michael Niewöhner (Code Review) 08 Oct '20

08 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45957 ) Change subject: [UNTESTED] soc/intel/{icl,tgl,jsl,ehl}: set PM ACPI timer state from Kconfig ...................................................................... Patch Set 22: (1 comment) https://review.coreboot.org/c/coreboot/+/45957/21/src/soc/intel/elkhartlake… File src/soc/intel/elkhartlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/45957/21/src/soc/intel/elkhartlake… PS21, Line 64: /* PM ACPI timer */ > Well then, I'll drop the comments for the other platforms, too Done -- To view, visit https://review.coreboot.org/c/coreboot/+/45957 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf1eee9297034b29b7250f6c752e6f7f52b4b908 Gerrit-Change-Number: 45957 Gerrit-PatchSet: 22 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 08 Oct 2020 18:22:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: [UNTESTED] soc/intel/{icl,tgl,jsl,ehl}: set PM ACPI timer state from ...
by Michael Niewöhner (Code Review) 08 Oct '20

08 Oct '20

Hello build bot (Jenkins), Nico Huber, Furquan Shaikh, Subrata Banik, Aamir Bohra, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45957 to look at the new patch set (#23). Change subject: [UNTESTED] soc/intel/{icl,tgl,jsl,ehl}: set PM ACPI timer state from Kconfig ...................................................................... [UNTESTED] soc/intel/{icl,tgl,jsl,ehl}: set PM ACPI timer state from Kconfig Set the FSP option for PM ACPI timer enablement from the Kconfig option, to be able to disable the timer for power savings. Change-Id: Iaf1eee9297034b29b7250f6c752e6f7f52b4b908 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/elkhartlake/fsp_params.c M src/soc/intel/icelake/fsp_params.c M src/soc/intel/jasperlake/fsp_params.c M src/soc/intel/tigerlake/fsp_params.c 4 files changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/45957/23 -- To view, visit https://review.coreboot.org/c/coreboot/+/45957 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf1eee9297034b29b7250f6c752e6f7f52b4b908 Gerrit-Change-Number: 45957 Gerrit-PatchSet: 23 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/{skl,cnl}: replace PM ACPI timer dt option by Kconfig
by Michael Niewöhner (Code Review) 08 Oct '20

08 Oct '20

Hello build bot (Jenkins), Nico Huber, Furquan Shaikh, Michał Żygowski, Frans Hendriks, Subrata Banik, Aamir Bohra, Patrick Rudolph, Wim Vervoorn, Piotr Król, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45955 to look at the new patch set (#22). Change subject: soc/intel/{skl,cnl}: replace PM ACPI timer dt option by Kconfig ...................................................................... soc/intel/{skl,cnl}: replace PM ACPI timer dt option by Kconfig Set the FSP option for PM ACPI timer enablement from the Kconfig option instead of the old devicetree option. Also drop the obsolete devicetree option from soc code and from the mainboards and add a corresponding Kconfig entry instead. Change-Id: I10724ccf1647594404cec15c2349ab05b6c9714f Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/asrock/h110m/devicetree.cb M src/mainboard/facebook/monolith/Kconfig M src/mainboard/facebook/monolith/devicetree.cb M src/mainboard/google/eve/Kconfig M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/Kconfig M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/glados/Kconfig M src/mainboard/google/glados/devicetree.cb M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/Kconfig M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/intel/kblrvp/Kconfig M src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb M src/mainboard/intel/kunimitsu/Kconfig M src/mainboard/intel/kunimitsu/devicetree.cb M src/mainboard/intel/saddlebrook/devicetree.cb M src/mainboard/libretrend/lt1000/Kconfig M src/mainboard/libretrend/lt1000/devicetree.cb M src/mainboard/protectli/vault_kbl/Kconfig M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_skl/devicetree.cb M src/mainboard/purism/librem_whl/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/devicetree.cb M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h 39 files changed, 39 insertions(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/45955/22 -- To view, visit https://review.coreboot.org/c/coreboot/+/45955 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I10724ccf1647594404cec15c2349ab05b6c9714f Gerrit-Change-Number: 45955 Gerrit-PatchSet: 22 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 08 Oct '20

08 Oct '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46079 ) Change subject: mb/google: Convert to ASL 2.0 syntax ...................................................................... mb/google: Convert to ASL 2.0 syntax Change-Id: Ib8020ccc204ae7d3145cdc2aa5d64207f783e088 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/google/auron/variants/buddy/include/variant/acpi/mainboard.asl M src/mainboard/google/cyan/variants/terra/include/variant/acpi/charger.asl M src/mainboard/google/cyan/variants/terra/include/variant/acpi/cpu.asl M src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl M src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam0.asl M src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam1.asl M src/mainboard/google/slippy/acpi/platform.asl M src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/mipi_camera.asl 8 files changed, 92 insertions(+), 95 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/46079/1 diff --git a/src/mainboard/google/auron/variants/buddy/include/variant/acpi/mainboard.asl b/src/mainboard/google/auron/variants/buddy/include/variant/acpi/mainboard.asl index b3dc42c..bb30c2e 100644 --- a/src/mainboard/google/auron/variants/buddy/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/auron/variants/buddy/include/variant/acpi/mainboard.asl @@ -24,7 +24,7 @@ Method (_STA) { - If (LEqual (\S1EN, 1)) { + If (\S1EN == 1) { Return (0xF) } Else { Return (0x0) @@ -59,7 +59,7 @@ Method (_STA) { - If (LEqual (\S2EN, 1)) { + If (\S2EN == 1) { Return (0xF) } Else { Return (0x0) @@ -70,8 +70,8 @@ Method (_DSW, 3, NotSerialized) { - Store (BOARD_TOUCHSCREEN_WAKE_GPIO, Local0) - If (LEqual (Arg0, 1)) { + Local0 = BOARD_TOUCHSCREEN_WAKE_GPIO + If (Arg0 == 1) { // Enable GPIO as wake source \_SB.PCI0.LPCB.GPIO.GWAK (Local0) } @@ -94,9 +94,9 @@ Method (_DSW, 3, NotSerialized) { - Store (BUDDY_NIC_WAKE_GPIO, Local0) + Local0 = BUDDY_NIC_WAKE_GPIO - If (LEqual (Arg0, 1)) { + If (Arg0 == 1) { // Enable GPIO as wake source \_SB.PCI0.LPCB.GPIO.GWAK (Local0) } diff --git a/src/mainboard/google/cyan/variants/terra/include/variant/acpi/charger.asl b/src/mainboard/google/cyan/variants/terra/include/variant/acpi/charger.asl index 98e7b7d..6957e92 100644 --- a/src/mainboard/google/cyan/variants/terra/include/variant/acpi/charger.asl +++ b/src/mainboard/google/cyan/variants/terra/include/variant/acpi/charger.asl @@ -9,7 +9,7 @@ Method (_STA) { - If (LEqual (\DPTE, One)) { + If (\DPTE == 1) { Return (0xF) } Else { Return (0x0) @@ -19,7 +19,7 @@ /* Return charger performance states defined by Terra2 or Terra3 mainboard */ Method (PPSS) { - If (LEqual (\_SB.GPID, TERRA2_PROJECT_ID)) + If (\_SB.GPID == TERRA2_PROJECT_ID) { Return (\_SB.CPT2) } Else { @@ -31,17 +31,17 @@ Method (PPPC) { /* Convert size of PPSS table to index */ - If (LEqual (\_SB.GPID, TERRA2_PROJECT_ID)) + If (\_SB.GPID == TERRA2_PROJECT_ID) { - Store (SizeOf (\_SB.CPT2), Local0) + Local0 = SizeOf (\_SB.CPT2) } Else { - Store (SizeOf (\_SB.CPT3), Local0) + Local0 = SizeOf (\_SB.CPT3) } - Decrement (Local0) + Local0-- /* Check if charging is disabled (AC removed) */ - If (LEqual (\_SB.PCI0.LPCB.EC0.ACEX, Zero)) { + If (\_SB.PCI0.LPCB.EC0.ACEX == 0) { /* Return last power state */ Return (Local0) } Else { @@ -57,13 +57,11 @@ { /* Retrieve Control (index 4) for specified PPSS level */ /* Convert size of PPSS table to index */ - If (LEqual (\_SB.GPID, TERRA2_PROJECT_ID)) + If (\_SB.GPID == TERRA2_PROJECT_ID) { - Store (DeRefOf (Index (DeRefOf (Index - (\_SB.CPT2, ToInteger (Arg0))), 4)), Local0) + Local0 = DeRefOf (DeRefOf (\_SB.CPT2 [ToInteger (Arg0)]) [4]) } Else { - Store (DeRefOf (Index (DeRefOf (Index - (\_SB.CPT3, ToInteger (Arg0))), 4)), Local0) + Local0 = DeRefOf (DeRefOf (\_SB.CPT3 [ToInteger (Arg0)]) [4]) } /* Pass Control value to EC to limit charging */ diff --git a/src/mainboard/google/cyan/variants/terra/include/variant/acpi/cpu.asl b/src/mainboard/google/cyan/variants/terra/include/variant/acpi/cpu.asl index 7ec48a3..ec02670 100644 --- a/src/mainboard/google/cyan/variants/terra/include/variant/acpi/cpu.asl +++ b/src/mainboard/google/cyan/variants/terra/include/variant/acpi/cpu.asl @@ -40,7 +40,7 @@ Method (_STA) { - If (LEqual (\DPTE, One)) { + If (\DPTE == 1) { Return (0xF) } Else { Return (0x0) @@ -100,8 +100,8 @@ Method (_TDL) { If (CondRefOf (\_SB.CP00._TSS)) { - Store (SizeOf (\_SB.CP00._TSS ()), Local0) - Decrement (Local0) + Local0 = SizeOf (\_SB.CP00._TSS ()) + Local0-- Return (Local0) } Else { Return (0) @@ -119,7 +119,7 @@ Method (SPPC, 1) { - Store (Arg0, \PPCM) + \PPCM = Arg0 /* Notify OS to re-read _PPC limit on each CPU */ \PPCN () @@ -143,8 +143,8 @@ If (CondRefOf (\_SB.MPDL)) { Return (\_SB.MPDL) } ElseIf (CondRefOf (\_SB.CP00._PSS)) { - Store (SizeOf (\_SB.CP00._PSS ()), Local0) - Decrement (Local0) + Local0 = SizeOf (\_SB.CP00._PSS ()) + Local0-- Return (Local0) } Else { Return (0) @@ -154,7 +154,7 @@ /* Return PPCC table defined by Terra2 or Terra3 mainboard */ Method (PPCC) { - If (LEqual (\_SB.GPID, TERRA2_PROJECT_ID)) + If (\_SB.GPID == TERRA2_PROJECT_ID) { Return (\_SB.PPT2) } Else { @@ -165,7 +165,7 @@ /* Return critical thermal point defined by Terra2 or Terra3 mainboard */ Method (_CRT) { - If (Lequal(\_SB.GPID, TERRA2_PROJECT_ID)) + If (\_SB.GPID == TERRA2_PROJECT_ID) { Return (\_SB.DPTF.CTOK(DPTF_TERRA2_CPU_CRITICAL)) } Else { @@ -176,7 +176,7 @@ /* Return passive thermal point defined by Terra2 or Terra3 mainboard */ Method (_PSV) { - If (Lequal(\_SB.GPID, TERRA2_PROJECT_ID)) + If (\_SB.GPID == TERRA2_PROJECT_ID) { Return (\_SB.DPTF.CTOK(DPTF_TERRA2_CPU_PASSIVE)) } Else { diff --git a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl index 5ad10ef..eb31c42 100644 --- a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl +++ b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl @@ -25,7 +25,7 @@ Method (PMOF, 0, Serialized) { /* Make Sure all PMIC outputs are off. */ - If (LEqual (VSIC, Zero)) { + If (VSIC == 0) { CTXS(EN_PP3300_DX_CAM) } } @@ -39,7 +39,7 @@ Method (_ON, 0, Serialized) { PMON() /* Do not reset PMIC across S3 and S0ix cycle */ - if (Lequal (RSTO, 1)) { + if (RSTO == 1) { CTXS(EN_CAM_PMIC_RST_L) Sleep(1) STXS(EN_CAM_PMIC_RST_L) @@ -64,46 +64,45 @@ Name (AVB3, Zero) Method (_REG, 2, NotSerialized) { - If (LEqual (Arg0, 0x08)) + If (Arg0 == 0x08) { /* Marks the availability of GeneralPurposeIO * 0x08: opregion space for GeneralPurposeIO */ - Store (Arg1, AVGP) + AVGP = Arg1 } - If (LEqual (Arg0, 0xB0)) + If (Arg0 == 0xB0) { /* Marks the availability of * TI_PMIC_POWER_OPREGION_ID */ - Store (Arg1, AVB0) + AVB0 = Arg1 } - If (LEqual (Arg0, 0xB1)) + If (Arg0 == 0xB1) { /* Marks the availability of * TI_PMIC_VR_VAL_OPREGION_ID */ - Store (Arg1, AVB1) + AVB1 = Arg1 } - If (LEqual (Arg0, 0xB2)) + If (Arg0 == 0xB2) { /* Marks the availability of * TI_PMIC_CLK_OPREGION_ID */ - Store (Arg1, AVB2) + AVB2 = Arg1 } - If (LEqual (Arg0, 0xB3)) + If (Arg0 == 0xB3) { /* Marks the availability of * TI_PMIC_CLK_FREQ_OPREGION_ID */ - Store (Arg1, AVB3) + AVB3 = Arg1 } - If (LAnd (AVGP, LAnd (LAnd (AVB0, AVB1), - LAnd(AVB2, AVB3)))) + If (AVGP & ((AVB0 & AVB1) & (AVB2 & AVB3))) { /* Marks the availability of all opregions */ - Store (1, AVBL) + AVBL = 1 } Else { - Store (0, AVBL) + AVBL = 0 } } @@ -321,12 +320,12 @@ Method (CLKE, 0, Serialized) { /* save Acquire result so we can check for Mutex acquired */ - Store (Acquire (MUTC, 1000), Local0) + Local0 = Acquire (MUTC, 1000) /* check for Mutex acquired */ - If (LEqual (Local0, Zero)) { + If (Local0 == 0) { /* Enable clocks only when a sensor is turned on and both the clocks are disabled */ - If (LNot (LOr (CLE0, CLE1))) { + If (!(CLE0 |CLE1)) { /* Set boost clock divider */ BODI = 3 /* Set buck clock divider */ @@ -365,10 +364,10 @@ Method (CLKD, 0, Serialized) { /* save Acquire result so we can check for Mutex acquired */ - Store (Acquire (MUTC, 1000), Local0) + Local0 = Acquire (MUTC, 1000) /* check for Mutex acquired */ - If (LEqual (Local0, Zero)) { - If (LNot (LOr (CLE0, CLE1))) { + If (Local0 == 0) { + If (!(CLE0 |CLE1)) { BODI = 0 BUDI = 0 PSWR = 0 @@ -390,37 +389,37 @@ Name (VSIC, 0) Method (DOVD, 1, Serialized) { /* Turn off VSIO */ - If (LEqual (Arg0, Zero)) { + If (Arg0 == 0) { /* Decrement only if VSIC > 0 */ - if (LGreater (VSIC, 0)) { - Decrement (VSIC) - If (LEqual (VSIC, Zero)) { + if (VSIC > 0) { + VSIC-- + If (VSIC == 0) { VSIO = 0 Sleep(1) PMOF() } } - } ElseIf (LEqual (Arg0, 1)) { + } ElseIf (Arg0 == 1) { /* Increment only if VSIC < 4 */ - If (LLess (VSIC, 4)) { + If (VSIC < 4) { /* Turn on VSIO */ - If (LEqual (VSIC, Zero)) { + If (VSIC == 0) { PMON() VSIO = 3 - if (LNotEqual (IOVA, 52)) { + if (IOVA != 52) { /* Set VSIO value as 1.8006 V */ IOVA = 52 } - if (LNotEqual (SIOV, 52)) { + if (SIOV != 52) { /* Set VSIO value as 1.8006 V */ SIOV = 52 } Sleep(3) } - Increment (VSIC) + VSIC++ } } } @@ -430,8 +429,8 @@ Name (STA, 0) Method (_ON, 0, Serialized) { /* TODO: Read Voltage and Sleep values from Sensor Obj */ - If (LEqual (AVBL, 1)) { - If (LEqual (STA, 0)) { + If (AVBL == 1) { + If (STA == 0) { /* Enable VSIO regulator + daisy chain */ DOVD(1) @@ -470,8 +469,8 @@ } Method (_OFF, 0, Serialized) { - If (LEqual (AVBL, 1)) { - If (LEqual (STA, 1)) { + If (AVBL == 1) { + If ((STA == 1) { Sleep(2) CLE0 = 0 \_SB.PCI0.I2C2.PMIC.CLKD() @@ -497,8 +496,8 @@ Name (STA, 0) Method (_ON, 0, Serialized) { /* TODO: Read Voltage and Sleep values from Sensor Obj */ - If (LEqual (AVBL, 1)) { - If (LEqual (STA, 0)) { + If (AVBL == 1) { + If (STA == 0) { /* Enable VSIO regulator + daisy chain */ DOVD(1) @@ -537,8 +536,8 @@ } Method (_OFF, 0, Serialized) { - If (LEqual (AVBL, 1)) { - If (LEqual (STA, 1)) { + If (AVBL == 1) { + If ((STA == 1) { Sleep(2) CLE1 = 0 \_SB.PCI0.I2C2.PMIC.CLKD() @@ -566,8 +565,8 @@ PowerResource (VCMP, 0, 0) { Name (STA, 0) Method (_ON, 0, Serialized) { - If (LEqual (AVBL, 1)) { - If (LEqual (STA, 0)) { + If (AVBL == 1) { + If (STA == 0) { /* Enable VSIO regulator + daisy chain */ DOVD(1) @@ -584,8 +583,8 @@ } Method (_OFF, 0, Serialized) { - If (LEqual (AVBL, 1)) { - If (LEqual (STA, 1)) { + If (AVBL == 1) { + If ((STA == 1) { VCMC = 0 /* Disable regulator */ Sleep(1) DOVD(0) /* Disable regulator */ @@ -603,8 +602,8 @@ PowerResource (NVMP, 0, 0) { Name (STA, 0) Method (_ON, 0, Serialized) { - If (LEqual (AVBL, 1)) { - If (LEqual (STA, 0)) { + If (AVBL == 1) { + If (STA == 0) { /* Enable VSIO regulator + daisy chain */ DOVD(1) @@ -614,8 +613,8 @@ } Method (_OFF, 0, Serialized) { - If (LEqual (AVBL, 1)) { - If (LEqual (STA, 1)) { + If (AVBL == 1) { + If ((STA == 1) { DOVD(0) /* Disable regulator */ STA = 0 } diff --git a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam0.asl b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam0.asl index 17fb82b..c3449a7 100644 --- a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam0.asl +++ b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam0.asl @@ -6,7 +6,7 @@ { Name (STA, 0) Method (_ON, 0, Serialized) { - If (LEqual(STA, 0)) { + If (STA == 0) { CTXS (GPIO_FCAM_RST_L) STXS (GPIO_FCAM_PWR_EN) STXS (GPIO_PCH_FCAM_CLK_EN) @@ -22,15 +22,15 @@ * sequence completes */ Sleep (11) - Store (1, STA) + STA = 1 } } Method (_OFF, 0, Serialized) { - If (LEqual(STA, 1)) { + If (STA == 1) { CTXS (GPIO_PCH_FCAM_CLK_EN) CTXS (GPIO_FCAM_RST_L) CTXS (GPIO_FCAM_PWR_EN) - Store (0, STA) + STA = 0 } } Method (_STA, 0, NotSerialized) { diff --git a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam1.asl b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam1.asl index a934901..0e31eee 100644 --- a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam1.asl +++ b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam1.asl @@ -6,7 +6,7 @@ { Name (STA, 0) Method (_ON, 0, Serialized) { - If (LEqual(STA, 0)) { + If (STA == 0) { CTXS (GPIO_RCAM_RST_L) STXS (GPIO_RCAM_PWR_EN) STXS (GPIO_PCH_RCAM_CLK_EN) @@ -21,15 +21,15 @@ * on sequence completes */ Sleep (12) - Store (1, STA) + STA = 1 } } Method (_OFF, 0, Serialized) { - If (LEqual(STA, 1)) { + If (STA == 1) { CTXS (GPIO_PCH_RCAM_CLK_EN) CTXS (GPIO_RCAM_RST_L) CTXS (GPIO_RCAM_PWR_EN) - Store (0, STA) + STA = 0 } } Method (_STA, 0, NotSerialized) { diff --git a/src/mainboard/google/slippy/acpi/platform.asl b/src/mainboard/google/slippy/acpi/platform.asl index 2813078..c98fc6e 100644 --- a/src/mainboard/google/slippy/acpi/platform.asl +++ b/src/mainboard/google/slippy/acpi/platform.asl @@ -15,16 +15,16 @@ Method(_WAK,1) { /* Update AC status */ - Store (\_SB.PCI0.LPCB.EC0.ACEX, Local0) - if (LNotEqual (Local0, \PWRS)) { - Store (Local0, \PWRS) + Local0 = \_SB.PCI0.LPCB.EC0.ACEX + if (Local0 != \PWRS) { + \PWRS = Local0 Notify (\_SB.PCI0.LPCB.EC0.AC, 0x80) } /* Update LID status */ - Store (\_SB.PCI0.LPCB.EC0.LIDS, Local0) - if (LNotEqual (Local0, \LIDS)) { - Store (Local0, \LIDS) + Local0 = \_SB.PCI0.LPCB.EC0.LIDS + if (Local0 != \LIDS) { + \LIDS = Local0 Notify (\_SB.PCI0.LPCB.EC0.LID0, 0x80) } diff --git a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/mipi_camera.asl b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/mipi_camera.asl index 51034c3..91f4e8f 100644 --- a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/mipi_camera.asl +++ b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/mipi_camera.asl @@ -178,12 +178,12 @@ #endif Sleep(1) /* t2 */ - Store(1,STA) + STA = 1 } } Method (_OFF, 0, Serialized) /* Rear camera _OFF: Power Off */ { - If ((STA == One)) + If (STA == 1) { /* Disable IMG_CLK */ Sleep(1) /* t0+t1 */ @@ -202,7 +202,7 @@ /* Pull SNRPWR_EN low */ CTXS(GPP_H14) - Store(0,STA) + STA = 0 } } Method (_STA, 0, NotSerialized) /* _STA: Status */ @@ -479,12 +479,12 @@ STXS(GPP_D4) Sleep(1) /* t2 */ - Store(1,STA) + STA = 1 } } Method (_OFF, 0, Serialized) /* Front camera_OFF_: Power Off */ { - If ((STA == One)) + If (STA == 1) { /* Disable IMG_CLK */ Sleep(1) /* t0+t1 */ @@ -499,7 +499,7 @@ /* Pull SNRPWR_EN low */ CTXS(GPP_D18) - Store(0,STA) + STA = 0 } } Method (_STA, 0, NotSerialized) /* _STA: Status */ -- To view, visit https://review.coreboot.org/c/coreboot/+/46079 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8020ccc204ae7d3145cdc2aa5d64207f783e088 Gerrit-Change-Number: 46079 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/i2c: Add chip driver for GPIO based I2C multiplexer
by Furquan Shaikh (Code Review) 08 Oct '20

08 Oct '20

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45911 ) Change subject: drivers/i2c: Add chip driver for GPIO based I2C multiplexer ...................................................................... Patch Set 6: (1 comment) https://review.coreboot.org/c/coreboot/+/45911/6/src/drivers/i2c/gpiomux/mu… File src/drivers/i2c/gpiomux/mux/mux.c: https://review.coreboot.org/c/coreboot/+/45911/6/src/drivers/i2c/gpiomux/mu… PS6, Line 37: "_HID", ACPI_DT_NAMESPACE_HID) > Wait but if you do this and use PRP0001, aren't you deferring into the DT world entirely, including […] Would this be applicable: https://www.kernel.org/doc/html/latest/firmware-guide/acpi/DSD-properties-r… "It often is useful to make _DSD return property sets that follow Device Tree bindings. In those cases, however, the above validity considerations must be taken into account in the first place and returning invalid property sets from _DSD must be avoided. For this reason, it may not be possible to make _DSD return a property set following the given DT binding literally and completely. Still, for the sake of code re-use, it may make sense to provide as much of the configuration data as possible in the form of device properties and complement that with an ACPI-specific mechanism suitable for the use case at hand." In my opinion, this should apply for the i2c-parent property. Even though it is a required option for dt-bindings, ACPI has a different way of defining relation between devices and so i2c-parent property can be skipped in case of ACPI. It also saves us having to allocate another ACPI ID just for this case. -- To view, visit https://review.coreboot.org/c/coreboot/+/45911 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib371108cc6043c133681066bf7bf4b2e00771e8b Gerrit-Change-Number: 45911 Gerrit-PatchSet: 6 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 08 Oct 2020 18:11:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Evan Green <evgreen(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/dedede: Enable SaGv support
by Karthik Ramasubramanian (Code Review) 08 Oct '20

08 Oct '20

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45196 ) Change subject: mb/intel/dedede: Enable SaGv support ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/45196/2//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/45196/2//COMMIT_MSG@7 PS2, Line 7: intel/ google -- To view, visit https://review.coreboot.org/c/coreboot/+/45196 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f60aad031ce9dfe23e54426753311c35db46c05 Gerrit-Change-Number: 45196 Gerrit-PatchSet: 2 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Comment-Date: Thu, 08 Oct 2020 17:47:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit October 2020