Change in coreboot[master]: soc/amd/picasso: Add Upd for support force USB3 to Gen1 by port

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chris wang (Code Review)

14 Sep 2020 14 Sep '20

9:17 a.m.

Hello Chris Wang,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/45333

to review the following change.

Change subject: soc/amd/picasso: Add Upd for support force USB3 to Gen1 by port ......................................................................

soc/amd/picasso: Add Upd for support force USB3 to Gen1 by port

add upd usb3_port_force_gen1 for support USB3 port to gen1

BUG=b:167651308 BRANCH=zork TEST=Build,verify the USB3 speed in gen1

Signed-off-by: Chris Wang chris.wang@amd.corp-partner.google.com Change-Id: I896c185988c3ea5dbdd72957b363ebdaa2747cff --- M src/soc/amd/picasso/chip.h M src/soc/amd/picasso/fsp_params.c 2 files changed, 2 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/45333/1

diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index e3da255..9868220 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -168,7 +168,7 @@ USB_OC_PIN_5 = 0x5, USB_OC_NONE = 0xf, } usb_port_overcurrent_pin[USB_PORT_COUNT]; - + uint32_t usb3_port_force_gen1; /* The array index is the general purpose PCIe clock output number. */ enum gpp_clk_req_setting gpp_clk_config[GPP_CLK_OUTPUT_COUNT]; }; diff --git a/src/soc/amd/picasso/fsp_params.c b/src/soc/amd/picasso/fsp_params.c index b21f237..e36ebd0 100644 --- a/src/soc/amd/picasso/fsp_params.c +++ b/src/soc/amd/picasso/fsp_params.c @@ -106,6 +106,7 @@ ASSERT(2 * sizeof(scfg->xhci_oc_pin_select) >= USB_PORT_COUNT);

scfg->xhci0_force_gen1 = cfg->xhci0_force_gen1; + scfg->fch_usb_3_port_force_gen1 = cfg->usb3_port_force_gen1;

if (cfg->has_usb2_phy_tune_params) { for (i = 0; i < FSPS_UPD_USB2_PORT_COUNT; i++) {

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Paul Menzel (Code Review)

14 Sep 14 Sep

10:46 a.m.

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45333 )

Change subject: soc/amd/picasso: Add Upd for support force USB3 to Gen1 by port ......................................................................

Patch Set 1:

(4 comments)

https://review.coreboot.org/c/coreboot/+/45333/1//COMMIT_MSG Commit Message:

https://review.coreboot.org/c/coreboot/+/45333/1//COMMIT_MSG@7 PS1, Line 7: soc/amd/picasso: Add Upd for support force USB3 to Gen1 by port Maybe:

...

Add UPD to force USB3 to Gen1 by port

https://review.coreboot.org/c/coreboot/+/45333/1//COMMIT_MSG@9 PS1, Line 9: add upd usb3_port_force_gen1 for support USB3 port to gen1 Please start sentences with a capital letter and finish with a dot/period.

https://review.coreboot.org/c/coreboot/+/45333/1//COMMIT_MSG@13 PS1, Line 13: TEST=Build,verify the USB3 speed in gen1 Please add a space after the comma.

https://review.coreboot.org/c/coreboot/+/45333/1/src/soc/amd/picasso/chip.h File src/soc/amd/picasso/chip.h:

https://review.coreboot.org/c/coreboot/+/45333/1/src/soc/amd/picasso/chip.h@... PS1, Line 171: uint32_t usb3_port_force_gen1; Keep the blank line before the comment?

Angel Pons (Code Review)

11 a.m.

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45333 )

Change subject: soc/amd/picasso: Add Upd for support force USB3 to Gen1 by port ......................................................................

Patch Set 1:

(2 comments)

https://review.coreboot.org/c/coreboot/+/45333/1//COMMIT_MSG Commit Message:

https://review.coreboot.org/c/coreboot/+/45333/1//COMMIT_MSG@7 PS1, Line 7: soc/amd/picasso: Add Upd for support force USB3 to Gen1 by port

...

Maybe: […]

Note that `UPD` should be spelled in uppercase

https://review.coreboot.org/c/coreboot/+/45333/1/src/soc/amd/picasso/chip.h File src/soc/amd/picasso/chip.h:

https://review.coreboot.org/c/coreboot/+/45333/1/src/soc/amd/picasso/chip.h@... PS1, Line 171: uint32_t The FSP UPD seems to be an uint8_t, so this should be uint8_t as well.

-- To view, visit https://review.coreboot.org/c/coreboot/+/45333 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I896c185988c3ea5dbdd72957b363ebdaa2747cff Gerrit-Change-Number: 45333 Gerrit-PatchSet: 1 Gerrit-Owner: chris wang Chris.Wang@amd.com Gerrit-Reviewer: Aaron Durbin adurbin@chromium.org Gerrit-Reviewer: Chris Wang chris.wang@amd.corp-partner.google.com Gerrit-Reviewer: Furquan Shaikh furquan@google.com Gerrit-Reviewer: Keith Tzeng keith.tzeng@quanta.corp-partner.google.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Angel Pons th3fanbus@gmail.com Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Mon, 14 Sep 2020 11:00:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel paulepanter@users.sourceforge.net Gerrit-MessageType: comment

chris wang (Code Review)

1:15 p.m.

New subject: Change in coreboot[master]: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port

Hello build bot (Jenkins), Furquan Shaikh, Chris Wang, Keith Tzeng, Aaron Durbin,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/45333

to look at the new patch set (#2).

Change subject: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port ......................................................................

soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port

add upd usb3_port_force_gen1 for support USB3 port to gen1

BUG=b:167651308 BRANCH=zork TEST=Build,verify the USB3 speed in gen1

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/45333/2

chris wang (Code Review)

1:31 p.m.

New subject: Change in coreboot[master]: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port

Hello build bot (Jenkins), Furquan Shaikh, Chris Wang, Keith Tzeng, Aaron Durbin,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/45333

to look at the new patch set (#3).

Change subject: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port ......................................................................

soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port

add UPD usb3_port_force_gen1 for support USB3 port force to gen1

BUG=b:167651308 BRANCH=zork TEST=Build, verify the USB3 speed in gen1

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/45333/3

chris wang (Code Review)

1:36 p.m.

New subject: Change in coreboot[master]: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port

Hello build bot (Jenkins), Furquan Shaikh, Chris Wang, Keith Tzeng, Aaron Durbin,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/45333

to look at the new patch set (#4).

Change subject: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port ......................................................................

soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port

Add UPD usb3_port_force_gen1 for support USB3 port force to gen1.

BUG=b:167651308 BRANCH=zork TEST=Build, verify the USB3 speed in gen1

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/45333/4

chris wang (Code Review)

1:36 p.m.

New subject: Change in coreboot[master]: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port

chris wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45333 )

Change subject: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port ......................................................................

Patch Set 4:

(3 comments)

https://review.coreboot.org/c/coreboot/+/45333/1//COMMIT_MSG Commit Message:

https://review.coreboot.org/c/coreboot/+/45333/1//COMMIT_MSG@7 PS1, Line 7: soc/amd/picasso: Add Upd for support force USB3 to Gen1 by port

...

Note that `UPD` should be spelled in uppercase

Done

https://review.coreboot.org/c/coreboot/+/45333/1/src/soc/amd/picasso/chip.h File src/soc/amd/picasso/chip.h:

https://review.coreboot.org/c/coreboot/+/45333/1/src/soc/amd/picasso/chip.h@... PS1, Line 171: uint32_t usb3_port_force_gen1;

...

Keep the blank line before the comment?

Done

https://review.coreboot.org/c/coreboot/+/45333/1/src/soc/amd/picasso/chip.h@... PS1, Line 171: uint32_t

...

The FSP UPD seems to be an uint8_t, so this should be uint8_t as well.

Done

-- To view, visit https://review.coreboot.org/c/coreboot/+/45333 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I896c185988c3ea5dbdd72957b363ebdaa2747cff Gerrit-Change-Number: 45333 Gerrit-PatchSet: 4 Gerrit-Owner: chris wang Chris.Wang@amd.com Gerrit-Reviewer: Aaron Durbin adurbin@chromium.org Gerrit-Reviewer: Chris Wang chris.wang@amd.corp-partner.google.com Gerrit-Reviewer: Furquan Shaikh furquan@google.com Gerrit-Reviewer: Keith Tzeng keith.tzeng@quanta.corp-partner.google.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Angel Pons th3fanbus@gmail.com Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Mon, 14 Sep 2020 13:36:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel paulepanter@users.sourceforge.net Comment-In-Reply-To: Angel Pons th3fanbus@gmail.com Gerrit-MessageType: comment

Raul Rangel (Code Review)

3:22 p.m.

New subject: Change in coreboot[master]: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port

Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45333 )

Change subject: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port ......................................................................

Patch Set 4:

(1 comment)

https://review.coreboot.org/c/coreboot/+/45333/4/src/soc/amd/picasso/chip.h File src/soc/amd/picasso/chip.h:

https://review.coreboot.org/c/coreboot/+/45333/4/src/soc/amd/picasso/chip.h@... PS4, Line 172: usb3_port_force_gen1 Can you add some documentation on this? Or better yet, is it possible to make it a bit field?

Aaron Durbin (Code Review)

5:34 p.m.

New subject: Change in coreboot[master]: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45333 )

Change subject: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port ......................................................................

Patch Set 4:

(1 comment)

https://review.coreboot.org/c/coreboot/+/45333/4/src/soc/amd/picasso/chip.h File src/soc/amd/picasso/chip.h:

https://review.coreboot.org/c/coreboot/+/45333/4/src/soc/amd/picasso/chip.h@... PS4, Line 172: usb3_port_force_gen1

...

Can you add some documentation on this? Or better yet, is it possible to make it a bit field?

Ya. this doesn't seem per port unless it's a bitfield.

-- To view, visit https://review.coreboot.org/c/coreboot/+/45333 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I896c185988c3ea5dbdd72957b363ebdaa2747cff Gerrit-Change-Number: 45333 Gerrit-PatchSet: 4 Gerrit-Owner: chris wang Chris.Wang@amd.com Gerrit-Reviewer: Aaron Durbin adurbin@chromium.org Gerrit-Reviewer: Chris Wang chris.wang@amd.corp-partner.google.com Gerrit-Reviewer: Furquan Shaikh furquan@google.com Gerrit-Reviewer: Keith Tzeng keith.tzeng@quanta.corp-partner.google.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Angel Pons th3fanbus@gmail.com Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-CC: Raul Rangel rrangel@chromium.org Gerrit-Comment-Date: Mon, 14 Sep 2020 17:34:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel rrangel@chromium.org Gerrit-MessageType: comment

Aaron Durbin (Code Review)

5:39 p.m.

New subject: Change in coreboot[master]: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45333 )

Change subject: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port ......................................................................

Patch Set 4:

(1 comment)

https://review.coreboot.org/c/coreboot/+/45333/4/src/soc/amd/picasso/chip.h File src/soc/amd/picasso/chip.h:

https://review.coreboot.org/c/coreboot/+/45333/4/src/soc/amd/picasso/chip.h@... PS4, Line 158: uint8_t xhci0_force_gen1; How is this different than the newly added one?

chris wang (Code Review)

21 Sep 21 Sep

12:31 p.m.

New subject: Change in coreboot[master]: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port

Hello build bot (Jenkins), Furquan Shaikh, Chris Wang, Keith Tzeng, Aaron Durbin,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/45333

to look at the new patch set (#5).

Change subject: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port ......................................................................

soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port

Add UPD usb3_port_force_gen1 for support USB3 port force to gen1.

BUG=b:167651308 BRANCH=zork TEST=Build, verify the USB3 speed in gen1

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/45333/5

chris wang (Code Review)

12:37 p.m.

New subject: Change in coreboot[master]: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port

chris wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45333 )

Change subject: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port ......................................................................

Patch Set 5:

(2 comments)

https://review.coreboot.org/c/coreboot/+/45333/4/src/soc/amd/picasso/chip.h File src/soc/amd/picasso/chip.h:

https://review.coreboot.org/c/coreboot/+/45333/4/src/soc/amd/picasso/chip.h@... PS4, Line 158: uint8_t xhci0_force_gen1;

...

How is this different than the newly added one?

for xhci0_force_gen1,it will set all port on xhci0 to gen1 but usb3_port_force_gen1 will set it by individual port.

https://review.coreboot.org/c/coreboot/+/45333/4/src/soc/amd/picasso/chip.h@... PS4, Line 172: usb3_port_force_gen1

...

Ya. this doesn't seem per port unless it's a bitfield.

Done

-- To view, visit https://review.coreboot.org/c/coreboot/+/45333 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I896c185988c3ea5dbdd72957b363ebdaa2747cff Gerrit-Change-Number: 45333 Gerrit-PatchSet: 5 Gerrit-Owner: chris wang Chris.Wang@amd.com Gerrit-Reviewer: Aaron Durbin adurbin@chromium.org Gerrit-Reviewer: Chris Wang chris.wang@amd.corp-partner.google.com Gerrit-Reviewer: Furquan Shaikh furquan@google.com Gerrit-Reviewer: Keith Tzeng keith.tzeng@quanta.corp-partner.google.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Angel Pons th3fanbus@gmail.com Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-CC: Raul Rangel rrangel@chromium.org Gerrit-Comment-Date: Mon, 21 Sep 2020 12:37:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel rrangel@chromium.org Comment-In-Reply-To: Aaron Durbin adurbin@chromium.org Gerrit-MessageType: comment

Raul Rangel (Code Review)

3:13 p.m.

New subject: Change in coreboot[master]: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port

Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45333 )

Change subject: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port ......................................................................

Patch Set 5:

(2 comments)

https://review.coreboot.org/c/coreboot/+/45333/5/src/soc/amd/picasso/chip.h File src/soc/amd/picasso/chip.h:

https://review.coreboot.org/c/coreboot/+/45333/5/src/soc/amd/picasso/chip.h@... PS5, Line 41: typedef no typedefs please.

https://review.coreboot.org/c/coreboot/+/45333/5/src/soc/amd/picasso/chip.h@... PS5, Line 47: xhci1_port0 Dali doesn't have an xhci1 right?

chris wang (Code Review)

22 Sep 22 Sep

12:55 p.m.

New subject: Change in coreboot[master]: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port

Hello build bot (Jenkins), Furquan Shaikh, Chris Wang, Keith Tzeng, Aaron Durbin,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/45333

to look at the new patch set (#6).

Change subject: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port ......................................................................

soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port

Add UPD usb3_port_force_gen1 for support USB3 port force to gen1.

BUG=b:167651308 BRANCH=zork TEST=Build, verify the USB3 speed in gen1

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/45333/6

chris wang (Code Review)

1 p.m.

New subject: Change in coreboot[master]: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port

Hello build bot (Jenkins), Furquan Shaikh, Chris Wang, Keith Tzeng, Aaron Durbin,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/45333

to look at the new patch set (#7).

Change subject: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port ......................................................................

soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port

Add UPD usb3_port_force_gen1 for support USB3 port force to gen1.

BUG=b:167651308 BRANCH=zork TEST=Build, verify the USB3 speed in gen1

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/45333/7

chris wang (Code Review)

1:02 p.m.

New subject: Change in coreboot[master]: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port

chris wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45333 )

Change subject: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port ......................................................................

Patch Set 7:

(2 comments)

https://review.coreboot.org/c/coreboot/+/45333/5/src/soc/amd/picasso/chip.h File src/soc/amd/picasso/chip.h:

https://review.coreboot.org/c/coreboot/+/45333/5/src/soc/amd/picasso/chip.h@... PS5, Line 41: typedef

...

no typedefs please.

Done

https://review.coreboot.org/c/coreboot/+/45333/5/src/soc/amd/picasso/chip.h@... PS5, Line 47: xhci1_port0

...

Dali doesn't have an xhci1 right?

yes, I add a comment for noticed the USB usage.

-- To view, visit https://review.coreboot.org/c/coreboot/+/45333 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I896c185988c3ea5dbdd72957b363ebdaa2747cff Gerrit-Change-Number: 45333 Gerrit-PatchSet: 7 Gerrit-Owner: chris wang Chris.Wang@amd.com Gerrit-Reviewer: Aaron Durbin adurbin@chromium.org Gerrit-Reviewer: Chris Wang chris.wang@amd.corp-partner.google.com Gerrit-Reviewer: Furquan Shaikh furquan@google.com Gerrit-Reviewer: Keith Tzeng keith.tzeng@quanta.corp-partner.google.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Angel Pons th3fanbus@gmail.com Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-CC: Raul Rangel rrangel@chromium.org Gerrit-Comment-Date: Tue, 22 Sep 2020 13:02:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel rrangel@chromium.org Gerrit-MessageType: comment

Aaron Durbin (Code Review)

4:08 p.m.

New subject: Change in coreboot[master]: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45333 )

Change subject: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port ......................................................................

Patch Set 7: Code-Review+1

(1 comment)

https://review.coreboot.org/c/coreboot/+/45333/7/src/soc/amd/picasso/chip.h File src/soc/amd/picasso/chip.h:

https://review.coreboot.org/c/coreboot/+/45333/7/src/soc/amd/picasso/chip.h@... PS7, Line 173: uint8_t xhci0_force_gen1; You should probably comment as to what this does, and the field below is likely the correct one to use for policy modifications. If anything, I think we should remove xhci0_force_gen1 from chip.h.

Raul Rangel (Code Review)

4:38 p.m.

New subject: Change in coreboot[master]: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port

Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45333 )

Change subject: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port ......................................................................

Patch Set 7:

(1 comment)

https://review.coreboot.org/c/coreboot/+/45333/7/src/soc/amd/picasso/chip.h File src/soc/amd/picasso/chip.h:

https://review.coreboot.org/c/coreboot/+/45333/7/src/soc/amd/picasso/chip.h@... PS7, Line 173: uint8_t xhci0_force_gen1;

...

You should probably comment as to what this does, and the field below is likely the correct one to u […]

+1 some documentation here would be helpful.

-- To view, visit https://review.coreboot.org/c/coreboot/+/45333 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I896c185988c3ea5dbdd72957b363ebdaa2747cff Gerrit-Change-Number: 45333 Gerrit-PatchSet: 7 Gerrit-Owner: chris wang Chris.Wang@amd.com Gerrit-Reviewer: Aaron Durbin adurbin@chromium.org Gerrit-Reviewer: Chris Wang chris.wang@amd.corp-partner.google.com Gerrit-Reviewer: Furquan Shaikh furquan@google.com Gerrit-Reviewer: Keith Tzeng keith.tzeng@quanta.corp-partner.google.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Angel Pons th3fanbus@gmail.com Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-CC: Raul Rangel rrangel@chromium.org Gerrit-Comment-Date: Tue, 22 Sep 2020 16:38:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Aaron Durbin adurbin@chromium.org Gerrit-MessageType: comment

chris wang (Code Review)

25 Sep 25 Sep

1:10 p.m.

New subject: Change in coreboot[master]: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port

Hello build bot (Jenkins), Furquan Shaikh, Chris Wang, Keith Tzeng, Aaron Durbin,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/45333

to look at the new patch set (#8).

Change subject: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port ......................................................................

soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port

Add UPD usb3_port_force_gen1 for support USB3 port force to gen1.

BUG=b:167651308 BRANCH=zork TEST=Build, verify the USB3 speed in gen1

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/45333/8

chris wang (Code Review)

1:12 p.m.

New subject: Change in coreboot[master]: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port

chris wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45333 )

Change subject: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port ......................................................................

Patch Set 8:

(1 comment)

https://review.coreboot.org/c/coreboot/+/45333/7/src/soc/amd/picasso/chip.h File src/soc/amd/picasso/chip.h:

https://review.coreboot.org/c/coreboot/+/45333/7/src/soc/amd/picasso/chip.h@... PS7, Line 173: uint8_t xhci0_force_gen1;

...

+1 some documentation here would be helpful.

Add comment for xhci0_force_gen1 and usb3_port_froce_gen1.

-- To view, visit https://review.coreboot.org/c/coreboot/+/45333 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I896c185988c3ea5dbdd72957b363ebdaa2747cff Gerrit-Change-Number: 45333 Gerrit-PatchSet: 8 Gerrit-Owner: chris wang Chris.Wang@amd.com Gerrit-Reviewer: Aaron Durbin adurbin@chromium.org Gerrit-Reviewer: Chris Wang chris.wang@amd.corp-partner.google.com Gerrit-Reviewer: Furquan Shaikh furquan@google.com Gerrit-Reviewer: Keith Tzeng keith.tzeng@quanta.corp-partner.google.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Angel Pons th3fanbus@gmail.com Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-CC: Raul Rangel rrangel@chromium.org Gerrit-Comment-Date: Fri, 25 Sep 2020 13:12:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel rrangel@chromium.org Comment-In-Reply-To: Aaron Durbin adurbin@chromium.org Gerrit-MessageType: comment

Furquan Shaikh (Code Review)

1:18 p.m.

New subject: Change in coreboot[master]: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45333 )

Change subject: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port ......................................................................

Patch Set 8:

(1 comment)

https://review.coreboot.org/c/coreboot/+/45333/8/src/soc/amd/picasso/chip.h File src/soc/amd/picasso/chip.h:

https://review.coreboot.org/c/coreboot/+/45333/8/src/soc/amd/picasso/chip.h@... PS8, Line 173: xhci0_force_gen1 Shouldn't this be dropped now?

chris wang (Code Review)

28 Sep 28 Sep

5:37 a.m.

New subject: Change in coreboot[master]: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port

chris wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45333 )

Change subject: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port ......................................................................

Patch Set 8:

(5 comments)

https://review.coreboot.org/c/coreboot/+/45333/1//COMMIT_MSG Commit Message:

https://review.coreboot.org/c/coreboot/+/45333/1//COMMIT_MSG@9 PS1, Line 9: add upd usb3_port_force_gen1 for support USB3 port to gen1

...

Please start sentences with a capital letter and finish with a dot/period.

Done

https://review.coreboot.org/c/coreboot/+/45333/1//COMMIT_MSG@13 PS1, Line 13: TEST=Build,verify the USB3 speed in gen1

...

Please add a space after the comma.

Done

https://review.coreboot.org/c/coreboot/+/45333/8/src/soc/amd/picasso/chip.h File src/soc/amd/picasso/chip.h:

https://review.coreboot.org/c/coreboot/+/45333/8/src/soc/amd/picasso/chip.h@... PS8, Line 173: xhci0_force_gen1

...

Shouldn't this be dropped now?

I can separate a CL to remove this and use the usb3_port_force_gen1 instead.

https://review.coreboot.org/c/coreboot/+/45333/5/src/soc/amd/picasso/chip.h File src/soc/amd/picasso/chip.h:

https://review.coreboot.org/c/coreboot/+/45333/5/src/soc/amd/picasso/chip.h@... PS5, Line 47: xhci1_port0

...

yes, I add a comment for noticed the USB usage.

Done

https://review.coreboot.org/c/coreboot/+/45333/4/src/soc/amd/picasso/chip.h File src/soc/amd/picasso/chip.h:

https://review.coreboot.org/c/coreboot/+/45333/4/src/soc/amd/picasso/chip.h@... PS4, Line 158: uint8_t xhci0_force_gen1;

...

for xhci0_force_gen1,it will set all port on xhci0 to gen1 but usb3_port_force_gen1 will set it by i […]

Done

-- To view, visit https://review.coreboot.org/c/coreboot/+/45333 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I896c185988c3ea5dbdd72957b363ebdaa2747cff Gerrit-Change-Number: 45333 Gerrit-PatchSet: 8 Gerrit-Owner: chris wang Chris.Wang@amd.com Gerrit-Reviewer: Aaron Durbin adurbin@chromium.org Gerrit-Reviewer: Chris Wang chris.wang@amd.corp-partner.google.com Gerrit-Reviewer: Furquan Shaikh furquan@google.com Gerrit-Reviewer: Keith Tzeng keith.tzeng@quanta.corp-partner.google.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Angel Pons th3fanbus@gmail.com Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-CC: Raul Rangel rrangel@chromium.org Gerrit-Comment-Date: Mon, 28 Sep 2020 05:37:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel rrangel@chromium.org Comment-In-Reply-To: Furquan Shaikh furquan@google.com Comment-In-Reply-To: Paul Menzel paulepanter@users.sourceforge.net Comment-In-Reply-To: chris wang Chris.Wang@amd.com Comment-In-Reply-To: Aaron Durbin adurbin@chromium.org Gerrit-MessageType: comment

chris wang (Code Review)

5 Oct 5 Oct

5:09 a.m.

New subject: Change in coreboot[master]: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port

Hello build bot (Jenkins), Furquan Shaikh, Chris Wang, Keith Tzeng, Aaron Durbin,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/45333

to look at the new patch set (#9).

Change subject: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port ......................................................................

soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port

Add UPD usb3_port_force_gen1 for support USB3 port force to gen1.

BUG=b:167651308 BRANCH=zork TEST=Build, verify the USB3 speed in gen1

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/45333/9

Martin Roth (Code Review)

6 Oct 6 Oct

7:21 p.m.

New subject: Change in coreboot[master]: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port

Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45333 )

Change subject: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port ......................................................................

Patch Set 9:

(1 comment)

https://review.coreboot.org/c/coreboot/+/45333/9/src/soc/amd/picasso/chip.h File src/soc/amd/picasso/chip.h:

https://review.coreboot.org/c/coreboot/+/45333/9/src/soc/amd/picasso/chip.h@... PS9, Line 175: usb3_port_force_gen1 usb3_port_force_gen1; Could you rename either the struct or the variable?

-- To view, visit https://review.coreboot.org/c/coreboot/+/45333 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I896c185988c3ea5dbdd72957b363ebdaa2747cff Gerrit-Change-Number: 45333 Gerrit-PatchSet: 9 Gerrit-Owner: chris wang Chris.Wang@amd.com Gerrit-Reviewer: Aaron Durbin adurbin@chromium.org Gerrit-Reviewer: Chris Wang chris.wang@amd.corp-partner.google.com Gerrit-Reviewer: Felix Held felix-coreboot@felixheld.de Gerrit-Reviewer: Furquan Shaikh furquan@google.com Gerrit-Reviewer: Keith Tzeng keith.tzeng@quanta.corp-partner.google.com Gerrit-Reviewer: Marshall Dawson marshalldawson3rd@gmail.com Gerrit-Reviewer: Martin Roth martinroth@google.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Angel Pons th3fanbus@gmail.com Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-CC: Raul Rangel rrangel@chromium.org Gerrit-Comment-Date: Tue, 06 Oct 2020 19:21:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

Marshall Dawson (Code Review)

11:56 p.m.

New subject: Change in coreboot[master]: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port

Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45333 )

Change subject: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port ......................................................................

Patch Set 9:

I had the same thought about the identical structure and variable names. If you change it in your daytime, Felix might approve it before Martin or I see it.

-- To view, visit https://review.coreboot.org/c/coreboot/+/45333 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I896c185988c3ea5dbdd72957b363ebdaa2747cff Gerrit-Change-Number: 45333 Gerrit-PatchSet: 9 Gerrit-Owner: chris wang Chris.Wang@amd.com Gerrit-Reviewer: Aaron Durbin adurbin@chromium.org Gerrit-Reviewer: Chris Wang chris.wang@amd.corp-partner.google.com Gerrit-Reviewer: Felix Held felix-coreboot@felixheld.de Gerrit-Reviewer: Furquan Shaikh furquan@google.com Gerrit-Reviewer: Keith Tzeng keith.tzeng@quanta.corp-partner.google.com Gerrit-Reviewer: Marshall Dawson marshalldawson3rd@gmail.com Gerrit-Reviewer: Martin Roth martinroth@google.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Angel Pons th3fanbus@gmail.com Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-CC: Raul Rangel rrangel@chromium.org Gerrit-Comment-Date: Tue, 06 Oct 2020 23:56:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

Marshall Dawson (Code Review)

7 Oct 7 Oct

12:20 a.m.

New subject: Change in coreboot[master]: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port

Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45333 )

Change subject: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port ......................................................................

Patch Set 9:

(1 comment)

I had the same thought about the identical structure and variable names. If you change it in your daytime, Felix might approve it before Martin or I see it.

https://review.coreboot.org/c/coreboot/+/45333/9/src/soc/amd/picasso/chip.h File src/soc/amd/picasso/chip.h:

https://review.coreboot.org/c/coreboot/+/45333/9/src/soc/amd/picasso/chip.h@... PS9, Line 49: xhci1_port0 Did you check that this one works? Maybe I'm missing it, but I only see AGESA checking bits 0-3.

-- To view, visit https://review.coreboot.org/c/coreboot/+/45333 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I896c185988c3ea5dbdd72957b363ebdaa2747cff Gerrit-Change-Number: 45333 Gerrit-PatchSet: 9 Gerrit-Owner: chris wang Chris.Wang@amd.com Gerrit-Reviewer: Aaron Durbin adurbin@chromium.org Gerrit-Reviewer: Chris Wang chris.wang@amd.corp-partner.google.com Gerrit-Reviewer: Felix Held felix-coreboot@felixheld.de Gerrit-Reviewer: Furquan Shaikh furquan@google.com Gerrit-Reviewer: Keith Tzeng keith.tzeng@quanta.corp-partner.google.com Gerrit-Reviewer: Marshall Dawson marshalldawson3rd@gmail.com Gerrit-Reviewer: Martin Roth martinroth@google.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Angel Pons th3fanbus@gmail.com Gerrit-CC: Marshall Dawson marshall.dawson@amd.corp-partner.google.com Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-CC: Raul Rangel rrangel@chromium.org Gerrit-Comment-Date: Wed, 07 Oct 2020 00:20:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

chris wang (Code Review)

1:58 a.m.

New subject: Change in coreboot[master]: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port

Hello build bot (Jenkins), Martin Roth, Furquan Shaikh, Marshall Dawson, Chris Wang, Keith Tzeng, Aaron Durbin, Felix Held,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/45333

to look at the new patch set (#10).

Change subject: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port ......................................................................

soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port

Add UPD usb3_port_force_gen1 for support USB3 port force to gen1.

BUG=b:167651308 BRANCH=zork TEST=Build, verify the USB3 speed in gen1

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/45333/10

-- To view, visit https://review.coreboot.org/c/coreboot/+/45333 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I896c185988c3ea5dbdd72957b363ebdaa2747cff Gerrit-Change-Number: 45333 Gerrit-PatchSet: 10 Gerrit-Owner: chris wang Chris.Wang@amd.com Gerrit-Reviewer: Aaron Durbin adurbin@chromium.org Gerrit-Reviewer: Chris Wang chris.wang@amd.corp-partner.google.com Gerrit-Reviewer: Felix Held felix-coreboot@felixheld.de Gerrit-Reviewer: Furquan Shaikh furquan@google.com Gerrit-Reviewer: Keith Tzeng keith.tzeng@quanta.corp-partner.google.com Gerrit-Reviewer: Marshall Dawson marshalldawson3rd@gmail.com Gerrit-Reviewer: Martin Roth martinroth@google.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Angel Pons th3fanbus@gmail.com Gerrit-CC: Marshall Dawson marshall.dawson@amd.corp-partner.google.com Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-CC: Raul Rangel rrangel@chromium.org Gerrit-MessageType: newpatchset

chris wang (Code Review)

2:01 a.m.

New subject: Change in coreboot[master]: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port

chris wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45333 )

Change subject: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port ......................................................................

Patch Set 10:

(2 comments)

https://review.coreboot.org/c/coreboot/+/45333/9/src/soc/amd/picasso/chip.h File src/soc/amd/picasso/chip.h:

https://review.coreboot.org/c/coreboot/+/45333/9/src/soc/amd/picasso/chip.h@... PS9, Line 49: xhci1_port0

...

Did you check that this one works? Maybe I'm missing it, but I only see AGESA checking bits 0-3.

yes, it only disable to port3. so remove the xhci1_port_0.

https://review.coreboot.org/c/coreboot/+/45333/9/src/soc/amd/picasso/chip.h@... PS9, Line 175: usb3_port_force_gen1 usb3_port_force_gen1;

...

Could you rename either the struct or the variable?

Done

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Felix Held (Code Review)

2:07 p.m.

New subject: Change in coreboot[master]: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45333 )

Change subject: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port ......................................................................

Patch Set 10:

(1 comment)

https://review.coreboot.org/c/coreboot/+/45333/10/src/soc/amd/picasso/chip.h File src/soc/amd/picasso/chip.h:

https://review.coreboot.org/c/coreboot/+/45333/10/src/soc/amd/picasso/chip.h... PS10, Line 41: struct __packed usb3_force_gen1 { I wonder if it's needed to wrap the union in a struct that only contains the union or if the outermost struct can be omitted

-- To view, visit https://review.coreboot.org/c/coreboot/+/45333 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I896c185988c3ea5dbdd72957b363ebdaa2747cff Gerrit-Change-Number: 45333 Gerrit-PatchSet: 10 Gerrit-Owner: chris wang Chris.Wang@amd.com Gerrit-Reviewer: Aaron Durbin adurbin@chromium.org Gerrit-Reviewer: Chris Wang chris.wang@amd.corp-partner.google.com Gerrit-Reviewer: Felix Held felix-coreboot@felixheld.de Gerrit-Reviewer: Furquan Shaikh furquan@google.com Gerrit-Reviewer: Keith Tzeng keith.tzeng@quanta.corp-partner.google.com Gerrit-Reviewer: Marshall Dawson marshalldawson3rd@gmail.com Gerrit-Reviewer: Martin Roth martinroth@google.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Angel Pons th3fanbus@gmail.com Gerrit-CC: Marshall Dawson marshall.dawson@amd.corp-partner.google.com Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-CC: Raul Rangel rrangel@chromium.org Gerrit-Comment-Date: Wed, 07 Oct 2020 14:07:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

chris wang (Code Review)

3:37 p.m.

New subject: Change in coreboot[master]: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port

Hello build bot (Jenkins), Martin Roth, Furquan Shaikh, Marshall Dawson, Chris Wang, Keith Tzeng, Aaron Durbin, Felix Held,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/45333

to look at the new patch set (#11).

Change subject: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port ......................................................................

soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port

Add UPD usb3_port_force_gen1 for support USB3 port force to gen1.

BUG=b:167651308 BRANCH=zork TEST=Build, verify the USB3 speed in gen1

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/45333/11

-- To view, visit https://review.coreboot.org/c/coreboot/+/45333 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I896c185988c3ea5dbdd72957b363ebdaa2747cff Gerrit-Change-Number: 45333 Gerrit-PatchSet: 11 Gerrit-Owner: chris wang Chris.Wang@amd.com Gerrit-Reviewer: Aaron Durbin adurbin@chromium.org Gerrit-Reviewer: Chris Wang chris.wang@amd.corp-partner.google.com Gerrit-Reviewer: Felix Held felix-coreboot@felixheld.de Gerrit-Reviewer: Furquan Shaikh furquan@google.com Gerrit-Reviewer: Keith Tzeng keith.tzeng@quanta.corp-partner.google.com Gerrit-Reviewer: Marshall Dawson marshalldawson3rd@gmail.com Gerrit-Reviewer: Martin Roth martinroth@google.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Angel Pons th3fanbus@gmail.com Gerrit-CC: Marshall Dawson marshall.dawson@amd.corp-partner.google.com Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-CC: Raul Rangel rrangel@chromium.org Gerrit-MessageType: newpatchset

Chris Wang (Code Review)

3:41 p.m.

New subject: Change in coreboot[master]: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port

Chris Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45333 )

Change subject: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port ......................................................................

Patch Set 11:

(1 comment)

https://review.coreboot.org/c/coreboot/+/45333/10/src/soc/amd/picasso/chip.h File src/soc/amd/picasso/chip.h:

https://review.coreboot.org/c/coreboot/+/45333/10/src/soc/amd/picasso/chip.h... PS10, Line 41: struct __packed usb3_force_gen1 {

...

I wonder if it's needed to wrap the union in a struct that only contains the union or if the outermo […]

Done

-- To view, visit https://review.coreboot.org/c/coreboot/+/45333 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I896c185988c3ea5dbdd72957b363ebdaa2747cff Gerrit-Change-Number: 45333 Gerrit-PatchSet: 11 Gerrit-Owner: chris wang Chris.Wang@amd.com Gerrit-Reviewer: Aaron Durbin adurbin@chromium.org Gerrit-Reviewer: Chris Wang chris.wang@amd.corp-partner.google.com Gerrit-Reviewer: Felix Held felix-coreboot@felixheld.de Gerrit-Reviewer: Furquan Shaikh furquan@google.com Gerrit-Reviewer: Keith Tzeng keith.tzeng@quanta.corp-partner.google.com Gerrit-Reviewer: Marshall Dawson marshalldawson3rd@gmail.com Gerrit-Reviewer: Martin Roth martinroth@google.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Angel Pons th3fanbus@gmail.com Gerrit-CC: Marshall Dawson marshall.dawson@amd.corp-partner.google.com Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-CC: Raul Rangel rrangel@chromium.org Gerrit-Comment-Date: Wed, 07 Oct 2020 15:41:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held felix-coreboot@felixheld.de Gerrit-MessageType: comment

Felix Held (Code Review)

3:47 p.m.

New subject: Change in coreboot[master]: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45333 )

Change subject: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port ......................................................................

Patch Set 11: Code-Review+2

-- To view, visit https://review.coreboot.org/c/coreboot/+/45333 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I896c185988c3ea5dbdd72957b363ebdaa2747cff Gerrit-Change-Number: 45333 Gerrit-PatchSet: 11 Gerrit-Owner: chris wang Chris.Wang@amd.com Gerrit-Reviewer: Aaron Durbin adurbin@chromium.org Gerrit-Reviewer: Chris Wang chris.wang@amd.corp-partner.google.com Gerrit-Reviewer: Felix Held felix-coreboot@felixheld.de Gerrit-Reviewer: Furquan Shaikh furquan@google.com Gerrit-Reviewer: Keith Tzeng keith.tzeng@quanta.corp-partner.google.com Gerrit-Reviewer: Marshall Dawson marshalldawson3rd@gmail.com Gerrit-Reviewer: Martin Roth martinroth@google.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Angel Pons th3fanbus@gmail.com Gerrit-CC: Marshall Dawson marshall.dawson@amd.corp-partner.google.com Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-CC: Raul Rangel rrangel@chromium.org Gerrit-Comment-Date: Wed, 07 Oct 2020 15:47:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

chris wang (Code Review)

4:25 p.m.

New subject: Change in coreboot[master]: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port

Hello build bot (Jenkins), Martin Roth, Furquan Shaikh, Marshall Dawson, Chris Wang, Keith Tzeng, Aaron Durbin, Felix Held,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/45333

to look at the new patch set (#12).

Change subject: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port ......................................................................

soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port

Add UPD usb3_port_force_gen1 for support USB3 port force to gen1.

BUG=b:167651308 BRANCH=zork TEST=Build, verify the USB3 speed in gen1

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/45333/12

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Felix Held (Code Review)

4:42 p.m.

New subject: Change in coreboot[master]: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45333 )

Change subject: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port ......................................................................

Patch Set 12: Code-Review+2

-- To view, visit https://review.coreboot.org/c/coreboot/+/45333 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I896c185988c3ea5dbdd72957b363ebdaa2747cff Gerrit-Change-Number: 45333 Gerrit-PatchSet: 12 Gerrit-Owner: chris wang Chris.Wang@amd.com Gerrit-Reviewer: Aaron Durbin adurbin@chromium.org Gerrit-Reviewer: Chris Wang chris.wang@amd.corp-partner.google.com Gerrit-Reviewer: Felix Held felix-coreboot@felixheld.de Gerrit-Reviewer: Furquan Shaikh furquan@google.com Gerrit-Reviewer: Keith Tzeng keith.tzeng@quanta.corp-partner.google.com Gerrit-Reviewer: Marshall Dawson marshalldawson3rd@gmail.com Gerrit-Reviewer: Martin Roth martinroth@google.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Angel Pons th3fanbus@gmail.com Gerrit-CC: Marshall Dawson marshall.dawson@amd.corp-partner.google.com Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-CC: Raul Rangel rrangel@chromium.org Gerrit-Comment-Date: Wed, 07 Oct 2020 16:42:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

Edward O'Callaghan (Code Review)

8 Oct 8 Oct

12:55 a.m.

New subject: Change in coreboot[master]: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port

Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45333 )

Change subject: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port ......................................................................

Patch Set 12: Code-Review+2

-- To view, visit https://review.coreboot.org/c/coreboot/+/45333 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I896c185988c3ea5dbdd72957b363ebdaa2747cff Gerrit-Change-Number: 45333 Gerrit-PatchSet: 12 Gerrit-Owner: chris wang Chris.Wang@amd.com Gerrit-Reviewer: Aaron Durbin adurbin@chromium.org Gerrit-Reviewer: Chris Wang chris.wang@amd.corp-partner.google.com Gerrit-Reviewer: Edward O'Callaghan quasisec@chromium.org Gerrit-Reviewer: Felix Held felix-coreboot@felixheld.de Gerrit-Reviewer: Furquan Shaikh furquan@google.com Gerrit-Reviewer: Keith Tzeng keith.tzeng@quanta.corp-partner.google.com Gerrit-Reviewer: Marshall Dawson marshalldawson3rd@gmail.com Gerrit-Reviewer: Martin Roth martinroth@google.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Angel Pons th3fanbus@gmail.com Gerrit-CC: Marshall Dawson marshall.dawson@amd.corp-partner.google.com Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-CC: Raul Rangel rrangel@chromium.org Gerrit-Comment-Date: Thu, 08 Oct 2020 00:55:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

Edward O'Callaghan (Code Review)

12:59 a.m.

New subject: Change in coreboot[master]: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port

Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45333 )

Change subject: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port ......................................................................

Patch Set 12:

(1 comment)

https://review.coreboot.org/c/coreboot/+/45333/12/src/soc/amd/picasso/chip.h File src/soc/amd/picasso/chip.h:

https://review.coreboot.org/c/coreboot/+/45333/12/src/soc/amd/picasso/chip.h... PS12, Line 41: usb3_force_gen1 feel free to make this as a follow up as its a bit of a nit but I think you could do a typedef here and have `usb3_force_gen1_t`.

-- To view, visit https://review.coreboot.org/c/coreboot/+/45333 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I896c185988c3ea5dbdd72957b363ebdaa2747cff Gerrit-Change-Number: 45333 Gerrit-PatchSet: 12 Gerrit-Owner: chris wang Chris.Wang@amd.com Gerrit-Reviewer: Aaron Durbin adurbin@chromium.org Gerrit-Reviewer: Chris Wang chris.wang@amd.corp-partner.google.com Gerrit-Reviewer: Edward O'Callaghan quasisec@chromium.org Gerrit-Reviewer: Felix Held felix-coreboot@felixheld.de Gerrit-Reviewer: Furquan Shaikh furquan@google.com Gerrit-Reviewer: Keith Tzeng keith.tzeng@quanta.corp-partner.google.com Gerrit-Reviewer: Marshall Dawson marshalldawson3rd@gmail.com Gerrit-Reviewer: Martin Roth martinroth@google.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Angel Pons th3fanbus@gmail.com Gerrit-CC: Marshall Dawson marshall.dawson@amd.corp-partner.google.com Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-CC: Raul Rangel rrangel@chromium.org Gerrit-Comment-Date: Thu, 08 Oct 2020 00:59:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

Sam McNally (Code Review)

1:27 a.m.

New subject: Change in coreboot[master]: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port

Sam McNally has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45333 )

Change subject: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port ......................................................................

Patch Set 12: Code-Review+2

-- To view, visit https://review.coreboot.org/c/coreboot/+/45333 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I896c185988c3ea5dbdd72957b363ebdaa2747cff Gerrit-Change-Number: 45333 Gerrit-PatchSet: 12 Gerrit-Owner: chris wang Chris.Wang@amd.com Gerrit-Reviewer: Aaron Durbin adurbin@chromium.org Gerrit-Reviewer: Chris Wang chris.wang@amd.corp-partner.google.com Gerrit-Reviewer: Edward O'Callaghan quasisec@chromium.org Gerrit-Reviewer: Felix Held felix-coreboot@felixheld.de Gerrit-Reviewer: Furquan Shaikh furquan@google.com Gerrit-Reviewer: Keith Tzeng keith.tzeng@quanta.corp-partner.google.com Gerrit-Reviewer: Marshall Dawson marshalldawson3rd@gmail.com Gerrit-Reviewer: Martin Roth martinroth@google.com Gerrit-Reviewer: Sam McNally sammc@google.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Angel Pons th3fanbus@gmail.com Gerrit-CC: Marshall Dawson marshall.dawson@amd.corp-partner.google.com Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-CC: Raul Rangel rrangel@chromium.org Gerrit-Comment-Date: Thu, 08 Oct 2020 01:27:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

Edward O'Callaghan (Code Review)

1:29 a.m.

New subject: Change in coreboot[master]: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port

Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45333 )

Change subject: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port ......................................................................

Patch Set 12:

(1 comment)

https://review.coreboot.org/c/coreboot/+/45333/12/src/soc/amd/picasso/chip.h File src/soc/amd/picasso/chip.h:

https://review.coreboot.org/c/coreboot/+/45333/12/src/soc/amd/picasso/chip.h... PS12, Line 41: usb3_force_gen1

...

feel free to make this as a follow up as its a bit of a nit but I think you could do a typedef here […]

-- To view, visit https://review.coreboot.org/c/coreboot/+/45333 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I896c185988c3ea5dbdd72957b363ebdaa2747cff Gerrit-Change-Number: 45333 Gerrit-PatchSet: 12 Gerrit-Owner: chris wang Chris.Wang@amd.com Gerrit-Reviewer: Aaron Durbin adurbin@chromium.org Gerrit-Reviewer: Chris Wang chris.wang@amd.corp-partner.google.com Gerrit-Reviewer: Edward O'Callaghan quasisec@chromium.org Gerrit-Reviewer: Felix Held felix-coreboot@felixheld.de Gerrit-Reviewer: Furquan Shaikh furquan@google.com Gerrit-Reviewer: Keith Tzeng keith.tzeng@quanta.corp-partner.google.com Gerrit-Reviewer: Marshall Dawson marshalldawson3rd@gmail.com Gerrit-Reviewer: Martin Roth martinroth@google.com Gerrit-Reviewer: Sam McNally sammc@google.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Angel Pons th3fanbus@gmail.com Gerrit-CC: Marshall Dawson marshall.dawson@amd.corp-partner.google.com Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-CC: Raul Rangel rrangel@chromium.org Gerrit-Comment-Date: Thu, 08 Oct 2020 01:29:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Edward O'Callaghan quasisec@chromium.org Gerrit-MessageType: comment

Edward O'Callaghan (Code Review)

1:30 a.m.

New subject: Change in coreboot[master]: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port

Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45333 )

Change subject: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port ......................................................................

soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port

Add UPD usb3_port_force_gen1 for support USB3 port force to gen1.

BUG=b:167651308 BRANCH=zork TEST=Build, verify the USB3 speed in gen1

Signed-off-by: Chris Wang chris.wang@amd.corp-partner.google.com Change-Id: I896c185988c3ea5dbdd72957b363ebdaa2747cff Reviewed-on: https://review.coreboot.org/c/coreboot/+/45333 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Felix Held felix-coreboot@felixheld.de Reviewed-by: Edward O'Callaghan quasisec@chromium.org Reviewed-by: Sam McNally sammc@google.com --- M src/soc/amd/picasso/chip.h M src/soc/amd/picasso/fsp_params.c 2 files changed, 15 insertions(+), 1 deletion(-)

Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Edward O'Callaghan: Looks good to me, approved Sam McNally: Looks good to me, approved

diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index a39549e..f4233de 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -37,6 +37,17 @@ uint8_t tx_res_tune; };

+/* force USB3 port to gen1, bit0 - controller0 Port0, bit1 - Port1, etc */ +union __packed usb3_force_gen1 { + struct { + uint8_t xhci0_port0:1; + uint8_t xhci0_port1:1; + uint8_t xhci0_port2:1; + uint8_t xhci0_port3:1; + } ports; + uint8_t usb3_port_force_gen1_en; +}; + #define USB_PORT_COUNT 6

enum sd_emmc_driver_strength { @@ -190,8 +201,10 @@ */ uint16_t init_khz_preset; } emmc_config; - + /* set xhci0 from gen2 to gen1 */ uint8_t xhci0_force_gen1; + /* Force USB3 port to gen1, bit0 - controller0 Port0, bit1 - Port1 */ + union usb3_force_gen1 usb3_port_force_gen1;

uint8_t has_usb2_phy_tune_params; struct usb2_phy_tune usb_2_port_tune_params[USB_PORT_COUNT]; diff --git a/src/soc/amd/picasso/fsp_params.c b/src/soc/amd/picasso/fsp_params.c index 95e691d..973bb87d4 100644 --- a/src/soc/amd/picasso/fsp_params.c +++ b/src/soc/amd/picasso/fsp_params.c @@ -111,6 +111,7 @@ ASSERT(2 * sizeof(scfg->xhci_oc_pin_select) >= USB_PORT_COUNT);

scfg->xhci0_force_gen1 = cfg->xhci0_force_gen1; + scfg->fch_usb_3_port_force_gen1 = cfg->usb3_port_force_gen1.usb3_port_force_gen1_en;

if (cfg->has_usb2_phy_tune_params) { for (i = 0; i < FSPS_UPD_USB2_PORT_COUNT; i++) {

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38 comments

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participants (12)

Aaron Durbin (Code Review)
Angel Pons (Code Review)
Chris Wang (Code Review)
chris wang (Code Review)
Edward O'Callaghan (Code Review)
Felix Held (Code Review)
Furquan Shaikh (Code Review)
Marshall Dawson (Code Review)
Martin Roth (Code Review)
Paul Menzel (Code Review)
Raul Rangel (Code Review)
Sam McNally (Code Review)