HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46239 )
Change subject: soc/intel/cannonlake: Convert to ASL 2.0 syntax ......................................................................
soc/intel/cannonlake: Convert to ASL 2.0 syntax
Change-Id: Ia587ec4831fcd93d9f53aa219544c8078c360aae Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/soc/intel/cannonlake/acpi/gpio.asl M src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl M src/soc/intel/cannonlake/acpi/pch_hda.asl M src/soc/intel/cannonlake/acpi/scs.asl 4 files changed, 83 insertions(+), 85 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/46239/1
diff --git a/src/soc/intel/cannonlake/acpi/gpio.asl b/src/soc/intel/cannonlake/acpi/gpio.asl index f1284e1..aa74a5e 100644 --- a/src/soc/intel/cannonlake/acpi/gpio.asl +++ b/src/soc/intel/cannonlake/acpi/gpio.asl @@ -30,20 +30,20 @@ /* GPIO Community 0 */ CreateDWordField (^RBUF, ^COM0._BAS, BAS0) CreateDWordField (^RBUF, ^COM0._LEN, LEN0) - Store (^^PCRB (PID_GPIOCOM0), BAS0) - Store (GPIO_BASE_SIZE, LEN0) + BAS0 = ^^PCRB (PID_GPIOCOM0) + LEN0 = GPIO_BASE_SIZE
/* GPIO Community 1 */ CreateDWordField (^RBUF, ^COM1._BAS, BAS1) CreateDWordField (^RBUF, ^COM1._LEN, LEN1) - Store (^^PCRB (PID_GPIOCOM1), BAS1) - Store (GPIO_BASE_SIZE, LEN1) + BAS1 = ^^PCRB (PID_GPIOCOM1) + LEN1 = GPIO_BASE_SIZE
/* GPIO Community 4 */ CreateDWordField (^RBUF, ^COM4._BAS, BAS4) CreateDWordField (^RBUF, ^COM4._LEN, LEN4) - Store (^^PCRB (PID_GPIOCOM4), BAS4) - Store (GPIO_BASE_SIZE, LEN4) + BAS4 = ^^PCRB (PID_GPIOCOM4) + LEN4 = GPIO_BASE_SIZE
Return (RBUF) } @@ -61,38 +61,38 @@ Method (GADD, 1, NotSerialized) { /* GPIO Community 0 */ - If (LAnd (LGreaterEqual (Arg0, GPP_A0), LLessEqual (Arg0, SPI0_CLK_LOOPBK))) + If ((Arg0 >= GPP_A0) && (Arg0 <= SPI0_CLK_LOOPBK)) { - Store (PID_GPIOCOM0, Local0) - Subtract (Arg0, GPP_A0, Local1) + Local0 = PID_GPIOCOM0 + Local1 = Arg0 - GPP_A0 } /* GPIO Community 1 */ - If (LAnd (LGreaterEqual (Arg0, GPP_D0), LLessEqual (Arg0, vSD3_CD_B))) + If ((Arg0 >= GPP_D0) && (Arg0 <= vSD3_CD_B)) { - Store (PID_GPIOCOM1, Local0) - Subtract (Arg0, GPP_D0, Local1) + Local0 = PID_GPIOCOM1 + Local1 = Arg0 - GPP_D0 } /* GPIO Community 2 */ - If (LAnd (LGreaterEqual (Arg0, GPD0), LLessEqual (Arg0, DRAM_RESET_B))) + If ((Arg0 >= GPD0) && (Arg0 <= DRAM_RESET_B)) { - Store (PID_GPIOCOM2, Local0) - Subtract (Arg0, GPD0, Local1) + Local0 = PID_GPIOCOM2 + Local1 = Arg0 - GPD0 } /* GPIO Community 3 */ - If (LAnd (LGreaterEqual (Arg0, HDA_BCLK), LLessEqual (Arg0, TRIGGER_OUT))) + If ((Arg0 >= HDA_BCLK) && (Arg0 <= TRIGGER_OUT)) { - Store (PID_GPIOCOM3, Local0) - Subtract (Arg0, HDA_BCLK, Local1) + Local0 = PID_GPIOCOM3 + Local1 = Arg0 - HDA_BCLK } /* GPIO Community 4*/ - If (LAnd (LGreaterEqual (Arg0, GPP_C0), LLessEqual (Arg0, CL_RST_B))) + If ((Arg0 >= GPP_C0) && (Arg0 <= CL_RST_B)) { - Store (PID_GPIOCOM4, Local0) - Subtract (Arg0, GPP_C0, Local1) + Local0 = PID_GPIOCOM4 + Local1 = Arg0 - GPP_C0 } - Store (PCRB (Local0), Local2) - Add (Local2, PAD_CFG_BASE, Local2) - Return (Add (Local2, Multiply (Local1, 16))) + Local2 = PCRB (Local0) + Local2 += PAD_CFG_BASE + Return (Local2 + (Local1 * 16)) }
/* @@ -105,19 +105,19 @@ Switch (ToInteger (Arg0)) { Case (0) { - Store (PID_GPIOCOM0, Local0) + Local0 = PID_GPIOCOM0 } Case (1) { - Store (PID_GPIOCOM1, Local0) + Local0 = PID_GPIOCOM1 } Case (2) { - Store (PID_GPIOCOM2, Local0) + Local0 = PID_GPIOCOM2 } Case (3) { - Store (PID_GPIOCOM3, Local0) + Local0 = PID_GPIOCOM3 } Case (4) { - Store (PID_GPIOCOM4, Local0) + Local0 = PID_GPIOCOM4 } Default { Return (0) @@ -135,8 +135,8 @@ */ Method (CGPM, 2, Serialized) { - Store (GPID (Arg0), Local0) - If (LNotEqual (Local0, 0)) { + Local0 = GPID (Arg0) + If (Local0 != 0) { /* Mask off current PM bits */ PCRA (Local0, GPIO_MISCCFG, Not (MISCCFG_ENABLE_GPIO_PM_CONFIG)) /* Mask in requested bits */ diff --git a/src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl b/src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl index 5b3123d..f4177c1 100644 --- a/src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl +++ b/src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl @@ -30,26 +30,26 @@ /* GPIO Community 0 */ CreateDWordField (^RBUF, ^COM0._BAS, BAS0) CreateDWordField (^RBUF, ^COM0._LEN, LEN0) - Store (^^PCRB (PID_GPIOCOM0), BAS0) - Store (GPIO_BASE_SIZE, LEN0) + BAS0 = ^^PCRB (PID_GPIOCOM0) + LEN0 = GPIO_BASE_SIZE
/* GPIO Community 1 */ CreateDWordField (^RBUF, ^COM1._BAS, BAS1) CreateDWordField (^RBUF, ^COM1._LEN, LEN1) - Store (^^PCRB (PID_GPIOCOM1), BAS1) - Store (GPIO_BASE_SIZE, LEN1) + BAS1 = ^^PCRB (PID_GPIOCOM1) + LEN1 = GPIO_BASE_SIZE
/* GPIO Community 3 */ CreateDWordField (^RBUF, ^COM3._BAS, BAS3) CreateDWordField (^RBUF, ^COM3._LEN, LEN3) - Store (^^PCRB (PID_GPIOCOM3), BAS3) - Store (GPIO_BASE_SIZE, LEN3) + BAS3 = ^^PCRB (PID_GPIOCOM3) + LEN3 = GPIO_BASE_SIZE
/* GPIO Community 4 */ CreateDWordField (^RBUF, ^COM4._BAS, BAS4) CreateDWordField (^RBUF, ^COM4._LEN, LEN4) - Store (^^PCRB (PID_GPIOCOM4), BAS4) - Store (GPIO_BASE_SIZE, LEN4) + BAS4 = ^^PCRB (PID_GPIOCOM4) + LEN4 = GPIO_BASE_SIZE
Return (RBUF) } @@ -67,30 +67,30 @@ Method (GADD, 1, NotSerialized) { /* GPIO Community 0 */ - If (LAnd (LGreaterEqual (Arg0, GPP_A0), LLessEqual (Arg0, GSPI1_CLK_LOOPBK))) + If ((Arg0 >= GPP_A0) && (Arg0 <= GSPI1_CLK_LOOPBK)) { - Store (PID_GPIOCOM0, Local0) - Subtract (Arg0, GPP_A0, Local1) + Local0 = PID_GPIOCOM0 + Local1 = Arg0 - GPP_A0 } /* GPIO Community 1 */ - If (LAnd (LGreaterEqual (Arg0, GPP_C0), LLessEqual (Arg0, vSSP2_RXD))) + If ((Arg0 >= GPP_C0) && (Arg0 <= vSSP2_RXD)) { - Store (PID_GPIOCOM1, Local0) - Subtract (Arg0, GPP_C0, Local1) + Local0 = PID_GPIOCOM1 + Local1 = Arg0 - GPP_C0 } /* GPIO Community 3*/ - If (LAnd (LGreaterEqual (Arg0, GPP_K0), LLessEqual (Arg0, SPI0_CLK_LOOPBK))) + If ((Arg0 >= GPP_K0) && (Arg0 <= SPI0_CLK_LOOPBK)) { - Store (PID_GPIOCOM3, Local0) - Subtract (Arg0, GPP_K0, Local1) + Local0 = PID_GPIOCOM3 + Local1 = Arg0 - GPP_K0 } /* GPIO Community 4*/ - If (LAnd (LGreaterEqual (Arg0, HDACPU_SDI), LLessEqual (Arg0, GPP_J11))) + If ((Arg0 >= HDACPU_SDI) && (Arg0 <= GPP_J11)) { - Store (PID_GPIOCOM4, Local0) - Subtract (Arg0, GPP_I0, Local1) + Local0 = PID_GPIOCOM4 + Local1 = Arg0 - GPP_I0 } - Store (PCRB (Local0), Local2) - Add (Local2, PAD_CFG_BASE, Local2) - Return (Add (Local2, Multiply (Local1, 16))) + Local2 = PCRB (Local0) + Local2 += PAD_CFG_BASE + Return (Local2 + (Local1 * 16)) } diff --git a/src/soc/intel/cannonlake/acpi/pch_hda.asl b/src/soc/intel/cannonlake/acpi/pch_hda.asl index 04e974f..3de64b7 100644 --- a/src/soc/intel/cannonlake/acpi/pch_hda.asl +++ b/src/soc/intel/cannonlake/acpi/pch_hda.asl @@ -26,19 +26,17 @@ */ Method (_DSM, 4) { - If (LEqual (Arg0, ^UUID)) { + If (Arg0 == ^UUID) { /* * Function 0: Function Support Query * Returns a bitmask of functions supported. */ - If (LEqual (Arg2, Zero)) { + If (Arg2 == 0) { /* * NHLT Query only supported for revision 1 and * if NHLT address and length are set in NVS. */ - If (LAnd (LEqual (Arg1, One), - LAnd (LNotEqual (NHLA, Zero), - LNotEqual (NHLL, Zero)))) { + If ((Arg1 == 1) && (NHLA != 0) && (NHLL != 0)) { Return (Buffer (One) { 0x03 }) } Else { Return (Buffer (One) { 0x01 }) @@ -52,14 +50,14 @@ * * Returns a pointer to NHLT table in memory. */ - If (LEqual (Arg2, One)) { + If (Arg2 == 1) { CreateQWordField (NBUF, ^NHLT._MIN, NBAS) CreateQWordField (NBUF, ^NHLT._MAX, NMAS) CreateQWordField (NBUF, ^NHLT._LEN, NLEN)
- Store (NHLA, NBAS) - Store (NHLA, NMAS) - Store (NHLL, NLEN) + NBAS = NHLA + NMAS = NHLA + NLEN = NHLL
Return (NBUF) } diff --git a/src/soc/intel/cannonlake/acpi/scs.asl b/src/soc/intel/cannonlake/acpi/scs.asl index 8e1de1e..dd8d4cb 100644 --- a/src/soc/intel/cannonlake/acpi/scs.asl +++ b/src/soc/intel/cannonlake/acpi/scs.asl @@ -40,22 +40,22 @@ Method(_PS0, 0, Serialized) { Stall (50) // Sleep 50 us
- Store(0, PGEN) // Disable PG + PGEN = 0 // Disable PG
/* Clear register 0x1C20/0x4820 */ ^^SCSC (PID_EMMC)
/* Set Power State to D0 */ - And (PMCR, 0xFFFC, PMCR) - Store (PMCR, ^TEMP) + PMCR &= 0xFFFC + ^TEMP = PMCR }
Method(_PS3, 0, Serialized) { - Store(1, PGEN) // Enable PG + PGEN = 1 // Enable PG
/* Set Power State to D3 */ - Or (PMCR, 0x0003, PMCR) - Store (PMCR, ^TEMP) + PMCR |= 0x0003 + ^TEMP = PMCR }
Device (CARD) @@ -74,9 +74,9 @@ */ Method (_DSM, 4) { - If (LEqual (Arg0, ^DSUU)) { + If (Arg0 == ^DSUU) { /* Check the revision */ - If (LGreaterEqual (Arg1, Zero)) { + If (Arg1 >= 0) { /* * Function Index 0 the return value is a buffer * containing one bit for each function index, starting @@ -93,8 +93,8 @@ * Bit 6 - Indicates support for HS400 mode * Bit 9 - Indicates eMMC I/O Driver Strength */ - If (LEqual (Arg2, Zero)) { - If (Lequal (VDID, 0x02c48086) ) { + If (Arg2 == 0) { + If (VDID == 0x02c48086) { /* * Set bit 9 for CML eMMC to indicate * eMMC I/O driver strength is supported @@ -112,7 +112,7 @@ * 3 - 100 ohm * 4 - 40 ohm */ - If (LEqual (Arg2, 9)) { + If ((Arg2 == 9) { Return(Buffer() {0x4}) } } @@ -147,9 +147,9 @@ */ Method (_DSM, 4) { - If (LEqual (Arg0, ^DSUU)) { + If (Arg0 == ^DSUU) { /* Check the revision */ - If (LGreaterEqual (Arg1, Zero)) { + If (Arg1 >= 0) { /* * Function Index 0 the return value is a buffer containing * one bit for each function index, starting with zero. @@ -166,7 +166,7 @@ * For SD we have to support functions to * set 1.8V signalling and 3.3V signalling [BIT4, BIT3] */ - If (LEqual (Arg2, Zero)) { + If (Arg2 == 0) { Return (Buffer () { 0x19 }) } /* @@ -176,7 +176,7 @@ * UHS SD card on PCH. This is to compensate * for the SD VR slowness. */ - If (LEqual (Arg2, 3)) { + If (Arg2 == 3) { Sleep (100) Return(Buffer () { 0x00 }) } @@ -187,7 +187,7 @@ * UHS SD card on PCH. This is to compensate * for the SD VR slowness. */ - If (LEqual (Arg2, 4)) { + If (Arg2 == 4) { Sleep (100) Return(Buffer () { 0x00 }) } @@ -204,14 +204,14 @@
Method (_PS0, 0, Serialized) { - Store (0, PGEN) /* Disable PG */ + PGEN = 0 /* Disable PG */
/* Clear register 0x1C20/0x4820 */ ^^SCSC (PID_SDX)
/* Set Power State to D0 */ - And (PMCR, 0xFFFC, PMCR) - Store (PMCR, ^TEMP) + PMCR &= 0xFFFC + ^TEMP = PMCR
#if CONFIG(MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE) /* Change pad mode to Native */ @@ -221,11 +221,11 @@
Method (_PS3, 0, Serialized) { - Store (1, PGEN) /* Enable PG */ + PGEN = 1 /* Enable PG */
/* Set Power State to D3 */ - Or (PMCR, 0x0003, PMCR) - Store (PMCR, ^TEMP) + PMCR |= 0x0003 + ^TEMP = PMCR
#if CONFIG(MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE) /* Change pad mode to GPIO control */
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46239
to look at the new patch set (#2).
Change subject: soc/intel/cannonlake: Convert to ASL 2.0 syntax ......................................................................
soc/intel/cannonlake: Convert to ASL 2.0 syntax
Change-Id: Ia587ec4831fcd93d9f53aa219544c8078c360aae Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/soc/intel/cannonlake/acpi/gpio.asl M src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl M src/soc/intel/cannonlake/acpi/pch_hda.asl M src/soc/intel/cannonlake/acpi/scs.asl 4 files changed, 83 insertions(+), 85 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/46239/2
-
HAOUAS Elyes (Code Review)