January 2020 - coreboot-gerrit

Change in coreboot[master]: abuild: Allow proper build tests with USE_AMD_BLOBS=y
by Nico Huber (Code Review) Jan. 5, 2020

Jan. 5, 2020

Hello Marshall Dawson, Richard Spiegel, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/38043 to review the following change. Change subject: abuild: Allow proper build tests with USE_AMD_BLOBS=y ...................................................................... abuild: Allow proper build tests with USE_AMD_BLOBS=y Properly build test AMD ports that rely on blobs, too. Change-Id: Ia82f38d0e57f463ee33844c7afebb9dd602cef05 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M util/abuild/abuild 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/38043/1 diff --git a/util/abuild/abuild b/util/abuild/abuild index 23b22aa..676a446 100755 --- a/util/abuild/abuild +++ b/util/abuild/abuild @@ -723,7 +723,7 @@ shift;; -B|--blobs) shift customizing="${customizing}, blobs" - configoptions="${configoptions}CONFIG_USE_BLOBS=y\nCONFIG_ADD_FSP_BINARIES=y\nCONFIG_FSP_USE_REPO=y\n" + configoptions="${configoptions}CONFIG_USE_BLOBS=y\nCONFIG_USE_AMD_BLOBS=y\nCONFIG_ADD_FSP_BINARIES=y\nCONFIG_FSP_USE_REPO=y\n" ;; -A|--any-toolchain) shift customizing="${customizing}, any-toolchain" -- To view, visit https://review.coreboot.org/c/coreboot/+/38043 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia82f38d0e57f463ee33844c7afebb9dd602cef05 Gerrit-Change-Number: 38043 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Populate 3rdparty/amd_blobs/
by Nico Huber (Code Review) Jan. 5, 2020

Jan. 5, 2020

Hello Marshall Dawson, Richard Spiegel, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/38042 to review the following change. Change subject: Populate 3rdparty/amd_blobs/ ...................................................................... Populate 3rdparty/amd_blobs/ Kconfig default paths already point into `3rdparty/amd_blobs/`. Change-Id: Ibb6f12183c48c7c07f76e794b4971c8b75116333 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M 3rdparty/amd_blobs 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/38042/1 diff --git a/3rdparty/amd_blobs b/3rdparty/amd_blobs index cf22731..17d0288 160000 --- a/3rdparty/amd_blobs +++ b/3rdparty/amd_blobs @@ -1 +1 @@ -Subproject commit cf227316b0fbd3995854ce21e81a63270b29bfb5 +Subproject commit 17d028869899e1ea0f6f385501088f7623121fcb -- To view, visit https://review.coreboot.org/c/coreboot/+/38042 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb6f12183c48c7c07f76e794b4971c8b75116333 Gerrit-Change-Number: 38042 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/i82801gx: Fix conversion from 'int' to 'signed char:1'
by HAOUAS Elyes (Code Review) Jan. 5, 2020

Jan. 5, 2020

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37341 ) Change subject: sb/intel/i82801gx: Fix conversion from 'int' to 'signed char:1' ...................................................................... sb/intel/i82801gx: Fix conversion from 'int' to 'signed char:1' Error found using -Wconversion on mainboard/macbook21/static.c Change-Id: I23d7b876f778ab78e922709a0a36f5eec4d60e3d Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/i82801gx/chip.h 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/37341/1 diff --git a/src/southbridge/intel/i82801gx/chip.h b/src/southbridge/intel/i82801gx/chip.h index 75b9575..f844515 100644 --- a/src/southbridge/intel/i82801gx/chip.h +++ b/src/southbridge/intel/i82801gx/chip.h @@ -76,9 +76,9 @@ /* Enable linear PCIe Root Port function numbers starting at zero */ uint8_t pcie_port_coalesce; - int c4onc3_enable:1; - int docking_supported:1; - int p_cnt_throttling_supported:1; + signed char c4onc3_enable:1; + signed char docking_supported:1; + signed char p_cnt_throttling_supported:1; int c3_latency; /* Additional LPC IO decode ranges */ -- To view, visit https://review.coreboot.org/c/coreboot/+/37341 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23d7b876f778ab78e922709a0a36f5eec4d60e3d Gerrit-Change-Number: 37341 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/i82801{i,j}x: Fix conversion from 'int' to 'signed char:6'
by HAOUAS Elyes (Code Review) Jan. 5, 2020

Jan. 5, 2020

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37342 ) Change subject: sb/intel/i82801{i,j}x: Fix conversion from 'int' to 'signed char:6' ...................................................................... sb/intel/i82801{i,j}x: Fix conversion from 'int' to 'signed char:6' Error found using option -Wconversion: "error: conversion from 'int' to 'signed char:6' changes value from '49' to '-15'" Change-Id: I3cdf4bf1b78b463846b3070ad4c6e82a7a329f5f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/i82801ix/chip.h M src/southbridge/intel/i82801jx/chip.h 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/37342/1 diff --git a/src/southbridge/intel/i82801ix/chip.h b/src/southbridge/intel/i82801ix/chip.h index 73ee822..a11e00b 100644 --- a/src/southbridge/intel/i82801ix/chip.h +++ b/src/southbridge/intel/i82801ix/chip.h @@ -79,7 +79,7 @@ int throttle_duty : 3; /* Bit mask to tell whether a PCIe slot is implemented as slot. */ - int pcie_slot_implemented : 6; + signed char pcie_slot_implemented : 6; /* Power limits for PCIe ports. Values are in 10^(-scale) watts. */ struct { diff --git a/src/southbridge/intel/i82801jx/chip.h b/src/southbridge/intel/i82801jx/chip.h index e4c68fb..d84de8e 100644 --- a/src/southbridge/intel/i82801jx/chip.h +++ b/src/southbridge/intel/i82801jx/chip.h @@ -69,7 +69,7 @@ int throttle_duty : 3; /* Bit mask to tell whether a PCIe slot is implemented as slot. */ - int pcie_slot_implemented : 6; + signed char pcie_slot_implemented : 6; /* Power limits for PCIe ports. Values are in 10^(-scale) watts. */ struct { -- To view, visit https://review.coreboot.org/c/coreboot/+/37342 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3cdf4bf1b78b463846b3070ad4c6e82a7a329f5f Gerrit-Change-Number: 37342 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: ec/lenovo/pmh7: Fix error: conversion from 'int' to 'signed char:1'
by HAOUAS Elyes (Code Review) Jan. 5, 2020

Jan. 5, 2020

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34092 ) Change subject: ec/lenovo/pmh7: Fix error: conversion from 'int' to 'signed char:1' ...................................................................... ec/lenovo/pmh7: Fix error: conversion from 'int' to 'signed char:1' Change-Id: Ie6c5a424ff49a2df586432e1390d5a30166d6c6a Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/ec/lenovo/pmh7/chip.h 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/34092/1 diff --git a/src/ec/lenovo/pmh7/chip.h b/src/ec/lenovo/pmh7/chip.h index 46f74c1..3189767 100644 --- a/src/ec/lenovo/pmh7/chip.h +++ b/src/ec/lenovo/pmh7/chip.h @@ -17,8 +17,8 @@ #define EC_LENOVO_PMH7_CHIP_H struct ec_lenovo_pmh7_config { - int backlight_enable:1; - int dock_event_enable:1; + signed char backlight_enable:1; + signed char dock_event_enable:1; }; #endif /* EC_LENOVO_PMH7_CHIP_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/34092 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6c5a424ff49a2df586432e1390d5a30166d6c6a Gerrit-Change-Number: 34092 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/device/pci: Add support for discrete VGA initialization and OpROM...
by mikeb mikeb (Code Review) Jan. 5, 2020

Jan. 5, 2020

Hello Mike Banon, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31448 to review the following change. Change subject: src/device/pci: Add support for discrete VGA initialization and OpROM loading ...................................................................... src/device/pci: Add support for discrete VGA initialization and OpROM loading Required to make the discrete VGA working at some boards like AMD Lenovo G505S. If CONFIG_MULTIPLE_VGA_ADAPTERS is enabled, coreboot will try to initialize the discrete VGA and load OpROM on it. ACPI VFCT table will be created only for discrete VGA instead of integrated, but everything seems to be working fine. Maybe later we would find a way to make a common VFCT table for both adapters. Based on the original patches by Hans Jürgen Kitter <eforname(a)freemail.hu>. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Signed-off-by: Hans Jürgen Kitter <eforname(a)freemail.hu> Change-Id: If3269a0911e86ea07014484365c7c830485e52ec --- M src/device/pci_device.c M src/device/pci_rom.c 2 files changed, 68 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/31448/1 diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 82033a6..96dec0b 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -764,7 +764,9 @@ * ROMs when coming out of an S3 resume. */ if (!IS_ENABLED(CONFIG_S3_VGA_ROM_RUN) && acpi_is_wakeup_s3() && - ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA)) + (((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA) || + (IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS) && + ((dev->class >> 8) == PCI_CLASS_DISPLAY_OTHER)))) return 0; if (IS_ENABLED(CONFIG_ALWAYS_LOAD_OPROM)) return 1; @@ -778,25 +780,41 @@ void pci_dev_init(struct device *dev) { struct rom_header *rom, *ram; + unsigned int pci_class = (dev->class >> 8); if (!IS_ENABLED(CONFIG_VGA_ROM_RUN)) return; - /* Only execute VGA ROMs. */ - if (((dev->class >> 8) != PCI_CLASS_DISPLAY_VGA)) - return; + /* Only load VGA ROMs. */ + if (pci_class != PCI_CLASS_DISPLAY_VGA) { + if (!IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS)) { + return; + } else if (pci_class != PCI_CLASS_DISPLAY_OTHER) { + return; + } + } if (!should_load_oprom(dev)) return; timestamp_add_now(TS_OPROM_INITIALIZE); rom = pci_rom_probe(dev); - if (rom == NULL) + if (rom == NULL) { + if (pci_class == PCI_CLASS_DISPLAY_VGA) + printk(BIOS_DEBUG, "Integrated VGA ROM probe failed\n"); + else + printk(BIOS_DEBUG, "Discrete VGA ROM probe failed\n"); return; + } ram = pci_rom_load(dev, rom); - if (ram == NULL) + if (ram == NULL) { + if (pci_class == PCI_CLASS_DISPLAY_VGA) + printk(BIOS_DEBUG, "Integrated VGA ROM load failed\n"); + else + printk(BIOS_DEBUG, "Discrete VGA ROM load failed\n"); return; + } timestamp_add_now(TS_OPROM_COPY_END); if (!should_run_oprom(dev)) @@ -804,7 +822,11 @@ run_bios(dev, (unsigned long)ram); gfx_set_init_done(1); - printk(BIOS_DEBUG, "VGA Option ROM was run\n"); + if (pci_class == PCI_CLASS_DISPLAY_VGA) + printk(BIOS_DEBUG, "Integrated VGA Option ROM was run\n"); + else + printk(BIOS_DEBUG, "Discrete VGA Option ROM was run\n"); + timestamp_add_now(TS_OPROM_END); } diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index 82d9a30..60f9aed 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -179,13 +179,24 @@ /* VBIOS may be modified after oprom init so use the copy if present. */ static struct rom_header *check_initialized(struct device *dev) { - struct rom_header *run_rom; + struct rom_header *run_rom = NULL; struct pci_data *rom_data; if (!IS_ENABLED(CONFIG_VGA_ROM_RUN)) return NULL; - run_rom = (struct rom_header *)(uintptr_t)PCI_VGA_RAM_IMAGE_START; + /* Set the start of shadow memory for this Integrated or Discrete VGA. */ + if ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA) { + run_rom = (struct rom_header *)(uintptr_t)PCI_VGA_RAM_IMAGE_START; + } else if (IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS)) { + if ((dev->class >> 8) == PCI_CLASS_DISPLAY_OTHER) { + run_rom = (struct rom_header *)(uintptr_t)PCI_RAM_IMAGE_START; + } + } + + if (run_rom == NULL) + return NULL; + if (read_le16(&run_rom->signature) != PCI_ROM_HDR) return NULL; @@ -217,11 +228,22 @@ return current; } - printk(BIOS_DEBUG, " Copying %sVBIOS image from %p\n", + if (!IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS)) { + /* Copy Integrated VGA VBIOS from CBFS to ACPI VFCT. */ + printk(BIOS_DEBUG, " Copying %sVBIOS image from %p\n", rom == (struct rom_header *) (uintptr_t)PCI_VGA_RAM_IMAGE_START ? "initialized " : "", rom); + } else { + /* Copy Discrete VGA VBIOS from CBFS to ACPI VFCT. */ + printk(BIOS_DEBUG, " Copying %sVBIOS image from %p\n", + rom == (struct rom_header *) + (uintptr_t)PCI_RAM_IMAGE_START ? + "initialized " : "", + rom); + /* TODO: do this also for Integrated VGA VBIOS. */ + } header->DeviceID = device->device; header->VendorID = device->vendor; @@ -243,8 +265,20 @@ struct rom_header *rom; /* Only handle VGA devices */ - if ((device->class >> 8) != PCI_CLASS_DISPLAY_VGA) - return current; + + if (!IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS)) { + if ((device->class >> 8) != PCI_CLASS_DISPLAY_VGA) { + return current; + } + } else { + /* Write ACPI VFCT only for Discrete VGA. */ + if ((device->class >> 8) == PCI_CLASS_DISPLAY_OTHER) { + ; + } else { + return current; + } + /* TODO: do this also for Integrated VGA. */ + } /* Only handle enabled devices */ if (!device->enabled) -- To view, visit https://review.coreboot.org/c/coreboot/+/31448 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3269a0911e86ea07014484365c7c830485e52ec Gerrit-Change-Number: 31448 Gerrit-PatchSet: 1 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/block/cse: Minor clean up some late comments
by Furquan Shaikh (Code Review) Jan. 5, 2020

Jan. 5, 2020

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35546 ) Change subject: soc/intel/common/block/cse: Minor clean up some late comments ...................................................................... Patch Set 14: (1 comment) https://review.coreboot.org/c/coreboot/+/35546/14/src/soc/intel/common/bloc… File src/soc/intel/common/block/include/intelblocks/cse.h: https://review.coreboot.org/c/coreboot/+/35546/14/src/soc/intel/common/bloc… PS14, Line 47: SOC_INTEL_APOLLOLAKE > Ideally, I would prefer having the definition of me_hfsts1 in SoC specific code to avoid polluting c […] In fact, I think I see at least one more deviation for TGL. Can you please check this across platforms to ensure if it is really a good idea to have this definition in common code. -- To view, visit https://review.coreboot.org/c/coreboot/+/35546 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7ea6043d7b5473d0c16e83d7b2d4b620c125652 Gerrit-Change-Number: 35546 Gerrit-PatchSet: 14 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <riz.pro(a)gmail.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 05 Jan 2020 18:49:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/cse: Minor clean up some late comments
by Furquan Shaikh (Code Review) Jan. 5, 2020

Jan. 5, 2020

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35546 ) Change subject: soc/intel/common/block/cse: Minor clean up some late comments ...................................................................... Patch Set 14: (1 comment) https://review.coreboot.org/c/coreboot/+/35546/14/src/soc/intel/common/bloc… File src/soc/intel/common/block/include/intelblocks/cse.h: https://review.coreboot.org/c/coreboot/+/35546/14/src/soc/intel/common/bloc… PS14, Line 47: SOC_INTEL_APOLLOLAKE Ideally, I would prefer having the definition of me_hfsts1 in SoC specific code to avoid polluting common files with SoC specific Kconfigs. If this is the only outlier, we might be okay to live with it. But if there are more changes across platforms, we should just get rid of this definition from common code. -- To view, visit https://review.coreboot.org/c/coreboot/+/35546 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7ea6043d7b5473d0c16e83d7b2d4b620c125652 Gerrit-Change-Number: 35546 Gerrit-PatchSet: 14 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <riz.pro(a)gmail.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 05 Jan 2020 18:45:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/cse: Minor clean up some late comments
by Furquan Shaikh (Code Review) Jan. 5, 2020

Jan. 5, 2020

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35546 ) Change subject: soc/intel/common/block/cse: Minor clean up some late comments ...................................................................... Patch Set 14: (17 comments) I started adding comments here and later noticed that some of the components that I commented on are also touched upon in follow up CLs. If you have already addressed any of the comments in the follow up CLs, please ACK/mark DONE for the comment here. Thanks! https://review.coreboot.org/c/coreboot/+/35546/14/src/soc/intel/common/bloc… File src/soc/intel/common/block/cse/cse.c: https://review.coreboot.org/c/coreboot/+/35546/14/src/soc/intel/common/bloc… PS14, Line 78: GR_ORIGIN_BIOS_POST Is this a command id or group id? From the name and the comment, it is not really clear to me what this macro is. https://review.coreboot.org/c/coreboot/+/35546/14/src/soc/intel/common/bloc… PS14, Line 84: operation and working modes Actually, this should be CWS = Current Working State and COM = Current Operation Mode https://review.coreboot.org/c/coreboot/+/35546/14/src/soc/intel/common/bloc… PS14, Line 85: HFS I think it would be better to add HFSTS1 or HFS1 to indicate that this is a field in HFSTS1 register. Same for the macros below. https://review.coreboot.org/c/coreboot/+/35546/14/src/soc/intel/common/bloc… PS14, Line 86: MODE I think it would be better to call this COM = Current Operation Mode. There are different things that can be referred to as mode. https://review.coreboot.org/c/coreboot/+/35546/14/src/soc/intel/common/bloc… PS14, Line 598: rst_type Are the different reset types supported by ME firmware for all platforms? For CML, I don't see all the different reset types in the latest BWG. https://review.coreboot.org/c/coreboot/+/35546/14/src/soc/intel/common/bloc… PS14, Line 606: heci_reset(); Why is heci_reset() done here? https://review.coreboot.org/c/coreboot/+/35546/14/src/soc/intel/common/bloc… PS14, Line 609: memset(&reply, 0, reply_size); What is the use of setting this to 0? https://review.coreboot.org/c/coreboot/+/35546/14/src/soc/intel/common/bloc… PS14, Line 650: padding Rather than padding, can we name this reserved just like it is in BWG? https://review.coreboot.org/c/coreboot/+/35546/14/src/soc/intel/common/bloc… PS14, Line 662: or temporary disable mode Is this correct? I don't see this in BWG. https://review.coreboot.org/c/coreboot/+/35546/14/src/soc/intel/common/bloc… PS14, Line 664: hfs1.fields.working_state Not for this change, but I think we should add helper fucntions for CWS and COP i.e. me_get_cws(hfs1) and me_get_cop(hfs1). Just makes it easier to read and write the struct fields. https://review.coreboot.org/c/coreboot/+/35546/14/src/soc/intel/common/bloc… PS14, Line 678: } Why is resp.status not checked here? https://review.coreboot.org/c/coreboot/+/35546/14/src/soc/intel/common/bloc… PS14, Line 679: return 1; HMRFPO enabling needs to be followed by a global reset. Why is that not done as part of this function? https://review.coreboot.org/c/coreboot/+/35546/14/src/soc/intel/common/bloc… PS14, Line 687: DISABLES DISABLED https://review.coreboot.org/c/coreboot/+/35546/14/src/soc/intel/common/bloc… PS14, Line 698: padding reserved https://review.coreboot.org/c/coreboot/+/35546/14/src/soc/intel/common/bloc… PS14, Line 711: This command can be sent only if CWS is normal. Shouldn't that be checked here? https://review.coreboot.org/c/coreboot/+/35546/14/src/soc/intel/common/bloc… File src/soc/intel/common/block/include/intelblocks/cse.h: https://review.coreboot.org/c/coreboot/+/35546/14/src/soc/intel/common/bloc… PS14, Line 143: nit: extra blank line not required. https://review.coreboot.org/c/coreboot/+/35546/14/src/soc/intel/common/bloc… PS14, Line 152: * nit: space after * -- To view, visit https://review.coreboot.org/c/coreboot/+/35546 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7ea6043d7b5473d0c16e83d7b2d4b620c125652 Gerrit-Change-Number: 35546 Gerrit-PatchSet: 14 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <riz.pro(a)gmail.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 05 Jan 2020 18:40:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: pci_ids: Correct whitespace for all AMD, ATI, National Semi
by Marshall Dawson (Code Review) Jan. 5, 2020

Jan. 5, 2020

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38170 ) Change subject: pci_ids: Correct whitespace for all AMD, ATI, National Semi ...................................................................... pci_ids: Correct whitespace for all AMD, ATI, National Semi Convert spaces to tabs to match surrounding definitions and fix alignment AMD products and prior assets. Change-Id: I37f1b7826afab8e224fb2d411247d77ea32664df Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/include/device/pci_ids.h 1 file changed, 100 insertions(+), 100 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/38170/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 52c6035..c13339a 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -228,8 +228,8 @@ #define PCI_DEVICE_ID_ATI_215_LR 0x4c52 #define PCI_DEVICE_ID_ATI_215_LS 0x4c53 #define PCI_DEVICE_ID_ATI_264_LT 0x4c54 -#define PCI_DEVICE_ID_ATI_215LG 0x4c47 -#define PCI_DEVICE_ID_ATI_264LT 0x4c54 +#define PCI_DEVICE_ID_ATI_215LG 0x4c47 +#define PCI_DEVICE_ID_ATI_264LT 0x4c54 /* Mach64 VT */ #define PCI_DEVICE_ID_ATI_264VT 0x5654 #define PCI_DEVICE_ID_ATI_264VU 0x5655 @@ -299,7 +299,7 @@ #define PCI_DEVICE_ID_AMD_15H_MODEL_606F_NB_HT 0x1570 #define PCI_DEVICE_ID_AMD_15H_MODEL_707F_NB_HT 0x15B0 #define PCI_DEVICE_ID_AMD_16H_MODEL_000F_NB_HT 0x1536 -#define PCI_DEVICE_ID_AMD_16H_MODEL_303F_NB_HT 0x1566 +#define PCI_DEVICE_ID_AMD_16H_MODEL_303F_NB_HT 0x1566 #define PCI_DEVICE_ID_AMD_17H_MODEL_101F_NB 0x15d0 #define PCI_DEVICE_ID_AMD_15H_MODEL_101F_NB_IOMMU 0x1419 #define PCI_DEVICE_ID_AMD_15H_MODEL_303F_NB_IOMMU 0x1423 @@ -330,60 +330,60 @@ #define PCI_DEVICE_ID_ATI_SB700_HDA 0x4383 #define PCI_DEVICE_ID_ATI_SB700_PCI 0x4384 #define PCI_DEVICE_ID_ATI_SB700_SM 0x4385 -#define PCI_DEVICE_ID_ATI_SB700_USB_18_0 0x4397 -#define PCI_DEVICE_ID_ATI_SB700_USB_18_1 0x4398 -#define PCI_DEVICE_ID_ATI_SB700_USB_18_2 0x4396 -#define PCI_DEVICE_ID_ATI_SB700_USB_19_0 0x4397 -#define PCI_DEVICE_ID_ATI_SB700_USB_19_1 0x4398 -#define PCI_DEVICE_ID_ATI_SB700_USB_19_2 0x4396 -#define PCI_DEVICE_ID_ATI_SB700_USB_20_5 0x4399 +#define PCI_DEVICE_ID_ATI_SB700_USB_18_0 0x4397 +#define PCI_DEVICE_ID_ATI_SB700_USB_18_1 0x4398 +#define PCI_DEVICE_ID_ATI_SB700_USB_18_2 0x4396 +#define PCI_DEVICE_ID_ATI_SB700_USB_19_0 0x4397 +#define PCI_DEVICE_ID_ATI_SB700_USB_19_1 0x4398 +#define PCI_DEVICE_ID_ATI_SB700_USB_19_2 0x4396 +#define PCI_DEVICE_ID_ATI_SB700_USB_20_5 0x4399 -#define PCI_DEVICE_ID_ATI_SB800_LPC 0x439D -#define PCI_DEVICE_ID_ATI_SB800_SATA 0x4390 -#define PCI_DEVICE_ID_ATI_SB800_SATA_AHCI 0x4391 -#define PCI_DEVICE_ID_ATI_SB800_SATA_RAID 0x4392 -#define PCI_DEVICE_ID_ATI_SB800_SATA_RAID5 0x4393 -#define PCI_DEVICE_ID_ATI_SB800_IDE 0x439C -#define PCI_DEVICE_ID_ATI_SB800_HDA 0x4383 -#define PCI_DEVICE_ID_ATI_SB800_PCI 0x4384 -#define PCI_DEVICE_ID_ATI_SB800_PCIEA 0x43A0 -#define PCI_DEVICE_ID_ATI_SB800_PCIEB 0x43A1 -#define PCI_DEVICE_ID_ATI_SB800_PCIEC 0x43A2 -#define PCI_DEVICE_ID_ATI_SB800_PCIED 0x43A3 -#define PCI_DEVICE_ID_ATI_SB800_SM 0x4385 -#define PCI_DEVICE_ID_ATI_SB800_USB_18_0 0x4397 -#define PCI_DEVICE_ID_ATI_SB800_USB_18_2 0x4396 -#define PCI_DEVICE_ID_ATI_SB800_USB_19_0 0x4397 -#define PCI_DEVICE_ID_ATI_SB800_USB_19_2 0x4396 -#define PCI_DEVICE_ID_ATI_SB800_USB_20_5 0x4399 -#define PCI_DEVICE_ID_ATI_SB800_USB_22_0 0x4397 -#define PCI_DEVICE_ID_ATI_SB800_USB_22_2 0x4396 -#define PCI_DEVICE_ID_ATI_SB800_GEC 0x1699 +#define PCI_DEVICE_ID_ATI_SB800_LPC 0x439D +#define PCI_DEVICE_ID_ATI_SB800_SATA 0x4390 +#define PCI_DEVICE_ID_ATI_SB800_SATA_AHCI 0x4391 +#define PCI_DEVICE_ID_ATI_SB800_SATA_RAID 0x4392 +#define PCI_DEVICE_ID_ATI_SB800_SATA_RAID5 0x4393 +#define PCI_DEVICE_ID_ATI_SB800_IDE 0x439C +#define PCI_DEVICE_ID_ATI_SB800_HDA 0x4383 +#define PCI_DEVICE_ID_ATI_SB800_PCI 0x4384 +#define PCI_DEVICE_ID_ATI_SB800_PCIEA 0x43A0 +#define PCI_DEVICE_ID_ATI_SB800_PCIEB 0x43A1 +#define PCI_DEVICE_ID_ATI_SB800_PCIEC 0x43A2 +#define PCI_DEVICE_ID_ATI_SB800_PCIED 0x43A3 +#define PCI_DEVICE_ID_ATI_SB800_SM 0x4385 +#define PCI_DEVICE_ID_ATI_SB800_USB_18_0 0x4397 +#define PCI_DEVICE_ID_ATI_SB800_USB_18_2 0x4396 +#define PCI_DEVICE_ID_ATI_SB800_USB_19_0 0x4397 +#define PCI_DEVICE_ID_ATI_SB800_USB_19_2 0x4396 +#define PCI_DEVICE_ID_ATI_SB800_USB_20_5 0x4399 +#define PCI_DEVICE_ID_ATI_SB800_USB_22_0 0x4397 +#define PCI_DEVICE_ID_ATI_SB800_USB_22_2 0x4396 +#define PCI_DEVICE_ID_ATI_SB800_GEC 0x1699 -#define PCI_DEVICE_ID_AMD_SB900_LPC 0x780E -#define PCI_DEVICE_ID_AMD_SB900_SATA 0x7800 -#define PCI_DEVICE_ID_AMD_SB900_SATA_AHCI 0x7801 -#define PCI_DEVICE_ID_AMD_SB900_SATA_RAID 0x7802 -#define PCI_DEVICE_ID_AMD_SB900_SATA_RAID5 0x7803 -#define PCI_DEVICE_ID_AMD_SB900_SATA_AMDAHCI 0x7804 -#define PCI_DEVICE_ID_AMD_SB900_IDE 0x780C -#define PCI_DEVICE_ID_AMD_SB900_HDA 0x780D -#define PCI_DEVICE_ID_AMD_SB900_PCI 0x780F -#define PCI_DEVICE_ID_AMD_SB900_PCIEA 0x43A0 -#define PCI_DEVICE_ID_AMD_SB900_PCIEB 0x43A1 -#define PCI_DEVICE_ID_AMD_SB900_PCIEC 0x43A2 -#define PCI_DEVICE_ID_AMD_SB900_PCIED 0x43A3 -#define PCI_DEVICE_ID_AMD_SB900_SM 0x780B -#define PCI_DEVICE_ID_AMD_SB900_USB_16_0 0x7812 -#define PCI_DEVICE_ID_AMD_SB900_USB_16_1 0x7812 -#define PCI_DEVICE_ID_AMD_SB900_USB_18_0 0x7807 -#define PCI_DEVICE_ID_AMD_SB900_USB_18_2 0x7808 -#define PCI_DEVICE_ID_AMD_SB900_USB_19_0 0x7807 -#define PCI_DEVICE_ID_AMD_SB900_USB_19_2 0x7808 -#define PCI_DEVICE_ID_AMD_SB900_USB_20_5 0x7809 -#define PCI_DEVICE_ID_AMD_SB900_GEC 0x7806 -#define PCI_DEVICE_ID_AMD_HUDSON_SD 0x7806 -#define PCI_DEVICE_ID_AMD_YANGTZE_SD 0x7813 +#define PCI_DEVICE_ID_AMD_SB900_LPC 0x780E +#define PCI_DEVICE_ID_AMD_SB900_SATA 0x7800 +#define PCI_DEVICE_ID_AMD_SB900_SATA_AHCI 0x7801 +#define PCI_DEVICE_ID_AMD_SB900_SATA_RAID 0x7802 +#define PCI_DEVICE_ID_AMD_SB900_SATA_RAID5 0x7803 +#define PCI_DEVICE_ID_AMD_SB900_SATA_AMDAHCI 0x7804 +#define PCI_DEVICE_ID_AMD_SB900_IDE 0x780C +#define PCI_DEVICE_ID_AMD_SB900_HDA 0x780D +#define PCI_DEVICE_ID_AMD_SB900_PCI 0x780F +#define PCI_DEVICE_ID_AMD_SB900_PCIEA 0x43A0 +#define PCI_DEVICE_ID_AMD_SB900_PCIEB 0x43A1 +#define PCI_DEVICE_ID_AMD_SB900_PCIEC 0x43A2 +#define PCI_DEVICE_ID_AMD_SB900_PCIED 0x43A3 +#define PCI_DEVICE_ID_AMD_SB900_SM 0x780B +#define PCI_DEVICE_ID_AMD_SB900_USB_16_0 0x7812 +#define PCI_DEVICE_ID_AMD_SB900_USB_16_1 0x7812 +#define PCI_DEVICE_ID_AMD_SB900_USB_18_0 0x7807 +#define PCI_DEVICE_ID_AMD_SB900_USB_18_2 0x7808 +#define PCI_DEVICE_ID_AMD_SB900_USB_19_0 0x7807 +#define PCI_DEVICE_ID_AMD_SB900_USB_19_2 0x7808 +#define PCI_DEVICE_ID_AMD_SB900_USB_20_5 0x7809 +#define PCI_DEVICE_ID_AMD_SB900_GEC 0x7806 +#define PCI_DEVICE_ID_AMD_HUDSON_SD 0x7806 +#define PCI_DEVICE_ID_AMD_YANGTZE_SD 0x7813 #define PCI_DEVICE_ID_ATI_RS690_HT 0x7910 #define PCI_DEVICE_ID_ATI_RS740_HT 0x7911 @@ -429,29 +429,29 @@ #define PCI_DEVICE_ID_AMD_SR5670_HT 0x5A12 #define PCI_DEVICE_ID_AMD_SR5650_HT 0x5A13 #define PCI_DEVICE_ID_AMD_990FX_HT 0x5A14 -#define PCI_DEVICE_ID_AMD_SR5650_PCIE 0x5A12 -#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV2 0x5A16 -#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV3 0x5A17 -#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV4 0x5A18 -#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV5 0x5A19 -#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV6 0x5A1A -#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV7 0x5A1B -#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV9 0x5A1C -#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV10 0x5A1D -#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV11 0x5A1F -#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV12 0x5A20 -#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV13 0x5A1E -#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV8 0x5A21 +#define PCI_DEVICE_ID_AMD_SR5650_PCIE 0x5A12 +#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV2 0x5A16 +#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV3 0x5A17 +#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV4 0x5A18 +#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV5 0x5A19 +#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV6 0x5A1A +#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV7 0x5A1B +#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV9 0x5A1C +#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV10 0x5A1D +#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV11 0x5A1F +#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV12 0x5A20 +#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV13 0x5A1E +#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV8 0x5A21 #define PCI_DEVICE_ID_AMD_SR5650_IOMMU 0x5A23 -#define PCI_DEVICE_ID_AMD_CZ_HDA 0x157A -#define PCI_DEVICE_ID_AMD_CZ_LPC 0x790E -#define PCI_DEVICE_ID_AMD_CZ_SATA 0x7900 -#define PCI_DEVICE_ID_AMD_CZ_SATA_AHCI 0x7901 -#define PCI_DEVICE_ID_AMD_CZ_USB_0 0x7907 -#define PCI_DEVICE_ID_AMD_CZ_USB_1 0x7908 -#define PCI_DEVICE_ID_AMD_CZ_USB3_0 0x7914 -#define PCI_DEVICE_ID_AMD_CZ_SMBUS 0x790B +#define PCI_DEVICE_ID_AMD_CZ_HDA 0x157A +#define PCI_DEVICE_ID_AMD_CZ_LPC 0x790E +#define PCI_DEVICE_ID_AMD_CZ_SATA 0x7900 +#define PCI_DEVICE_ID_AMD_CZ_SATA_AHCI 0x7901 +#define PCI_DEVICE_ID_AMD_CZ_USB_0 0x7907 +#define PCI_DEVICE_ID_AMD_CZ_USB_1 0x7908 +#define PCI_DEVICE_ID_AMD_CZ_USB3_0 0x7914 +#define PCI_DEVICE_ID_AMD_CZ_SMBUS 0x790B #define PCI_DEVICE_ID_AMD_PCO_LPC 0x790e #define PCI_DEVICE_ID_AMD_PCO_HDA0 0x15de @@ -490,12 +490,12 @@ #define PCI_DEVICE_ID_NS_CS5535_AUDIO 0x002e #define PCI_DEVICE_ID_NS_CS5535_USB 0x002f #define PCI_DEVICE_ID_NS_CS5535_GX2VGA 0x0030 -#define PCI_DEVICE_ID_NS_SCx200_BRIDGE 0x0500 -#define PCI_DEVICE_ID_NS_SCx200_SMI 0x0501 -#define PCI_DEVICE_ID_NS_SCx200_IDE 0x0502 -#define PCI_DEVICE_ID_NS_SCx200_AUDIO 0x0503 -#define PCI_DEVICE_ID_NS_SCx200_VIDEO 0x0504 -#define PCI_DEVICE_ID_NS_SCx200_XBUS 0x0505 +#define PCI_DEVICE_ID_NS_SCx200_BRIDGE 0x0500 +#define PCI_DEVICE_ID_NS_SCx200_SMI 0x0501 +#define PCI_DEVICE_ID_NS_SCx200_IDE 0x0502 +#define PCI_DEVICE_ID_NS_SCx200_AUDIO 0x0503 +#define PCI_DEVICE_ID_NS_SCx200_VIDEO 0x0504 +#define PCI_DEVICE_ID_NS_SCx200_XBUS 0x0505 #define PCI_DEVICE_ID_NS_87410 0xd001 @@ -597,11 +597,11 @@ #define PCI_DEVICE_ID_AMD_VIPER_7410 0x7410 #define PCI_DEVICE_ID_AMD_VIPER_7411 0x7411 -#define PCI_DEVICE_ID_AMD_SB768_7440 0x7440 -#define PCI_DEVICE_ID_AMD_SB768_7441 0x7441 -#define PCI_DEVICE_ID_AMD_SB768_7443 0x7443 -#define PCI_DEVICE_ID_AMD_SB768_7448 0x7448 -#define PCI_DEVICE_ID_AMD_SB768_7449 0x7449 +#define PCI_DEVICE_ID_AMD_SB768_7440 0x7440 +#define PCI_DEVICE_ID_AMD_SB768_7441 0x7441 +#define PCI_DEVICE_ID_AMD_SB768_7443 0x7443 +#define PCI_DEVICE_ID_AMD_SB768_7448 0x7448 +#define PCI_DEVICE_ID_AMD_SB768_7449 0x7449 #define PCI_DEVICE_ID_AMD_VIPER_7413 0x7413 #define PCI_DEVICE_ID_AMD_VIPER_7414 0x7414 @@ -611,22 +611,22 @@ #define PCI_DEVICE_ID_AMD_VIPER_7448 0x7448 #define PCI_DEVICE_ID_AMD_VIPER_7449 0x7449 -#define PCI_DEVICE_ID_AMD_8151_SYSCTRL 0x7454 -#define PCI_DEVICE_ID_AMD_8151_AGP 0x7455 -#define PCI_DEVICE_ID_AMD_8111_PCI 0x7460 -#define PCI_DEVICE_ID_AMD_8111_USB 0x7464 -#define PCI_DEVICE_ID_AMD_8111_ISA 0x7468 -#define PCI_DEVICE_ID_AMD_8111_IDE 0x7469 -#define PCI_DEVICE_ID_AMD_8111_SMB 0x746a -#define PCI_DEVICE_ID_AMD_8111_ACPI 0x746b -#define PCI_DEVICE_ID_AMD_8111_NIC 0x7462 +#define PCI_DEVICE_ID_AMD_8151_SYSCTRL 0x7454 +#define PCI_DEVICE_ID_AMD_8151_AGP 0x7455 +#define PCI_DEVICE_ID_AMD_8111_PCI 0x7460 +#define PCI_DEVICE_ID_AMD_8111_USB 0x7464 +#define PCI_DEVICE_ID_AMD_8111_ISA 0x7468 +#define PCI_DEVICE_ID_AMD_8111_IDE 0x7469 +#define PCI_DEVICE_ID_AMD_8111_SMB 0x746a +#define PCI_DEVICE_ID_AMD_8111_ACPI 0x746b +#define PCI_DEVICE_ID_AMD_8111_NIC 0x7462 -#define PCI_DEVICE_ID_AMD_8111_USB2 0x7463 +#define PCI_DEVICE_ID_AMD_8111_USB2 0x7463 #define PCI_DEVICE_ID_AMD_8131_PCIX 0x7450 -#define PCI_DEVICE_ID_AMD_8131_IOAPIC 0x7451 +#define PCI_DEVICE_ID_AMD_8131_IOAPIC 0x7451 -#define PCI_DEVICE_ID_AMD_8132_PCIX 0x7458 -#define PCI_DEVICE_ID_AMD_8132_IOAPIC 0x7459 +#define PCI_DEVICE_ID_AMD_8132_PCIX 0x7458 +#define PCI_DEVICE_ID_AMD_8132_IOAPIC 0x7459 #define PCI_DEVICE_ID_AMD_AES 0x2082 #define PCI_DEVICE_ID_AMD_CS5536_ISA 0x2090 #define PCI_DEVICE_ID_AMD_CS5536_FLASH 0x2091 -- To view, visit https://review.coreboot.org/c/coreboot/+/38170 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37f1b7826afab8e224fb2d411247d77ea32664df Gerrit-Change-Number: 38170 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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