coreboot-gerrit January 2020

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Change in coreboot[master]: sb/amd/{agesa,pi,cimx}: use ACPIMMIO common block wherever possible
by Michał Żygowski (Code Review) 05 Jan '20

05 Jan '20

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37400 ) Change subject: sb/amd/{agesa,pi,cimx}: use ACPIMMIO common block wherever possible ...................................................................... sb/amd/{agesa,pi,cimx}: use ACPIMMIO common block wherever possible TEST=boot PC Engines apu1 and apu2 and launch Debian Linux Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Ic3d5abc8f3b235ea61f66950ada8aff1dc48f8c3 --- M src/southbridge/amd/agesa/hudson/early_setup.c M src/southbridge/amd/agesa/hudson/smbus_spd.c M src/southbridge/amd/pi/hudson/early_setup.c M src/southbridge/amd/pi/hudson/smbus_spd.c 4 files changed, 24 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/37400/1 diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c index c3a4d41..f6cba68 100644 --- a/src/southbridge/amd/agesa/hudson/early_setup.c +++ b/src/southbridge/amd/agesa/hudson/early_setup.c @@ -17,6 +17,7 @@ #define _HUDSON_EARLY_SETUP_C_ #include <stdint.h> +#include <amdblocks/acpimmio.h> #include <arch/io.h> #include <device/pci_ops.h> #include <console/console.h> @@ -74,11 +75,7 @@ pci_devfn_t dev; /* Enable LPC controller */ - outb(0xEC, 0xCD6); - byte = inb(0xCD7); - byte |= 1; - outb(0xEC, 0xCD6); - outb(byte, 0xCD7); + pm_io_write8(0xec, pm_io_read8(0xec) | 1); /* Enable port 80 LPC decode in pci function 3 configuration space. */ dev = PCI_DEV(0, 0x14, 3); diff --git a/src/southbridge/amd/agesa/hudson/smbus_spd.c b/src/southbridge/amd/agesa/hudson/smbus_spd.c index 8eb36f4..a63f5e6 100644 --- a/src/southbridge/amd/agesa/hudson/smbus_spd.c +++ b/src/southbridge/amd/agesa/hudson/smbus_spd.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <amdblocks/acpimmio.h> #include <device/pci_def.h> #include <device/device.h> #include <console/console.h> @@ -126,16 +127,10 @@ return 0; } -static void writePmReg (int reg, int data) -{ - __outbyte (0xCD6, reg); - __outbyte (0xCD7, data); -} - static void setupFch (int ioBase) { - writePmReg (0x2D, ioBase >> 8); - writePmReg (0x2C, ioBase | 1); + pm_io_write8(0x2d, ioBase >> 8); + pm_io_write8(0x2c, ioBase | 1); __outbyte (ioBase + 0x0E, 66000000 / 400000 / 4); // set SMBus clock to 400 KHz } diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c index 34a3513..6e47e42 100644 --- a/src/southbridge/amd/pi/hudson/early_setup.c +++ b/src/southbridge/amd/pi/hudson/early_setup.c @@ -18,6 +18,7 @@ #include <assert.h> #include <stdint.h> +#include <amdblocks/acpimmio.h> #include <arch/io.h> #include <device/mmio.h> #include <device/pci_ops.h> @@ -36,18 +37,17 @@ { u8 byte; - byte = read8((void *)(ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG56 + - CONFIG_UART_FOR_CONSOLE * sizeof(u16))); + byte = aoac_read8(FCH_AOAC_REG56 + + CONFIG_UART_FOR_CONSOLE * sizeof(u16))); byte |= 1 << 3; - write8((void *)(ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG56 + - CONFIG_UART_FOR_CONSOLE * sizeof(u16)), byte); - byte = read8((void *)(ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG62)); - byte |= 1 << 3; - write8((void *)(ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG62), byte); - write8((void *)FCH_IOMUXx89_UART0_RTS_L_EGPIO137, 0); - write8((void *)FCH_IOMUXx8A_UART0_TXD_EGPIO138, 0); - write8((void *)FCH_IOMUXx8E_UART1_RTS_L_EGPIO142, 0); - write8((void *)FCH_IOMUXx8F_UART1_TXD_EGPIO143, 0); + aoac_write8(FCH_AOAC_REG56 + CONFIG_UART_FOR_CONSOLE * sizeof(u16)), + byte); + + aoac_write8(FCH_AOAC_REG62, aoac_read8(FCH_AOAC_REG62) | (1 << 3)); + iomux_write8(0x89, 0); /* UART0_RTS_L_EGPIO137 */ + iomux_write8(0x8a, 0); /* UART0_TXD_EGPIO138 */ + iomux_write8(0x8e, 0); /* UART1_RTS_L_EGPIO142 */ + iomux_write8(0x8f, 0); /* UART1_TXD_EGPIO143 */ udelay(2000); write8((void *)(0xFEDC6000 + 0x2000 * CONFIG_UART_FOR_CONSOLE + 0x88), @@ -107,11 +107,7 @@ pci_devfn_t dev; /* Enable LPC controller */ - outb(0xEC, 0xCD6); - byte = inb(0xCD7); - byte |= 1; - outb(0xEC, 0xCD6); - outb(byte, 0xCD7); + pm_io_write8(0xec, pm_io_read8(0xec) | 1); /* Enable port 80 LPC decode in pci function 3 configuration space. */ dev = PCI_DEV(0, 0x14, 3); @@ -236,8 +232,7 @@ printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos); for (i = 0; i < size; i++) { - outb(nvram_pos, BIOSRAM_INDEX); - outb((dword >> (8 * i)) & 0xff, BIOSRAM_DATA); + biosram_write8(nvram_pos, (dword >> (8 * i)) & 0xff); nvram_pos++; } @@ -249,9 +244,8 @@ u32 data = *old_dword; int i; for (i = 0; i < size; i++) { - outb(nvram_pos, BIOSRAM_INDEX); data &= ~(0xff << (i * 8)); - data |= inb(BIOSRAM_DATA) << (i *8); + data |= biosram_read8(nvram_pos) << (i *8); nvram_pos++; } *old_dword = data; @@ -268,11 +262,11 @@ * Enable the X14M_25M_48M_OSC pin and leaving it at it's default so * 48Mhz will be on ball AP13 (FT3b package) */ - ctrl = read32((void *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40)); + ctrl = misc_read32(FCH_MISC_REG40); /* clear the OSCOUT1_ClkOutputEnb to enable the 48 Mhz clock */ ctrl &= (u32)~(1<<2); - write32((void *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40), ctrl); + misc_write32(FCH_MISC_REG40, ctrl); } static uintptr_t hudson_spibase(void) diff --git a/src/southbridge/amd/pi/hudson/smbus_spd.c b/src/southbridge/amd/pi/hudson/smbus_spd.c index c49ccff..c046c28 100644 --- a/src/southbridge/amd/pi/hudson/smbus_spd.c +++ b/src/southbridge/amd/pi/hudson/smbus_spd.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <amdblocks/acpimmio.h> #include <console/console.h> #include <device/pci_def.h> #include <device/device.h> @@ -127,16 +128,10 @@ return 0; } -static void writePmReg (int reg, int data) -{ - __outbyte (0xCD6, reg); - __outbyte (0xCD7, data); -} - static void setupFch (int ioBase) { - writePmReg (0x2D, ioBase >> 8); - writePmReg (0x2C, ioBase | 1); + pm_io_write8(0x2d, ioBase >> 8); + pm_io_write8(0x2c, ioBase | 1); __outbyte (ioBase + 0x0E, 66000000 / 400000 / 4); // set SMBus clock to 400 KHz } -- To view, visit https://review.coreboot.org/c/coreboot/+/37400 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3d5abc8f3b235ea61f66950ada8aff1dc48f8c3 Gerrit-Change-Number: 37400 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/amd/model_fxx: Fix invalid P-state power values
by Paul Menzel (Code Review) 05 Jan '20

05 Jan '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/12233 ) Change subject: cpu/amd/model_fxx: Fix invalid P-state power values ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/12233/2//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/12233/2//COMMIT_MSG@8 PS2, Line 8: Please elaborate. Casts were missing? -- To view, visit https://review.coreboot.org/c/coreboot/+/12233 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifdb1d1f267af289d962effe1150c7bc0a39cb5d2 Gerrit-Change-Number: 12233 Gerrit-PatchSet: 3 Gerrit-Owner: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Reviewer: Jonathan Kollasch <jakllsch(a)kollasch.net> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Sun, 05 Jan 2020 10:32:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] util/inteltool: Add GPIO dumping capabilites for Icelake U systems
by Paul Menzel (Code Review) 05 Jan '20

05 Jan '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38175 ) Change subject: [WIP] util/inteltool: Add GPIO dumping capabilites for Icelake U systems ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/38175 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib40f1dbae57169678e92ea9ad0df60ff91b5b22c Gerrit-Change-Number: 38175 Gerrit-PatchSet: 1 Gerrit-Owner: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 05 Jan 2020 10:29:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/sapphire/pureplatinumh61: Make devicetree prettier
by Angel Pons (Code Review) 05 Jan '20

05 Jan '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38062 ) Change subject: mb/sapphire/pureplatinumh61: Make devicetree prettier ...................................................................... mb/sapphire/pureplatinumh61: Make devicetree prettier Align contents, and fix some redundant comments. Change-Id: I0c9e98281aeb887308c3cbb421105b1faf922063 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/sapphire/pureplatinumh61/devicetree.cb 1 file changed, 26 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/38062/1 diff --git a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb index cb7ef9a..468c35a 100644 --- a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb +++ b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb @@ -30,7 +30,7 @@ end end device domain 0x0 on - chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "c2_latency" = "0x0065" register "gen1_dec" = "0x000c0291" register "gen2_dec" = "0x000c0a01" @@ -46,48 +46,38 @@ {0x9f, READ_NO_ADDR}, {0xad, WRITE_NO_ADDR}, {0x04, WRITE_NO_ADDR}}" - device pci 16.0 on # Management Engine Interface 1 + device pci 16.0 on # Management Engine Interface 1 subsystemid 0x174b 0x1007 end - device pci 16.1 off # Management Engine Interface 2 - end - device pci 16.2 off # Management Engine IDE-R - end - device pci 16.3 off # Management Engine KT - end - device pci 19.0 off # Intel Gigabit Ethernet - end - device pci 1a.0 on # USB2 EHCI #2 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 off end # Intel Gigabit Ethernet + device pci 1a.0 on # USB2 EHCI #2 subsystemid 0x174b 0x1007 end - device pci 1b.0 on # High Definition Audio Audio controller + device pci 1b.0 on # HD Audio Controller subsystemid 0x8086 0x1c20 end - device pci 1c.0 on # PCIe Port #1 + device pci 1c.0 on # PCIe Port #1 subsystemid 0x174b 0x1007 end - device pci 1c.1 off # PCIe Port #2 - end - device pci 1c.2 off # PCIe Port #3 - end - device pci 1c.3 off # PCIe Port #4 - end - device pci 1c.4 on # PCIe Port #5 + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 on # PCIe Port #5 subsystemid 0x174b 0x1007 end - device pci 1c.5 on # PCIe Port #6 + device pci 1c.5 on # PCIe Port #6 subsystemid 0x174b 0x1007 end - device pci 1c.6 off # PCIe Port #7 - end - device pci 1c.7 off # PCIe Port #8 - end - device pci 1d.0 on # USB2 EHCI #1 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on # USB2 EHCI #1 subsystemid 0x174b 0x1007 end - device pci 1e.0 off # PCI bridge - end - device pci 1f.0 on # LPC bridge PCI-LPC bridge + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on # LPC bridge subsystemid 0x174b 0x1007 chip superio/fintek/f71808a register "multi_function_register_0" = "0x00" @@ -130,24 +120,22 @@ end end end - device pci 1f.2 on # SATA Controller 1 + device pci 1f.2 on # SATA Controller 1 subsystemid 0x174b 0x1007 end - device pci 1f.3 on # SMBus + device pci 1f.3 on # SMBus subsystemid 0x174b 0x1007 end - device pci 1f.5 off # SATA Controller 2 - end - device pci 1f.6 off # Thermal - end + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 off end # Thermal end - device pci 00.0 on # Host bridge Host bridge + device pci 00.0 on # Host bridge subsystemid 0x174b 0x1007 end - device pci 01.0 on # PCIe Bridge for discrete graphics + device pci 01.0 on # PCIe Bridge for discrete graphics subsystemid 0x174b 0x1007 end - device pci 02.0 on # Internal graphics VGA controller + device pci 02.0 on # Internal graphics VGA controller subsystemid 0x8086 0x2010 end end -- To view, visit https://review.coreboot.org/c/coreboot/+/38062 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c9e98281aeb887308c3cbb421105b1faf922063 Gerrit-Change-Number: 38062 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/sapphire/pureplatinumh61/devicetree.cb: Drop zero values
by Angel Pons (Code Review) 05 Jan '20

05 Jan '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38061 ) Change subject: mb/sapphire/pureplatinumh61/devicetree.cb: Drop zero values ...................................................................... mb/sapphire/pureplatinumh61/devicetree.cb: Drop zero values They default to zero already. Change-Id: Ib888377f06d6fcb79cff5e30155971c17aa2597c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/sapphire/pureplatinumh61/devicetree.cb 1 file changed, 0 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/38061/1 diff --git a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb index b863c308..cb7ef9a 100644 --- a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb +++ b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb @@ -16,20 +16,7 @@ chip northbridge/intel/sandybridge register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" - register "gfx.link_frequency_270_mhz" = "0" register "gfx.ndid" = "3" - register "gfx.use_spread_spectrum_clock" = "0" - register "gpu_cpu_backlight" = "0x00000000" - register "gpu_dp_b_hotplug" = "0" - register "gpu_dp_c_hotplug" = "0" - register "gpu_dp_d_hotplug" = "0" - register "gpu_panel_port_select" = "0" - register "gpu_panel_power_backlight_off_delay" = "0" - register "gpu_panel_power_backlight_on_delay" = "0" - register "gpu_panel_power_cycle_delay" = "0" - register "gpu_panel_power_down_delay" = "0" - register "gpu_panel_power_up_delay" = "0" - register "gpu_pch_backlight" = "0x00000000" device cpu_cluster 0x0 on chip cpu/intel/model_206ax register "c1_acpower" = "1" @@ -45,12 +32,8 @@ device domain 0x0 on chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "c2_latency" = "0x0065" - register "docking_supported" = "0" register "gen1_dec" = "0x000c0291" register "gen2_dec" = "0x000c0a01" - register "gen3_dec" = "0x00000000" - register "gen4_dec" = "0x00000000" - register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" register "pcie_port_coalesce" = "1" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x33" -- To view, visit https://review.coreboot.org/c/coreboot/+/38061 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib888377f06d6fcb79cff5e30155971c17aa2597c Gerrit-Change-Number: 38061 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/gigabyte/ga-b75m-d3h/devicetree.cb: Drop zero fields
by Angel Pons (Code Review) 05 Jan '20

05 Jan '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38060 ) Change subject: mb/gigabyte/ga-b75m-d3h/devicetree.cb: Drop zero fields ...................................................................... mb/gigabyte/ga-b75m-d3h/devicetree.cb: Drop zero fields They default to zero already. Change-Id: I76bbf4593c43ce24c28568f1b8faefb1be81b4cb Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb 1 file changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/38060/1 diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb index b5a10fc..e581470 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb +++ b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb @@ -30,8 +30,6 @@ end chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH - # GPI routing - register "alt_gp_smi_en" = "0x0000" register "gen1_dec" = "0x003c0a01" # Set max SATA speed to 6.0 Gb/s @@ -41,8 +39,6 @@ register "xhci_switchable_ports" = "0xf" register "superspeed_capable_ports" = "0xf" - register "pcie_port_coalesce" = "0" - register "docking_supported" = "0" register "c2_latency" = "0x0065" device pci 14.0 on # USB 3.0 Controller -- To view, visit https://review.coreboot.org/c/coreboot/+/38060 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I76bbf4593c43ce24c28568f1b8faefb1be81b4cb Gerrit-Change-Number: 38060 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/gigabyte/ga-b75m-d3h: Align devicetree lines
by Angel Pons (Code Review) 05 Jan '20

05 Jan '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38059 ) Change subject: mb/gigabyte/ga-b75m-d3h: Align devicetree lines ...................................................................... mb/gigabyte/ga-b75m-d3h: Align devicetree lines Aligned text is easier to read. Change-Id: I66a8efec3587649746bd56cd17eac2a06c9cc500 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb M src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/overridetree.cb 2 files changed, 41 insertions(+), 41 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/38059/1 diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb index 7b47067..b5a10fc 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb +++ b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb @@ -21,15 +21,15 @@ device domain 0 on subsystemid 0x1458 0x5000 inherit - device pci 00.0 on # Host bridge + device pci 00.0 on # Host bridge subsystemid 0x1458 0x5000 end - device pci 01.0 on end # PCIe Bridge for discrete graphics - device pci 02.0 on # Integrated VGA controller + device pci 01.0 on end # PCIe Bridge for discrete graphics + device pci 02.0 on # Integrated VGA controller subsystemid 0x1458 0xd000 end - chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH + chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH # GPI routing register "alt_gp_smi_en" = "0x0000" register "gen1_dec" = "0x003c0a01" @@ -45,41 +45,41 @@ register "docking_supported" = "0" register "c2_latency" = "0x0065" - device pci 14.0 on # USB 3.0 Controller + device pci 14.0 on # USB 3.0 Controller subsystemid 0x1458 0x5007 end - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 off end # Intel Gigabit Ethernet - device pci 1a.0 on # USB2 EHCI #2 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 off end # Intel Gigabit Ethernet + device pci 1a.0 on # USB2 EHCI #2 subsystemid 0x1458 0x5006 end - device pci 1b.0 on # High Definition Audio + device pci 1b.0 on # High Definition Audio subsystemid 0x1458 0xa002 end - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 on # PCIe Port #5 - device pci 00.0 on # PCI 10ec:8168 + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 on # PCIe Port #5 + device pci 00.0 on # PCI 10ec:8168 subsystemid 0x1458 0xe000 end end - device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on # USB2 EHCI #1 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on # USB2 EHCI #1 subsystemid 0x1458 0x5006 end device pci 1e.0 on end # PCI bridge device pci 1f.0 on # ISA/LPC bridge subsystemid 0x1458 0x5001 chip superio/ite/it8728f - device pnp 2e.0 off end # FDC - device pnp 2e.1 on # Serial Port 1 + device pnp 2e.0 off end # FDC + device pnp 2e.1 on # Serial Port 1 io 0x60 = 0x3f8 irq 0x70 = 4 end @@ -92,35 +92,35 @@ irq 0x70 = 7 drq 0x74 = 4 end - device pnp 2e.4 on # EC + device pnp 2e.4 on # EC io 0x60 = 0xa30 irq 0x70 = 9 io 0x62 = 0xa20 end - device pnp 2e.5 on # Keyboard + device pnp 2e.5 on # Keyboard io 0x60 = 0x60 irq 0x70 = 1 io 0x62 = 0x64 end - device pnp 2e.6 on # Mouse + device pnp 2e.6 on # Mouse irq 0x70 = 12 end - device pnp 2e.7 off end # GPIO - device pnp 2e.a off end # IR + device pnp 2e.7 off end # GPIO + device pnp 2e.a off end # IR end chip drivers/pc80/tpm device pnp 0c31.0 on end end end - device pci 1f.2 on # SATA Controller 1 + device pci 1f.2 on # SATA Controller 1 subsystemid 0x1458 0xb005 end - device pci 1f.3 on # SMBus + device pci 1f.3 on # SMBus subsystemid 0x1458 0x5001 end device pci 1f.4 off end - device pci 1f.5 off end # SATA Controller 2 + device pci 1f.5 off end # SATA Controller 2 end end end diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/overridetree.cb b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/overridetree.cb index 2fd3cd5..b496fe1 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/overridetree.cb +++ b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/overridetree.cb @@ -1,21 +1,21 @@ chip northbridge/intel/sandybridge device domain 0 on - chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH - device pci 16.0 off end # Management Engine Interface 1 + chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH + device pci 16.0 off end # Management Engine Interface 1 register "xhci_overcurrent_mapping" = "0x00000c03" - device pci 1c.1 on end # PCIe Port #2 + device pci 1c.1 on end # PCIe Port #2 device pci 1c.2 on - device pci 00.0 on # PCI 1969:1091 + device pci 00.0 on # PCI 1969:1091 subsystemid 0x1458 0xe000 end end # PCIe Port #3 - device pci 1c.3 on end # PCIe Port #4 - device pci 1c.4 on end # PCIe Port #5 - device pci 1f.0 on # ISA/LPC bridge + device pci 1c.3 on end # PCIe Port #4 + device pci 1c.4 on end # PCIe Port #5 + device pci 1f.0 on # ISA/LPC bridge subsystemid 0x1458 0x5001 chip superio/ite/it8728f - device pnp 2e.2 off end # COM2 - device pnp 2e.3 off end # LPT + device pnp 2e.2 off end # COM2 + device pnp 2e.3 off end # LPT end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/38059 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66a8efec3587649746bd56cd17eac2a06c9cc500 Gerrit-Change-Number: 38059 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/gigabyte/ga-g41m-es2l/devicetree.cb: Indent with tabs
by Angel Pons (Code Review) 05 Jan '20

05 Jan '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38058 ) Change subject: mb/gigabyte/ga-g41m-es2l/devicetree.cb: Indent with tabs ...................................................................... mb/gigabyte/ga-g41m-es2l/devicetree.cb: Indent with tabs As on most other boards, use tabs to indent the devicetree. Change-Id: If95f1ce6a5347658ecc32097a85b1b6bcc6a1114 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb 1 file changed, 148 insertions(+), 148 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/38058/1 diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb index 13da3e8..76dd819 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb @@ -15,157 +15,157 @@ # chip northbridge/intel/x4x # Northbridge - device cpu_cluster 0 on # APIC cluster - chip cpu/intel/socket_LGA775 - device lapic 0 on end - end - chip cpu/intel/model_1067x # CPU - device lapic 0xACAC off end - end - end - device domain 0 on # PCI domain - subsystemid 0x1458 0x5000 inherit - device pci 0.0 on # Host Bridge - subsystemid 0x1458 0x5000 - end - device pci 2.0 on # Integrated graphics controller - subsystemid 0x1458 0xd000 - end - device pci 2.1 on # Integrated graphics controller 2 - subsystemid 0x1458 0xd001 - end - device pci 3.0 off end # ME - device pci 3.1 off end # ME - chip southbridge/intel/i82801gx # Southbridge - register "pirqa_routing" = "0x0b" - register "pirqb_routing" = "0x0b" - register "pirqc_routing" = "0x0b" - register "pirqd_routing" = "0x0b" - register "pirqe_routing" = "0x0b" - register "pirqf_routing" = "0x0b" - register "pirqg_routing" = "0x0b" - register "pirqh_routing" = "0x0b" - register "ide_enable_primary" = "0x1" - register "ide_enable_secondary" = "0x0" - register "sata_ports_implemented" = "0x3" - register "gpe0_en" = "0x40" + device cpu_cluster 0 on # APIC cluster + chip cpu/intel/socket_LGA775 + device lapic 0 on end + end + chip cpu/intel/model_1067x # CPU + device lapic 0xACAC off end + end + end + device domain 0 on # PCI domain + subsystemid 0x1458 0x5000 inherit + device pci 0.0 on # Host Bridge + subsystemid 0x1458 0x5000 + end + device pci 2.0 on # Integrated graphics controller + subsystemid 0x1458 0xd000 + end + device pci 2.1 on # Integrated graphics controller 2 + subsystemid 0x1458 0xd001 + end + device pci 3.0 off end # ME + device pci 3.1 off end # ME + chip southbridge/intel/i82801gx # Southbridge + register "pirqa_routing" = "0x0b" + register "pirqb_routing" = "0x0b" + register "pirqc_routing" = "0x0b" + register "pirqd_routing" = "0x0b" + register "pirqe_routing" = "0x0b" + register "pirqf_routing" = "0x0b" + register "pirqg_routing" = "0x0b" + register "pirqh_routing" = "0x0b" + register "ide_enable_primary" = "0x1" + register "ide_enable_secondary" = "0x0" + register "sata_ports_implemented" = "0x3" + register "gpe0_en" = "0x40" - register "gen2_dec" = "0x007c0291" # HWM + register "gen2_dec" = "0x007c0291" # HWM - device pci 1b.0 on # Audio - subsystemid 0x1458 0xa002 - end - device pci 1c.0 on end # PCIe 1 - device pci 1c.1 on # PCIe 2 (NIC) - device pci 00.0 on # PCI 10ec:8168 - subsystemid 0x1458 0xe000 - end - end - device pci 1c.2 off end # PCIe 3 - device pci 1c.3 off end # PCIe 4 - device pci 1d.0 on # USB - subsystemid 0x1458 0x5004 - end - device pci 1d.1 on # USB - subsystemid 0x1458 0x5004 - end - device pci 1d.2 on # USB - subsystemid 0x1458 0x5004 - end - device pci 1d.3 on # USB - subsystemid 0x1458 0x5004 - end - device pci 1d.7 on # USB - subsystemid 0x1458 0x5006 - end - device pci 1e.0 on end # PCI bridge - device pci 1e.2 off end # AC'97 Audio - device pci 1e.3 off end # AC'97 Modem - device pci 1f.0 on # ISA bridge - subsystemid 0x1458 0x5001 - chip superio/ite/it8718f # Super I/O - register "TMPIN1.mode" = "THERMAL_RESISTOR" - register "TMPIN2.mode" = "THERMAL_RESISTOR" - register "TMPIN3.mode" = "THERMAL_DIODE" - register "TMPIN3.offset" = "0" - register "ec.vin_mask" = "VIN7 | VIN4 | VIN3 | VIN2 | VIN1 | VIN0" + device pci 1b.0 on # Audio + subsystemid 0x1458 0xa002 + end + device pci 1c.0 on end # PCIe 1 + device pci 1c.1 on # PCIe 2 (NIC) + device pci 00.0 on # PCI 10ec:8168 + subsystemid 0x1458 0xe000 + end + end + device pci 1c.2 off end # PCIe 3 + device pci 1c.3 off end # PCIe 4 + device pci 1d.0 on # USB + subsystemid 0x1458 0x5004 + end + device pci 1d.1 on # USB + subsystemid 0x1458 0x5004 + end + device pci 1d.2 on # USB + subsystemid 0x1458 0x5004 + end + device pci 1d.3 on # USB + subsystemid 0x1458 0x5004 + end + device pci 1d.7 on # USB + subsystemid 0x1458 0x5006 + end + device pci 1e.0 on end # PCI bridge + device pci 1e.2 off end # AC'97 Audio + device pci 1e.3 off end # AC'97 Modem + device pci 1f.0 on # ISA bridge + subsystemid 0x1458 0x5001 + chip superio/ite/it8718f # Super I/O + register "TMPIN1.mode" = "THERMAL_RESISTOR" + register "TMPIN2.mode" = "THERMAL_RESISTOR" + register "TMPIN3.mode" = "THERMAL_DIODE" + register "TMPIN3.offset" = "0" + register "ec.vin_mask" = "VIN7 | VIN4 | VIN3 | VIN2 | VIN1 | VIN0" - register "FAN1.mode" = "FAN_SMART_AUTOMATIC" - register "FAN1.smart.tmpin" = "3" - register "FAN1.smart.tmp_off" = "25" - register "FAN1.smart.tmp_start" = "30" - register "FAN1.smart.tmp_full" = "65" - register "FAN1.smart.tmp_delta" = "3" - register "FAN1.smart.smoothing" = "1" - register "FAN1.smart.pwm_start" = "0" - register "FAN1.smart.slope" = "10" + register "FAN1.mode" = "FAN_SMART_AUTOMATIC" + register "FAN1.smart.tmpin" = "3" + register "FAN1.smart.tmp_off" = "25" + register "FAN1.smart.tmp_start" = "30" + register "FAN1.smart.tmp_full" = "65" + register "FAN1.smart.tmp_delta" = "3" + register "FAN1.smart.smoothing" = "1" + register "FAN1.smart.pwm_start" = "0" + register "FAN1.smart.slope" = "10" - register "FAN2.mode" = "FAN_SMART_AUTOMATIC" - register "FAN2.smart.tmpin" = "3" - register "FAN2.smart.tmp_off" = "25" - register "FAN2.smart.tmp_start" = "30" - register "FAN2.smart.tmp_full" = "65" - register "FAN2.smart.tmp_delta" = "3" - register "FAN2.smart.smoothing" = "1" - register "FAN2.smart.pwm_start" = "0" - register "FAN2.smart.slope" = "10" + register "FAN2.mode" = "FAN_SMART_AUTOMATIC" + register "FAN2.smart.tmpin" = "3" + register "FAN2.smart.tmp_off" = "25" + register "FAN2.smart.tmp_start" = "30" + register "FAN2.smart.tmp_full" = "65" + register "FAN2.smart.tmp_delta" = "3" + register "FAN2.smart.smoothing" = "1" + register "FAN2.smart.pwm_start" = "0" + register "FAN2.smart.slope" = "10" - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - irq 0xf0 = 0x00 - irq 0xf1 = 0x80 - end - device pnp 2e.1 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - io 0x62 = 0x000 - drq 0x74 = 4 - irq 0xf0 = 0x08 - end - device pnp 2e.4 on # Environment controller - io 0x60 = 0x290 - irq 0x70 = 0x00 - io 0x62 = 0x000 - irq 0xf0 = 0x80 - irq 0xf1 = 0x00 - irq 0xf2 = 0x0a - irq 0xf3 = 0x80 - irq 0xf4 = 0x00 - irq 0xf5 = 0x00 - irq 0xf6 = 0xff - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - irq 0x70 = 1 - io 0x62 = 0x64 - irq 0xf0 = 0x48 - end - device pnp 2e.6 on # Mouse - irq 0x70 = 12 - irq 0x71 = 2 - irq 0xf0 = 0 - end - end - end - device pci 1f.1 on # PATA/IDE - subsystemid 0x1458 0xb004 - end - device pci 1f.2 on # SATA - subsystemid 0x1458 0xb005 - end - device pci 1f.3 on # SMbus - subsystemid 0x1458 0x5001 - end - end - end + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + irq 0xf0 = 0x00 + irq 0xf1 = 0x80 + end + device pnp 2e.1 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + io 0x62 = 0x000 + drq 0x74 = 4 + irq 0xf0 = 0x08 + end + device pnp 2e.4 on # Environment controller + io 0x60 = 0x290 + irq 0x70 = 0x00 + io 0x62 = 0x000 + irq 0xf0 = 0x80 + irq 0xf1 = 0x00 + irq 0xf2 = 0x0a + irq 0xf3 = 0x80 + irq 0xf4 = 0x00 + irq 0xf5 = 0x00 + irq 0xf6 = 0xff + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + irq 0x70 = 1 + io 0x62 = 0x64 + irq 0xf0 = 0x48 + end + device pnp 2e.6 on # Mouse + irq 0x70 = 12 + irq 0x71 = 2 + irq 0xf0 = 0 + end + end + end + device pci 1f.1 on # PATA/IDE + subsystemid 0x1458 0xb004 + end + device pci 1f.2 on # SATA + subsystemid 0x1458 0xb005 + end + device pci 1f.3 on # SMbus + subsystemid 0x1458 0x5001 + end + end + end end -- To view, visit https://review.coreboot.org/c/coreboot/+/38058 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If95f1ce6a5347658ecc32097a85b1b6bcc6a1114 Gerrit-Change-Number: 38058 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: device/smbus: Drop unused smbus_set_link()
by Kyösti Mälkki (Code Review) 04 Jan '20

04 Jan '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38161 ) Change subject: device/smbus: Drop unused smbus_set_link() ...................................................................... device/smbus: Drop unused smbus_set_link() I expect it to be easier to just remodel the support for i2c multiplexers instead. Besides, there was no proper bounds for pbus_num when accessing pbus_a[]. Change-Id: I17f33b308c01e48bc03b142550535c32862442ac Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/device/smbus_ops.c M src/include/device/device.h M src/include/device/smbus.h 3 files changed, 0 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/38161/1 diff --git a/src/device/smbus_ops.c b/src/device/smbus_ops.c index 13e6cad..3b7a69e 100644 --- a/src/device/smbus_ops.c +++ b/src/device/smbus_ops.c @@ -27,43 +27,6 @@ return pbus; } -/* - * Multi-level I2C MUX? May need to find the first I2C device and then set link - * down to current dev. - * - * 1 store get_pbus_smbus list link - * 2 reverse the link and call set link. - * - * @param dev TODO. - */ -int smbus_set_link(struct device *dev) -{ - struct bus *pbus_a[4]; // 4 level mux only. Enough? - struct bus *pbus = dev->bus; - int pbus_num = 0; - int i; - - while (pbus && pbus->dev && (pbus->dev->path.type == DEVICE_PATH_I2C)) { - pbus_a[pbus_num++] = pbus; - pbus = pbus->dev->bus; - } - - // printk(BIOS_INFO, "smbus_set_link: "); - for (i = pbus_num - 1; i >= 0; i--) { - // printk(BIOS_INFO, " %s[%d] -> ", dev_path(pbus_a[i]->dev), - // pbus_a[i]->link); - if (ops_smbus_bus(get_pbus_smbus(pbus_a[i]->dev))) { - if (pbus_a[i]->dev->ops - && pbus_a[i]->dev->ops->set_link) - pbus_a[i]->dev->ops->set_link(pbus_a[i]->dev, - pbus_a[i]->link_num); - } - } - // printk(BIOS_INFO, " %s\n", dev_path(dev)); - - return pbus_num; -} - #define CHECK_PRESENCE(x) \ if (!ops_smbus_bus(get_pbus_smbus(dev))->x) { \ printk(BIOS_ERR, "%s missing " #x "\n", \ diff --git a/src/include/device/device.h b/src/include/device/device.h index e391291..2d7400b 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -41,7 +41,6 @@ void (*scan_bus)(struct device *bus); void (*enable)(struct device *dev); void (*disable)(struct device *dev); - void (*set_link)(struct device *dev, unsigned int link); void (*reset_bus)(struct bus *bus); #if CONFIG(GENERATE_SMBIOS_TABLES) int (*get_smbios_data)(struct device *dev, int *handle, diff --git a/src/include/device/smbus.h b/src/include/device/smbus.h index 094ad42..cae4f3f 100644 --- a/src/include/device/smbus.h +++ b/src/include/device/smbus.h @@ -28,7 +28,6 @@ } struct bus *get_pbus_smbus(struct device *dev); -int smbus_set_link(struct device *dev); static inline int smbus_recv_byte(struct device *const dev) { -- To view, visit https://review.coreboot.org/c/coreboot/+/38161 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I17f33b308c01e48bc03b142550535c32862442ac Gerrit-Change-Number: 38161 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/i2c/i2cmux2: Drop unused i2c multiplex
by Kyösti Mälkki (Code Review) 04 Jan '20

04 Jan '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38160 ) Change subject: drivers/i2c/i2cmux2: Drop unused i2c multiplex ...................................................................... drivers/i2c/i2cmux2: Drop unused i2c multiplex There is no documentation what hardware this was compatible with. Change-Id: I9bfada83388373962929f35794bca56132ee3d9e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- D src/drivers/i2c/i2cmux2/Kconfig D src/drivers/i2c/i2cmux2/Makefile.inc D src/drivers/i2c/i2cmux2/i2cmux2.c 3 files changed, 0 insertions(+), 47 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/38160/1 diff --git a/src/drivers/i2c/i2cmux2/Kconfig b/src/drivers/i2c/i2cmux2/Kconfig deleted file mode 100644 index 0213e55..0000000 --- a/src/drivers/i2c/i2cmux2/Kconfig +++ /dev/null @@ -1,2 +0,0 @@ -config DRIVERS_I2C_I2CMUX2 - bool diff --git a/src/drivers/i2c/i2cmux2/Makefile.inc b/src/drivers/i2c/i2cmux2/Makefile.inc deleted file mode 100644 index 34e3613..0000000 --- a/src/drivers/i2c/i2cmux2/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -ramstage-$(CONFIG_DRIVERS_I2C_I2CMUX2) += i2cmux2.c diff --git a/src/drivers/i2c/i2cmux2/i2cmux2.c b/src/drivers/i2c/i2cmux2/i2cmux2.c deleted file mode 100644 index c3440af..0000000 --- a/src/drivers/i2c/i2cmux2/i2cmux2.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/device.h> -#include <device/smbus.h> - -static void i2cmux2_set_link(struct device *dev, unsigned int link) -{ - if (dev->enabled && dev->path.type == DEVICE_PATH_I2C) { - if (ops_smbus_bus(get_pbus_smbus(dev))) { - smbus_send_byte(dev, link); // output value - } - } -} - -static struct device_operations i2cmux2_operations = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, - .init = DEVICE_NOOP, - .scan_bus = scan_smbus, - .set_link = i2cmux2_set_link, -}; - -static void enable_dev(struct device *dev) -{ - if (dev->link_list != NULL) - dev->ops = &i2cmux2_operations; -} - -struct chip_operations drivers_i2c_i2cmux2_ops = { - CHIP_NAME("i2cmux2") - .enable_dev = enable_dev, -}; -- To view, visit https://review.coreboot.org/c/coreboot/+/38160 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9bfada83388373962929f35794bca56132ee3d9e Gerrit-Change-Number: 38160 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit January 2020