coreboot-gerrit January 2020

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Change in coreboot[master]: soc/intel/cannonlake: Add VR config for CFL and WHL
by Patrick Rudolph (Code Review) 06 Jan '20

06 Jan '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37466 ) Change subject: soc/intel/cannonlake: Add VR config for CFL and WHL ...................................................................... soc/intel/cannonlake: Add VR config for CFL and WHL Add VR config IccMax, DC and AC loadline defaults for all CFL and WHL. I couldn't find CNL datasheet, but it looks like only a single SoC without graphics was ever produced. I couldn't find CML datasheet, so those are left out for now. Used Doc #337344 and #338023 Section 7. Change-Id: I1d2e174157d468830cc0baf2a2d8295ef61a1a63 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/cannonlake/include/soc/vr_config.h M src/soc/intel/cannonlake/vr_config.c 2 files changed, 236 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/37466/1 diff --git a/src/soc/intel/cannonlake/include/soc/vr_config.h b/src/soc/intel/cannonlake/include/soc/vr_config.h index 8bcf001..4cb35a0 100644 --- a/src/soc/intel/cannonlake/include/soc/vr_config.h +++ b/src/soc/intel/cannonlake/include/soc/vr_config.h @@ -56,6 +56,7 @@ }; #define VR_CFG_AMP(i) ((i) * 4) +#define VR_CFG_MOHMS(i) (uint16_t)((i) * 100) /* VrConfig Settings for 4 domains * 0 = System Agent, 1 = IA Core, @@ -68,6 +69,22 @@ NUM_VR_DOMAINS }; +#define VR_CFG_ALL_DOMAINS_ICC(sa, ia, gt_unsl, gt_sl) \ + { \ + [VR_SYSTEM_AGENT] = VR_CFG_AMP(sa), \ + [VR_IA_CORE] = VR_CFG_AMP(ia), \ + [VR_GT_UNSLICED] = VR_CFG_AMP(gt_unsl), \ + [VR_GT_SLICED] = VR_CFG_AMP(gt_sl), \ + } + +#define VR_CFG_ALL_DOMAINS_LOADLINE(sa, ia, gt_unsl, gt_sl) \ + { \ + [VR_SYSTEM_AGENT] = VR_CFG_MOHMS(sa), \ + [VR_IA_CORE] = VR_CFG_MOHMS(ia), \ + [VR_GT_UNSLICED] = VR_CFG_MOHMS(gt_unsl), \ + [VR_GT_SLICED] = VR_CFG_MOHMS(gt_sl), \ + } + void fill_vr_domain_config(void *params, int domain, const struct vr_config *cfg); diff --git a/src/soc/intel/cannonlake/vr_config.c b/src/soc/intel/cannonlake/vr_config.c index 25270d8..035a270 100644 --- a/src/soc/intel/cannonlake/vr_config.c +++ b/src/soc/intel/cannonlake/vr_config.c @@ -14,9 +14,13 @@ * */ +#include <device/pci_ids.h> +#include <device/pci_ops.h> #include <fsp/api.h> #include <soc/ramstage.h> #include <soc/vr_config.h> +#include <console/console.h> +#include <intelblocks/cpulib.h> static const struct vr_config default_configs[NUM_VR_DOMAINS] = { [VR_SYSTEM_AGENT] = { @@ -28,7 +32,7 @@ .psi4enable = 1, .imon_slope = 0x0, .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(6), + .icc_max = 0, .voltage_limit = 1520, }, [VR_IA_CORE] = { @@ -40,7 +44,7 @@ .psi4enable = 1, .imon_slope = 0x0, .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(70), + .icc_max = 0, .voltage_limit = 1520, }, [VR_GT_UNSLICED] = { @@ -52,7 +56,7 @@ .psi4enable = 1, .imon_slope = 0x0, .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(31), + .icc_max = 0, .voltage_limit = 1520, }, [VR_GT_SLICED] = { @@ -64,11 +68,207 @@ .psi4enable = 1, .imon_slope = 0x0, .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(31), + .icc_max = 0, .voltage_limit = 1520, }, }; + +static uint16_t get_sku_icc_max(int domain) +{ + const uint16_t tdp = cpu_get_power_max(); + + static uint16_t mch_id = 0; + if (!mch_id) { + struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); + mch_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff; + } + + /* + * Iccmax table from Doc #337344 Section 7.2 DC Specifications for CFL. + * Iccmax table from Doc #338023 Section 7.2 DC Specifications for WHL. + * + * Platform Segment SA IA GT (GT/GTx) + * --------------------------------------------------------------------- + * CFL-U (28W) GT3 quad 8.5 64 64 + * CFL-U (28W) GT3 dual 8.5 64 64 + * + * CFL-H (45W) GT2 hex 11.1 128 0 + * CFL-H (45W) GT2 quad 11.1 64 0 + * + * CFL-S (95W) GT2 octa 11.1 193 45 + * + * CFL-S (95W) GT2 hex 11.1 138 45 + * CFL-S (65W) GT2 hex 11.1 133 45 + * CFL-S (80W) GT2 hex 11.1 133 45 + * CFL-S (35W) GT2 hex 11.1 104 35 + * + * CFL-S (91W) GT2 quad 11.1 100 45 + * CFL-S (83W) GT2 quad 11.1 100 45 + * CFL-S (71W) GT2 quad 11.1 100 45 + * CFL-S (65W) GT2 quad 11.1 79 45 + * CFL-S (62W) GT2 quad 11.1 79 45 + * CFL-S (35W) GT2 quad 11.1 66 35 + * + * CFL-S (58W) GT2 dual 11.1 79 45 + * CFL-S (54W) GT2 dual 11.1 58 45 + * CFL-S (35W) GT2 dual 11.1 40 35 + * + * CNL-U (15W) ? ? 0 + * + * WHL-U (15W) GT2 quad 6 70 31 + * WHL-U (15W) GT2 dual 6 35 31 + * + */ + + switch (mch_id) { + case PCI_DEVICE_ID_INTEL_CNL_ID_U: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_CNL_ID_Y: { + uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(8.5, 64, 0, 0); + + return icc_max[domain]; + } + case PCI_DEVICE_ID_INTEL_WHL_ID_W_4: { + uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(6, 70, 31, 31); + + return icc_max[domain]; + } + case PCI_DEVICE_ID_INTEL_WHL_ID_W_2: { + uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(6, 35, 31, 31); + + return icc_max[domain]; + } + case PCI_DEVICE_ID_INTEL_CFL_ID_U: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_CFL_ID_U_2: { + uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(8.5, 64, 64, 64); + + return icc_max[domain]; + } + case PCI_DEVICE_ID_INTEL_CFL_ID_H_8: /* fallthrough - undocumented */ + case PCI_DEVICE_ID_INTEL_CFL_ID_H: { /* 6 core */ + uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(11.1, 128, 0, 0); + + return icc_max[domain]; + } + case PCI_DEVICE_ID_INTEL_CFL_ID_H_4: { /* 4 core */ + uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(11.1, 64, 0, 0); + + return icc_max[domain]; + } + case PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_2: { /* 2 core */ + uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(11.1, 40, 35, 35); + + if (tdp >= 54) { + if (tdp >= 58) + icc_max[VR_IA_CORE] = VR_CFG_AMP(79); + else + icc_max[VR_IA_CORE] = VR_CFG_AMP(58); + + icc_max[VR_GT_SLICED] = VR_CFG_AMP(45); + icc_max[VR_GT_UNSLICED] = VR_CFG_AMP(45); + } + + return icc_max[domain]; + } + case PCI_DEVICE_ID_INTEL_CFL_ID_S_S_8: { + uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(11.1, 193, 45, 45); + + return icc_max[domain]; + } + case PCI_DEVICE_ID_INTEL_CFL_ID_S: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_6: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_CFL_ID_S_S_6: { + uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(11.1, 104, 35, 35); + if (tdp > 35) { + if (tdp >= 95) { + icc_max[VR_IA_CORE] = VR_CFG_AMP(138); + } else if (tdp >= 65) { + icc_max[VR_IA_CORE] = VR_CFG_AMP(133); + } + + icc_max[VR_GT_SLICED] = VR_CFG_AMP(45); + icc_max[VR_GT_UNSLICED] = VR_CFG_AMP(45); + } + return icc_max[domain]; + } + case PCI_DEVICE_ID_INTEL_CFL_ID_S_S_4: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_4: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_4: { + uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(11.1, 66, 35, 35); + if (tdp > 35) { + if (tdp >= 71) { + icc_max[VR_IA_CORE] = VR_CFG_AMP(100); + } else if (tdp >= 62) { + icc_max[VR_IA_CORE] = VR_CFG_AMP(79); + } + + icc_max[VR_GT_SLICED] = VR_CFG_AMP(45); + icc_max[VR_GT_UNSLICED] = VR_CFG_AMP(45); + } + return icc_max[domain]; + } + default: + printk(BIOS_ERR, "ERROR: Unknown MCH (0x%x) in VR-config\n", mch_id); + } + return 0; +} + +static uint16_t get_sku_ac_dc_loadline(const int domain) +{ + static uint16_t mch_id = 0; + if (!mch_id) { + struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); + mch_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff; + } + + switch (mch_id) { + case PCI_DEVICE_ID_INTEL_WHL_ID_W_4: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_CFL_ID_H_8: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_CFL_ID_H: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_CFL_ID_H_4: { /* fallthrough */ + uint16_t loadline[NUM_VR_DOMAINS] = + VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.8, 2.7, 2.7); + if (mch_id == PCI_DEVICE_ID_INTEL_WHL_ID_W_4) { + loadline[VR_GT_SLICED] = 0; /* unspecified */ + loadline[VR_GT_UNSLICED] = 0; /* unspecified */ + } + return loadline[domain]; + } + case PCI_DEVICE_ID_INTEL_WHL_ID_W_2: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_CFL_ID_U: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_CFL_ID_U_2: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_CNL_ID_U: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_CNL_ID_Y: { + uint16_t loadline[NUM_VR_DOMAINS] = + VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.4, 2.0, 2.0); + if (mch_id == PCI_DEVICE_ID_INTEL_WHL_ID_W_2) { + loadline[VR_GT_SLICED] = 0; /* unspecified */ + loadline[VR_GT_UNSLICED] = 0; /* unspecified */ + } + return loadline[domain]; + } + case PCI_DEVICE_ID_INTEL_CFL_ID_S_S_8: { + const uint16_t loadline[NUM_VR_DOMAINS] = + VR_CFG_ALL_DOMAINS_LOADLINE(11.1, 1.6, 3.1, 3.1); + return loadline[domain]; + } + case PCI_DEVICE_ID_INTEL_CFL_ID_S: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_6: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_CFL_ID_S_S_6: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_CFL_ID_S_S_4: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_4: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_4: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_2: { + const uint16_t loadline[NUM_VR_DOMAINS] = + VR_CFG_ALL_DOMAINS_LOADLINE(11.1, 2.1, 3.1, 3.1); + return loadline[domain]; + } + default: + printk(BIOS_ERR, "ERROR: Unknown MCH (0x%x) in VR-config\n", mch_id); + } + return 0; +} + void fill_vr_domain_config(void *params, int domain, const struct vr_config *chip_cfg) { @@ -96,4 +296,19 @@ vr_params->VrVoltageLimit[domain] = cfg->voltage_limit; vr_params->AcLoadline[domain] = cfg->ac_loadline; vr_params->DcLoadline[domain] = cfg->dc_loadline; + + /* If board provided non-zero value, use it. */ + if (cfg->icc_max) + vr_params->IccMax[domain] = cfg->icc_max; + else + vr_params->IccMax[domain] = get_sku_icc_max(domain); + + if (cfg->ac_loadline) + vr_params->AcLoadline[domain] = cfg->ac_loadline; + else + vr_params->AcLoadline[domain] = get_sku_ac_dc_loadline(domain); + if (cfg->dc_loadline) + vr_params->DcLoadline[domain] = cfg->dc_loadline; + else + vr_params->DcLoadline[domain] = get_sku_ac_dc_loadline(domain); } -- To view, visit https://review.coreboot.org/c/coreboot/+/37466 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d2e174157d468830cc0baf2a2d8295ef61a1a63 Gerrit-Change-Number: 37466 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/inteltool: Add GPIO dumping capabilites for Icelake U systems
by Mimoja (Code Review) 06 Jan '20

06 Jan '20

Hello Stefan Reinauer, Philipp Deppenwiese, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/38175 to look at the new patch set (#6). Change subject: util/inteltool: Add GPIO dumping capabilites for Icelake U systems ...................................................................... util/inteltool: Add GPIO dumping capabilites for Icelake U systems This GPIO dumping was implemented using the Intel® 495 Series Chipset Family On-Package Platform Controller Hub datasheet. The GPIO community ports can be found in table 36-1, while the community and pin descriptions are taken from linux/pinctrl/intel/pinctrl-icelake.c . This commit was tested on the late 2019 Razer Blade Stealth with 1065G7 and Chipset 495 PCH and the output manually compared against linux/pinctrl-intel. Change-Id: Ib40f1dbae57169678e92ea9ad0df60ff91b5b22c Signed-off-by: Johanna Schander <coreboot(a)mimoja.de> --- M util/inteltool/gpio.c M util/inteltool/gpio_groups.c M util/inteltool/pcr.c 3 files changed, 439 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/38175/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/38175 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib40f1dbae57169678e92ea9ad0df60ff91b5b22c Gerrit-Change-Number: 38175 Gerrit-PatchSet: 6 Gerrit-Owner: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jeremy Soller <jeremy(a)system76.com> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: util/inteltool: Add GPIO dumping capabilites for Icelake U systems
by Mimoja (Code Review) 06 Jan '20

06 Jan '20

Hello Stefan Reinauer, Philipp Deppenwiese, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/38175 to look at the new patch set (#5). Change subject: util/inteltool: Add GPIO dumping capabilites for Icelake U systems ...................................................................... util/inteltool: Add GPIO dumping capabilites for Icelake U systems This GPIO dumping was implemented using the Intel® 495 Series Chipset Family On-Package Platform Controller Hub datasheet. The GPIO community ports can be found in table 36-1, while the community and pin descriptions are taken from linux/pinctrl/intel/pinctrl-icelake.c . This commit was tested on the late 2019 Razer Blade Stealth with 1065G7 and Chipset 495 PCH and the output manually compared against linux/pinctrl-intel. Change-Id: Ib40f1dbae57169678e92ea9ad0df60ff91b5b22c Signed-off-by: Johanna Schander <coreboot(a)mimoja.de> --- M util/inteltool/gpio.c M util/inteltool/gpio_groups.c M util/inteltool/pcr.c 3 files changed, 439 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/38175/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/38175 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib40f1dbae57169678e92ea9ad0df60ff91b5b22c Gerrit-Change-Number: 38175 Gerrit-PatchSet: 5 Gerrit-Owner: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jeremy Soller <jeremy(a)system76.com> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: util/inteltool: Add GPIO dumping capabilites for Icelake U systems
by Mimoja (Code Review) 06 Jan '20

06 Jan '20

Mimoja has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38175 ) Change subject: util/inteltool: Add GPIO dumping capabilites for Icelake U systems ...................................................................... Patch Set 4: (4 comments) This change is ready for review. https://review.coreboot.org/c/coreboot/+/38175/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/38175/1//COMMIT_MSG@7 PS1, Line 7: capabilites > capabilit*i*es Done https://review.coreboot.org/c/coreboot/+/38175/1//COMMIT_MSG@7 PS1, Line 7: Icelake > Ice Lake Done https://review.coreboot.org/c/coreboot/+/38175/1//COMMIT_MSG@7 PS1, Line 7: [WIP] > I guess the Gerrit tag is enough, if you do not need that tag in your local workflow. Done https://review.coreboot.org/c/coreboot/+/38175/1//COMMIT_MSG@8 PS1, Line 8: > What datasheet (with version) did you use? […] Document Number: 341081-001 Intel® 495 Series Chipset Family On-Package Platform Controller Hub (PCH) -- To view, visit https://review.coreboot.org/c/coreboot/+/38175 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib40f1dbae57169678e92ea9ad0df60ff91b5b22c Gerrit-Change-Number: 38175 Gerrit-PatchSet: 4 Gerrit-Owner: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jeremy Soller <jeremy(a)system76.com> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 06 Jan 2020 09:23:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP]util/inteltool: Add GPIO dumping support for Icelake
by Mimoja (Code Review) 06 Jan '20

06 Jan '20

Mimoja has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37988 ) Change subject: [WIP]util/inteltool: Add GPIO dumping support for Icelake ...................................................................... [WIP]util/inteltool: Add GPIO dumping support for Icelake Change-Id: I05c5b6f348277fedf2f919a369887a78fdfc005b Signed-off-by: Johanna Schander <coreboot(a)mimoja.de> --- M util/inteltool/gpio.c M util/inteltool/gpio_groups.c M util/inteltool/pcr.c 3 files changed, 424 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/37988/1 diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index efeab56..11dbc32 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -1047,6 +1047,7 @@ case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM: + case PCI_DEVICE_ID_INTEL_ICELAKE_LP_U: case PCI_DEVICE_ID_INTEL_C621: case PCI_DEVICE_ID_INTEL_C622: case PCI_DEVICE_ID_INTEL_C624: diff --git a/util/inteltool/gpio_groups.c b/util/inteltool/gpio_groups.c index 321cf97..3d624bb 100644 --- a/util/inteltool/gpio_groups.c +++ b/util/inteltool/gpio_groups.c @@ -2157,6 +2157,422 @@ &cannonlake_pch_h_community_4, }; +/* Ice Lake-LP */ +static const char *const icelake_pch_h_group_names[] = { + /* GPP_G */ + "GPP_G0", "SD3_CMD", + "GPP_G1", "SD3_D0", + "GPP_G2", "SD3_D1", + "GPP_G3", "SD3_D2", + "GPP_G4", "SD3_D3", + "GPP_G5", "SD3_CDB", + "GPP_G6", "SD3_CLK", + "GPP_G7", "SD3_WP", + /* GPP_B */ + "GPP_B0", "CORE_VID_0", + "GPP_B1", "CORE_VID_1", + "GPP_B2", "VRALERTB", + "GPP_B3", "CPU_GP_2", + "GPP_B4", "CPU_GP_3", + "GPP_B5", "ISH_I2C0_SDA", + "GPP_B6", "ISH_I2C0_SCL", + "GPP_B7", "ISH_I2C1_SDA", + "GPP_B8", "ISH_I2C1_SCL", + "GPP_B9", "I2C5_SDA", + "GPP_B10", "I2C5_SCL", + "GPP_B11", "PMCALERTB", + "GPP_B12", "SLP_S0B", + "GPP_B13", "PLTRSTB", + "GPP_B14", "SPKR", + "GPP_B15", "GSPI0_CS0B", + "GPP_B16", "GSPI0_CLK", + "GPP_B17", "GSPI0_MISO", + "GPP_B18", "GSPI0_MOSI", + "GPP_B19", "GSPI1_CS0B", + "GPP_B20", "GSPI1_CLK", + "GPP_B21", "GSPI1_MISO", + "GPP_B22", "GSPI1_MOSI", + "GPP_B23", "SML1ALERTB", + "GPP_B24", "GSPI0_CLK_LOOPBK", + "GPP_B25", "GSPI1_CLK_LOOPBK", + /* GPP_A */ + "GPP_A0", "ESPI_IO_0", + "GPP_A1", "ESPI_IO_1", + "GPP_A2", "ESPI_IO_2", + "GPP_A3", "ESPI_IO_3", + "GPP_A4", "ESPI_CSB", + "GPP_A5", "ESPI_CLK", + "GPP_A6", "ESPI_RESETB", + "GPP_A7", "I2S2_SCLK", + "GPP_A8", "I2S2_SFRM", + "GPP_A9", "I2S2_TXD", + "GPP_A10", "I2S2_RXD", + "GPP_A11", "SATA_DEVSLP_2", + "GPP_A12", "SATAXPCIE_1", + "GPP_A13", "SATAXPCIE_2", + "GPP_A14", "USB2_OCB_1", + "GPP_A15", "USB2_OCB_2", + "GPP_A16", "USB2_OCB_3", + "GPP_A17", "DDSP_HPD_C", + "GPP_A18", "DDSP_HPD_B", + "GPP_A19", "DDSP_HPD_1", + "GPP_A20", "DDSP_HPD_2", + "GPP_A21", "I2S5_TXD", + "GPP_A22", "I2S5_RXD", + "GPP_A23", "I2S1_SCLK", + "GPP_A24", "ESPI_CLK_LOOPBK", + /* GPP_H */ + "GPP_H0", "SD_1P8_SEL", + "GPP_H1", "SD_PWR_EN_B", + "GPP_H2", "GPPC_H_2", + "GPP_H3", "SX_EXIT_HOLDOFFB", + "GPP_H4", "I2C2_SDA", + "GPP_H5", "I2C2_SCL", + "GPP_H6", "I2C3_SDA", + "GPP_H7", "I2C3_SCL", + "GPP_H8", "I2C4_SDA", + "GPP_H9", "I2C4_SCL", + "GPP_H10", "SRCCLKREQB_4", + "GPP_H11", "SRCCLKREQB_5", + "GPP_H12", "M2_SKT2_CFG_0", + "GPP_H13", "M2_SKT2_CFG_1", + "GPP_H14", "M2_SKT2_CFG_2", + "GPP_H15", "M2_SKT2_CFG_3", + "GPP_H16", "DDPB_CTRLCLK", + "GPP_H17", "DDPB_CTRLDATA", + "GPP_H18", "CPU_VCCIO_PWR_GATEB", + "GPP_H19", "TIME_SYNC_0", + "GPP_H20", "IMGCLKOUT_1", + "GPP_H21", "IMGCLKOUT_2", + "GPP_H22", "IMGCLKOUT_3", + "GPP_H23", "IMGCLKOUT_4", + /* GPP_D */ + "GPP_D0", "ISH_GP_0", + "GPP_D1", "ISH_GP_1", + "GPP_D2", "ISH_GP_2", + "GPP_D3", "ISH_GP_3", + "GPP_D4", "IMGCLKOUT_0", + "GPP_D5", "SRCCLKREQB_0", + "GPP_D6", "SRCCLKREQB_1", + "GPP_D7", "SRCCLKREQB_2", + "GPP_D8", "SRCCLKREQB_3", + "GPP_D9", "ISH_SPI_CSB", + "GPP_D10", "ISH_SPI_CLK", + "GPP_D11", "ISH_SPI_MISO", + "GPP_D12", "ISH_SPI_MOSI", + "GPP_D13", "ISH_UART0_RXD", + "GPP_D14", "ISH_UART0_TXD", + "GPP_D15", "ISH_UART0_RTSB", + "GPP_D16", "ISH_UART0_CTSB", + "GPP_D17", "ISH_GP_4", + "GPP_D18", "ISH_GP_5", + "GPP_D19", "I2S_MCLK", + "GPP_D10", "GSPI2_CLK_LOOPBK", + /* GPP_F */ + "GPP_F0", "CNV_BRI_DT", + "GPP_F1", "CNV_BRI_RSP", + "GPP_F2", "CNV_RGI_DT", + "GPP_F3", "CNV_RGI_RSP", + "GPP_F4", "CNV_RF_RESET_B", + "GPP_F5", "EMMC_HIP_MON", + "GPP_F6", "CNV_PA_BLANKING", + "GPP_F7", "EMMC_CMD", + "GPP_F8", "EMMC_DATA0", + "GPP_F9", "EMMC_DATA1", + "GPP_F10", "EMMC_DATA2", + "GPP_F11", "EMMC_DATA3", + "GPP_F12", "EMMC_DATA4", + "GPP_F13", "EMMC_DATA5", + "GPP_F14", "EMMC_DATA6", + "GPP_F15", "EMMC_DATA7", + "GPP_F16", "EMMC_RCLK", + "GPP_F17", "EMMC_CLK", + "GPP_F18", "EMMC_RESETB", + "GPP_F19", "A4WP_PRESENT", + /* vGPIO */ + "CNV_BTEN", "", + "CNV_WCEN", "", + "CNV_BT_HOST_WAKEB", "", + "CNV_BT_IF_SELECT", "", + "vCNV_BT_UART_TXD", "", + "vCNV_BT_UART_RXD", "", + "vCNV_BT_UART_CTS_B", "", + "vCNV_BT_UART_RTS_B", "", + "vCNV_MFUART1_TXD", "", + "vCNV_MFUART1_RXD", "", + "vCNV_MFUART1_CTS_B", "", + "vCNV_MFUART1_RTS_B", "", + "vUART0_TXD", "", + "vUART0_RXD", "", + "vUART0_CTS_B", "", + "vUART0_RTS_B", "", + "vISH_UART0_TXD", "", + "vISH_UART0_RXD", "", + "vISH_UART0_CTS_B", "", + "vISH_UART0_RTS_B", "", + "vCNV_BT_I2S_BCLK", "", + "vCNV_BT_I2S_WS_SYNC", "", + "vCNV_BT_I2S_SDO", "", + "vCNV_BT_I2S_SDI", "", + "vI2S2_SCLK", "", + "vI2S2_SFRM", "", + "vI2S2_TXD", "", + "vI2S2_RXD", "", + "vSD3_CD_B", "", + /* GPP_C */ + "GPP_C0", "SMBCLK", + "GPP_C1", "SMBDATA", + "GPP_C2", "SMBALERTB", + "GPP_C3", "SML0CLK", + "GPP_C4", "SML0DATA", + "GPP_C5", "SML0ALERTB", + "GPP_C6", "SML1CLK", + "GPP_C7", "SML1DATA", + "GPP_C8", "UART0_RXD", + "GPP_C9", "UART0_TXD", + "GPP_C10", "UART0_RTSB", + "GPP_C11", "UART0_CTSB", + "GPP_C12", "UART1_RXD", + "GPP_C13", "UART1_TXD", + "GPP_C14", "UART1_RTSB", + "GPP_C15", "UART1_CTSB", + "GPP_C16", "I2C0_SDA", + "GPP_C17", "I2C0_SCL", + "GPP_C18", "I2C1_SDA", + "GPP_C19", "I2C1_SCL", + "GPP_C20", "UART2_RXD", + "GPP_C21", "UART2_TXD", + "GPP_C22", "UART2_RTSB", + "GPP_C23", "UART2_CTSB", + /* HVCMOS */ + "L_BKLTEN", "", + "L_BKLTCTL", "", + "L_VDDEN", "", + "SYS_PWROK", "", + "SYS_RESETB", "", + "MLK_RSTB", "", + /* GPP_E */ + "GPP_E0", "SATAXPCIE_0", + "GPP_E1", "SPI1_IO_2", + "GPP_E2", "SPI1_IO_3", + "GPP_E3", "CPU_GP_0", + "GPP_E4", "SATA_DEVSLP_0", + "GPP_E5", "SATA_DEVSLP_1", + "GPP_E6", "GPPC_E_6", + "GPP_E7", "CPU_GP_1", + "GPP_E8", "SATA_LEDB", + "GPP_E9", "USB2_OCB_0", + "GPP_E10", "SPI1_CSB", + "GPP_E11", "SPI1_CLK", + "GPP_E12", "SPI1_MISO_IO_1", + "GPP_E13", "SPI1_MOSI_IO_0", + "GPP_E14", "DDSP_HPD_A", + "GPP_E15", "ISH_GP_6", + "GPP_E16", "ISH_GP_7", + "GPP_E17", "DISP_MISC_4", + "GPP_E18", "DDP1_CTRLCLK", + "GPP_E19", "DDP1_CTRLDATA", + "GPP_E20", "DDP2_CTRLCLK", + "GPP_E21", "DDP2_CTRLDATA", + "GPP_E22", "DDPA_CTRLCLK", + "GPP_E23", "DDPA_CTRLDATA", + /* JTAG */ + "JTAG_TDO", "", + "JTAGX", "", + "PRDYB", "", + "PREQB", "", + "CPU_TRSTB", "", + "JTAG_TDI", "", + "JTAG_TMS", "", + "JTAG_TCK", "", + "ITP_PMODE", "", + /* GPP_R */ + "GPP_R0", "HDA_BCLK", + "GPP_R1", "HDA_SYNC", + "GPP_R2", "HDA_SDO", + "GPP_R3", "HDA_SDI_0", + "GPP_R4", "HDA_RSTB", + "GPP_R5", "HDA_SDI_1", + "GPP_R6", "I2S1_TXD", + "GPP_R7", "I2S1_RXD", + /* GPP_S */ + "GPP_S0", "SNDW1_CLK", + "GPP_S1", "SNDW1_DATA", + "GPP_S2", "SNDW2_CLK", + "GPP_S3", "SNDW2_DATA", + "GPP_S4", "SNDW3_CLK", + "GPP_S5", "SNDW3_DATA", + "GPP_S6", "SNDW4_CLK", + "GPP_S7", "SNDW4_DATA", + /* SPI */ + "SPI0_IO_2", "", + "SPI0_IO_3", "", + "SPI0_MOSI_IO_0", "", + "SPI0_MISO_IO_1", "", + "SPI0_TPM_CSB", "", + "SPI0_FLASH_0_CSB", "", + "SPI0_FLASH_1_CSB", "", + "SPI0_CLK", "", + "SPI0_CLK_LOOPBK", "", +}; + +static const struct gpio_group icelake_pch_h_group_g = { + .display = "------- GPIO Group GPP_G -------", + .pad_count = 8, + .func_count = 2, + .pad_names = &icelake_pch_h_group_names[0 * 2], +}; + +static const struct gpio_group icelake_pch_h_group_b = { + .display = "------- GPIO Group GPP_B -------", + .pad_count = 26, + .func_count = 2, + .pad_names = &icelake_pch_h_group_names[8 * 2], +}; + +static const struct gpio_group icelake_pch_h_group_a = { + .display = "------- GPIO Group GPP_A -------", + .pad_count = 25, + .func_count = 2, + .pad_names = &icelake_pch_h_group_names[34 * 2], +}; + +static const struct gpio_group *const icelake_pch_h_community_0_groups[] = { + &icelake_pch_h_group_g, + &icelake_pch_h_group_b, + &icelake_pch_h_group_a, +}; + +static const struct gpio_community icelake_pch_h_community_0 = { + .name = "------- GPIO Community 0 -------", + .pcr_port_id = 0x6d, + .group_count = ARRAY_SIZE(icelake_pch_h_community_0_groups), + .groups = icelake_pch_h_community_0_groups, +}; + +static const struct gpio_group icelake_pch_h_group_h = { + .display = "------- GPIO Group GPP_H -------", + .pad_count = 82 - 59 + 1, + .func_count = 2, + .pad_names = &icelake_pch_h_group_names[59 * 2], +}; + +static const struct gpio_group icelake_pch_h_group_d = { + .display = "------- GPIO Group GPP_D -------", + .pad_count = 103 - 83 + 1, + .func_count = 2, + .pad_names = &icelake_pch_h_group_names[83 * 2], +}; + +static const struct gpio_group icelake_pch_h_group_f = { + .display = "------- GPIO Group GPP_F -------", + .pad_count = 123 - 104 + 1, + .func_count = 2, + .pad_names = &icelake_pch_h_group_names[104 * 2], +}; + +static const struct gpio_group icelake_pch_h_group_vgpio_0 = { + .display = "------- GPIO Group vGPIO_0 -------", + .pad_count = 152 - 124 + 1, + .func_count = 2, + .pad_names = &icelake_pch_h_group_names[124 * 2], +}; + +static const struct gpio_group *const icelake_pch_h_community_1_groups[] = { + &icelake_pch_h_group_h, + &icelake_pch_h_group_d, + &icelake_pch_h_group_f, + &icelake_pch_h_group_vgpio_0, +}; + +static const struct gpio_community icelake_pch_h_community_1 = { + .name = "------- GPIO Community 1 -------", + .pcr_port_id = 0x6c, + .group_count = ARRAY_SIZE(icelake_pch_h_community_1_groups), + .groups = icelake_pch_h_community_1_groups, +}; + +static const struct gpio_group icelake_pch_h_group_c = { + .display = "------- GPIO Group GPP_C -------", + .pad_count = 176 - 153 + 1, + .func_count = 2, + .pad_names = &icelake_pch_h_group_names[153 * 2], +}; + +static const struct gpio_group icelake_pch_h_group_hvcmos = { + .display = "------- GPIO Group HVCMOS -------", + .pad_count = 182 - 177 + 1, + .func_count = 2, + .pad_names = &icelake_pch_h_group_names[177 * 2], +}; + +static const struct gpio_group icelake_pch_h_group_e = { + .display = "------- GPIO Group E -------", + .pad_count = 206 - 183 + 1, + .func_count = 2, + .pad_names = &icelake_pch_h_group_names[183 * 2], +}; + +static const struct gpio_group icelake_pch_h_group_jtag = { + .display = "------- GPIO Group JTAG -------", + .pad_count = 215 - 207 + 1, + .func_count = 2, + .pad_names = &icelake_pch_h_group_names[206 * 2], +}; + +static const struct gpio_group *const icelake_pch_h_community_4_groups[] = { + &icelake_pch_h_group_c, + &icelake_pch_h_group_hvcmos, + &icelake_pch_h_group_e, + &icelake_pch_h_group_jtag, +}; + +static const struct gpio_community icelake_pch_h_community_4 = { + .name = "------- GPIO Community 4 -------", + .pcr_port_id = 0x6b, + .group_count = ARRAY_SIZE(icelake_pch_h_community_4_groups), + .groups = icelake_pch_h_community_4_groups, +}; + +static const struct gpio_group icelake_pch_h_group_r = { + .display = "------- GPIO Group R -------", + .pad_count = 223 - 216 + 1, + .func_count = 2, + .pad_names = &icelake_pch_h_group_names[216 * 2], +}; + +static const struct gpio_group icelake_pch_h_group_s = { + .display = "------- GPIO Group S -------", + .pad_count = 231 - 224 + 1, + .func_count = 2, + .pad_names = &icelake_pch_h_group_names[224 * 2], +}; + +static const struct gpio_group icelake_pch_h_group_spi = { + .display = "------- GPIO Group SPI -------", + .pad_count = 240 - 232 + 1, + .func_count = 2, + .pad_names = &icelake_pch_h_group_names[232 * 2], +}; + +static const struct gpio_group *const icelake_pch_h_community_5_groups[] = { + &icelake_pch_h_group_r, + &icelake_pch_h_group_s, + &icelake_pch_h_group_spi, +}; +static const struct gpio_community icelake_pch_h_community_5 = { + .name = "------- GPIO Community 5 -------", + .pcr_port_id = 0x6a, + .group_count = ARRAY_SIZE(icelake_pch_h_community_5_groups), + .groups = icelake_pch_h_community_5_groups, +}; + +static const struct gpio_community *const icelake_pch_h_communities[] = { + &icelake_pch_h_community_0, + &icelake_pch_h_community_1, + &icelake_pch_h_community_4, + &icelake_pch_h_community_5, +}; static const char *decode_pad_mode(const struct gpio_group *const group, const size_t pad, const uint32_t dw0) @@ -2299,6 +2715,12 @@ pad_stepping = 16; pcr_init(sb); break; + case PCI_DEVICE_ID_INTEL_ICELAKE_LP_U: + community_count = ARRAY_SIZE(icelake_pch_h_communities); + communities = icelake_pch_h_communities; + pad_stepping = 16; + pcr_init(sb); + break; default: return; } diff --git a/util/inteltool/pcr.c b/util/inteltool/pcr.c index ef6bb39..f4bf87b 100644 --- a/util/inteltool/pcr.c +++ b/util/inteltool/pcr.c @@ -132,6 +132,7 @@ case PCI_DEVICE_ID_INTEL_QM370: case PCI_DEVICE_ID_INTEL_HM370: case PCI_DEVICE_ID_INTEL_CM246: + case PCI_DEVICE_ID_INTEL_ICELAKE_LP_U: sbbar_phys = 0xfd000000; use_p2sb = false; break; -- To view, visit https://review.coreboot.org/c/coreboot/+/37988 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I05c5b6f348277fedf2f919a369887a78fdfc005b Gerrit-Change-Number: 37988 Gerrit-PatchSet: 1 Gerrit-Owner: Mimoja <coreboot(a)mimoja.de> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: soc/intel/dnv: Remove commented out Kconfig option
by Subrata Banik (Code Review) 06 Jan '20

06 Jan '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38126 ) Change subject: soc/intel/dnv: Remove commented out Kconfig option ...................................................................... soc/intel/dnv: Remove commented out Kconfig option Change-Id: Ibe646bad09dcfe348dcbfec439129b2d22ec4744 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/denverton_ns/Kconfig 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/38126/1 diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 713aae6..fa49eb0 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -45,7 +45,6 @@ select SOC_INTEL_COMMON_BLOCK_ACPI select SOC_INTEL_COMMON_BLOCK_PMC select ACPI_INTEL_HARDWARE_SLEEP_VALUES -# select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_FAST_SPI select SOC_INTEL_COMMON_BLOCK_GPIO select SOC_INTEL_COMMON_BLOCK_PCR -- To view, visit https://review.coreboot.org/c/coreboot/+/38126 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe646bad09dcfe348dcbfec439129b2d22ec4744 Gerrit-Change-Number: 38126 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: mb/*/*: Remove unused option_table.h includes
by Kyösti Mälkki (Code Review) 06 Jan '20

06 Jan '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38177 ) Change subject: mb/*/*: Remove unused option_table.h includes ...................................................................... mb/*/*: Remove unused option_table.h includes These should have been removed together with read_option(). Change-Id: Ia6f268ac4551de14f9821c789844adfdf428b843 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/getac/p470/early_init.c M src/mainboard/kontron/986lcd-m/early_init.c M src/mainboard/roda/rk886ex/early_init.c 3 files changed, 0 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/38177/1 diff --git a/src/mainboard/getac/p470/early_init.c b/src/mainboard/getac/p470/early_init.c index 8272d5e..0581f80 100644 --- a/src/mainboard/getac/p470/early_init.c +++ b/src/mainboard/getac/p470/early_init.c @@ -24,7 +24,6 @@ #include <console/console.h> #include <northbridge/intel/i945/i945.h> #include <southbridge/intel/i82801gx/i82801gx.h> -#include "option_table.h" void mainboard_pre_raminit_config(int s3_resume) { diff --git a/src/mainboard/kontron/986lcd-m/early_init.c b/src/mainboard/kontron/986lcd-m/early_init.c index 80ce896..995a346 100644 --- a/src/mainboard/kontron/986lcd-m/early_init.c +++ b/src/mainboard/kontron/986lcd-m/early_init.c @@ -23,8 +23,6 @@ #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627thg/w83627thg.h> -#include "option_table.h" - /* Override the default lpc decode ranges */ void mainboard_lpc_decode(void) { diff --git a/src/mainboard/roda/rk886ex/early_init.c b/src/mainboard/roda/rk886ex/early_init.c index 597501a..efecb0d 100644 --- a/src/mainboard/roda/rk886ex/early_init.c +++ b/src/mainboard/roda/rk886ex/early_init.c @@ -26,8 +26,6 @@ #include <southbridge/intel/i82801gx/i82801gx.h> #include <superio/smsc/lpc47n227/lpc47n227.h> -#include "option_table.h" - /* Override the default lpc decode ranges */ void mainboard_lpc_decode(void) { -- To view, visit https://review.coreboot.org/c/coreboot/+/38177 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia6f268ac4551de14f9821c789844adfdf428b843 Gerrit-Change-Number: 38177 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/pc80/rtc: Swap cmos_write32() parameter order
by Kyösti Mälkki (Code Review) 06 Jan '20

06 Jan '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38178 ) Change subject: drivers/pc80/rtc: Swap cmos_write32() parameter order ...................................................................... drivers/pc80/rtc: Swap cmos_write32() parameter order Make it consistent with the more used cmos_write(). Change-Id: I9cf643c770e9819de08dbede48b73f3d4fe15bd7 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/console/post.c M src/include/pc80/mc146818rtc.h M src/northbridge/intel/sandybridge/raminit_mrc.c 3 files changed, 7 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/38178/1 diff --git a/src/console/post.c b/src/console/post.c index a426fcc..9d535cb 100644 --- a/src/console/post.c +++ b/src/console/post.c @@ -98,8 +98,8 @@ cmos_write(0, CMOS_POST_BANK_0_OFFSET); cmos_write(0, CMOS_POST_BANK_1_OFFSET); #if CONFIG(CMOS_POST_EXTRA) - cmos_write32(CMOS_POST_BANK_0_EXTRA, 0); - cmos_write32(CMOS_POST_BANK_1_EXTRA, 0); + cmos_write32(0, CMOS_POST_BANK_0_EXTRA); + cmos_write32(0, CMOS_POST_BANK_1_EXTRA); #endif } @@ -113,10 +113,10 @@ switch (cmos_read(CMOS_POST_BANK_OFFSET)) { case CMOS_POST_BANK_0_MAGIC: - cmos_write32(CMOS_POST_BANK_0_EXTRA, value); + cmos_write32(value, CMOS_POST_BANK_0_EXTRA); break; case CMOS_POST_BANK_1_MAGIC: - cmos_write32(CMOS_POST_BANK_1_EXTRA, value); + cmos_write32(value, CMOS_POST_BANK_1_EXTRA); break; } diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h index aa50773..a8221c7 100644 --- a/src/include/pc80/mc146818rtc.h +++ b/src/include/pc80/mc146818rtc.h @@ -171,7 +171,7 @@ return value; } -static inline void cmos_write32(u8 offset, u32 value) +static inline void cmos_write32(u32 value, u8 offset) { u8 i; for (i = 0; i < sizeof(value); ++i) diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index aa166c9..959ea41 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -66,11 +66,11 @@ pei_data->mrc_output_len); /* Save the MRC seed values to CMOS */ - cmos_write32(CMOS_OFFSET_MRC_SEED, pei_data->scrambler_seed); + cmos_write32(pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED); printk(BIOS_DEBUG, "Save scrambler seed 0x%08x to CMOS 0x%02x\n", pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED); - cmos_write32(CMOS_OFFSET_MRC_SEED_S3, pei_data->scrambler_seed_s3); + cmos_write32(pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3); printk(BIOS_DEBUG, "Save s3 scrambler seed 0x%08x to CMOS 0x%02x\n", pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3); -- To view, visit https://review.coreboot.org/c/coreboot/+/38178 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9cf643c770e9819de08dbede48b73f3d4fe15bd7 Gerrit-Change-Number: 38178 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [UNTESTED] nb/intel/sandybridge: Introduce indexed MCHBAR macros
by Angel Pons (Code Review) 06 Jan '20

06 Jan '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38045 ) Change subject: [UNTESTED] nb/intel/sandybridge: Introduce indexed MCHBAR macros ...................................................................... [UNTESTED] nb/intel/sandybridge: Introduce indexed MCHBAR macros Change-Id: I2a9b28485f94dee51a937fad8a3c5b58b987958e Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/sandybridge.h 2 files changed, 536 insertions(+), 670 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/38045/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 4ecf001..d8bf7fa 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -202,14 +202,14 @@ if (IS_SANDY_CPU(cpu) && IS_SANDY_CPU_C(cpu)) { if (stretch == 2) stretch = 3; - addr = SCHED_SECOND_CBIT_C0 + 0x400 * channel; + addr = SCHED_SECOND_CBIT_Cx(channel); MCHBAR32_AND_OR(addr, 0xffffc3ff, (stretch << 12) | (stretch << 10)); printk(RAM_DEBUG, "OTHP Workaround [%x] = %x\n", addr, MCHBAR32(addr)); } else { // OTHP - addr = TC_OTHP_C0 + 0x400 * channel; + addr = TC_OTHP_Cx(channel); MCHBAR32_AND_OR(addr, 0xfff0ffff, (stretch << 16) | (stretch << 18)); printk(RAM_DEBUG, "OTHP [%x] = %x\n", addr, MCHBAR32(addr)); @@ -229,8 +229,8 @@ reg |= (ctrl->CAS << 8); reg |= (ctrl->CWL << 12); reg |= (ctrl->tRAS << 16); - printram("DBP [%x] = %x\n", TC_DBP_C0 + 0x400 * channel, reg); - MCHBAR32(TC_DBP_C0 + 0x400 * channel) = reg; + printram("DBP [%x] = %x\n", TC_DBP_Cx(channel), reg); + MCHBAR32(TC_DBP_Cx(channel)) = reg; // RAP reg = 0; @@ -241,11 +241,11 @@ reg |= (ctrl->tFAW << 16); reg |= (ctrl->tWR << 24); reg |= (3 << 30); - printram("RAP [%x] = %x\n", TC_RAP_C0 + 0x400 * channel, reg); - MCHBAR32(TC_RAP_C0 + 0x400 * channel) = reg; + printram("RAP [%x] = %x\n", TC_RAP_Cx(channel), reg); + MCHBAR32(TC_RAP_Cx(channel)) = reg; // OTHP - addr = 0x400 * channel + TC_OTHP_C0; + addr = TC_OTHP_Cx(channel); reg = 0; reg |= ctrl->tXPDLL; reg |= (ctrl->tXP << 5); @@ -272,10 +272,10 @@ reg = ((ctrl->tREFI & 0xffff) << 0) | ((ctrl->tRFC & 0x1ff) << 16) | (((val32 / 1024) & 0x7f) << 25); - printram("REFI [%x] = %x\n", TC_RFTP_C0 + 0x400 * channel, reg); - MCHBAR32(TC_RFTP_C0 + 0x400 * channel) = reg; + printram("REFI [%x] = %x\n", TC_RFTP_Cx(channel), reg); + MCHBAR32(TC_RFTP_Cx(channel)) = reg; - MCHBAR32_OR(TC_RFP_C0 + 0x400 * channel, 0xff); + MCHBAR32_OR(TC_RFP_Cx(channel), 0xff); // SRFTP reg = 0; @@ -287,9 +287,9 @@ reg = (reg & ~0x3ff0000) | (val32 << 16); val32 = ctrl->tMOD - 8; reg = (reg & ~0xf0000000) | (val32 << 28); - printram("SRFTP [%x] = %x\n", 0x400 * channel + TC_SRFTP_C0, + printram("SRFTP [%x] = %x\n", TC_SRFTP_Cx(channel), reg); - MCHBAR32(0x400 * channel + TC_SRFTP_C0) = reg; + MCHBAR32(TC_SRFTP_Cx(channel)) = reg; } } @@ -619,7 +619,7 @@ static void wait_428c(int channel) { while (1) { - if (MCHBAR32(IOSAV_STATUS_C0 + (channel << 10)) & 0x50) + if (MCHBAR32(IOSAV_STATUS_Cx(channel)) & 0x50) return; } } @@ -637,14 +637,13 @@ slotrank = (ctrl->rankmap[channel] & 1) ? 0 : 2; /* DRAM command ZQCS */ - MCHBAR32(IOSAV_0_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x0f003; - MCHBAR32(IOSAV_0_SUBSEQ_CTL_C0 + 0x400 * channel) = 0x80c01; - MCHBAR32(IOSAV_0_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = - (slotrank << 24) | 0x60000; - MCHBAR32(IOSAV_0_ADDR_UPD_C0 + 0x400 * channel) = 0; + MCHBAR32(IOSAV_y_SP_CMD_CTL_Cx(channel, 0)) = 0x0f003; + MCHBAR32(IOSAV_y_SUBSEQ_CTL_Cx(channel, 0)) = 0x80c01; + MCHBAR32(IOSAV_y_SP_CMD_ADDR_Cx(channel, 0)) = (slotrank << 24) | 0x60000; + MCHBAR32(IOSAV_y_ADDR_UPD_Cx(channel, 0)) = 0; // execute command queue - why is bit 22 set here?! - MCHBAR32(IOSAV_SEQ_CTL_C0 + 0x400 * channel) = (1 << 22) | RUN_QUEUE_4284(1); + MCHBAR32(IOSAV_SEQ_CTL_Cx(channel)) = (1 << 22) | RUN_QUEUE_4284(1); wait_428c(channel); } @@ -656,7 +655,7 @@ while (!(MCHBAR32(RCOMP_TIMER) & 0x10000)); do { - reg = MCHBAR32(IOSAV_STATUS_C0); + reg = MCHBAR32(IOSAV_STATUS_Cx(0)); } while ((reg & 0x14) == 0); // Set state of memory controller @@ -687,13 +686,13 @@ FOR_ALL_CHANNELS { // Set valid rank CKE reg = ctrl->rankmap[channel]; - MCHBAR32(MC_INIT_STATE_C0 + 0x400 * channel) = reg; + MCHBAR32(MC_INIT_STATE_Cx(channel)) = reg; // Wait 10ns for ranks to settle //udelay(0.01); reg = (reg & ~0xf0) | (ctrl->rankmap[channel] << 4); - MCHBAR32(MC_INIT_STATE_C0 + 0x400 * channel) = reg; + MCHBAR32(MC_INIT_STATE_Cx(channel)) = reg; // Write reset using a NOP write_reset(ctrl); @@ -728,28 +727,28 @@ } /* DRAM command MRS */ - MCHBAR32(IOSAV_0_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x0f000; - MCHBAR32(IOSAV_0_SUBSEQ_CTL_C0 + 0x400 * channel) = 0x41001; - MCHBAR32(IOSAV_0_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = + MCHBAR32(IOSAV_y_SP_CMD_CTL_Cx(channel, 0)) = 0x0f000; + MCHBAR32(IOSAV_y_SUBSEQ_CTL_Cx(channel, 0)) = 0x41001; + MCHBAR32(IOSAV_y_SP_CMD_ADDR_Cx(channel, 0)) = (slotrank << 24) | (reg << 20) | val | 0x60000; - MCHBAR32(IOSAV_0_ADDR_UPD_C0 + 0x400 * channel) = 0; + MCHBAR32(IOSAV_y_ADDR_UPD_Cx(channel, 0)) = 0; /* DRAM command MRS */ - MCHBAR32(IOSAV_1_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f000; - MCHBAR32(IOSAV_1_SUBSEQ_CTL_C0 + 0x400 * channel) = 0x41001; - MCHBAR32(IOSAV_1_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = + MCHBAR32(IOSAV_y_SP_CMD_CTL_Cx(channel, 1)) = 0x1f000; + MCHBAR32(IOSAV_y_SUBSEQ_CTL_Cx(channel, 1)) = 0x41001; + MCHBAR32(IOSAV_y_SP_CMD_ADDR_Cx(channel, 1)) = (slotrank << 24) | (reg << 20) | val | 0x60000; - MCHBAR32(IOSAV_1_ADDR_UPD_C0 + 0x400 * channel) = 0; + MCHBAR32(IOSAV_y_ADDR_UPD_Cx(channel, 1)) = 0; /* DRAM command MRS */ - MCHBAR32(IOSAV_2_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x0f000; - MCHBAR32(IOSAV_2_SUBSEQ_CTL_C0 + 0x400 * channel) = 0x1001 | (ctrl->tMOD << 16); - MCHBAR32(IOSAV_2_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = + MCHBAR32(IOSAV_y_SP_CMD_CTL_Cx(channel, 2)) = 0x0f000; + MCHBAR32(IOSAV_y_SUBSEQ_CTL_Cx(channel, 2)) = 0x1001 | (ctrl->tMOD << 16); + MCHBAR32(IOSAV_y_SP_CMD_ADDR_Cx(channel, 2)) = (slotrank << 24) | (reg << 20) | val | 0x60000; - MCHBAR32(IOSAV_2_ADDR_UPD_C0 + 0x400 * channel) = 0; + MCHBAR32(IOSAV_y_ADDR_UPD_Cx(channel, 2)) = 0; // execute command queue - MCHBAR32(IOSAV_SEQ_CTL_C0 + 0x400 * channel) = RUN_QUEUE_4284(3); + MCHBAR32(IOSAV_SEQ_CTL_Cx(channel)) = RUN_QUEUE_4284(3); } static u32 make_mr0(ramctr_timing * ctrl, u8 rank) @@ -872,16 +871,16 @@ } /* DRAM command NOP */ - MCHBAR32(IOSAV_0_SPECIAL_COMMAND_CTL) = 0x7; - MCHBAR32(IOSAV_0_SUBSEQ_CTL) = 0xf1001; - MCHBAR32(IOSAV_0_SPECIAL_COMMAND_ADDR) = 0x60002; - MCHBAR32(IOSAV_0_ADDR_UPD) = 0; + MCHBAR32(IOSAV_y_SP_CMD_CTL(0)) = 0x7; + MCHBAR32(IOSAV_y_SUBSEQ_CTL(0)) = 0xf1001; + MCHBAR32(IOSAV_y_SP_CMD_ADDR(0)) = 0x60002; + MCHBAR32(IOSAV_y_ADDR_UPD(0)) = 0; /* DRAM command ZQCL */ - MCHBAR32(IOSAV_0_SPECIAL_COMMAND_CTL) = 0x1f003; - MCHBAR32(IOSAV_0_SUBSEQ_CTL) = 0x1901001; - MCHBAR32(IOSAV_0_SPECIAL_COMMAND_ADDR) = 0x60400; - MCHBAR32(IOSAV_0_ADDR_UPD) = 0x288; + MCHBAR32(IOSAV_y_SP_CMD_CTL(1)) = 0x1f003; + MCHBAR32(IOSAV_y_SUBSEQ_CTL(1)) = 0x1901001; + MCHBAR32(IOSAV_y_SP_CMD_ADDR(1)) = 0x60400; + MCHBAR32(IOSAV_y_ADDR_UPD(1)) = 0x288; // execute command queue on all channels? Why isn't bit 0 set here? MCHBAR32(IOSAV_SEQ_CTL) = 0x40004; @@ -896,7 +895,7 @@ MCHBAR32_OR(MC_INIT_STATE_G, 8); FOR_ALL_POPULATED_CHANNELS { - MCHBAR32_AND(SCHED_CBIT_C0 + 0x400 * channel, ~0x200000); + MCHBAR32_AND(SCHED_CBIT_Cx(channel), ~0x200000); wait_428c(channel); @@ -906,14 +905,13 @@ wait_428c(channel); /* DRAM command ZQCS */ - MCHBAR32(IOSAV_0_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x0f003; - MCHBAR32(IOSAV_0_SUBSEQ_CTL_C0 + 0x400 * channel) = 0x659001; - MCHBAR32(IOSAV_0_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = - (slotrank << 24) | 0x60000; - MCHBAR32(IOSAV_0_ADDR_UPD_C0 + 0x400 * channel) = 0x3e0; + MCHBAR32(IOSAV_y_SP_CMD_CTL_Cx(channel, 0)) = 0x0f003; + MCHBAR32(IOSAV_y_SUBSEQ_CTL_Cx(channel, 0)) = 0x659001; + MCHBAR32(IOSAV_y_SP_CMD_ADDR_Cx(channel, 0)) = (slotrank << 24) | 0x60000; + MCHBAR32(IOSAV_y_ADDR_UPD_Cx(channel, 0)) = 0x3e0; // execute command queue - MCHBAR32(IOSAV_SEQ_CTL_C0 + 0x400 * channel) = RUN_QUEUE_4284(1); + MCHBAR32(IOSAV_SEQ_CTL_Cx(channel)) = RUN_QUEUE_4284(1); // Drain wait_428c(channel); @@ -990,7 +988,7 @@ MCHBAR32(GDCRCKPICODE_C0 + channel * 0x100) = reg_c14; MCHBAR32(GDCRCKLOGICDELAY_C0 + channel * 0x100) = reg_c18; - reg_io_latency = MCHBAR32(SC_IO_LATENCY_C0 + 0x400 * channel); + reg_io_latency = MCHBAR32(SC_IO_LATENCY_Cx(channel)); reg_io_latency &= 0xffff0000; reg_4024 = 0; @@ -1066,8 +1064,8 @@ timC + shift) & 0x40) << 13)); } } - MCHBAR32(SC_ROUNDT_LAT_C0 + 0x400 * channel) = reg_4024; - MCHBAR32(SC_IO_LATENCY_C0 + 0x400 * channel) = reg_io_latency; + MCHBAR32(SC_ROUNDT_LAT_Cx(channel)) = reg_4024; + MCHBAR32(SC_IO_LATENCY_Cx(channel)) = reg_io_latency; } static void test_timA(ramctr_timing * ctrl, int channel, int slotrank) @@ -1078,35 +1076,32 @@ * write MR3 MPR enable * in this mode only RD and RDA are allowed * all reads return a predefined pattern */ - MCHBAR32(IOSAV_0_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f000; - MCHBAR32(IOSAV_0_SUBSEQ_CTL_C0 + 0x400 * channel) = (0xc01 | (ctrl->tMOD << 16)); - MCHBAR32(IOSAV_0_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = - (slotrank << 24) | 0x360004; - MCHBAR32(IOSAV_0_ADDR_UPD_C0 + 0x400 * channel) = 0; + MCHBAR32(IOSAV_y_SP_CMD_CTL_Cx(channel, 0)) = 0x1f000; + MCHBAR32(IOSAV_y_SUBSEQ_CTL_Cx(channel, 0)) = (0xc01 | (ctrl->tMOD << 16)); + MCHBAR32(IOSAV_y_SP_CMD_ADDR_Cx(channel, 0)) = (slotrank << 24) | 0x360004; + MCHBAR32(IOSAV_y_ADDR_UPD_Cx(channel, 0)) = 0; /* DRAM command RD */ - MCHBAR32(IOSAV_1_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f105; - MCHBAR32(IOSAV_1_SUBSEQ_CTL_C0 + 0x400 * channel) = 0x4040c01; - MCHBAR32(IOSAV_1_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = (slotrank << 24); - MCHBAR32(IOSAV_1_ADDR_UPD_C0 + 0x400 * channel) = 0; + MCHBAR32(IOSAV_y_SP_CMD_CTL_Cx(channel, 1)) = 0x1f105; + MCHBAR32(IOSAV_y_SUBSEQ_CTL_Cx(channel, 1)) = 0x4040c01; + MCHBAR32(IOSAV_y_SP_CMD_ADDR_Cx(channel, 1)) = (slotrank << 24); + MCHBAR32(IOSAV_y_ADDR_UPD_Cx(channel, 1)) = 0; /* DRAM command RD */ - MCHBAR32(IOSAV_2_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f105; - MCHBAR32(IOSAV_2_SUBSEQ_CTL_C0 + 0x400 * channel) = 0x100f | ((ctrl->CAS + 36) << 16); - MCHBAR32(IOSAV_2_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = - (slotrank << 24) | 0x60000; - MCHBAR32(IOSAV_2_ADDR_UPD_C0 + 0x400 * channel) = 0; + MCHBAR32(IOSAV_y_SP_CMD_CTL_Cx(channel, 2)) = 0x1f105; + MCHBAR32(IOSAV_y_SUBSEQ_CTL_Cx(channel, 2)) = 0x100f | ((ctrl->CAS + 36) << 16); + MCHBAR32(IOSAV_y_SP_CMD_ADDR_Cx(channel, 2)) = (slotrank << 24) | 0x60000; + MCHBAR32(IOSAV_y_ADDR_UPD_Cx(channel, 2)) = 0; /* DRAM command MRS * write MR3 MPR disable */ - MCHBAR32(IOSAV_3_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f000; - MCHBAR32(IOSAV_3_SUBSEQ_CTL_C0 + 0x400 * channel) = 0xc01 | (ctrl->tMOD << 16); - MCHBAR32(IOSAV_3_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = - (slotrank << 24) | 0x360000; - MCHBAR32(IOSAV_3_ADDR_UPD_C0 + 0x400 * channel) = 0; + MCHBAR32(IOSAV_y_SP_CMD_CTL_Cx(channel, 3)) = 0x1f000; + MCHBAR32(IOSAV_y_SUBSEQ_CTL_Cx(channel, 3)) = 0xc01 | (ctrl->tMOD << 16); + MCHBAR32(IOSAV_y_SP_CMD_ADDR_Cx(channel, 3)) = (slotrank << 24) | 0x360000; + MCHBAR32(IOSAV_y_ADDR_UPD_Cx(channel, 3)) = 0; // execute command queue - MCHBAR32(IOSAV_SEQ_CTL_C0 + 0x400 * channel) = RUN_QUEUE_4284(4); + MCHBAR32(IOSAV_SEQ_CTL_Cx(channel)) = RUN_QUEUE_4284(4); wait_428c(channel); } @@ -1362,14 +1357,13 @@ wait_428c(channel); /* DRAM command PREA */ - MCHBAR32(IOSAV_0_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f002; - MCHBAR32(IOSAV_0_SUBSEQ_CTL_C0 + 0x400 * channel) = 0xc01 | (ctrl->tRP << 16); - MCHBAR32(IOSAV_0_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = - (slotrank << 24) | 0x60400; - MCHBAR32(IOSAV_0_ADDR_UPD_C0 + 0x400 * channel) = 0; + MCHBAR32(IOSAV_y_SP_CMD_CTL_Cx(channel, 0)) = 0x1f002; + MCHBAR32(IOSAV_y_SUBSEQ_CTL_Cx(channel, 0)) = 0xc01 | (ctrl->tRP << 16); + MCHBAR32(IOSAV_y_SP_CMD_ADDR_Cx(channel, 0)) = (slotrank << 24) | 0x60400; + MCHBAR32(IOSAV_y_ADDR_UPD_Cx(channel, 0)) = 0; // execute command queue - MCHBAR32(IOSAV_SEQ_CTL_C0 + 0x400 * channel) = RUN_QUEUE_4284(1); + MCHBAR32(IOSAV_SEQ_CTL_Cx(channel)) = RUN_QUEUE_4284(1); MCHBAR32(GDCRTRAININGMOD) = (slotrank << 2) | 0x8001; @@ -1448,7 +1442,7 @@ program_timings(ctrl, channel); } FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - MCHBAR32(IOSAV_B0_BW_MASK_C0 + 0x400 * channel + 4 * lane) = 0; + MCHBAR32(IOSAV_By_BW_MASK_Cx(channel, lane)) = 0; } return 0; } @@ -1458,77 +1452,70 @@ int lane; FOR_ALL_LANES { - MCHBAR32(IOSAV_B0_ERROR_COUNT_C0 + 0x400 * channel + 4 * lane) = 0; - MCHBAR32(IOSAV_B0_BW_SERROR_C_C0 + 0x400 * channel + 4 * lane); + MCHBAR32(IOSAV_By_ERROR_COUNT_Cx(channel, lane)) = 0; + MCHBAR32(IOSAV_By_BW_SERROR_C_Cx(channel, lane)); } wait_428c(channel); /* DRAM command ACT */ - MCHBAR32(IOSAV_0_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f006; - MCHBAR32(IOSAV_0_SUBSEQ_CTL_C0 + 0x400 * channel) = - (MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD) << 10) - | 4 | (ctrl->tRCD << 16); - MCHBAR32(IOSAV_0_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = - (slotrank << 24) | (6 << 16); - MCHBAR32(IOSAV_0_ADDR_UPD_C0 + 0x400 * channel) = 0x244; + MCHBAR32(IOSAV_y_SP_CMD_CTL_Cx(channel, 0)) = 0x1f006; + MCHBAR32(IOSAV_y_SUBSEQ_CTL_Cx(channel, 0)) = + (MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD) << 10) | 4 | (ctrl->tRCD << 16); + MCHBAR32(IOSAV_y_SP_CMD_ADDR_Cx(channel, 0)) = (slotrank << 24) | (6 << 16); + MCHBAR32(IOSAV_y_ADDR_UPD_Cx(channel, 0)) = 0x244; /* DRAM command NOP */ - MCHBAR32(IOSAV_1_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f207; - MCHBAR32(IOSAV_1_SUBSEQ_CTL_C0 + 0x400 * channel) = 0x8041001; - MCHBAR32(IOSAV_1_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = (slotrank << 24) | 8; - MCHBAR32(IOSAV_1_ADDR_UPD_C0 + 0x400 * channel) = 0x3e0; + MCHBAR32(IOSAV_y_SP_CMD_CTL_Cx(channel, 1)) = 0x1f207; + MCHBAR32(IOSAV_y_SUBSEQ_CTL_Cx(channel, 1)) = 0x8041001; + MCHBAR32(IOSAV_y_SP_CMD_ADDR_Cx(channel, 1)) = (slotrank << 24) | 8; + MCHBAR32(IOSAV_y_ADDR_UPD_Cx(channel, 1)) = 0x3e0; /* DRAM command WR */ - MCHBAR32(IOSAV_2_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f201; - MCHBAR32(IOSAV_2_SUBSEQ_CTL_C0 + 0x400 * channel) = 0x80411f4; - MCHBAR32(IOSAV_2_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = slotrank << 24; - MCHBAR32(IOSAV_2_ADDR_UPD_C0 + 0x400 * channel) = 0x242; + MCHBAR32(IOSAV_y_SP_CMD_CTL_Cx(channel, 2)) = 0x1f201; + MCHBAR32(IOSAV_y_SUBSEQ_CTL_Cx(channel, 2)) = 0x80411f4; + MCHBAR32(IOSAV_y_SP_CMD_ADDR_Cx(channel, 2)) = slotrank << 24; + MCHBAR32(IOSAV_y_ADDR_UPD_Cx(channel, 2)) = 0x242; /* DRAM command NOP */ - MCHBAR32(IOSAV_3_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f207; - MCHBAR32(IOSAV_3_SUBSEQ_CTL_C0 + 0x400 * channel) = + MCHBAR32(IOSAV_y_SP_CMD_CTL_Cx(channel, 3)) = 0x1f207; + MCHBAR32(IOSAV_y_SUBSEQ_CTL_Cx(channel, 3)) = 0x8000c01 | ((ctrl->CWL + ctrl->tWTR + 5) << 16); - MCHBAR32(IOSAV_3_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = (slotrank << 24) | 8; - MCHBAR32(IOSAV_3_ADDR_UPD_C0 + 0x400 * channel) = 0x3e0; + MCHBAR32(IOSAV_y_SP_CMD_ADDR_Cx(channel, 3)) = (slotrank << 24) | 8; + MCHBAR32(IOSAV_y_ADDR_UPD_Cx(channel, 3)) = 0x3e0; // execute command queue - MCHBAR32(IOSAV_SEQ_CTL_C0 + 0x400 * channel) = RUN_QUEUE_4284(4); + MCHBAR32(IOSAV_SEQ_CTL_Cx(channel)) = RUN_QUEUE_4284(4); wait_428c(channel); /* DRAM command PREA */ - MCHBAR32(IOSAV_0_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f002; - MCHBAR32(IOSAV_0_SUBSEQ_CTL_C0 + 0x400 * channel) = 0xc01 | (ctrl->tRP << 16); - MCHBAR32(IOSAV_0_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = - (slotrank << 24) | 0x60400; - MCHBAR32(IOSAV_0_ADDR_UPD_C0 + 0x400 * channel) = 0x240; + MCHBAR32(IOSAV_y_SP_CMD_CTL_Cx(channel, 0)) = 0x1f002; + MCHBAR32(IOSAV_y_SUBSEQ_CTL_Cx(channel, 0)) = 0xc01 | (ctrl->tRP << 16); + MCHBAR32(IOSAV_y_SP_CMD_ADDR_Cx(channel, 0)) = (slotrank << 24) | 0x60400; + MCHBAR32(IOSAV_y_ADDR_UPD_Cx(channel, 0)) = 0x240; /* DRAM command ACT */ - MCHBAR32(IOSAV_1_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f006; - MCHBAR32(IOSAV_1_SUBSEQ_CTL_C0 + 0x400 * channel) = - (MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1) << 10) - | 8 | (ctrl->CAS << 16); - MCHBAR32(IOSAV_1_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = - (slotrank << 24) | 0x60000; - MCHBAR32(IOSAV_1_ADDR_UPD_C0 + 0x400 * channel) = 0x244; + MCHBAR32(IOSAV_y_SP_CMD_CTL_Cx(channel, 1)) = 0x1f006; + MCHBAR32(IOSAV_y_SUBSEQ_CTL_Cx(channel, 1)) = + (MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1) << 10) | 8 | (ctrl->CAS << 16); + MCHBAR32(IOSAV_y_SP_CMD_ADDR_Cx(channel, 1)) = (slotrank << 24) | 0x60000; + MCHBAR32(IOSAV_y_ADDR_UPD_Cx(channel, 1)) = 0x244; /* DRAM command RD */ - MCHBAR32(IOSAV_2_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f105; - MCHBAR32(IOSAV_2_SUBSEQ_CTL_C0 + 0x400 * channel) = - 0x40011f4 | (MAX(ctrl->tRTP, 8) << 16); - MCHBAR32(IOSAV_2_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = (slotrank << 24); - MCHBAR32(IOSAV_2_ADDR_UPD_C0 + 0x400 * channel) = 0x242; + MCHBAR32(IOSAV_y_SP_CMD_CTL_Cx(channel, 2)) = 0x1f105; + MCHBAR32(IOSAV_y_SUBSEQ_CTL_Cx(channel, 2)) = 0x40011f4 | (MAX(ctrl->tRTP, 8) << 16); + MCHBAR32(IOSAV_y_SP_CMD_ADDR_Cx(channel, 2)) = (slotrank << 24); + MCHBAR32(IOSAV_y_ADDR_UPD_Cx(channel, 2)) = 0x242; /* DRAM command PREA */ - MCHBAR32(IOSAV_3_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f002; - MCHBAR32(IOSAV_3_SUBSEQ_CTL_C0 + 0x400 * channel) = 0xc01 | (ctrl->tRP << 16); - MCHBAR32(IOSAV_3_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = - (slotrank << 24) | 0x60400; - MCHBAR32(IOSAV_3_ADDR_UPD_C0 + 0x400 * channel) = 0x240; + MCHBAR32(IOSAV_y_SP_CMD_CTL_Cx(channel, 3)) = 0x1f002; + MCHBAR32(IOSAV_y_SUBSEQ_CTL_Cx(channel, 3)) = 0xc01 | (ctrl->tRP << 16); + MCHBAR32(IOSAV_y_SP_CMD_ADDR_Cx(channel, 3)) = (slotrank << 24) | 0x60400; + MCHBAR32(IOSAV_y_ADDR_UPD_Cx(channel, 3)) = 0x240; // execute command queue - MCHBAR32(IOSAV_SEQ_CTL_C0 + 0x400 * channel) = RUN_QUEUE_4284(4); + MCHBAR32(IOSAV_SEQ_CTL_Cx(channel)) = RUN_QUEUE_4284(4); wait_428c(channel); } @@ -1560,14 +1547,13 @@ wait_428c(channel); /* DRAM command PREA */ - MCHBAR32(IOSAV_0_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f002; - MCHBAR32(IOSAV_0_SUBSEQ_CTL_C0 + 0x400 * channel) = 0xc01 | (ctrl->tRP << 16); - MCHBAR32(IOSAV_0_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = - (slotrank << 24) | 0x60400; - MCHBAR32(IOSAV_0_ADDR_UPD_C0 + 0x400 * channel) = 0x240; + MCHBAR32(IOSAV_y_SP_CMD_CTL_Cx(channel, 0)) = 0x1f002; + MCHBAR32(IOSAV_y_SUBSEQ_CTL_Cx(channel, 0)) = 0xc01 | (ctrl->tRP << 16); + MCHBAR32(IOSAV_y_SP_CMD_ADDR_Cx(channel, 0)) = (slotrank << 24) | 0x60400; + MCHBAR32(IOSAV_y_ADDR_UPD_Cx(channel, 0)) = 0x240; // execute command queue - MCHBAR32(IOSAV_SEQ_CTL_C0 + 0x400 * channel) = RUN_QUEUE_4284(1); + MCHBAR32(IOSAV_SEQ_CTL_Cx(channel)) = RUN_QUEUE_4284(1); for (timC = 0; timC <= MAX_TIMC; timC++) { FOR_ALL_LANES ctrl->timings[channel][slotrank].lanes[lane]. @@ -1578,7 +1564,7 @@ FOR_ALL_LANES { statistics[lane][timC] = - MCHBAR32(IOSAV_B0_ERROR_COUNT_C0 + 4 * lane + 0x400 * channel); + MCHBAR32(IOSAV_By_ERROR_COUNT_Cx(channel, lane)); } } FOR_ALL_LANES { @@ -1667,39 +1653,38 @@ * write MR3 MPR enable * in this mode only RD and RDA are allowed * all reads return a predefined pattern */ - MCHBAR32(IOSAV_0_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f000; - MCHBAR32(IOSAV_0_SUBSEQ_CTL_C0 + 0x400 * channel) = + MCHBAR32(IOSAV_y_SP_CMD_CTL_Cx(channel, 0)) = 0x1f000; + MCHBAR32(IOSAV_y_SUBSEQ_CTL_Cx(channel, 0)) = 0xc01 | (ctrl->tMOD << 16); - MCHBAR32(IOSAV_0_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = + MCHBAR32(IOSAV_y_SP_CMD_ADDR_Cx(channel, 0)) = (slotrank << 24) | 0x360004; - MCHBAR32(IOSAV_0_ADDR_UPD_C0 + 0x400 * channel) = 0; + MCHBAR32(IOSAV_y_ADDR_UPD_Cx(channel, 0)) = 0; /* DRAM command RD */ - MCHBAR32(IOSAV_1_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f105; - MCHBAR32(IOSAV_1_SUBSEQ_CTL_C0 + 0x400 * channel) = 0x4041003; - MCHBAR32(IOSAV_1_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = - (slotrank << 24) | 0; - MCHBAR32(IOSAV_1_ADDR_UPD_C0 + 0x400 * channel) = 0; + MCHBAR32(IOSAV_y_SP_CMD_CTL_Cx(channel, 1)) = 0x1f105; + MCHBAR32(IOSAV_y_SUBSEQ_CTL_Cx(channel, 1)) = 0x4041003; + MCHBAR32(IOSAV_y_SP_CMD_ADDR_Cx(channel, 1)) = (slotrank << 24) | 0; + MCHBAR32(IOSAV_y_ADDR_UPD_Cx(channel, 1)) = 0; /* DRAM command RD */ - MCHBAR32(IOSAV_2_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f105; - MCHBAR32(IOSAV_2_SUBSEQ_CTL_C0 + 0x400 * channel) = + MCHBAR32(IOSAV_y_SP_CMD_CTL_Cx(channel, 2)) = 0x1f105; + MCHBAR32(IOSAV_y_SUBSEQ_CTL_Cx(channel, 2)) = 0x1001 | ((ctrl->CAS + 8) << 16); - MCHBAR32(IOSAV_2_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = + MCHBAR32(IOSAV_y_SP_CMD_ADDR_Cx(channel, 2)) = (slotrank << 24) | 0x60000; - MCHBAR32(IOSAV_2_ADDR_UPD_C0 + 0x400 * channel) = 0; + MCHBAR32(IOSAV_y_ADDR_UPD_Cx(channel, 2)) = 0; /* DRAM command MRS * write MR3 MPR disable */ - MCHBAR32(IOSAV_3_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f000; - MCHBAR32(IOSAV_3_SUBSEQ_CTL_C0 + 0x400 * channel) = + MCHBAR32(IOSAV_y_SP_CMD_CTL_Cx(channel, 3)) = 0x1f000; + MCHBAR32(IOSAV_y_SUBSEQ_CTL_Cx(channel, 3)) = 0xc01 | (ctrl->tMOD << 16); - MCHBAR32(IOSAV_3_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = + MCHBAR32(IOSAV_y_SP_CMD_ADDR_Cx(channel, 3)) = (slotrank << 24) | 0x360000; - MCHBAR32(IOSAV_3_ADDR_UPD_C0 + 0x400 * channel) = 0; + MCHBAR32(IOSAV_y_ADDR_UPD_Cx(channel, 3)) = 0; // execute command queue - MCHBAR32(IOSAV_SEQ_CTL_C0 + 0x400 * channel) = RUN_QUEUE_4284(4); + MCHBAR32(IOSAV_SEQ_CTL_Cx(channel)) = RUN_QUEUE_4284(4); wait_428c(channel); } @@ -1719,39 +1704,38 @@ * write MR3 MPR enable * in this mode only RD and RDA are allowed * all reads return a predefined pattern */ - MCHBAR32(IOSAV_0_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f000; - MCHBAR32(IOSAV_0_SUBSEQ_CTL_C0 + 0x400 * channel) = + MCHBAR32(IOSAV_y_SP_CMD_CTL_Cx(channel, 0)) = 0x1f000; + MCHBAR32(IOSAV_y_SUBSEQ_CTL_Cx(channel, 0)) = 0xc01 | (ctrl->tMOD << 16); - MCHBAR32(IOSAV_0_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = + MCHBAR32(IOSAV_y_SP_CMD_ADDR_Cx(channel, 0)) = (slotrank << 24) | 0x360004; - MCHBAR32(IOSAV_0_ADDR_UPD_C0 + 0x400 * channel) = 0; + MCHBAR32(IOSAV_y_ADDR_UPD_Cx(channel, 0)) = 0; /* DRAM command RD */ - MCHBAR32(IOSAV_1_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f105; - MCHBAR32(IOSAV_1_SUBSEQ_CTL_C0 + 0x400 * channel) = 0x4041003; - MCHBAR32(IOSAV_1_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = - (slotrank << 24) | 0; - MCHBAR32(IOSAV_1_ADDR_UPD_C0 + 0x400 * channel) = 0; + MCHBAR32(IOSAV_y_SP_CMD_CTL_Cx(channel, 1)) = 0x1f105; + MCHBAR32(IOSAV_y_SUBSEQ_CTL_Cx(channel, 1)) = 0x4041003; + MCHBAR32(IOSAV_y_SP_CMD_ADDR_Cx(channel, 1)) = (slotrank << 24) | 0; + MCHBAR32(IOSAV_y_ADDR_UPD_Cx(channel, 1)) = 0; /* DRAM command RD */ - MCHBAR32(IOSAV_2_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f105; - MCHBAR32(IOSAV_2_SUBSEQ_CTL_C0 + 0x400 * channel) = + MCHBAR32(IOSAV_y_SP_CMD_CTL_Cx(channel, 2)) = 0x1f105; + MCHBAR32(IOSAV_y_SUBSEQ_CTL_Cx(channel, 2)) = 0x1001 | ((ctrl->CAS + 8) << 16); - MCHBAR32(IOSAV_2_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = + MCHBAR32(IOSAV_y_SP_CMD_ADDR_Cx(channel, 2)) = (slotrank << 24) | 0x60000; - MCHBAR32(IOSAV_2_ADDR_UPD_C0 + 0x400 * channel) = 0; + MCHBAR32(IOSAV_y_ADDR_UPD_Cx(channel, 2)) = 0; /* DRAM command MRS * write MR3 MPR disable */ - MCHBAR32(IOSAV_3_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f000; - MCHBAR32(IOSAV_3_SUBSEQ_CTL_C0 + 0x400 * channel) = + MCHBAR32(IOSAV_y_SP_CMD_CTL_Cx(channel, 3)) = 0x1f000; + MCHBAR32(IOSAV_y_SUBSEQ_CTL_Cx(channel, 3)) = 0xc01 | (ctrl->tMOD << 16); - MCHBAR32(IOSAV_3_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = + MCHBAR32(IOSAV_y_SP_CMD_ADDR_Cx(channel, 3)) = (slotrank << 24) | 0x360000; - MCHBAR32(IOSAV_3_ADDR_UPD_C0 + 0x400 * channel) = 0; + MCHBAR32(IOSAV_y_ADDR_UPD_Cx(channel, 3)) = 0; // execute command queue - MCHBAR32(IOSAV_SEQ_CTL_C0 + 0x400 * channel) = RUN_QUEUE_4284(4); + MCHBAR32(IOSAV_SEQ_CTL_Cx(channel)) = RUN_QUEUE_4284(4); wait_428c(channel); } @@ -1766,21 +1750,20 @@ wait_428c(channel); /* DRAM command NOP */ - MCHBAR32(IOSAV_0_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f207; - MCHBAR32(IOSAV_0_SUBSEQ_CTL_C0 + 0x400 * channel) = + MCHBAR32(IOSAV_y_SP_CMD_CTL_Cx(channel, 0)) = 0x1f207; + MCHBAR32(IOSAV_y_SUBSEQ_CTL_Cx(channel, 0)) = 0x8000c01 | ((ctrl->CWL + ctrl->tWLO) << 16); - MCHBAR32(IOSAV_0_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = 8 | (slotrank << 24); - MCHBAR32(IOSAV_0_ADDR_UPD_C0 + 0x400 * channel) = 0; + MCHBAR32(IOSAV_y_SP_CMD_ADDR_Cx(channel, 0)) = 8 | (slotrank << 24); + MCHBAR32(IOSAV_y_ADDR_UPD_Cx(channel, 0)) = 0; /* DRAM command NOP */ - MCHBAR32(IOSAV_1_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f107; - MCHBAR32(IOSAV_1_SUBSEQ_CTL_C0 + 0x400 * channel) = - 0x4000c01 | ((ctrl->CAS + 38) << 16); - MCHBAR32(IOSAV_1_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = (slotrank << 24) | 4; - MCHBAR32(IOSAV_1_ADDR_UPD_C0 + 0x400 * channel) = 0; + MCHBAR32(IOSAV_y_SP_CMD_CTL_Cx(channel, 1)) = 0x1f107; + MCHBAR32(IOSAV_y_SUBSEQ_CTL_Cx(channel, 1)) = 0x4000c01 | ((ctrl->CAS + 38) << 16); + MCHBAR32(IOSAV_y_SP_CMD_ADDR_Cx(channel, 1)) = (slotrank << 24) | 4; + MCHBAR32(IOSAV_y_ADDR_UPD_Cx(channel, 1)) = 0; // execute command queue - MCHBAR32(0x400 * channel + IOSAV_SEQ_CTL_C0) = RUN_QUEUE_4284(2); + MCHBAR32(IOSAV_SEQ_CTL_Cx(channel)) = RUN_QUEUE_4284(2); wait_428c(channel); @@ -1867,74 +1850,66 @@ MCHBAR32(GDCRTRAININGMOD) = 0x200; FOR_ALL_POPULATED_CHANNELS { fill_pattern1(ctrl, channel); - MCHBAR32(IOSAV_DATA_CTL_C0 + (channel << 10)) = 1; + MCHBAR32(IOSAV_DATA_CTL_Cx(channel)) = 1; } FOR_ALL_POPULATED_CHANNELS FOR_ALL_POPULATED_RANKS { - MCHBAR32(IOSAV_DATA_CTL_C0 + 0x400 * channel) = 0x10001; + MCHBAR32(IOSAV_DATA_CTL_Cx(channel)) = 0x10001; wait_428c(channel); /* DRAM command ACT */ - MCHBAR32(IOSAV_0_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f006; - MCHBAR32(IOSAV_0_SUBSEQ_CTL_C0 + 0x400 * channel) = 0xc01 | (ctrl->tRCD << 16); - MCHBAR32(IOSAV_0_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = - (slotrank << 24) | 0x60000; - MCHBAR32(IOSAV_0_ADDR_UPD_C0 + 0x400 * channel) = 0; + MCHBAR32(IOSAV_y_SP_CMD_CTL_Cx(channel, 0)) = 0x1f006; + MCHBAR32(IOSAV_y_SUBSEQ_CTL_Cx(channel, 0)) = 0xc01 | (ctrl->tRCD << 16); + MCHBAR32(IOSAV_y_SP_CMD_ADDR_Cx(channel, 0)) = (slotrank << 24) | 0x60000; + MCHBAR32(IOSAV_y_ADDR_UPD_Cx(channel, 0)) = 0; /* DRAM command NOP */ - MCHBAR32(IOSAV_1_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f207; - MCHBAR32(IOSAV_1_SUBSEQ_CTL_C0 + 0x400 * channel) = 0x8040c01; - MCHBAR32(IOSAV_1_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = - (slotrank << 24) | 0x8; - MCHBAR32(IOSAV_1_ADDR_UPD_C0 + 0x400 * channel) = 0x3e0; + MCHBAR32(IOSAV_y_SP_CMD_CTL_Cx(channel, 1)) = 0x1f207; + MCHBAR32(IOSAV_y_SUBSEQ_CTL_Cx(channel, 1)) = 0x8040c01; + MCHBAR32(IOSAV_y_SP_CMD_ADDR_Cx(channel, 1)) = (slotrank << 24) | 0x8; + MCHBAR32(IOSAV_y_ADDR_UPD_Cx(channel, 1)) = 0x3e0; /* DRAM command WR */ - MCHBAR32(IOSAV_2_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f201; - MCHBAR32(IOSAV_2_SUBSEQ_CTL_C0 + 0x400 * channel) = 0x8041003; - MCHBAR32(IOSAV_2_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = (slotrank << 24); - MCHBAR32(IOSAV_2_ADDR_UPD_C0 + 0x400 * channel) = 0x3e2; + MCHBAR32(IOSAV_y_SP_CMD_CTL_Cx(channel, 2)) = 0x1f201; + MCHBAR32(IOSAV_y_SUBSEQ_CTL_Cx(channel, 2)) = 0x8041003; + MCHBAR32(IOSAV_y_SP_CMD_ADDR_Cx(channel, 2)) = (slotrank << 24); + MCHBAR32(IOSAV_y_ADDR_UPD_Cx(channel, 2)) = 0x3e2; /* DRAM command NOP */ - MCHBAR32(IOSAV_3_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f207; - MCHBAR32(IOSAV_3_SUBSEQ_CTL_C0 + 0x400 * channel) = + MCHBAR32(IOSAV_y_SP_CMD_CTL_Cx(channel, 3)) = 0x1f207; + MCHBAR32(IOSAV_y_SUBSEQ_CTL_Cx(channel, 3)) = 0x8000c01 | ((ctrl->CWL + ctrl->tWTR + 5) << 16); - MCHBAR32(IOSAV_3_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = - (slotrank << 24) | 0x8; - MCHBAR32(IOSAV_3_ADDR_UPD_C0 + 0x400 * channel) = 0x3e0; + MCHBAR32(IOSAV_y_SP_CMD_ADDR_Cx(channel, 3)) = (slotrank << 24) | 0x8; + MCHBAR32(IOSAV_y_ADDR_UPD_Cx(channel, 3)) = 0x3e0; // execute command queue - MCHBAR32(IOSAV_SEQ_CTL_C0 + 0x400 * channel) = RUN_QUEUE_4284(4); + MCHBAR32(IOSAV_SEQ_CTL_Cx(channel)) = RUN_QUEUE_4284(4); wait_428c(channel); /* DRAM command PREA */ - MCHBAR32(IOSAV_0_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f002; - MCHBAR32(IOSAV_0_SUBSEQ_CTL_C0 + 0x400 * channel) = - 0xc01 | ((ctrl->tRP) << 16); - MCHBAR32(IOSAV_0_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = - (slotrank << 24) | 0x60400; - MCHBAR32(IOSAV_0_ADDR_UPD_C0 + 0x400 * channel) = 0x240; + MCHBAR32(IOSAV_y_SP_CMD_CTL_Cx(channel, 0)) = 0x1f002; + MCHBAR32(IOSAV_y_SUBSEQ_CTL_Cx(channel, 0)) = 0xc01 | ((ctrl->tRP) << 16); + MCHBAR32(IOSAV_y_SP_CMD_ADDR_Cx(channel, 0)) = (slotrank << 24) | 0x60400; + MCHBAR32(IOSAV_y_ADDR_UPD_Cx(channel, 0)) = 0x240; /* DRAM command ACT */ - MCHBAR32(IOSAV_1_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f006; - MCHBAR32(IOSAV_1_SUBSEQ_CTL_C0 + 0x400 * channel) = - 0xc01 | ((ctrl->tRCD) << 16); - MCHBAR32(IOSAV_1_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = - (slotrank << 24) | 0x60000; - MCHBAR32(IOSAV_1_ADDR_UPD_C0 + 0x400 * channel) = 0; + MCHBAR32(IOSAV_y_SP_CMD_CTL_Cx(channel, 1)) = 0x1f006; + MCHBAR32(IOSAV_y_SUBSEQ_CTL_Cx(channel, 1)) = 0xc01 | ((ctrl->tRCD) << 16); + MCHBAR32(IOSAV_y_SP_CMD_ADDR_Cx(channel, 1)) = (slotrank << 24) | 0x60000; + MCHBAR32(IOSAV_y_ADDR_UPD_Cx(channel, 1)) = 0; /* DRAM command RD */ - MCHBAR32(IOSAV_2_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x3f105; - MCHBAR32(IOSAV_2_SUBSEQ_CTL_C0 + 0x400 * channel) = 0x4000c01 | ((ctrl->tRP + + MCHBAR32(IOSAV_y_SP_CMD_CTL_Cx(channel, 2)) = 0x3f105; + MCHBAR32(IOSAV_y_SUBSEQ_CTL_Cx(channel, 2)) = 0x4000c01 | ((ctrl->tRP + ctrl->timings[channel][slotrank].val_4024 + ctrl->timings[channel][slotrank].val_4028) << 16); - MCHBAR32(IOSAV_2_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = - (slotrank << 24) | 0x60008; - MCHBAR32(IOSAV_2_ADDR_UPD_C0 + 0x400 * channel) = 0; + MCHBAR32(IOSAV_y_SP_CMD_ADDR_Cx(channel, 2)) = (slotrank << 24) | 0x60008; + MCHBAR32(IOSAV_y_ADDR_UPD_Cx(channel, 2)) = 0; // execute command queue - MCHBAR32(IOSAV_SEQ_CTL_C0 + 0x400 * channel) = RUN_QUEUE_4284(3); + MCHBAR32(IOSAV_SEQ_CTL_Cx(channel)) = RUN_QUEUE_4284(3); wait_428c(channel); FOR_ALL_LANES { @@ -1966,14 +1941,13 @@ slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; /* DRAM command ACT */ - MCHBAR32(IOSAV_0_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x0f003; - MCHBAR32(IOSAV_0_SUBSEQ_CTL_C0 + 0x400 * channel) = 0x41001; - MCHBAR32(IOSAV_0_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = - (slotrank << 24) | 0x60000; - MCHBAR32(IOSAV_0_ADDR_UPD_C0 + 0x400 * channel) = 0x3e0; + MCHBAR32(IOSAV_y_SP_CMD_CTL_Cx(channel, 0)) = 0x0f003; + MCHBAR32(IOSAV_y_SUBSEQ_CTL_Cx(channel, 0)) = 0x41001; + MCHBAR32(IOSAV_y_SP_CMD_ADDR_Cx(channel, 0)) = (slotrank << 24) | 0x60000; + MCHBAR32(IOSAV_y_ADDR_UPD_Cx(channel, 0)) = 0x3e0; // execute command queue - MCHBAR32(IOSAV_SEQ_CTL_C0 + 0x400 * channel) = RUN_QUEUE_4284(1); + MCHBAR32(IOSAV_SEQ_CTL_Cx(channel)) = RUN_QUEUE_4284(1); wait_428c(channel); } @@ -1996,11 +1970,11 @@ int err; FOR_ALL_POPULATED_CHANNELS - MCHBAR32_OR(TC_RWP_C0 + 0x400 * channel, 0x8000000); + MCHBAR32_OR(TC_RWP_Cx(channel), 0x8000000); FOR_ALL_POPULATED_CHANNELS { write_op(ctrl, channel); - MCHBAR32_OR(SCHED_CBIT_C0 + 0x400 * channel, 0x200000); + MCHBAR32_OR(SCHED_CBIT_Cx(channel), 0x200000); } /* refresh disable */ @@ -2042,18 +2016,18 @@ MCHBAR32_OR(MC_INIT_STATE_G, 8); FOR_ALL_POPULATED_CHANNELS { - MCHBAR32_AND(SCHED_CBIT_C0 + 0x400 * channel, ~0x00200000); - MCHBAR32(IOSAV_STATUS_C0 + 0x400 * channel); + MCHBAR32_AND(SCHED_CBIT_Cx(channel), ~0x00200000); + MCHBAR32(IOSAV_STATUS_Cx(channel)); wait_428c(channel); /* DRAM command ZQCS */ - MCHBAR32(IOSAV_0_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x0f003; - MCHBAR32(IOSAV_0_SUBSEQ_CTL_C0 + 0x400 * channel) = 0x659001; - MCHBAR32(IOSAV_0_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = 0x60000; - MCHBAR32(IOSAV_0_ADDR_UPD_C0 + 0x400 * channel) = 0x3e0; + MCHBAR32(IOSAV_y_SP_CMD_CTL_Cx(channel, 0)) = 0x0f003; + MCHBAR32(IOSAV_y_SUBSEQ_CTL_Cx(channel, 0)) = 0x659001; + MCHBAR32(IOSAV_y_SP_CMD_ADDR_Cx(channel, 0)) = 0x60000; + MCHBAR32(IOSAV_y_ADDR_UPD_Cx(channel, 0)) = 0x3e0; // execute command queue - MCHBAR32(IOSAV_SEQ_CTL_C0 + 0x400 * channel) = RUN_QUEUE_4284(1); + MCHBAR32(IOSAV_SEQ_CTL_Cx(channel)) = RUN_QUEUE_4284(1); wait_428c(channel); } @@ -2065,12 +2039,12 @@ printram("CPF\n"); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - MCHBAR32_AND(IOSAV_B0_BW_MASK_C0 + 0x400 * channel + 4 * lane, 0); + MCHBAR32_AND(IOSAV_By_BW_MASK_Cx(channel, lane), 0); } FOR_ALL_POPULATED_CHANNELS { fill_pattern0(ctrl, channel, 0xaaaaaaaa, 0x55555555); - MCHBAR32(IOSAV_DATA_CTL_C0 + (channel << 10)) = 0; + MCHBAR32(IOSAV_DATA_CTL_Cx(channel)) = 0; } FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { @@ -2089,7 +2063,7 @@ program_timings(ctrl, channel); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - MCHBAR32_AND(IOSAV_B0_BW_MASK_C0 + 0x400 * channel + 4 * lane, 0); + MCHBAR32_AND(IOSAV_By_BW_MASK_Cx(channel, lane), 0); } return 0; } @@ -2109,51 +2083,49 @@ } program_timings(ctrl, channel); FOR_ALL_LANES { - MCHBAR32(4 * lane + IOSAV_B0_ERROR_COUNT) = 0; + MCHBAR32(IOSAV_By_ERROR_COUNT(lane)) = 0; } - MCHBAR32(IOSAV_DATA_CTL_C0 + 0x400 * channel) = 0x1f; + MCHBAR32(IOSAV_DATA_CTL_Cx(channel)) = 0x1f; wait_428c(channel); + /* DRAM command ACT */ - MCHBAR32(IOSAV_0_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f006; - MCHBAR32(IOSAV_0_SUBSEQ_CTL_C0 + 0x400 * channel) = + MCHBAR32(IOSAV_y_SP_CMD_CTL_Cx(channel, 0)) = 0x1f006; + MCHBAR32(IOSAV_y_SUBSEQ_CTL_Cx(channel, 0)) = ((MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1)) << 10) | 8 | (ctrl->tRCD << 16); - MCHBAR32(IOSAV_0_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = - (slotrank << 24) | ctr | 0x60000; - MCHBAR32(IOSAV_0_ADDR_UPD_C0 + 0x400 * channel) = 0x244; + MCHBAR32(IOSAV_y_SP_CMD_ADDR_Cx(channel, 0)) = (slotrank << 24) | ctr | 0x60000; + MCHBAR32(IOSAV_y_ADDR_UPD_Cx(channel, 0)) = 0x244; /* DRAM command WR */ - MCHBAR32(IOSAV_1_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f201; - MCHBAR32(IOSAV_1_SUBSEQ_CTL_C0 + 0x400 * channel) = + MCHBAR32(IOSAV_y_SP_CMD_CTL_Cx(channel, 1)) = 0x1f201; + MCHBAR32(IOSAV_y_SUBSEQ_CTL_Cx(channel, 1)) = 0x8001020 | ((ctrl->CWL + ctrl->tWTR + 8) << 16); - MCHBAR32(IOSAV_1_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = (slotrank << 24); - MCHBAR32(IOSAV_1_ADDRESS_LFSR_C0 + 0x400 * channel) = 0x389abcd; - MCHBAR32(IOSAV_1_ADDR_UPD_C0 + 0x400 * channel) = 0x20e42; + MCHBAR32(IOSAV_y_SP_CMD_ADDR_Cx(channel, 1)) = (slotrank << 24); + MCHBAR32(IOSAV_y_ADDRESS_LFSR_Cx(channel, 1)) = 0x389abcd; + MCHBAR32(IOSAV_y_ADDR_UPD_Cx(channel, 1)) = 0x20e42; /* DRAM command RD */ - MCHBAR32(IOSAV_2_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f105; - MCHBAR32(IOSAV_2_SUBSEQ_CTL_C0 + 0x400 * channel) = + MCHBAR32(IOSAV_y_SP_CMD_CTL_Cx(channel, 2)) = 0x1f105; + MCHBAR32(IOSAV_y_SUBSEQ_CTL_Cx(channel, 2)) = 0x4001020 | (MAX(ctrl->tRTP, 8) << 16); - MCHBAR32(IOSAV_2_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = (slotrank << 24); - MCHBAR32(IOSAV_2_ADDRESS_LFSR_C0 + 0x400 * channel) = 0x389abcd; - MCHBAR32(IOSAV_2_ADDR_UPD_C0 + 0x400 * channel) = 0x20e42; + MCHBAR32(IOSAV_y_SP_CMD_ADDR_Cx(channel, 2)) = (slotrank << 24); + MCHBAR32(IOSAV_y_ADDRESS_LFSR_Cx(channel, 2)) = 0x389abcd; + MCHBAR32(IOSAV_y_ADDR_UPD_Cx(channel, 2)) = 0x20e42; /* DRAM command PRE */ - MCHBAR32(IOSAV_3_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f002; - MCHBAR32(IOSAV_3_SUBSEQ_CTL_C0 + 0x400 * channel) = 0xf1001; - MCHBAR32(IOSAV_3_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = - (slotrank << 24) | 0x60400; - MCHBAR32(IOSAV_3_ADDR_UPD_C0 + 0x400 * channel) = 0x240; + MCHBAR32(IOSAV_y_SP_CMD_CTL_Cx(channel, 3)) = 0x1f002; + MCHBAR32(IOSAV_y_SUBSEQ_CTL_Cx(channel, 3)) = 0xf1001; + MCHBAR32(IOSAV_y_SP_CMD_ADDR_Cx(channel, 3)) = (slotrank << 24) | 0x60400; + MCHBAR32(IOSAV_y_ADDR_UPD_Cx(channel, 3)) = 0x240; // execute command queue - MCHBAR32(IOSAV_SEQ_CTL_C0 + 0x400 * channel) = RUN_QUEUE_4284(4); + MCHBAR32(IOSAV_SEQ_CTL_Cx(channel)) = RUN_QUEUE_4284(4); wait_428c(channel); FOR_ALL_LANES { - u32 r32 = - MCHBAR32(IOSAV_B0_ERROR_COUNT_C0 + 4 * lane + 0x400 * channel); + u32 r32 = MCHBAR32(IOSAV_By_ERROR_COUNT_Cx(channel, lane)); if (r32 == 0) lanes_ok |= 1 << lane; @@ -2211,17 +2183,16 @@ slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; /* DRAM command ZQCS */ - MCHBAR32(IOSAV_0_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x0f003; - MCHBAR32(IOSAV_0_SUBSEQ_CTL_C0 + 0x400 * channel) = 0x41001; - MCHBAR32(IOSAV_0_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = - (slotrank << 24) | 0x60000; - MCHBAR32(IOSAV_0_ADDR_UPD_C0 + 0x400 * channel) = 0x3e0; + MCHBAR32(IOSAV_y_SP_CMD_CTL_Cx(channel, 0)) = 0x0f003; + MCHBAR32(IOSAV_y_SUBSEQ_CTL_Cx(channel, 0)) = 0x41001; + MCHBAR32(IOSAV_y_SP_CMD_ADDR_Cx(channel, 0)) = (slotrank << 24) | 0x60000; + MCHBAR32(IOSAV_y_ADDR_UPD_Cx(channel, 0)) = 0x3e0; // execute command queue - MCHBAR32(IOSAV_SEQ_CTL_C0 + 0x400 * channel) = RUN_QUEUE_4284(1); + MCHBAR32(IOSAV_SEQ_CTL_Cx(channel)) = RUN_QUEUE_4284(1); wait_428c(channel); - MCHBAR32_OR(SCHED_CBIT_C0 + 0x400 * channel, 0x200000); + MCHBAR32_OR(SCHED_CBIT_Cx(channel), 0x200000); } /* refresh disable */ @@ -2233,14 +2204,13 @@ slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; /* DRAM command ZQCS */ - MCHBAR32(IOSAV_0_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x0f003; - MCHBAR32(IOSAV_0_SUBSEQ_CTL_C0 + 0x400 * channel) = 0x41001; - MCHBAR32(IOSAV_0_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = - (slotrank << 24) | 0x60000; - MCHBAR32(IOSAV_0_ADDR_UPD_C0 + 0x400 * channel) = 0x3e0; + MCHBAR32(IOSAV_y_SP_CMD_CTL_Cx(channel, 0)) = 0x0f003; + MCHBAR32(IOSAV_y_SUBSEQ_CTL_Cx(channel, 0)) = 0x41001; + MCHBAR32(IOSAV_y_SP_CMD_ADDR_Cx(channel, 0)) = (slotrank << 24) | 0x60000; + MCHBAR32(IOSAV_y_ADDR_UPD_Cx(channel, 0)) = 0x3e0; // execute command queue - MCHBAR32(IOSAV_SEQ_CTL_C0 + 0x400 * channel) = RUN_QUEUE_4284(1); + MCHBAR32(IOSAV_SEQ_CTL_Cx(channel)) = RUN_QUEUE_4284(1); wait_428c(channel); } @@ -2272,7 +2242,7 @@ ctrl->cmd_stretch[channel] = cmd_stretch; - MCHBAR32(TC_RAP_C0 + 0x400 * channel) = + MCHBAR32(TC_RAP_Cx(channel)) = ctrl->tRRD | (ctrl->tRTP << 4) | (ctrl->tCKE << 8) @@ -2328,7 +2298,7 @@ FOR_ALL_POPULATED_CHANNELS { fill_pattern5(ctrl, channel, 0); - MCHBAR32(IOSAV_DATA_CTL_C0 + 0x400 * channel) = 0x1f; + MCHBAR32(IOSAV_DATA_CTL_Cx(channel)) = 0x1f; } FOR_ALL_POPULATED_CHANNELS { @@ -2392,8 +2362,8 @@ program_timings(ctrl, channel); FOR_ALL_LANES { - MCHBAR32(IOSAV_B0_ERROR_COUNT_C0 + 0x400 * channel + 4 * lane) = 0; - MCHBAR32(0x400 * channel + 4 * lane + IOSAV_B0_BW_SERROR_C_C0); + MCHBAR32(IOSAV_By_ERROR_COUNT_Cx(channel, lane)) = 0; + MCHBAR32(IOSAV_By_BW_SERROR_C_Cx(channel, lane)); } wait_428c(channel); @@ -2401,42 +2371,38 @@ * write MR3 MPR enable * in this mode only RD and RDA are allowed * all reads return a predefined pattern */ - MCHBAR32(IOSAV_0_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f000; - MCHBAR32(IOSAV_0_SUBSEQ_CTL_C0 + 0x400 * channel) = 0xc01 | (ctrl->tMOD << 16); - MCHBAR32(IOSAV_0_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = - (slotrank << 24) | 0x360004; - MCHBAR32(IOSAV_0_ADDR_UPD_C0 + 0x400 * channel) = 0; + MCHBAR32(IOSAV_y_SP_CMD_CTL_Cx(channel, 0)) = 0x1f000; + MCHBAR32(IOSAV_y_SUBSEQ_CTL_Cx(channel, 0)) = 0xc01 | (ctrl->tMOD << 16); + MCHBAR32(IOSAV_y_SP_CMD_ADDR_Cx(channel, 0)) = (slotrank << 24) | 0x360004; + MCHBAR32(IOSAV_y_ADDR_UPD_Cx(channel, 0)) = 0; /* DRAM command RD */ - MCHBAR32(IOSAV_1_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f105; - MCHBAR32(IOSAV_1_SUBSEQ_CTL_C0 + 0x400 * channel) = 0x40411f4; - MCHBAR32(IOSAV_1_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = slotrank << 24; - MCHBAR32(IOSAV_1_ADDR_UPD_C0 + 0x400 * channel) = 0; + MCHBAR32(IOSAV_y_SP_CMD_CTL_Cx(channel, 1)) = 0x1f105; + MCHBAR32(IOSAV_y_SUBSEQ_CTL_Cx(channel, 1)) = 0x40411f4; + MCHBAR32(IOSAV_y_SP_CMD_ADDR_Cx(channel, 1)) = slotrank << 24; + MCHBAR32(IOSAV_y_ADDR_UPD_Cx(channel, 1)) = 0; /* DRAM command RD */ - MCHBAR32(IOSAV_2_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f105; - MCHBAR32(IOSAV_2_SUBSEQ_CTL_C0 + 0x400 * channel) = - 0x1001 | ((ctrl->CAS + 8) << 16); - MCHBAR32(IOSAV_2_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = - (slotrank << 24) | 0x60000; - MCHBAR32(IOSAV_2_ADDR_UPD_C0 + 0x400 * channel) = 0; + MCHBAR32(IOSAV_y_SP_CMD_CTL_Cx(channel, 2)) = 0x1f105; + MCHBAR32(IOSAV_y_SUBSEQ_CTL_Cx(channel, 2)) = 0x1001 | ((ctrl->CAS + 8) << 16); + MCHBAR32(IOSAV_y_SP_CMD_ADDR_Cx(channel, 2)) = (slotrank << 24) | 0x60000; + MCHBAR32(IOSAV_y_ADDR_UPD_Cx(channel, 2)) = 0; /* DRAM command MRS * MR3 disable MPR */ - MCHBAR32(IOSAV_3_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f000; - MCHBAR32(IOSAV_3_SUBSEQ_CTL_C0 + 0x400 * channel) = 0xc01 | (ctrl->tMOD << 16); - MCHBAR32(IOSAV_3_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = - (slotrank << 24) | 0x360000; - MCHBAR32(IOSAV_3_ADDR_UPD_C0 + 0x400 * channel) = 0; + MCHBAR32(IOSAV_y_SP_CMD_CTL_Cx(channel, 3)) = 0x1f000; + MCHBAR32(IOSAV_y_SUBSEQ_CTL_Cx(channel, 3)) = 0xc01 | (ctrl->tMOD << 16); + MCHBAR32(IOSAV_y_SP_CMD_ADDR_Cx(channel, 3)) = (slotrank << 24) | 0x360000; + MCHBAR32(IOSAV_y_ADDR_UPD_Cx(channel, 3)) = 0; // execute command queue - MCHBAR32(IOSAV_SEQ_CTL_C0 + 0x400 * channel) = RUN_QUEUE_4284(4); + MCHBAR32(IOSAV_SEQ_CTL_Cx(channel)) = RUN_QUEUE_4284(4); wait_428c(channel); FOR_ALL_LANES { statistics[lane][edge] = - MCHBAR32(IOSAV_B0_ERROR_COUNT_C0 + 0x400 * channel + lane * 4); + MCHBAR32(IOSAV_By_ERROR_COUNT_Cx(channel, lane)); } } FOR_ALL_LANES { @@ -2466,14 +2432,14 @@ toggle_io_reset(); FOR_ALL_POPULATED_CHANNELS FOR_ALL_LANES { - MCHBAR32(4 * lane + 0x400 * channel + IOSAV_B0_BW_MASK_C0) = 0; + MCHBAR32(IOSAV_By_BW_MASK_Cx(channel, lane)) = 0; } FOR_ALL_POPULATED_CHANNELS { fill_pattern0(ctrl, channel, 0, 0); - MCHBAR32(IOSAV_DATA_CTL_C0 + (channel << 10)) = 0; + MCHBAR32(IOSAV_DATA_CTL_Cx(channel)) = 0; FOR_ALL_LANES { - MCHBAR32(0x400 * channel + lane * 4 + IOSAV_B0_BW_SERROR_C_C0); + MCHBAR32(IOSAV_By_BW_SERROR_C_Cx(channel, lane)); } FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { @@ -2493,39 +2459,38 @@ * write MR3 MPR enable * in this mode only RD and RDA are allowed * all reads return a predefined pattern */ - MCHBAR32(IOSAV_0_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f000; - MCHBAR32(IOSAV_0_SUBSEQ_CTL_C0 + 0x400 * channel) = + MCHBAR32(IOSAV_y_SP_CMD_CTL_Cx(channel, 0)) = 0x1f000; + MCHBAR32(IOSAV_y_SUBSEQ_CTL_Cx(channel, 0)) = 0xc01 | (ctrl->tMOD << 16); - MCHBAR32(IOSAV_0_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = + MCHBAR32(IOSAV_y_SP_CMD_ADDR_Cx(channel, 0)) = (slotrank << 24) | 0x360004; - MCHBAR32(IOSAV_0_ADDR_UPD_C0 + 0x400 * channel) = 0; + MCHBAR32(IOSAV_y_ADDR_UPD_Cx(channel, 0)) = 0; /* DRAM command RD */ - MCHBAR32(IOSAV_1_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f105; - MCHBAR32(IOSAV_1_SUBSEQ_CTL_C0 + 0x400 * channel) = 0x4041003; - MCHBAR32(IOSAV_1_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = - (slotrank << 24) | 0; - MCHBAR32(IOSAV_1_ADDR_UPD_C0 + 0x400 * channel) = 0; + MCHBAR32(IOSAV_y_SP_CMD_CTL_Cx(channel, 1)) = 0x1f105; + MCHBAR32(IOSAV_y_SUBSEQ_CTL_Cx(channel, 1)) = 0x4041003; + MCHBAR32(IOSAV_y_SP_CMD_ADDR_Cx(channel, 1)) = (slotrank << 24) | 0; + MCHBAR32(IOSAV_y_ADDR_UPD_Cx(channel, 1)) = 0; /* DRAM command RD */ - MCHBAR32(IOSAV_2_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f105; - MCHBAR32(IOSAV_2_SUBSEQ_CTL_C0 + 0x400 * channel) = + MCHBAR32(IOSAV_y_SP_CMD_CTL_Cx(channel, 2)) = 0x1f105; + MCHBAR32(IOSAV_y_SUBSEQ_CTL_Cx(channel, 2)) = 0x1001 | ((ctrl->CAS + 8) << 16); - MCHBAR32(IOSAV_2_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = + MCHBAR32(IOSAV_y_SP_CMD_ADDR_Cx(channel, 2)) = (slotrank << 24) | 0x60000; - MCHBAR32(IOSAV_2_ADDR_UPD_C0 + 0x400 * channel) = 0; + MCHBAR32(IOSAV_y_ADDR_UPD_Cx(channel, 2)) = 0; /* DRAM command MRS * MR3 disable MPR */ - MCHBAR32(IOSAV_3_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f000; - MCHBAR32(IOSAV_3_SUBSEQ_CTL_C0 + 0x400 * channel) = + MCHBAR32(IOSAV_y_SP_CMD_CTL_Cx(channel, 3)) = 0x1f000; + MCHBAR32(IOSAV_y_SUBSEQ_CTL_Cx(channel, 3)) = 0xc01 | (ctrl->tMOD << 16); - MCHBAR32(IOSAV_3_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = + MCHBAR32(IOSAV_y_SP_CMD_ADDR_Cx(channel, 3)) = (slotrank << 24) | 0x360000; - MCHBAR32(IOSAV_3_ADDR_UPD_C0 + 0x400 * channel) = 0; + MCHBAR32(IOSAV_y_ADDR_UPD_Cx(channel, 3)) = 0; // execute command queue - MCHBAR32(IOSAV_SEQ_CTL_C0 + 0x400 * channel) = RUN_QUEUE_4284(4); + MCHBAR32(IOSAV_SEQ_CTL_Cx(channel)) = RUN_QUEUE_4284(4); wait_428c(channel); } @@ -2549,39 +2514,38 @@ * write MR3 MPR enable * in this mode only RD and RDA are allowed * all reads return a predefined pattern */ - MCHBAR32(IOSAV_0_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f000; - MCHBAR32(IOSAV_0_SUBSEQ_CTL_C0 + 0x400 * channel) = + MCHBAR32(IOSAV_y_SP_CMD_CTL_Cx(channel, 0)) = 0x1f000; + MCHBAR32(IOSAV_y_SUBSEQ_CTL_Cx(channel, 0)) = 0xc01 | (ctrl->tMOD << 16); - MCHBAR32(IOSAV_0_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = + MCHBAR32(IOSAV_y_SP_CMD_ADDR_Cx(channel, 0)) = (slotrank << 24) | 0x360004; - MCHBAR32(IOSAV_0_ADDR_UPD_C0 + 0x400 * channel) = 0; + MCHBAR32(IOSAV_y_ADDR_UPD_Cx(channel, 0)) = 0; /* DRAM command RD */ - MCHBAR32(IOSAV_1_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f105; - MCHBAR32(IOSAV_1_SUBSEQ_CTL_C0 + 0x400 * channel) = 0x4041003; - MCHBAR32(IOSAV_1_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = - (slotrank << 24) | 0; - MCHBAR32(IOSAV_1_ADDR_UPD_C0 + 0x400 * channel) = 0; + MCHBAR32(IOSAV_y_SP_CMD_CTL_Cx(channel, 1)) = 0x1f105; + MCHBAR32(IOSAV_y_SUBSEQ_CTL_Cx(channel, 1)) = 0x4041003; + MCHBAR32(IOSAV_y_SP_CMD_ADDR_Cx(channel, 1)) = (slotrank << 24) | 0; + MCHBAR32(IOSAV_y_ADDR_UPD_Cx(channel, 1)) = 0; /* DRAM command RD */ - MCHBAR32(IOSAV_2_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f105; - MCHBAR32(IOSAV_2_SUBSEQ_CTL_C0 + 0x400 * channel) = + MCHBAR32(IOSAV_y_SP_CMD_CTL_Cx(channel, 2)) = 0x1f105; + MCHBAR32(IOSAV_y_SUBSEQ_CTL_Cx(channel, 2)) = 0x1001 | ((ctrl->CAS + 8) << 16); - MCHBAR32(IOSAV_2_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = + MCHBAR32(IOSAV_y_SP_CMD_ADDR_Cx(channel, 2)) = (slotrank << 24) | 0x60000; - MCHBAR32(IOSAV_2_ADDR_UPD_C0 + 0x400 * channel) = 0; + MCHBAR32(IOSAV_y_ADDR_UPD_Cx(channel, 2)) = 0; /* DRAM command MRS * MR3 disable MPR */ - MCHBAR32(IOSAV_3_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f000; - MCHBAR32(IOSAV_3_SUBSEQ_CTL_C0 + 0x400 * channel) = + MCHBAR32(IOSAV_y_SP_CMD_CTL_Cx(channel, 3)) = 0x1f000; + MCHBAR32(IOSAV_y_SUBSEQ_CTL_Cx(channel, 3)) = 0xc01 | (ctrl->tMOD << 16); - MCHBAR32(IOSAV_3_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = + MCHBAR32(IOSAV_y_SP_CMD_ADDR_Cx(channel, 3)) = (slotrank << 24) | 0x360000; - MCHBAR32(IOSAV_3_ADDR_UPD_C0 + 0x400 * channel) = 0; + MCHBAR32(IOSAV_y_ADDR_UPD_Cx(channel, 3)) = 0; // execute command queue - MCHBAR32(IOSAV_SEQ_CTL_C0 + 0x400 * channel) = RUN_QUEUE_4284(4); + MCHBAR32(IOSAV_SEQ_CTL_Cx(channel)) = RUN_QUEUE_4284(4); wait_428c(channel); } @@ -2589,13 +2553,12 @@ /* XXX: check any measured value ? */ FOR_ALL_LANES { - MCHBAR32(IOSAV_B0_BW_MASK_C0 + 0x400 * channel + lane * 4) = - ~MCHBAR32(IOSAV_B0_BW_SERROR_C0 + 0x400 * channel + lane * 4) - & 0xff; + MCHBAR32(IOSAV_By_BW_MASK_Cx(channel, lane)) = + ~MCHBAR32(IOSAV_By_BW_SERROR_Cx(channel, lane)) & 0xff; } fill_pattern0(ctrl, channel, 0, 0xffffffff); - MCHBAR32(IOSAV_DATA_CTL_C0 + (channel << 10)) = 0; + MCHBAR32(IOSAV_DATA_CTL_Cx(channel)) = 0; } /* FIXME: under some conditions (older chipsets?) vendor BIOS sets both edges to the same value. */ @@ -2633,7 +2596,7 @@ } FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - MCHBAR32(IOSAV_B0_BW_MASK_C0 + 0x400 * channel + 4 * lane) = 0; + MCHBAR32(IOSAV_By_BW_MASK_Cx(channel, lane)) = 0; } return 0; } @@ -2661,7 +2624,7 @@ GDCRTRAININGMOD_C0 + 0x100 * channel, reg3000b24[i] << 24); for (pat = 0; pat < NUM_PATTERNS; pat++) { fill_pattern5(ctrl, channel, pat); - MCHBAR32(IOSAV_DATA_CTL_C0 + 0x400 * channel) = 0x1f; + MCHBAR32(IOSAV_DATA_CTL_Cx(channel)) = 0x1f; printram("using pattern %d\n", pat); for (edge = 0; edge <= MAX_EDGE_TIMING; edge++) { FOR_ALL_LANES { @@ -2673,59 +2636,48 @@ program_timings(ctrl, channel); FOR_ALL_LANES { - MCHBAR32(IOSAV_B0_ERROR_COUNT_C0 + 0x400 * channel + - 4 * lane) = 0; - MCHBAR32(0x400 * channel + - 4 * lane + IOSAV_B0_BW_SERROR_C_C0); + MCHBAR32(IOSAV_By_ERROR_COUNT_Cx(channel, lane)) = 0; + MCHBAR32(IOSAV_By_BW_SERROR_C_Cx(channel, lane)); } wait_428c(channel); /* DRAM command ACT */ - MCHBAR32(IOSAV_0_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = - 0x1f006; - MCHBAR32(IOSAV_0_SUBSEQ_CTL_C0 + 0x400 * channel) = + MCHBAR32(IOSAV_y_SP_CMD_CTL_Cx(channel, 0)) = 0x1f006; + MCHBAR32(IOSAV_y_SUBSEQ_CTL_Cx(channel, 0)) = 0x4 | (ctrl->tRCD << 16) | - (MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1) - << 10); - MCHBAR32(IOSAV_0_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = + (MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1) << 10); + MCHBAR32(IOSAV_y_SP_CMD_ADDR_Cx(channel, 0)) = (slotrank << 24) | 0x60000; - MCHBAR32(IOSAV_0_ADDR_UPD_C0 + 0x400 * channel) = 0x240; + MCHBAR32(IOSAV_y_ADDR_UPD_Cx(channel, 0)) = 0x240; /* DRAM command WR */ - MCHBAR32(IOSAV_1_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = - 0x1f201; - MCHBAR32(IOSAV_1_SUBSEQ_CTL_C0 + 0x400 * channel) = 0x8005020 | + MCHBAR32(IOSAV_y_SP_CMD_CTL_Cx(channel, 1)) = 0x1f201; + MCHBAR32(IOSAV_y_SUBSEQ_CTL_Cx(channel, 1)) = 0x8005020 | ((ctrl->tWTR + ctrl->CWL + 8) << 16); - MCHBAR32(IOSAV_1_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = - slotrank << 24; - MCHBAR32(IOSAV_1_ADDR_UPD_C0 + 0x400 * channel) = 0x242; + MCHBAR32(IOSAV_y_SP_CMD_ADDR_Cx(channel, 1)) = slotrank << 24; + MCHBAR32(IOSAV_y_ADDR_UPD_Cx(channel, 1)) = 0x242; /* DRAM command RD */ - MCHBAR32(IOSAV_2_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = - 0x1f105; - MCHBAR32(IOSAV_2_SUBSEQ_CTL_C0 + 0x400 * channel) = + MCHBAR32(IOSAV_y_SP_CMD_CTL_Cx(channel, 2)) = 0x1f105; + MCHBAR32(IOSAV_y_SUBSEQ_CTL_Cx(channel, 2)) = 0x4005020 | (MAX(ctrl->tRTP, 8) << 16); - MCHBAR32(IOSAV_2_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = - slotrank << 24; - MCHBAR32(IOSAV_2_ADDR_UPD_C0 + 0x400 * channel) = 0x242; + MCHBAR32(IOSAV_y_SP_CMD_ADDR_Cx(channel, 2)) = slotrank << 24; + MCHBAR32(IOSAV_y_ADDR_UPD_Cx(channel, 2)) = 0x242; /* DRAM command PRE */ - MCHBAR32(IOSAV_3_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = - 0x1f002; - MCHBAR32(IOSAV_3_SUBSEQ_CTL_C0 + 0x400 * channel) = + MCHBAR32(IOSAV_y_SP_CMD_CTL_Cx(channel, 3)) = 0x1f002; + MCHBAR32(IOSAV_y_SUBSEQ_CTL_Cx(channel, 3)) = 0xc01 | (ctrl->tRP << 16); - MCHBAR32(IOSAV_3_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = + MCHBAR32(IOSAV_y_SP_CMD_ADDR_Cx(channel, 3)) = (slotrank << 24) | 0x60400; - MCHBAR32(IOSAV_3_ADDR_UPD_C0 + 0x400 * channel) = 0; + MCHBAR32(IOSAV_y_ADDR_UPD_Cx(channel, 3)) = 0; // execute command queue - MCHBAR32(IOSAV_SEQ_CTL_C0 + 0x400 * channel) = - RUN_QUEUE_4284(4); + MCHBAR32(IOSAV_SEQ_CTL_Cx(channel)) = RUN_QUEUE_4284(4); wait_428c(channel); FOR_ALL_LANES { - MCHBAR32(IOSAV_B0_ERROR_COUNT_C0 + - 0x400 * channel + lane * 4); + MCHBAR32(IOSAV_By_ERROR_COUNT_Cx(channel, lane)); } /* FIXME: Register 0x436c does not seem to exist. */ @@ -2803,7 +2755,7 @@ program_timings(ctrl, channel); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - MCHBAR32(IOSAV_B0_BW_MASK_C0 + 0x400 * channel + 4 * lane) = 0; + MCHBAR32(IOSAV_By_BW_MASK_Cx(channel, lane)) = 0; } return 0; } @@ -2812,37 +2764,33 @@ { wait_428c(channel); /* DRAM command ACT */ - MCHBAR32(IOSAV_0_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f006; - MCHBAR32(IOSAV_0_SUBSEQ_CTL_C0 + 0x400 * channel) = - (MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD) - << 10) | (ctrl->tRCD << 16) | 4; - MCHBAR32(IOSAV_0_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = - (slotrank << 24) | 0x60000; - MCHBAR32(IOSAV_0_ADDR_UPD_C0 + 0x400 * channel) = 0x244; + MCHBAR32(IOSAV_y_SP_CMD_CTL_Cx(channel, 0)) = 0x1f006; + MCHBAR32(IOSAV_y_SUBSEQ_CTL_Cx(channel, 0)) = + (MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD) << 10) | (ctrl->tRCD << 16) | 4; + MCHBAR32(IOSAV_y_SP_CMD_ADDR_Cx(channel, 0)) = (slotrank << 24) | 0x60000; + MCHBAR32(IOSAV_y_ADDR_UPD_Cx(channel, 0)) = 0x244; /* DRAM command WR */ - MCHBAR32(IOSAV_1_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f201; - MCHBAR32(IOSAV_1_SUBSEQ_CTL_C0 + 0x400 * channel) = + MCHBAR32(IOSAV_y_SP_CMD_CTL_Cx(channel, 1)) = 0x1f201; + MCHBAR32(IOSAV_y_SUBSEQ_CTL_Cx(channel, 1)) = 0x80011e0 | ((ctrl->tWTR + ctrl->CWL + 8) << 16); - MCHBAR32(IOSAV_1_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = slotrank << 24; - MCHBAR32(IOSAV_1_ADDR_UPD_C0 + 0x400 * channel) = 0x242; + MCHBAR32(IOSAV_y_SP_CMD_ADDR_Cx(channel, 1)) = slotrank << 24; + MCHBAR32(IOSAV_y_ADDR_UPD_Cx(channel, 1)) = 0x242; /* DRAM command RD */ - MCHBAR32(IOSAV_2_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f105; - MCHBAR32(IOSAV_2_SUBSEQ_CTL_C0 + 0x400 * channel) = - 0x40011e0 | (MAX(ctrl->tRTP, 8) << 16); - MCHBAR32(IOSAV_2_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = slotrank << 24; - MCHBAR32(IOSAV_2_ADDR_UPD_C0 + 0x400 * channel) = 0x242; + MCHBAR32(IOSAV_y_SP_CMD_CTL_Cx(channel, 2)) = 0x1f105; + MCHBAR32(IOSAV_y_SUBSEQ_CTL_Cx(channel, 2)) = 0x40011e0 | (MAX(ctrl->tRTP, 8) << 16); + MCHBAR32(IOSAV_y_SP_CMD_ADDR_Cx(channel, 2)) = slotrank << 24; + MCHBAR32(IOSAV_y_ADDR_UPD_Cx(channel, 2)) = 0x242; /* DRAM command PRE */ - MCHBAR32(IOSAV_3_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f002; - MCHBAR32(IOSAV_3_SUBSEQ_CTL_C0 + 0x400 * channel) = 0x1001 | (ctrl->tRP << 16); - MCHBAR32(IOSAV_3_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = - (slotrank << 24) | 0x60400; - MCHBAR32(IOSAV_3_ADDR_UPD_C0 + 0x400 * channel) = 0; + MCHBAR32(IOSAV_y_SP_CMD_CTL_Cx(channel, 3)) = 0x1f002; + MCHBAR32(IOSAV_y_SUBSEQ_CTL_Cx(channel, 3)) = 0x1001 | (ctrl->tRP << 16); + MCHBAR32(IOSAV_y_SP_CMD_ADDR_Cx(channel, 3)) = (slotrank << 24) | 0x60400; + MCHBAR32(IOSAV_y_ADDR_UPD_Cx(channel, 3)) = 0; // execute command queue - MCHBAR32(IOSAV_SEQ_CTL_C0 + 0x400 * channel) = RUN_QUEUE_4284(4); + MCHBAR32(IOSAV_SEQ_CTL_Cx(channel)) = RUN_QUEUE_4284(4); wait_428c(channel); } @@ -2862,7 +2810,7 @@ } /* - * Enable IOSAV_n_SPECIAL_COMMAND_ADDR optimization. + * Enable IOSAV_n_SP_CMD_ADDR optimization. * FIXME: This must only be done on Ivy Bridge. */ MCHBAR32(MCMNTS_SPARE) = 1; @@ -2883,8 +2831,7 @@ statistics[MAX_TIMC] = 1; fill_pattern5(ctrl, channel, pat); - MCHBAR32(IOSAV_DATA_CTL_C0 + 0x400 * channel) = - 0x1f; + MCHBAR32(IOSAV_DATA_CTL_Cx(channel)) = 0x1f; for (timC = 0; timC < MAX_TIMC; timC++) { FOR_ALL_LANES ctrl->timings[channel][slotrank].lanes[lane].timC = timC; @@ -2933,7 +2880,7 @@ } /* - * Disable IOSAV_n_SPECIAL_COMMAND_ADDR optimization. + * Disable IOSAV_n_SP_CMD_ADDR optimization. * FIXME: This must only be done on Ivy Bridge. */ MCHBAR32(MCMNTS_SPARE) = 0; @@ -2999,7 +2946,7 @@ slotrank = 0; FOR_ALL_POPULATED_CHANNELS - if (MCHBAR32(MC_INIT_STATE_C0 + (channel << 10)) & 0xa000) { + if (MCHBAR32(MC_INIT_STATE_Cx(channel)) & 0xa000) { printk(BIOS_EMERG, "Mini channel test failed (1): %d\n", channel); return MAKE_ERR; @@ -3007,52 +2954,48 @@ FOR_ALL_POPULATED_CHANNELS { fill_pattern0(ctrl, channel, 0x12345678, 0x98765432); - MCHBAR32(IOSAV_DATA_CTL_C0 + (channel << 10)) = 0; + MCHBAR32(IOSAV_DATA_CTL_Cx(channel)) = 0; } for (slotrank = 0; slotrank < 4; slotrank++) FOR_ALL_CHANNELS if (ctrl->rankmap[channel] & (1 << slotrank)) { FOR_ALL_LANES { - MCHBAR32(IOSAV_B0_ERROR_COUNT + 4 * lane) = 0; - MCHBAR32(IOSAV_B0_BW_SERROR_C + 4 * lane) = 0; + MCHBAR32(IOSAV_By_ERROR_COUNT(lane)) = 0; + MCHBAR32(IOSAV_By_BW_SERROR_C(lane)) = 0; } wait_428c(channel); /* DRAM command ACT */ - MCHBAR32(IOSAV_0_SPECIAL_COMMAND_CTL_C0 + (channel << 10)) = 0x0001f006; - MCHBAR32(IOSAV_0_SUBSEQ_CTL_C0 + (channel << 10)) = 0x0028a004; - MCHBAR32(IOSAV_0_SPECIAL_COMMAND_ADDR_C0 + (channel << 10)) = - 0x00060000 | (slotrank << 24); - MCHBAR32(IOSAV_0_ADDR_UPD_C0 + (channel << 10)) = 0x00000244; + MCHBAR32(IOSAV_y_SP_CMD_CTL_Cx(channel, 0)) = 0x0001f006; + MCHBAR32(IOSAV_y_SUBSEQ_CTL_Cx(channel, 0)) = 0x0028a004; + MCHBAR32(IOSAV_y_SP_CMD_ADDR_Cx(channel, 0)) = 0x00060000 | (slotrank << 24); + MCHBAR32(IOSAV_y_ADDR_UPD_Cx(channel, 0)) = 0x00000244; /* DRAM command WR */ - MCHBAR32(IOSAV_1_SPECIAL_COMMAND_CTL_C0 + (channel << 10)) = 0x0001f201; - MCHBAR32(IOSAV_1_SUBSEQ_CTL_C0 + (channel << 10)) = 0x08281064; - MCHBAR32(IOSAV_1_SPECIAL_COMMAND_ADDR_C0 + (channel << 10)) = - 0x00000000 | (slotrank << 24); - MCHBAR32(IOSAV_1_ADDR_UPD_C0 + (channel << 10)) = 0x00000242; + MCHBAR32(IOSAV_y_SP_CMD_CTL_Cx(channel, 1)) = 0x0001f201; + MCHBAR32(IOSAV_y_SUBSEQ_CTL_Cx(channel, 1)) = 0x08281064; + MCHBAR32(IOSAV_y_SP_CMD_ADDR_Cx(channel, 1)) = 0x00000000 | (slotrank << 24); + MCHBAR32(IOSAV_y_ADDR_UPD_Cx(channel, 1)) = 0x00000242; /* DRAM command RD */ - MCHBAR32(IOSAV_2_SPECIAL_COMMAND_CTL_C0 + (channel << 10)) = 0x0001f105; - MCHBAR32(IOSAV_2_SUBSEQ_CTL_C0 + (channel << 10)) = 0x04281064; - MCHBAR32(IOSAV_2_SPECIAL_COMMAND_ADDR_C0 + (channel << 10)) = - 0x00000000 | (slotrank << 24); - MCHBAR32(IOSAV_2_ADDR_UPD_C0 + (channel << 10)) = 0x00000242; + MCHBAR32(IOSAV_y_SP_CMD_CTL_Cx(channel, 2)) = 0x0001f105; + MCHBAR32(IOSAV_y_SUBSEQ_CTL_Cx(channel, 2)) = 0x04281064; + MCHBAR32(IOSAV_y_SP_CMD_ADDR_Cx(channel, 2)) = 0x00000000 | (slotrank << 24); + MCHBAR32(IOSAV_y_ADDR_UPD_Cx(channel, 2)) = 0x00000242; /* DRAM command PRE */ - MCHBAR32(IOSAV_3_SPECIAL_COMMAND_CTL_C0 + (channel << 10)) = 0x0001f002; - MCHBAR32(IOSAV_3_SUBSEQ_CTL_C0 + (channel << 10)) = 0x00280c01; - MCHBAR32(IOSAV_3_SPECIAL_COMMAND_ADDR_C0 + (channel << 10)) = - 0x00060400 | (slotrank << 24); - MCHBAR32(IOSAV_3_ADDR_UPD_C0 + (channel << 10)) = 0x00000240; + MCHBAR32(IOSAV_y_SP_CMD_CTL_Cx(channel, 3)) = 0x0001f002; + MCHBAR32(IOSAV_y_SUBSEQ_CTL_Cx(channel, 3)) = 0x00280c01; + MCHBAR32(IOSAV_y_SP_CMD_ADDR_Cx(channel, 3)) = 0x00060400 | (slotrank << 24); + MCHBAR32(IOSAV_y_ADDR_UPD_Cx(channel, 3)) = 0x00000240; // execute command queue - MCHBAR32(IOSAV_SEQ_CTL_C0 + (channel << 10)) = RUN_QUEUE_4284(4); + MCHBAR32(IOSAV_SEQ_CTL_Cx(channel)) = RUN_QUEUE_4284(4); wait_428c(channel); FOR_ALL_LANES - if (MCHBAR32(IOSAV_B0_ERROR_COUNT_C0 + (channel << 10) + 4 * lane)) { + if (MCHBAR32(IOSAV_By_ERROR_COUNT_Cx(channel, lane))) { printk(BIOS_EMERG, "Mini channel test failed (2): %d, %d, %d\n", channel, slotrank, lane); return MAKE_ERR; @@ -3072,10 +3015,10 @@ {0x00028bfa, 0x53fe4b49, 0x19ed5483} }; FOR_ALL_POPULATED_CHANNELS { - MCHBAR32(SCHED_CBIT_C0 + 0x400 * channel) &= ~0x10000000; - MCHBAR32(SCRAMBLING_SEED_1_C0 + 0x400 * channel) = seeds[channel][0]; - MCHBAR32(SCRAMBLING_SEED_2_HIGH_C0 + 0x400 * channel) = seeds[channel][1]; - MCHBAR32(SCRAMBLING_SEED_2_LOW_C0 + 0x400 * channel) = seeds[channel][2]; + MCHBAR32(SCHED_CBIT_Cx(channel)) &= ~0x10000000; + MCHBAR32(SCRAMBLING_SEED_1_Cx(channel)) = seeds[channel][0]; + MCHBAR32(SCRAMBLING_SEED_2_HIGH_Cx(channel)) = seeds[channel][1]; + MCHBAR32(SCRAMBLING_SEED_2_LOW_Cx(channel)) = seeds[channel][2]; } } @@ -3097,7 +3040,7 @@ FOR_ALL_POPULATED_CHANNELS { // Always drive command bus - MCHBAR32_OR(TC_RAP_C0 + 0x400 * channel, 0x20000000); + MCHBAR32_OR(TC_RAP_Cx(channel), 0x20000000); } udelay(1); @@ -3133,8 +3076,7 @@ dram_odt_stretch(ctrl, channel); - MCHBAR32(TC_RWP_C0 + (channel << 10)) = - 0x0a000000 | (b20 << 20) | + MCHBAR32(TC_RWP_Cx(channel)) = 0x0a000000 | (b20 << 20) | ((ctrl->ref_card_offset[channel] + 2) << 16) | b4_8_12; } } @@ -3143,9 +3085,8 @@ { int channel; FOR_ALL_POPULATED_CHANNELS { - MCHBAR32(MC_INIT_STATE_C0 + 0x400 * channel) = - 0x00001000 | ctrl->rankmap[channel]; - MCHBAR32_AND(TC_RAP_C0 + 0x400 * channel, ~0x20000000); + MCHBAR32(MC_INIT_STATE_Cx(channel)) = 0x00001000 | ctrl->rankmap[channel]; + MCHBAR32_AND(TC_RAP_Cx(channel), ~0x20000000); } } @@ -3168,7 +3109,7 @@ MCHBAR32(WMM_READ_CONFIG) = 0x00000046; FOR_ALL_CHANNELS - MCHBAR32_AND_OR(TC_OTHP_C0 + 0x400 * channel, 0xFFFFCFFF, 0x1000); + MCHBAR32_AND_OR(TC_OTHP_Cx(channel), 0xFFFFCFFF, 0x1000); if (is_mobile) /* APD - DLL Off, 64 DCLKs until idle, decision per rank */ @@ -3178,7 +3119,7 @@ MCHBAR32(PM_PDWN_CONFIG) = 0x00000340; FOR_ALL_CHANNELS - MCHBAR32(PM_TRML_M_CONFIG_C0 + 0x400 * channel) = 0x00000aaa; + MCHBAR32(PM_TRML_M_CONFIG_Cx(channel)) = 0x00000aaa; MCHBAR32(PM_BW_LIMIT_CONFIG) = 0x5f7003ff; // OK MCHBAR32(PM_DLL_CONFIG) = 0x00073000 | ctrl->reg_5064b0; // OK @@ -3187,17 +3128,17 @@ switch (ctrl->rankmap[channel]) { /* Unpopulated channel. */ case 0: - MCHBAR32(PM_CMD_PWR_C0 + channel * 0x400) = 0; + MCHBAR32(PM_CMD_PWR_Cx(channel)) = 0; break; /* Only single-ranked dimms. */ case 1: case 4: case 5: - MCHBAR32(PM_CMD_PWR_C0 + channel * 0x400) = 0x373131; + MCHBAR32(PM_CMD_PWR_Cx(channel)) = 0x373131; break; /* Dual-ranked dimms present. */ default: - MCHBAR32(PM_CMD_PWR_C0 + channel * 0x400) = 0x9b6ea1; + MCHBAR32(PM_CMD_PWR_Cx(channel)) = 0x9b6ea1; break; } } @@ -3207,7 +3148,7 @@ MCHBAR32_AND(MEM_TRML_INTERRUPT, ~0x1f); FOR_ALL_CHANNELS - MCHBAR32_AND_OR(TC_RFP_C0 + 0x400 * channel, ~0x30000, 1 << 16); + MCHBAR32_AND_OR(TC_RFP_Cx(channel), ~0x30000, 1 << 16); MCHBAR32_OR(MC_INIT_STATE_G, 1); MCHBAR32_OR(MC_INIT_STATE_G, 0x80); @@ -3219,11 +3160,11 @@ FOR_ALL_POPULATED_CHANNELS break; - t1_cycles = (MCHBAR32(TC_ZQCAL_C0 + channel * 0x400) >> 8) & 0xff; + t1_cycles = (MCHBAR32(TC_ZQCAL_Cx(channel)) >> 8) & 0xff; r32 = MCHBAR32(PM_DLL_CONFIG); if (r32 & 0x20000) t1_cycles += (r32 & 0xfff); - t1_cycles += MCHBAR32(channel * 0x400 + TC_SRFTP_C0) & 0xfff; + t1_cycles += MCHBAR32(TC_SRFTP_Cx(channel)) & 0xfff; t1_ns = t1_cycles * ctrl->tCK / 256 + 544; if (!(r32 & 0x20000)) t1_ns += 500; @@ -3253,7 +3194,7 @@ int channel, slotrank, lane; FOR_ALL_POPULATED_CHANNELS - MCHBAR32(TC_RAP_C0 + 0x400 * channel) = + MCHBAR32(TC_RAP_Cx(channel)) = ctrl->tRRD | (ctrl->tRTP << 4) | (ctrl->tCKE << 8) @@ -3269,15 +3210,15 @@ } FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - MCHBAR32(IOSAV_B0_BW_MASK_C0 + 0x400 * channel + 4 * lane) = 0; + MCHBAR32(IOSAV_By_BW_MASK_Cx(channel, lane)) = 0; } FOR_ALL_POPULATED_CHANNELS - MCHBAR32_OR(TC_RWP_C0 + 0x400 * channel, 0x8000000); + MCHBAR32_OR(TC_RWP_Cx(channel), 0x8000000); FOR_ALL_POPULATED_CHANNELS { udelay (1); - MCHBAR32_OR(SCHED_CBIT_C0 + 0x400 * channel, 0x200000); + MCHBAR32_OR(SCHED_CBIT_Cx(channel), 0x200000); } printram("CPE\n"); @@ -3295,7 +3236,7 @@ while (!(MCHBAR32(RCOMP_TIMER) & 0x10000)); do { - reg = MCHBAR32(IOSAV_STATUS_C0); + reg = MCHBAR32(IOSAV_STATUS_Cx(0)); } while ((reg & 0x14) == 0); // Set state of memory controller @@ -3309,7 +3250,7 @@ // Set valid rank CKE reg = 0; reg = (reg & ~0xf) | ctrl->rankmap[channel]; - addr = 0x400 * channel + MC_INIT_STATE_C0; + addr = MC_INIT_STATE_Cx(channel); MCHBAR32(addr) = reg; // Wait 10ns for ranks to settle @@ -3335,7 +3276,7 @@ } /* - * Disable IOSAV_n_SPECIAL_COMMAND_ADDR optimization. + * Disable IOSAV_n_SP_CMD_ADDR optimization. * FIXME: This must only be done on Ivy Bridge. Moreover, this instance seems to be * spurious, because nothing else enabled this optimization before. */ diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 4aaa34e..63181e5 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -173,278 +173,203 @@ #define CRCOMPOFST2 0x3714 /* CMD DRV, SComp and Static Leg controls */ + +/* Indexed register helper macros */ +#define Ly(r, y) ((r) + ((y) * 4)) +#define Cx(r, x) ((r) + ((x) * 0x400)) +#define CxLy(r, x, y) Cx(Ly(r, y), x) + /* MC Channel 0 */ -#define TC_DBP_C0 0x4000 /* Timing of DDR - bin parameters */ -#define TC_RAP_C0 0x4004 /* Timing of DDR - regular access parameters */ -#define TC_RWP_C0 0x4008 /* Timing of DDR - read/write parameters */ -#define TC_OTHP_C0 0x400c /* Timing of DDR - other timing parameters */ -#define SCHED_SECOND_CBIT_C0 0x401c /* More chicken bits */ -#define SCHED_CBIT_C0 0x4020 /* Chicken bits in scheduler */ -#define SC_ROUNDT_LAT_C0 0x4024 /* Round-trip latency per rank */ -#define SC_IO_LATENCY_C0 0x4028 /* IO Latency Configuration */ -#define SCRAMBLING_SEED_1_C0 0x4034 /* Scrambling seed 1 */ -#define SCRAMBLING_SEED_2_LOW_C0 0x4038 /* Scrambling seed 2 low */ -#define SCRAMBLING_SEED_2_HIGH_C0 0x403c /* Scrambling seed 2 high */ +#define TC_DBP_Cx(x) Cx(0x4000, x) /* Timing of DDR - bin parameters */ +#define TC_RAP_Cx(x) Cx(0x4004, x) /* Timing of DDR - regular access parameters */ +#define TC_RWP_Cx(x) Cx(0x4008, x) /* Timing of DDR - read/write parameters */ +#define TC_OTHP_Cx(x) Cx(0x400c, x) /* Timing of DDR - other timing parameters */ +#define SCHED_SECOND_CBIT_Cx(x) Cx(0x401c, x) /* More chicken bits */ +#define SCHED_CBIT_Cx(x) Cx(0x4020, x) /* Chicken bits in scheduler */ +#define SC_ROUNDT_LAT_Cx(x) Cx(0x4024, x) /* Round-trip latency per rank */ +#define SC_IO_LATENCY_Cx(x) Cx(0x4028, x) /* IO Latency Configuration */ -#define IOSAV_B0_BW_SERROR_C0 0x4040 /* IOSAV Bytelane 0 Bit-wise error */ -#define IOSAV_B1_BW_SERROR_C0 0x4044 -#define IOSAV_B2_BW_SERROR_C0 0x4048 -#define IOSAV_B3_BW_SERROR_C0 0x404c -#define IOSAV_B4_BW_SERROR_C0 0x4050 -#define IOSAV_B5_BW_SERROR_C0 0x4054 -#define IOSAV_B6_BW_SERROR_C0 0x4058 -#define IOSAV_B7_BW_SERROR_C0 0x405c -#define IOSAV_B8_BW_SERROR_C0 0x4060 +#define SCRAMBLING_SEED_1_Cx(x) Cx(0x4034, x) /* Scrambling seed 1 */ +#define SCRAMBLING_SEED_2_LOW_Cx(x) Cx(0x4038, x) /* Scrambling seed 2 low */ +#define SCRAMBLING_SEED_2_HIGH_Cx(x) Cx(0x403c, x) /* Scrambling seed 2 high */ -#define IOSAV_B0_BW_MASK_C0 0x4080 /* IOSAV Bytelane 0 Bit-wise compare mask */ -#define IOSAV_B1_BW_MASK_C0 0x4084 -#define IOSAV_B2_BW_MASK_C0 0x4088 -#define IOSAV_B3_BW_MASK_C0 0x408c -#define IOSAV_B4_BW_MASK_C0 0x4090 -#define IOSAV_B5_BW_MASK_C0 0x4094 -#define IOSAV_B6_BW_MASK_C0 0x4098 -#define IOSAV_B7_BW_MASK_C0 0x409c -#define IOSAV_B8_BW_MASK_C0 0x40a0 +/* IOSAV Bytelane Bit-wise error */ +#define IOSAV_By_BW_SERROR_Cx(x, y) CxLy(0x4040, x, y) + +/* IOSAV Bytelane Bit-wise compare mask */ +#define IOSAV_By_BW_MASK_Cx(x, y) CxLy(0x4080, x, y) /* * Defines the number of transactions (non-VC1 RD CAS commands) between two priority ticks. * Different counters for transactions that are issued on the ring agents (core or GT) and * transactions issued in the SA. */ -#define SC_PR_CNT_CONFIG_C0 0x40a8 -#define SC_PCIT_C0 0x40ac /* Page-close idle timer setup - 8 bits */ -#define PM_PDWN_CONFIG_C0 0x40b0 /* Power-down (CKE-off) operation config */ -#define ECC_INJECT_COUNT_C0 0x40b4 /* ECC error injection count */ -#define ECC_DFT_C0 0x40b8 /* ECC DFT features (ECC4ANA, error inject) */ +#define SC_PR_CNT_CONFIG_Cx(x) Cx(0x40a8, x) +#define SC_PCIT_Cx(x) Cx(0x40ac, x) /* Page-close idle timer setup - 8 bits */ +#define PM_PDWN_CONFIG_Cx(x) Cx(0x40b0, x) /* Power-down (CKE-off) operation config */ +#define ECC_INJECT_COUNT_Cx(x) Cx(0x40b4, x) /* ECC error injection count */ +#define ECC_DFT_Cx(x) Cx(0x40b8, x) /* ECC DFT features (ECC4ANA, error inject) */ -#define SC_WR_ADD_DELAY_C0 0x40d0 /* Extra WR delay to overcome WR-flyby issue */ +#define SC_WR_ADD_DELAY_Cx(x) Cx(0x40d0, x) /* Extra WR delay to overcome WR-flyby issue */ -#define IOSAV_B0_BW_SERROR_C_C0 0x4140 /* IOSAV Bytelane 0 Bit-wise error */ -#define IOSAV_B1_BW_SERROR_C_C0 0x4144 /* IOSAV Bytelane 0 Bit-wise error */ -#define IOSAV_B2_BW_SERROR_C_C0 0x4148 /* IOSAV Bytelane 0 Bit-wise error */ -#define IOSAV_B3_BW_SERROR_C_C0 0x414c /* IOSAV Bytelane 0 Bit-wise error */ -#define IOSAV_B4_BW_SERROR_C_C0 0x4150 /* IOSAV Bytelane 0 Bit-wise error */ -#define IOSAV_B5_BW_SERROR_C_C0 0x4154 /* IOSAV Bytelane 0 Bit-wise error */ -#define IOSAV_B6_BW_SERROR_C_C0 0x4158 /* IOSAV Bytelane 0 Bit-wise error */ -#define IOSAV_B7_BW_SERROR_C_C0 0x415c /* IOSAV Bytelane 0 Bit-wise error */ -#define IOSAV_B8_BW_SERROR_C_C0 0x4160 /* IOSAV Bytelane 0 Bit-wise error */ +/* IOSAV Bytelane Bit-wise error */ +#define IOSAV_By_BW_SERROR_C_Cx(x, y) CxLy(0x4140, x, y) -#define IOSAV_0_SPECIAL_COMMAND_ADDR_C0 0x4200 /* Sub-sequence command address */ -#define IOSAV_1_SPECIAL_COMMAND_ADDR_C0 0x4204 -#define IOSAV_2_SPECIAL_COMMAND_ADDR_C0 0x4208 -#define IOSAV_3_SPECIAL_COMMAND_ADDR_C0 0x420c -#define IOSAV_0_ADDR_UPD_C0 0x4210 /* Address update after command execution */ -#define IOSAV_1_ADDR_UPD_C0 0x4214 -#define IOSAV_2_ADDR_UPD_C0 0x4218 -#define IOSAV_3_ADDR_UPD_C0 0x421c -#define IOSAV_0_SPECIAL_COMMAND_CTL_C0 0x4220 /* Command signals in sub-sequence command */ -#define IOSAV_1_SPECIAL_COMMAND_CTL_C0 0x4224 -#define IOSAV_2_SPECIAL_COMMAND_CTL_C0 0x4228 -#define IOSAV_3_SPECIAL_COMMAND_CTL_C0 0x422c -#define IOSAV_0_SUBSEQ_CTL_C0 0x4230 /* Sub-sequence command parameter control */ -#define IOSAV_1_SUBSEQ_CTL_C0 0x4234 -#define IOSAV_2_SUBSEQ_CTL_C0 0x4238 -#define IOSAV_3_SUBSEQ_CTL_C0 0x423c -#define IOSAV_0_ADDRESS_LFSR_C0 0x4240 /* 23-bit LFSR value of the sequence */ -#define IOSAV_1_ADDRESS_LFSR_C0 0x4244 -#define IOSAV_2_ADDRESS_LFSR_C0 0x4248 -#define IOSAV_3_ADDRESS_LFSR_C0 0x424c +/* Sub-sequence special command address */ +#define IOSAV_y_SP_CMD_ADDR_Cx(x, y) CxLy(0x4200, x, y) -#define PM_THML_STAT_C0 0x4280 /* Thermal status of each rank */ -#define IOSAV_SEQ_CTL_C0 0x4284 /* IOSAV sequence level control */ -#define IOSAV_DATA_CTL_C0 0x4288 /* Data control in IOSAV mode */ -#define IOSAV_STATUS_C0 0x428c /* State of the IOSAV sequence machine */ -#define TC_ZQCAL_C0 0x4290 /* ZQCAL control register */ -#define TC_RFP_C0 0x4294 /* Refresh Parameters */ -#define TC_RFTP_C0 0x4298 /* Refresh Timing Parameters */ -#define TC_MR2_SHADOW_C0 0x429c /* MR2 shadow - copy of DDR configuration */ -#define MC_INIT_STATE_C0 0x42a0 /* IOSAV mode control */ -#define TC_SRFTP_C0 0x42a4 /* Self-refresh timing parameters */ -#define IOSAV_ERROR_C0 0x42ac /* Data vector count of the first error */ -#define IOSAV_DC_MASK_C0 0x42b0 /* IOSAV data check masking */ +/* Address update after command execution */ +#define IOSAV_y_ADDR_UPD_Cx(x, y) CxLy(0x4210, x, y) -#define IOSAV_B0_ERROR_COUNT_C0 0x4340 /* Per-byte 16-bit error counter */ -#define IOSAV_B1_ERROR_COUNT_C0 0x4344 -#define IOSAV_B2_ERROR_COUNT_C0 0x4348 -#define IOSAV_B3_ERROR_COUNT_C0 0x434c -#define IOSAV_B4_ERROR_COUNT_C0 0x4350 -#define IOSAV_B5_ERROR_COUNT_C0 0x4354 -#define IOSAV_B6_ERROR_COUNT_C0 0x4358 -#define IOSAV_B7_ERROR_COUNT_C0 0x435c -#define IOSAV_B8_ERROR_COUNT_C0 0x4360 -#define IOSAV_G_ERROR_COUNT_C0 0x4364 /* Global 16-bit error counter */ +/* Command signals in sub-sequence command */ +#define IOSAV_y_SP_CMD_CTL_Cx(x, y) CxLy(0x4220, x, y) -#define PM_TRML_M_CONFIG_C0 0x4380 /* Thermal mode configuration */ -#define PM_CMD_PWR_C0 0x4384 /* Power contribution of commands */ -#define PM_BW_LIMIT_CONFIG_C0 0x4388 /* Bandwidth throttling on overtemperature */ -#define SC_WDBWM_C0 0x438c /* Watermarks and starvation counter config */ +/* Sub-sequence command parameter control */ +#define IOSAV_y_SUBSEQ_CTL_Cx(x, y) CxLy(0x4230, x, y) + +/* 23-bit LFSR value of the sequence */ +#define IOSAV_y_ADDRESS_LFSR_Cx(x, y) CxLy(0x4240, x, y) + +#define PM_THML_STAT_Cx(x) Cx(0x4280, x) /* Thermal status of each rank */ +#define IOSAV_SEQ_CTL_Cx(x) Cx(0x4284, x) /* IOSAV sequence level control */ +#define IOSAV_DATA_CTL_Cx(x) Cx(0x4288, x) /* Data control in IOSAV mode */ +#define IOSAV_STATUS_Cx(x) Cx(0x428c, x) /* State of the IOSAV sequence machine */ +#define TC_ZQCAL_Cx(x) Cx(0x4290, x) /* ZQCAL control register */ +#define TC_RFP_Cx(x) Cx(0x4294, x) /* Refresh Parameters */ +#define TC_RFTP_Cx(x) Cx(0x4298, x) /* Refresh Timing Parameters */ +#define TC_MR2_SHADOW_Cx(x) Cx(0x429c, x) /* MR2 shadow - copy of DDR configuration */ +#define MC_INIT_STATE_Cx(x) Cx(0x42a0, x) /* IOSAV mode control */ +#define TC_SRFTP_Cx(x) Cx(0x42a4, x) /* Self-refresh timing parameters */ +#define IOSAV_ERROR_Cx(x) Cx(0x42ac, x) /* Data vector count of the first error */ +#define IOSAV_DC_MASK_Cx(x) Cx(0x42b0, x) /* IOSAV data check masking */ + +#define IOSAV_By_ERROR_COUNT_Cx(x, y) CxLy(0x4340, x, y) /* Per-byte 16-bit error counter */ +#define IOSAV_G_ERROR_COUNT_Cx(x) Cx(0x4364, x) /* Global 16-bit error counter */ + +#define PM_TRML_M_CONFIG_Cx(x) Cx(0x4380, x) /* Thermal mode configuration */ +#define PM_CMD_PWR_Cx(x) Cx(0x4384, x) /* Power contribution of commands */ +#define PM_BW_LIMIT_CONFIG_Cx(x) Cx(0x4388, x) /* Bandwidth throttling on overtemp */ +#define SC_WDBWM_Cx(x) Cx(0x438c, x) /* Watermarks and starvation counter */ /* MC Channel Broadcast */ -#define TC_DBP 0x4c00 /* Timing of DDR - bin parameters */ -#define TC_RAP 0x4c04 /* Timing of DDR - regular access parameters */ -#define TC_RWP 0x4c08 /* Timing of DDR - read/write parameters */ -#define TC_OTHP 0x4c0c /* Timing of DDR - other timing parameters */ -#define SCHED_SECOND_CBIT 0x4c1c /* More chicken bits */ -#define SCHED_CBIT 0x4c20 /* Chicken bits in scheduler */ -#define SC_ROUNDT_LAT 0x4c24 /* Round-trip latency per rank */ -#define SC_IO_LATENCY 0x4c28 /* IO Latency Configuration */ -#define SCRAMBLING_SEED_1 0x4c34 /* Scrambling seed 1 */ -#define SCRAMBLING_SEED_2_LOW 0x4c38 /* Scrambling seed 2 low */ -#define SCRAMBLING_SEED_2_HIGH 0x4c3c /* Scrambling seed 2 high */ +#define TC_DBP 0x4c00 /* Timing of DDR - bin parameters */ +#define TC_RAP 0x4c04 /* Timing of DDR - regular access parameters */ +#define TC_RWP 0x4c08 /* Timing of DDR - read/write parameters */ +#define TC_OTHP 0x4c0c /* Timing of DDR - other timing parameters */ +#define SCHED_SECOND_CBIT 0x4c1c /* More chicken bits */ +#define SCHED_CBIT 0x4c20 /* Chicken bits in scheduler */ +#define SC_ROUNDT_LAT 0x4c24 /* Round-trip latency per rank */ +#define SC_IO_LATENCY 0x4c28 /* IO Latency Configuration */ +#define SCRAMBLING_SEED_1 0x4c34 /* Scrambling seed 1 */ +#define SCRAMBLING_SEED_2_LOW 0x4c38 /* Scrambling seed 2 low */ +#define SCRAMBLING_SEED_2_HIGH 0x4c3c /* Scrambling seed 2 high */ -#define IOSAV_B0_BW_SERROR 0x4c40 /* IOSAV Bytelane 0 Bit-wise error */ -#define IOSAV_B1_BW_SERROR 0x4c44 -#define IOSAV_B2_BW_SERROR 0x4c48 -#define IOSAV_B3_BW_SERROR 0x4c4c -#define IOSAV_B4_BW_SERROR 0x4c50 -#define IOSAV_B5_BW_SERROR 0x4c54 -#define IOSAV_B6_BW_SERROR 0x4c58 -#define IOSAV_B7_BW_SERROR 0x4c5c -#define IOSAV_B8_BW_SERROR 0x4c60 +#define IOSAV_By_BW_SERROR(y) Ly(0x4c40, y) /* IOSAV Bytelane Bit-wise error */ -#define IOSAV_B0_BW_MASK 0x4c80 /* IOSAV Bytelane 0 Bit-wise compare mask */ -#define IOSAV_B1_BW_MASK 0x4c84 -#define IOSAV_B2_BW_MASK 0x4c88 -#define IOSAV_B3_BW_MASK 0x4c8c -#define IOSAV_B4_BW_MASK 0x4c90 -#define IOSAV_B5_BW_MASK 0x4c94 -#define IOSAV_B6_BW_MASK 0x4c98 -#define IOSAV_B7_BW_MASK 0x4c9c -#define IOSAV_B8_BW_MASK 0x4ca0 +#define IOSAV_By_BW_MASK(y) Ly(0x4c80, y) /* IOSAV Bytelane Bit-wise compare mask */ /* * Defines the number of transactions (non-VC1 RD CAS commands) between two priority ticks. * Different counters for transactions that are issued on the ring agents (core or GT) and * transactions issued in the SA. */ -#define SC_PR_CNT_CONFIG 0x4ca8 -#define SC_PCIT 0x4cac /* Page-close idle timer setup - 8 bits */ -#define PM_PDWN_CONFIG 0x4cb0 /* Power-down (CKE-off) operation config */ -#define ECC_INJECT_COUNT 0x4cb4 /* ECC error injection count */ -#define ECC_DFT 0x4cb8 /* ECC DFT features (ECC4ANA, error inject) */ +#define SC_PR_CNT_CONFIG 0x4ca8 +#define SC_PCIT 0x4cac /* Page-close idle timer setup - 8 bits */ +#define PM_PDWN_CONFIG 0x4cb0 /* Power-down (CKE-off) operation config */ +#define ECC_INJECT_COUNT 0x4cb4 /* ECC error injection count */ +#define ECC_DFT 0x4cb8 /* ECC DFT features (ECC4ANA, error inject) */ -#define SC_WR_ADD_DELAY 0x4cd0 /* Extra WR delay to overcome WR-flyby issue */ +#define SC_WR_ADD_DELAY 0x4cd0 /* Extra WR delay to overcome WR-flyby issue */ /* Opportunistic reads configuration during write-major-mode (WMM) */ -#define WMM_READ_CONFIG 0x4cd4 /** WARNING: Only exists on IVB! */ +#define WMM_READ_CONFIG 0x4cd4 /** WARNING: Only exists on IVB! */ -#define IOSAV_B0_BW_SERROR_C 0x4d40 /* IOSAV Bytelane 0 Bit-wise error */ -#define IOSAV_B1_BW_SERROR_C 0x4d44 /* IOSAV Bytelane 0 Bit-wise error */ -#define IOSAV_B2_BW_SERROR_C 0x4d48 /* IOSAV Bytelane 0 Bit-wise error */ -#define IOSAV_B3_BW_SERROR_C 0x4d4c /* IOSAV Bytelane 0 Bit-wise error */ -#define IOSAV_B4_BW_SERROR_C 0x4d50 /* IOSAV Bytelane 0 Bit-wise error */ -#define IOSAV_B5_BW_SERROR_C 0x4d54 /* IOSAV Bytelane 0 Bit-wise error */ -#define IOSAV_B6_BW_SERROR_C 0x4d58 /* IOSAV Bytelane 0 Bit-wise error */ -#define IOSAV_B7_BW_SERROR_C 0x4d5c /* IOSAV Bytelane 0 Bit-wise error */ -#define IOSAV_B8_BW_SERROR_C 0x4d60 /* IOSAV Bytelane 0 Bit-wise error */ +#define IOSAV_By_BW_SERROR_C(y) Ly(0x4d40, y) /* IOSAV Bytelane Bit-wise error */ -#define IOSAV_0_SPECIAL_COMMAND_ADDR 0x4e00 /* Sub-sequence command address */ -#define IOSAV_1_SPECIAL_COMMAND_ADDR 0x4e04 -#define IOSAV_2_SPECIAL_COMMAND_ADDR 0x4e08 -#define IOSAV_3_SPECIAL_COMMAND_ADDR 0x4e0c -#define IOSAV_0_ADDR_UPD 0x4e10 /* Address update after command execution */ -#define IOSAV_1_ADDR_UPD 0x4e14 -#define IOSAV_2_ADDR_UPD 0x4e18 -#define IOSAV_3_ADDR_UPD 0x4e1c -#define IOSAV_0_SPECIAL_COMMAND_CTL 0x4e20 /* Command signals in sub-sequence command */ -#define IOSAV_1_SPECIAL_COMMAND_CTL 0x4e24 -#define IOSAV_2_SPECIAL_COMMAND_CTL 0x4e28 -#define IOSAV_3_SPECIAL_COMMAND_CTL 0x4e2c -#define IOSAV_0_SUBSEQ_CTL 0x4e30 /* Sub-sequence command parameter control */ -#define IOSAV_1_SUBSEQ_CTL 0x4e34 -#define IOSAV_2_SUBSEQ_CTL 0x4e38 -#define IOSAV_3_SUBSEQ_CTL 0x4e3c -#define IOSAV_0_ADDRESS_LFSR 0x4e40 /* 23-bit LFSR value of the sequence */ -#define IOSAV_1_ADDRESS_LFSR 0x4e44 -#define IOSAV_2_ADDRESS_LFSR 0x4e48 -#define IOSAV_3_ADDRESS_LFSR 0x4e4c +#define IOSAV_y_SP_CMD_ADDR(y) Ly(0x4e00, y) /* Sub-sequence special command address */ +#define IOSAV_y_ADDR_UPD(y) Ly(0x4e10, y) /* Address update after command execution */ +#define IOSAV_y_SP_CMD_CTL(y) Ly(0x4e20, y) /* Command signals in sub-sequence command */ +#define IOSAV_y_SUBSEQ_CTL(y) Ly(0x4e30, y) /* Sub-sequence command parameter control */ +#define IOSAV_y_ADDRESS_LFSR(y) Ly(0x4e40, y) /* 23-bit LFSR value of the sequence */ -#define PM_THML_STAT 0x4e80 /* Thermal status of each rank */ -#define IOSAV_SEQ_CTL 0x4e84 /* IOSAV sequence level control */ -#define IOSAV_DATA_CTL 0x4e88 /* Data control in IOSAV mode */ -#define IOSAV_STATUS 0x4e8c /* State of the IOSAV sequence machine */ -#define TC_ZQCAL 0x4e90 /* ZQCAL control register */ -#define TC_RFP 0x4e94 /* Refresh Parameters */ -#define TC_RFTP 0x4e98 /* Refresh Timing Parameters */ -#define TC_MR2_SHADOW 0x4e9c /* MR2 shadow - copy of DDR configuration */ -#define MC_INIT_STATE 0x4ea0 /* IOSAV mode control */ -#define TC_SRFTP 0x4ea4 /* Self-refresh timing parameters */ +#define PM_THML_STAT 0x4e80 /* Thermal status of each rank */ +#define IOSAV_SEQ_CTL 0x4e84 /* IOSAV sequence level control */ +#define IOSAV_DATA_CTL 0x4e88 /* Data control in IOSAV mode */ +#define IOSAV_STATUS 0x4e8c /* State of the IOSAV sequence machine */ +#define TC_ZQCAL 0x4e90 /* ZQCAL control register */ +#define TC_RFP 0x4e94 /* Refresh Parameters */ +#define TC_RFTP 0x4e98 /* Refresh Timing Parameters */ +#define TC_MR2_SHADOW 0x4e9c /* MR2 shadow - copy of DDR configuration */ +#define MC_INIT_STATE 0x4ea0 /* IOSAV mode control */ +#define TC_SRFTP 0x4ea4 /* Self-refresh timing parameters */ /* * Auxiliary register in mcmnts synthesis FUB (Functional Unit Block). Additionally, this - * register is also used to enable IOSAV_n_SPECIAL_COMMAND_ADDR optimization on Ivy Bridge. + * register is also used to enable IOSAV_n_SP_CMD_ADDR optimization on Ivy Bridge. */ -#define MCMNTS_SPARE 0x4ea8 /** WARNING: Reserved, use only on IVB! */ +#define MCMNTS_SPARE 0x4ea8 /** WARNING: Reserved, use only on IVB! */ -#define IOSAV_ERROR 0x4eac /* Data vector count of the first error */ -#define IOSAV_DC_MASK 0x4eb0 /* IOSAV data check masking */ +#define IOSAV_ERROR 0x4eac /* Data vector count of the first error */ +#define IOSAV_DC_MASK 0x4eb0 /* IOSAV data check masking */ -#define IOSAV_B0_ERROR_COUNT 0x4f40 /* Per-byte 16-bit error counter */ -#define IOSAV_B1_ERROR_COUNT 0x4f44 -#define IOSAV_B2_ERROR_COUNT 0x4f48 -#define IOSAV_B3_ERROR_COUNT 0x4f4c -#define IOSAV_B4_ERROR_COUNT 0x4f50 -#define IOSAV_B5_ERROR_COUNT 0x4f54 -#define IOSAV_B6_ERROR_COUNT 0x4f58 -#define IOSAV_B7_ERROR_COUNT 0x4f5c -#define IOSAV_B8_ERROR_COUNT 0x4f60 -#define IOSAV_G_ERROR_COUNT 0x4f64 /* Global 16-bit error counter */ +#define IOSAV_By_ERROR_COUNT(y) Ly(0x4f40, y) /* Per-byte 16-bit error counter */ +#define IOSAV_G_ERROR_COUNT 0x4f64 /* Global 16-bit error counter */ -#define PM_TRML_M_CONFIG 0x4f80 /* Thermal mode configuration */ -#define PM_CMD_PWR 0x4f84 /* Power contribution of commands */ -#define PM_BW_LIMIT_CONFIG 0x4f88 /* Bandwidth throttling on overtemperature */ -#define SC_WDBWM 0x4f8c /* Watermarks and starvation counter config */ +#define PM_TRML_M_CONFIG 0x4f80 /* Thermal mode configuration */ +#define PM_CMD_PWR 0x4f84 /* Power contribution of commands */ +#define PM_BW_LIMIT_CONFIG 0x4f88 /* Bandwidth throttling on overtemperature */ +#define SC_WDBWM 0x4f8c /* Watermarks and starvation counter config */ -#define MAD_CHNL 0x5000 /* Address Decoder Channel Configuration */ -#define MAD_DIMM_CH0 0x5004 /* Address Decode Channel 0 */ -#define MAD_DIMM_CH1 0x5008 /* Address Decode Channel 1 */ -#define MAD_DIMM_CH2 0x500c /* Address Decode Channel 2 (unused on SNB) */ -#define MAD_ZR 0x5014 /* Address Decode Zones */ -#define MCDECS_SPARE 0x5018 /* Spare register in mcdecs synthesis FUB */ -#define MCDECS_CBIT 0x501c /* Chicken bits in mcdecs synthesis FUB */ +#define MAD_CHNL 0x5000 /* Address Decoder Channel Configuration */ +#define MAD_DIMM_CH0 0x5004 /* Address Decode Channel 0 */ +#define MAD_DIMM_CH1 0x5008 /* Address Decode Channel 1 */ +#define MAD_DIMM_CH2 0x500c /* Address Decode Channel 2 (unused on SNB) */ +#define MAD_ZR 0x5014 /* Address Decode Zones */ +#define MCDECS_SPARE 0x5018 /* Spare register in mcdecs synthesis FUB */ +#define MCDECS_CBIT 0x501c /* Chicken bits in mcdecs synthesis FUB */ -#define CHANNEL_HASH 0x5024 /** WARNING: Only exists on IVB! */ +#define CHANNEL_HASH 0x5024 /** WARNING: Only exists on IVB! */ -#define MC_INIT_STATE_G 0x5030 /* High-level behavior in IOSAV mode */ -#define MRC_REVISION 0x5034 /* MRC Revision */ -#define PM_DLL_CONFIG 0x5064 /* Memory Controller I/O DLL config */ -#define RCOMP_TIMER 0x5084 /* RCOMP evaluation timer register */ +#define MC_INIT_STATE_G 0x5030 /* High-level behavior in IOSAV mode */ +#define MRC_REVISION 0x5034 /* MRC Revision */ +#define PM_DLL_CONFIG 0x5064 /* Memory Controller I/O DLL config */ +#define RCOMP_TIMER 0x5084 /* RCOMP evaluation timer register */ -#define MC_LOCK 0x50fc /* Memory Controlller Lock register */ +#define MC_LOCK 0x50fc /* Memory Controlller Lock register */ -#define VTD1_BASE 0x5400 /* Base address for IGD */ -#define VTD2_BASE 0x5410 /* Base address for PEG, USB, SATA, etc. */ -#define PAIR_CTL 0x5418 /* Power Aware Interrupt Routing Control */ +#define VTD1_BASE 0x5400 /* Base address for IGD */ +#define VTD2_BASE 0x5410 /* Base address for PEG, USB, SATA, etc. */ +#define PAIR_CTL 0x5418 /* Power Aware Interrupt Routing Control */ /* PAVP control register, undocumented. Different from PAVPC on PCI config space. */ -#define MMIO_PAVP_CTL 0x5500 /* Bit 0 locks PAVP settings */ +#define MMIO_PAVP_CTL 0x5500 /* Bit 0 locks PAVP settings */ #define MEM_TRML_ESTIMATION_CONFIG 0x5880 #define MEM_TRML_THRESHOLDS_CONFIG 0x5888 #define MEM_TRML_INTERRUPT 0x58a8 -#define MC_TURBO_PL1 0x59a0 /* Turbo Power Limit 1 parameters */ -#define MC_TURBO_PL2 0x59a4 /* Turbo Power Limit 2 parameters */ +#define MC_TURBO_PL1 0x59a0 /* Turbo Power Limit 1 parameters */ +#define MC_TURBO_PL2 0x59a4 /* Turbo Power Limit 2 parameters */ -#define MC_BIOS_REQ 0x5e00 -#define MC_BIOS_DATA 0x5e04 -#define SSKPD_OK 0x5d10 /* 64-bit scratchpad register */ -#define SSKPD 0x5d14 /* 16bit (scratchpad) */ -#define BIOS_RESET_CPL 0x5da8 /* 8bit */ +#define MC_BIOS_REQ 0x5e00 +#define MC_BIOS_DATA 0x5e04 +#define SSKPD_OK 0x5d10 /* 64-bit scratchpad register */ +#define SSKPD 0x5d14 /* 16bit (scratchpad) */ +#define BIOS_RESET_CPL 0x5da8 /* 8bit */ /* PCODE will sample SAPM-related registers at the end of Phase 4. */ -#define MC_BIOS_REQ 0x5e00 /* Memory frequency request register */ -#define MC_BIOS_DATA 0x5e04 /* Miscellaneous information for BIOS */ -#define SAPMCTL 0x5f00 /* Bit 3 enables DDR EPG (C7i) on IVB */ -#define M_COMP 0x5f08 /* Memory COMP control */ -#define SAPMTIMERS 0x5f10 /* SAPM timers in 10ns (100 MHz) units */ +#define MC_BIOS_REQ 0x5e00 /* Memory frequency request register */ +#define MC_BIOS_DATA 0x5e04 /* Miscellaneous information for BIOS */ +#define SAPMCTL 0x5f00 /* Bit 3 enables DDR EPG (C7i) on IVB */ +#define M_COMP 0x5f08 /* Memory COMP control */ +#define SAPMTIMERS 0x5f10 /* SAPM timers in 10ns (100 MHz) units */ /* WARNING: Only applies to Sandy Bridge! */ -#define BANDTIMERS_SNB 0x5f18 /* MPLL and PPLL time to do self-banding */ +#define BANDTIMERS_SNB 0x5f18 /* MPLL and PPLL time to do self-banding */ /** WARNING: Only applies to Ivy Bridge! */ -#define SAPMTIMERS2_IVB 0x5f18 /** Extra latency for DDRIO EPG exit (C7i) */ -#define BANDTIMERS_IVB 0x5f20 /** MPLL and PPLL time to do self-banding */ +#define SAPMTIMERS2_IVB 0x5f18 /** Extra latency for DDRIO EPG exit (C7i) */ +#define BANDTIMERS_IVB 0x5f20 /** MPLL and PPLL time to do self-banding */ /* * EPBAR - Egress Port Root Complex Register Block -- To view, visit https://review.coreboot.org/c/coreboot/+/38045 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a9b28485f94dee51a937fad8a3c5b58b987958e Gerrit-Change-Number: 38045 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: vc/amd/pi/00670F00: Fix typo in phony target declaration
by Marshall Dawson (Code Review) 05 Jan '20

05 Jan '20

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38145 ) Change subject: vc/amd/pi/00670F00: Fix typo in phony target declaration ...................................................................... vc/amd/pi/00670F00: Fix typo in phony target declaration Correct a copy/paste error for warn_no_agesa. Change-Id: Ife2cca47f1f816f99395b33976d08826c53e3c3e Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/vendorcode/amd/pi/00670F00/Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/38145/1 diff --git a/src/vendorcode/amd/pi/00670F00/Makefile.inc b/src/vendorcode/amd/pi/00670F00/Makefile.inc index c78e15a..f6cd8eb 100644 --- a/src/vendorcode/amd/pi/00670F00/Makefile.inc +++ b/src/vendorcode/amd/pi/00670F00/Makefile.inc @@ -121,7 +121,7 @@ printf "coreboot has been built with no AGESA support. Successfully " printf "booting this image will be impossible.\n\n" -PHONY+=warn_no_amdfw +PHONY+=warn_no_agesa ifeq ($(CONFIG_AGESA_SPLIT_MEMORY_FILES), y) -- To view, visit https://review.coreboot.org/c/coreboot/+/38145 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife2cca47f1f816f99395b33976d08826c53e3c3e Gerrit-Change-Number: 38145 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit January 2020