coreboot-gerrit January 2020

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Change in coreboot[master]: nb/intel/sandybridge: add and use ME stolen memory and lock bit defines
by Felix Held (Code Review) 01 Jan '20

01 Jan '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38012 ) Change subject: nb/intel/sandybridge: add and use ME stolen memory and lock bit defines ...................................................................... nb/intel/sandybridge: add and use ME stolen memory and lock bit defines Change-Id: If4663498b10a5eedcc1aa51088b984ecc49ef23e Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/northbridge/intel/sandybridge/finalize.c M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/sandybridge.h 3 files changed, 5 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/38012/1 diff --git a/src/northbridge/intel/sandybridge/finalize.c b/src/northbridge/intel/sandybridge/finalize.c index 60e7a74..e07c6c2 100644 --- a/src/northbridge/intel/sandybridge/finalize.c +++ b/src/northbridge/intel/sandybridge/finalize.c @@ -24,7 +24,7 @@ pci_or_config16(PCI_DEV_SNB, GGC, 1 << 0); pci_or_config16(PCI_DEV_SNB, PAVPC, 1 << 2); pci_or_config32(PCI_DEV_SNB, DPR, 1 << 0); - pci_or_config32(PCI_DEV_SNB, MESEG_MASK, 1 << 10); + pci_or_config32(PCI_DEV_SNB, MESEG_MASK, MELCK); pci_or_config32(PCI_DEV_SNB, REMAPBASE, 1 << 0); pci_or_config32(PCI_DEV_SNB, REMAPLIMIT, 1 << 0); pci_or_config32(PCI_DEV_SNB, TOM, 1 << 0); diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 5b388de..4e42c71 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -608,8 +608,8 @@ reg = pci_read_config32(PCI_DEV(0, 0, 0), MESEG_MASK); val = (0x80000 - me_uma_size) & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); - reg = reg | (1 << 10); // set lockbit on ME mem - reg = reg | (1 << 11); // set ME memory enable + reg = reg | ME_STLEN_EN; // set ME memory enable + reg = reg | MELCK; // set lockbit on ME mem printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_MASK, reg); pci_write_config32(PCI_DEV(0, 0, 0), MESEG_MASK, reg); } diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 4bb7003..6dcb3ce 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -83,6 +83,8 @@ #define MESEG_BASE 0x70 #define MESEG_MASK 0x78 +#define MELCK (1 << 10) /* ME Range Lock */ +#define ME_STLEN_EN (1 << 11) /* ME Stolen Memory Enable */ #define PAM0 0x80 #define PAM1 0x81 -- To view, visit https://review.coreboot.org/c/coreboot/+/38012 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4663498b10a5eedcc1aa51088b984ecc49ef23e Gerrit-Change-Number: 38012 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/sandybridge: remove unused duplicate PCIEXBAR define X60BAR
by Felix Held (Code Review) 01 Jan '20

01 Jan '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38011 ) Change subject: nb/intel/sandybridge: remove unused duplicate PCIEXBAR define X60BAR ...................................................................... nb/intel/sandybridge: remove unused duplicate PCIEXBAR define X60BAR Change-Id: Ie5a28ceb3d1b684b9c94dcae5b303a4dce75f273 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/northbridge/intel/sandybridge/sandybridge.h 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/38011/1 diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 9ad3551..4bb7003 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -65,7 +65,6 @@ #define MCHBAR 0x48 #define PCIEXBAR 0x60 #define DMIBAR 0x68 -#define X60BAR 0x60 #define GGC 0x50 /* GMCH Graphics Control */ -- To view, visit https://review.coreboot.org/c/coreboot/+/38011 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie5a28ceb3d1b684b9c94dcae5b303a4dce75f273 Gerrit-Change-Number: 38011 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/sandybridge: add and use more MCHBAR register defines
by Felix Held (Code Review) 01 Jan '20

01 Jan '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38010 ) Change subject: nb/intel/sandybridge: add and use more MCHBAR register defines ...................................................................... nb/intel/sandybridge: add and use more MCHBAR register defines Change-Id: Ie0a9be0899830a2bf9a994d10c417b0968d1cd47 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/raminit_mrc.c M src/northbridge/intel/sandybridge/sandybridge.h 4 files changed, 30 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/38010/1 diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index c13ae37..0362330 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -101,9 +101,9 @@ u32 addr_decoder_common, addr_decode_ch[NUM_CHANNELS]; int i, refclk; - addr_decoder_common = MCHBAR32(0x5000); - addr_decode_ch[0] = MCHBAR32(0x5004); - addr_decode_ch[1] = MCHBAR32(0x5008); + addr_decoder_common = MCHBAR32(MAD_CHNL); + addr_decode_ch[0] = MCHBAR32(MAD_DIMM_CH0); + addr_decode_ch[1] = MCHBAR32(MAD_DIMM_CH1); refclk = MCHBAR32(MC_BIOS_REQ) & 0x100 ? 100 : 133; diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 0ba1678..5b388de 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -229,8 +229,8 @@ reg |= (ctrl->CAS << 8); reg |= (ctrl->CWL << 12); reg |= (ctrl->tRAS << 16); - printram("DBP [%x] = %x\n", 0x400 * channel + 0x4000, reg); - MCHBAR32(0x400 * channel + 0x4000) = reg; + printram("DBP [%x] = %x\n", TC_DBP_C0 + 0x400 * channel, reg); + MCHBAR32(TC_DBP_C0 + 0x400 * channel) = reg; // RAP reg = 0; @@ -241,8 +241,8 @@ reg |= (ctrl->tFAW << 16); reg |= (ctrl->tWR << 24); reg |= (3 << 30); - printram("RAP [%x] = %x\n", 0x400 * channel + 0x4004, reg); - MCHBAR32(0x400 * channel + 0x4004) = reg; + printram("RAP [%x] = %x\n", TC_RAP_C0 + 0x400 * channel, reg); + MCHBAR32(TC_RAP_C0 + 0x400 * channel) = reg; // OTHP addr = 0x400 * channel + 0x400c; @@ -271,10 +271,10 @@ reg = ((ctrl->tREFI & 0xffff) << 0) | ((ctrl->tRFC & 0x1ff) << 16) | (((val32 / 1024) & 0x7f) << 25); - printram("REFI [%x] = %x\n", 0x400 * channel + 0x4298, reg); - MCHBAR32(0x400 * channel + 0x4298) = reg; + printram("REFI [%x] = %x\n", TC_RFTP_C0 + 0x400 * channel, reg); + MCHBAR32(TC_RFTP_C0 + 0x400 * channel) = reg; - MCHBAR32_OR(0x400 * channel + 0x4294, 0xff); + MCHBAR32_OR(TC_RFP_C0 + 0x400 * channel, 0xff); // SRFTP reg = 0; @@ -340,7 +340,7 @@ { int channel; FOR_ALL_CHANNELS { - MCHBAR32(0x5004 + channel * 4) = ctrl->mad_dimm[channel]; + MCHBAR32(MAD_DIMM_CH0 + channel * 4) = ctrl->mad_dimm[channel]; } } @@ -364,14 +364,14 @@ reg = (reg & ~0xff000000) | val << 24; reg = (reg & ~0xff0000) | (2 * val) << 16; MCHBAR32(0x5014) = reg; - MCHBAR32(0x5000) = 0x24; + MCHBAR32(MAD_CHNL) = 0x24; } else { reg = MCHBAR32(0x5014); val = ch0size / 256; reg = (reg & ~0xff000000) | val << 24; reg = (reg & ~0xff0000) | (2 * val) << 16; MCHBAR32(0x5014) = reg; - MCHBAR32(0x5000) = 0x21; + MCHBAR32(MAD_CHNL) = 0x21; } } @@ -926,7 +926,7 @@ void program_timings(ramctr_timing * ctrl, int channel) { - u32 reg32, reg_4024, reg_c14, reg_c18, reg_4028; + u32 reg32, reg_4024, reg_c14, reg_c18, reg_io_latency; int lane; int slotrank, slot; int full_shift = 0; @@ -988,8 +988,8 @@ MCHBAR32(0xc14 + channel * 0x100) = reg_c14; MCHBAR32(0xc18 + channel * 0x100) = reg_c18; - reg_4028 = MCHBAR32(0x4028 + 0x400 * channel); - reg_4028 &= 0xffff0000; + reg_io_latency = MCHBAR32(SC_IO_LATENCY_C0 + 0x400 * channel); + reg_io_latency &= 0xffff0000; reg_4024 = 0; @@ -1025,7 +1025,7 @@ post_timA_max_high - post_timA_min_high) shift_402x = -1; - reg_4028 |= + reg_io_latency |= (ctrl->timings[channel][slotrank].val_4028 + shift_402x - post_timA_min_high) << (4 * slotrank); reg_4024 |= @@ -1065,7 +1065,7 @@ } } MCHBAR32(0x4024 + 0x400 * channel) = reg_4024; - MCHBAR32(0x4028 + 0x400 * channel) = reg_4028; + MCHBAR32(SC_IO_LATENCY_C0 + 0x400 * channel) = reg_io_latency; } static void test_timA(ramctr_timing * ctrl, int channel, int slotrank) @@ -3169,7 +3169,7 @@ MCHBAR32_AND(0x58a8, ~0x1f); FOR_ALL_CHANNELS - MCHBAR32_AND_OR(0x4294 + 0x400 * channel, ~0x30000, 1 << 16); + MCHBAR32_AND_OR(TC_RFP_C0 + 0x400 * channel, ~0x30000, 1 << 16); MCHBAR32_OR(0x5030, 1); MCHBAR32_OR(0x5030, 0x80); diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 84100e7..cab5588 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -149,9 +149,9 @@ u32 addr_decoder_common, addr_decode_ch[2]; int i; - addr_decoder_common = MCHBAR32(0x5000); - addr_decode_ch[0] = MCHBAR32(0x5004); - addr_decode_ch[1] = MCHBAR32(0x5008); + addr_decoder_common = MCHBAR32(MAD_CHNL); + addr_decode_ch[0] = MCHBAR32(MAD_DIMM_CH0); + addr_decode_ch[1] = MCHBAR32(MAD_DIMM_CH1); printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", (MCHBAR32(0x5e04) * 13333 * 2 + 50)/100); diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index a0fcb10..9ad3551 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -127,7 +127,15 @@ #define MCHBAR32_AND_OR(x, and, or) \ (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or)) +#define TC_DBP_C0 0x4000 /* Timing of DDR - bin parameters */ +#define TC_RAP_C0 0x4004 /* Timing of DDR - regular access parameters */ +#define SC_IO_LATENCY_C0 0x4028 /* IO Latency Configuration */ +#define TC_RFP_C0 0x4294 /* Refresh Parameters */ +#define TC_RFTP_C0 0x4298 /* Refresh Timing Parameters */ #define PM_PDWN_Config 0x4cb0 +#define MAD_CHNL 0x5000 /* Address Decoder Channel Configuration */ +#define MAD_DIMM_CH0 0x5004 /* Address Decode Channel 0 */ +#define MAD_DIMM_CH1 0x5008 /* Address Decode Channel 1 */ #define MC_BIOS_REQ 0x5e00 #define MC_BIOS_DATA 0x5e04 #define SSKPD 0x5d14 /* 16bit (scratchpad) */ -- To view, visit https://review.coreboot.org/c/coreboot/+/38010 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie0a9be0899830a2bf9a994d10c417b0968d1cd47 Gerrit-Change-Number: 38010 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/sandybridge: move MCHBAR register definitions to sandybridge.h
by Felix Held (Code Review) 01 Jan '20

01 Jan '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38009 ) Change subject: nb/intel/sandybridge: move MCHBAR register definitions to sandybridge.h ...................................................................... nb/intel/sandybridge: move MCHBAR register definitions to sandybridge.h Change-Id: Ibce9f043d3b3fa9acd297f4130bda7a3c595aaa0 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/northbridge/intel/sandybridge/raminit_common.h M src/northbridge/intel/sandybridge/sandybridge.h 2 files changed, 5 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/38009/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index 317071c..6bbc8b3 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -149,10 +149,6 @@ #define MAKE_ERR ((channel<<16)|(slotrank<<8)|1) #define GET_ERR_CHANNEL(x) (x>>16) -#define MC_BIOS_REQ 0x5e00 -#define MC_BIOS_DATA 0x5e04 -#define PM_PDWN_Config 0x4cb0 - u8 get_CWL(u32 tCK); void dram_mrscommands(ramctr_timing * ctrl); void program_timings(ramctr_timing * ctrl, int channel); diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 6a9c00f..a0fcb10 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -127,8 +127,11 @@ #define MCHBAR32_AND_OR(x, and, or) \ (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or)) -#define SSKPD 0x5d14 /* 16bit (scratchpad) */ -#define BIOS_RESET_CPL 0x5da8 /* 8bit */ +#define PM_PDWN_Config 0x4cb0 +#define MC_BIOS_REQ 0x5e00 +#define MC_BIOS_DATA 0x5e04 +#define SSKPD 0x5d14 /* 16bit (scratchpad) */ +#define BIOS_RESET_CPL 0x5da8 /* 8bit */ /* * EPBAR - Egress Port Root Complex Register Block -- To view, visit https://review.coreboot.org/c/coreboot/+/38009 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibce9f043d3b3fa9acd297f4130bda7a3c595aaa0 Gerrit-Change-Number: 38009 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/sandybridge: use MESEG register names from datasheet
by Felix Held (Code Review) 01 Jan '20

01 Jan '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38008 ) Change subject: nb/intel/sandybridge: use MESEG register names from datasheet ...................................................................... nb/intel/sandybridge: use MESEG register names from datasheet I used register names guessed on what the registers do, since the SNB documentation marked those registers as reserved; the IVB documentation (326765-005) has names for the registers, so I'll use those. Change-Id: I2f1194438a56546d9836dd12635d064a900a2fd8 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/northbridge/intel/sandybridge/finalize.c M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/sandybridge.h 3 files changed, 15 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/38008/1 diff --git a/src/northbridge/intel/sandybridge/finalize.c b/src/northbridge/intel/sandybridge/finalize.c index fc970ba..60e7a74 100644 --- a/src/northbridge/intel/sandybridge/finalize.c +++ b/src/northbridge/intel/sandybridge/finalize.c @@ -24,7 +24,7 @@ pci_or_config16(PCI_DEV_SNB, GGC, 1 << 0); pci_or_config16(PCI_DEV_SNB, PAVPC, 1 << 2); pci_or_config32(PCI_DEV_SNB, DPR, 1 << 0); - pci_or_config32(PCI_DEV_SNB, MEMASK, 1 << 10); + pci_or_config32(PCI_DEV_SNB, MESEG_MASK, 1 << 10); pci_or_config32(PCI_DEV_SNB, REMAPBASE, 1 << 0); pci_or_config32(PCI_DEV_SNB, REMAPLIMIT, 1 << 0); pci_or_config32(PCI_DEV_SNB, TOM, 1 << 0); diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index b12ea25..0ba1678 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -585,33 +585,33 @@ pci_write_config32(PCI_DEV(0, 0, 0), BGSM, reg); if (me_uma_size) { - reg = pci_read_config32(PCI_DEV(0, 0, 0), MEMASK + 4); + reg = pci_read_config32(PCI_DEV(0, 0, 0), MESEG_MASK + 4); val = (0x80000 - me_uma_size) & 0xfffff000; reg = (reg & ~0x000fffff) | (val >> 12); - printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MEMASK + 4, reg); - pci_write_config32(PCI_DEV(0, 0, 0), MEMASK + 4, reg); + printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_MASK + 4, reg); + pci_write_config32(PCI_DEV(0, 0, 0), MESEG_MASK + 4, reg); // ME base - reg = pci_read_config32(PCI_DEV(0, 0, 0), MEBASE); + reg = pci_read_config32(PCI_DEV(0, 0, 0), MESEG_BASE); val = mestolenbase & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); - printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MEBASE, reg); - pci_write_config32(PCI_DEV(0, 0, 0), MEBASE, reg); + printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_BASE, reg); + pci_write_config32(PCI_DEV(0, 0, 0), MESEG_BASE, reg); - reg = pci_read_config32(PCI_DEV(0, 0, 0), MEBASE + 4); + reg = pci_read_config32(PCI_DEV(0, 0, 0), MESEG_BASE + 4); val = mestolenbase & 0xfffff000; reg = (reg & ~0x000fffff) | (val >> 12); - printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MEBASE + 4, reg); - pci_write_config32(PCI_DEV(0, 0, 0), MEBASE + 4, reg); + printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_BASE + 4, reg); + pci_write_config32(PCI_DEV(0, 0, 0), MESEG_BASE + 4, reg); // ME mask - reg = pci_read_config32(PCI_DEV(0, 0, 0), MEMASK); + reg = pci_read_config32(PCI_DEV(0, 0, 0), MESEG_MASK); val = (0x80000 - me_uma_size) & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); reg = reg | (1 << 10); // set lockbit on ME mem reg = reg | (1 << 11); // set ME memory enable - printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MEMASK, reg); - pci_write_config32(PCI_DEV(0, 0, 0), MEMASK, reg); + printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_MASK, reg); + pci_write_config32(PCI_DEV(0, 0, 0), MESEG_MASK, reg); } } diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 6bfe88b..6a9c00f 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -82,8 +82,8 @@ #define PAVPC 0x58 /* Protected Audio Video Path Control */ #define DPR 0x5c /* DMA Protected Range */ -#define MEBASE 0x70 -#define MEMASK 0x78 +#define MESEG_BASE 0x70 +#define MESEG_MASK 0x78 #define PAM0 0x80 #define PAM1 0x81 -- To view, visit https://review.coreboot.org/c/coreboot/+/38008 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f1194438a56546d9836dd12635d064a900a2fd8 Gerrit-Change-Number: 38008 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/stoneyridge: Change default locations for blobs
by Marshall Dawson (Code Review) 01 Jan '20

01 Jan '20

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37222 ) Change subject: soc/amd/stoneyridge: Change default locations for blobs ...................................................................... soc/amd/stoneyridge: Change default locations for blobs Set the default location strings to point to the 3rdparty/amd_blobs files. Change-Id: I5426b8de2501ba55843efc1cda4b03bc3768f8cb Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/Kconfig M src/vendorcode/amd/pi/Kconfig 2 files changed, 9 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/37222/1 diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index c477e03..2fe3ef7 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -177,8 +177,8 @@ config VGA_BIOS_FILE string default "" if !USE_AMD_BLOBS - default "3rdparty/blobs/soc/amd/merlinfalcon/VBIOS.bin" if AMD_APU_MERLINFALCON - default "3rdparty/blobs/soc/amd/stoneyridge/VBIOS.bin" + default "3rdparty/amd_blobs/stoneyridge/CarrizoGenericVbios.bin" if AMD_APU_MERLINFALCON + default "3rdparty/amd_blobs/stoneyridge/StoneyGenericVbios.bin" config S3_VGA_ROM_RUN bool @@ -218,7 +218,7 @@ config STONEYRIDGE_XHCI_FWM_FILE string "XHCI firmware path and filename" default "" if !USE_AMD_BLOBS - default "3rdparty/blobs/soc/amd/stoneyridge/xhci.bin" + default "3rdparty/amd_blobs/stoneyridge/xhci.bin" depends on STONEYRIDGE_XHCI_FWM config STONEYRIDGE_GEC_FWM_FILE @@ -228,8 +228,8 @@ config AMD_PUBKEY_FILE string "AMD public Key" default "" if !USE_AMD_BLOBS - default "3rdparty/blobs/soc/amd/merlinfalcon/PSP/AmdPubKeyCZ.bin" if AMD_APU_MERLINFALCON - default "3rdparty/blobs/soc/amd/stoneyridge/PSP/AmdPubKeyST.bin" + default "3rdparty/amd_blobs/stoneyridge/PSP/CZ/AmdPubKeyCZ.bin" if AMD_APU_MERLINFALCON + default "3rdparty/amd_blobs/stoneyridge/PSP/ST/AmdPubKeyST.bin" config STONEYRIDGE_SATA_MODE int "SATA Mode" diff --git a/src/vendorcode/amd/pi/Kconfig b/src/vendorcode/amd/pi/Kconfig index 0605563..9f5d94d 100644 --- a/src/vendorcode/amd/pi/Kconfig +++ b/src/vendorcode/amd/pi/Kconfig @@ -44,10 +44,10 @@ string "AGESA PI binary file name" default "3rdparty/blobs/pi/amd/00630F01/FP3/AGESA.bin" if CPU_AMD_PI_00630F01 default "3rdparty/blobs/pi/amd/00730F01/FT3b/AGESA.bin" if CPU_AMD_PI_00730F01 - default "3rdparty/blobs/pi/amd/merlinfalcon/$(CONFIG_AMD_SOC_PACKAGE)/AGESA_CZ_FP4.bin" if SOC_AMD_MERLINFALCON && HAVE_MERLINFALCON_BINARIES - default "3rdparty/blobs/pi/amd/00670F00/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_MERLINFALCON && !HAVE_MERLINFALCON_BINARIES - default "3rdparty/blobs/pi/amd/00670F00/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_STONEYRIDGE_FP4 - default "3rdparty/blobs/pi/amd/00670F00/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_STONEYRIDGE_FT4 + default "3rdparty/amd_blobs/stoneyridge/pi/ST/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_MERLINFALCON && HAVE_MERLINFALCON_BINARIES + default "3rdparty/amd_blobs/stoneyridge/pi/CZ/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_MERLINFALCON + default "3rdparty/amd_blobs/stoneyridge/pi/ST/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_STONEYRIDGE_FP4 + default "3rdparty/amd_blobs/stoneyridge/pi/ST/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_STONEYRIDGE_FT4 default "3rdparty/blobs/pi/amd/00660F01/FP4/AGESA.bin" if CPU_AMD_PI_00660F01 help Specify the binary file to use for AMD platform initialization. -- To view, visit https://review.coreboot.org/c/coreboot/+/37222 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5426b8de2501ba55843efc1cda4b03bc3768f8cb Gerrit-Change-Number: 37222 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit January 2020