coreboot-gerrit January 2020

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Change in coreboot[master]: mainboard/google/puff: Enable rtd2142 i2c driver in dt
by Edward O'Callaghan (Code Review) 02 Jan '20

02 Jan '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37905 ) Change subject: mainboard/google/puff: Enable rtd2142 i2c driver in dt ...................................................................... mainboard/google/puff: Enable rtd2142 i2c driver in dt BUG=b:142769041 BRANCH=none TEST=builds Change-Id: Ib885b6f229a016e100256597216a930be27fb4b5 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M src/mainboard/google/hatch/variants/puff/overridetree.cb 1 file changed, 3 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/37905/1 diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb index a24d7fc..15568ea 100644 --- a/src/mainboard/google/hatch/variants/puff/overridetree.cb +++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb @@ -154,11 +154,9 @@ device pci 15.1 off end # I2C #1 device pci 15.2 on end # I2C #2, PCON PS175. device pci 15.3 on -# chip drivers/i2c/generic -# register "name" = ""RTD21"" -# register "desc" = ""Realtek RTD2142"" -# device i2c 4a on end -# end + chip drivers/i2c/rtd2142 + device i2c 4a on end + end end # I2C #3 device pci 19.0 on chip drivers/i2c/generic -- To view, visit https://review.coreboot.org/c/coreboot/+/37905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib885b6f229a016e100256597216a930be27fb4b5 Gerrit-Change-Number: 37905 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/i2c: Add rtd2142 stub driver
by Edward O'Callaghan (Code Review) 02 Jan '20

02 Jan '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37904 ) Change subject: drivers/i2c: Add rtd2142 stub driver ...................................................................... drivers/i2c: Add rtd2142 stub driver Currently this driver is a nop however forms the boilerplate for the required support. BUG=b:142769041 BRANCH=none TEST=builds Change-Id: I1716e6f186a097b309504762017b98747972547c Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- A src/drivers/i2c/rtd2142/Kconfig A src/drivers/i2c/rtd2142/Makefile.inc A src/drivers/i2c/rtd2142/chip.h A src/drivers/i2c/rtd2142/rtd2142.c 4 files changed, 75 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/37904/1 diff --git a/src/drivers/i2c/rtd2142/Kconfig b/src/drivers/i2c/rtd2142/Kconfig new file mode 100644 index 0000000..614df35 --- /dev/null +++ b/src/drivers/i2c/rtd2142/Kconfig @@ -0,0 +1,5 @@ +config DRIVERS_I2C_RTD2142 + bool + default n + help + Enable support for Realtek RTD2142 DisplayPort MST bridge chip. diff --git a/src/drivers/i2c/rtd2142/Makefile.inc b/src/drivers/i2c/rtd2142/Makefile.inc new file mode 100644 index 0000000..df9edae --- /dev/null +++ b/src/drivers/i2c/rtd2142/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_I2C_RTD2142) += rtd2142.c diff --git a/src/drivers/i2c/rtd2142/chip.h b/src/drivers/i2c/rtd2142/chip.h new file mode 100644 index 0000000..182b1b7 --- /dev/null +++ b/src/drivers/i2c/rtd2142/chip.h @@ -0,0 +1,15 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +struct drivers_i2c_rtd2142_config { +}; diff --git a/src/drivers/i2c/rtd2142/rtd2142.c b/src/drivers/i2c/rtd2142/rtd2142.c new file mode 100644 index 0000000..580a6b8 --- /dev/null +++ b/src/drivers/i2c/rtd2142/rtd2142.c @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/smbus.h> +#include <device/pci.h> + +#include "chip.h" + +static void rtd2142_setup(struct device *dev) +{ + struct drivers_i2c_rtd2142_config *config = dev->chip_info; + + if (!config) + return; + + /* nop */ +} + +static void rtd2142_init(struct device *dev) +{ + if (dev->enabled && dev->path.type == DEVICE_PATH_I2C && + ops_smbus_bus(get_pbus_smbus(dev))) { + rtd2142_setup(dev); + } +} + +static struct device_operations rtd2142_operations = { + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, + .init = rtd2142_init, +}; + +static void enable_dev(struct device *dev) +{ + dev->ops = &rtd2142_operations; +} + +struct chip_operations drivers_i2c_rtd2142_ops = { + CHIP_NAME("Realtek RTD2142 MST") + .enable_dev = enable_dev, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/37904 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1716e6f186a097b309504762017b98747972547c Gerrit-Change-Number: 37904 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: {sb,lynxpoint,soc/broadwell}: Drop _HID and _UID
by HAOUAS Elyes (Code Review) 02 Jan '20

02 Jan '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38052 ) Change subject: {sb,lynxpoint,soc/broadwell}: Drop _HID and _UID ...................................................................... {sb,lynxpoint,soc/broadwell}: Drop _HID and _UID A device object must contain either a _HID object or an _ADR object, but should not contain both. If the adress is correct, _HID and _UID are not needed Change-Id: I687b77e93ed52ad4d909a176277a4f23d700cf06 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/broadwell/acpi/serialio.asl M src/southbridge/intel/lynxpoint/acpi/serialio.asl 2 files changed, 14 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/38052/1 diff --git a/src/soc/intel/broadwell/acpi/serialio.asl b/src/soc/intel/broadwell/acpi/serialio.asl index 1b44e95..ed47284 100644 --- a/src/soc/intel/broadwell/acpi/serialio.asl +++ b/src/soc/intel/broadwell/acpi/serialio.asl @@ -156,9 +156,7 @@ Device (SDMA) { - // Serial IO DMA Controller - Name (_HID, "INTL9C60") - Name (_UID, 1) + Name (_DDN, "Serial IO DMA Controller") Name (_ADR, 0x00150000) // BAR0 is assigned during PCI enumeration and saved into NVS @@ -193,8 +191,7 @@ Device (I2C0) { - // Serial IO I2C0 Controller - Method (_HID) + Name (_DDN, "Serial IO I2C0 Controller") { If (\ISWP ()) { // WildcatPoint @@ -204,7 +201,6 @@ // LynxPoint-LP Return ("INT33C2") } - Name (_UID, 1) Name (_ADR, 0x00150001) Name (SSCN, Package () { 432, 507, 30 }) @@ -264,8 +260,7 @@ Device (I2C1) { - // Serial IO I2C1 Controller - Method (_HID) + Name (_DDN, "Serial IO I2C1 Controller") { If (\ISWP ()) { // WildcatPoint @@ -275,7 +270,6 @@ // LynxPoint-LP Return ("INT33C3") } - Name (_UID, 1) Name (_ADR, 0x00150002) Name (SSCN, Package () { 432, 507, 30 }) @@ -335,8 +329,7 @@ Device (SPI0) { - // Serial IO SPI0 Controller - Method (_HID) + Name (_DDN, "Serial IO SPI0 Controller") { If (\ISWP ()) { // WildcatPoint @@ -346,7 +339,6 @@ // LynxPoint-LP Return ("INT33C0") } - Name (_UID, 1) Name (_ADR, 0x00150003) // BAR0 is assigned during PCI enumeration and saved into NVS @@ -391,8 +383,7 @@ Device (SPI1) { - // Serial IO SPI1 Controller - Method (_HID) + Name (_DDN, "Serial IO SPI1 Controller") { If (\ISWP ()) { // WildcatPoint @@ -402,7 +393,6 @@ // LynxPoint-LP Return ("INT33C1") } - Name (_UID, 1) Name (_ADR, 0x00150004) // BAR0 is assigned during PCI enumeration and saved into NVS @@ -459,8 +449,7 @@ Device (UAR0) { - // Serial IO UART0 Controller - Method (_HID) + Name (_DDN, "Serial IO UART0 Controller") { If (\ISWP ()) { // WildcatPoint @@ -470,7 +459,6 @@ // LynxPoint-LP Return ("INT33C4") } - Name (_UID, 1) Name (_ADR, 0x00150005) // BAR0 is assigned during PCI enumeration and saved into NVS @@ -527,8 +515,7 @@ Device (UAR1) { - // Serial IO UART1 Controller - Method (_HID) + Name (_DDN, "Serial IO UART1 Controller") { If (\ISWP ()) { // WildcatPoint @@ -538,7 +525,6 @@ // LynxPoint-LP Return ("INT33C5") } - Name (_UID, 1) Name (_ADR, 0x00150006) // BAR0 is assigned during PCI enumeration and saved into NVS diff --git a/src/southbridge/intel/lynxpoint/acpi/serialio.asl b/src/southbridge/intel/lynxpoint/acpi/serialio.asl index 9323b91..970e777 100644 --- a/src/southbridge/intel/lynxpoint/acpi/serialio.asl +++ b/src/southbridge/intel/lynxpoint/acpi/serialio.asl @@ -122,9 +122,7 @@ Device (SDMA) { - // Serial IO DMA Controller - Name (_HID, "INTL9C60") - Name (_UID, 1) + Name (_DDN, "Serial IO DMA Controller") Name (_ADR, 0x00150000) // BAR0 is assigned during PCI enumeration and saved into NVS @@ -159,10 +157,8 @@ Device (I2C0) { - // Serial IO I2C0 Controller - Name (_HID, "INT33C2") + Name (_DDN, "Serial IO I2C0 Controller") Name (_CID, "INT33C2") - Name (_UID, 1) Name (_ADR, 0x00150001) Name (SSCN, Package () { 432, 507, 30 }) @@ -241,10 +237,8 @@ Device (I2C1) { - // Serial IO I2C1 Controller - Name (_HID, "INT33C3") + Name (_DDN, "Serial IO I2C1 Controller") Name (_CID, "INT33C3") - Name (_UID, 1) Name (_ADR, 0x00150002) Name (SSCN, Package () { 432, 507, 30 }) @@ -323,10 +317,8 @@ Device (SPI0) { - // Serial IO SPI0 Controller - Name (_HID, "INT33C0") + Name (_DDN, "Serial IO SPI0 Controller") Name (_CID, "INT33C0") - Name (_UID, 1) Name (_ADR, 0x00150003) // BAR0 is assigned during PCI enumeration and saved into NVS @@ -361,10 +353,8 @@ Device (SPI1) { - // Serial IO SPI1 Controller - Name (_HID, "INT33C1") + Name (_DDN, "Serial IO SPI1 Controller") Name (_CID, "INT33C1") - Name (_UID, 1) Name (_ADR, 0x00150004) // BAR0 is assigned during PCI enumeration and saved into NVS @@ -412,10 +402,8 @@ Device (UAR0) { - // Serial IO UART0 Controller - Name (_HID, "INT33C4") + Name (_DDN, "Serial IO UART0 Controller") Name (_CID, "INT33C4") - Name (_UID, 1) Name (_ADR, 0x00150005) // BAR0 is assigned during PCI enumeration and saved into NVS @@ -463,10 +451,8 @@ Device (UAR1) { - // Serial IO UART1 Controller - Name (_HID, "INT33C5") + Name (_DDN, "Serial IO UART1 Controller") Name (_CID, "INT33C5") - Name (_UID, 1) Name (_ADR, 0x00150006) // BAR0 is assigned during PCI enumeration and saved into NVS -- To view, visit https://review.coreboot.org/c/coreboot/+/38052 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I687b77e93ed52ad4d909a176277a4f23d700cf06 Gerrit-Change-Number: 38052 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/broadwell: Drop _HID and _UID
by HAOUAS Elyes (Code Review) 02 Jan '20

02 Jan '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38053 ) Change subject: soc/intel/broadwell: Drop _HID and _UID ...................................................................... soc/intel/broadwell: Drop _HID and _UID A device object must contain either a _HID object or an _ADR object, but should not contain both. If the adress is correct, _HID and _UID are not needed. Change-Id: I46a3acc3a56bdc34079fa7eb256801baa7f778b9 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/broadwell/acpi/serialio.asl 1 file changed, 7 insertions(+), 75 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/38053/1 diff --git a/src/soc/intel/broadwell/acpi/serialio.asl b/src/soc/intel/broadwell/acpi/serialio.asl index 1b44e95..e0245ed 100644 --- a/src/soc/intel/broadwell/acpi/serialio.asl +++ b/src/soc/intel/broadwell/acpi/serialio.asl @@ -156,9 +156,7 @@ Device (SDMA) { - // Serial IO DMA Controller - Name (_HID, "INTL9C60") - Name (_UID, 1) + Name (_DDN, "Serial IO DMA Controller") Name (_ADR, 0x00150000) // BAR0 is assigned during PCI enumeration and saved into NVS @@ -193,18 +191,7 @@ Device (I2C0) { - // Serial IO I2C0 Controller - Method (_HID) - { - If (\ISWP ()) { - // WildcatPoint - Return ("INT3432") - } - - // LynxPoint-LP - Return ("INT33C2") - } - Name (_UID, 1) + Name (_DDN, "Serial IO I2C0 Controller") Name (_ADR, 0x00150001) Name (SSCN, Package () { 432, 507, 30 }) @@ -264,18 +251,7 @@ Device (I2C1) { - // Serial IO I2C1 Controller - Method (_HID) - { - If (\ISWP ()) { - // WildcatPoint - Return ("INT3433") - } - - // LynxPoint-LP - Return ("INT33C3") - } - Name (_UID, 1) + Name (_DDN, "Serial IO I2C1 Controller") Name (_ADR, 0x00150002) Name (SSCN, Package () { 432, 507, 30 }) @@ -335,18 +311,7 @@ Device (SPI0) { - // Serial IO SPI0 Controller - Method (_HID) - { - If (\ISWP ()) { - // WildcatPoint - Return ("INT3430") - } - - // LynxPoint-LP - Return ("INT33C0") - } - Name (_UID, 1) + Name (_DDN, "Serial IO SPI0 Controller") Name (_ADR, 0x00150003) // BAR0 is assigned during PCI enumeration and saved into NVS @@ -391,18 +356,7 @@ Device (SPI1) { - // Serial IO SPI1 Controller - Method (_HID) - { - If (\ISWP ()) { - // WildcatPoint - Return ("INT3431") - } - - // LynxPoint-LP - Return ("INT33C1") - } - Name (_UID, 1) + Name (_DDN, "Serial IO SPI1 Controller") Name (_ADR, 0x00150004) // BAR0 is assigned during PCI enumeration and saved into NVS @@ -459,18 +413,7 @@ Device (UAR0) { - // Serial IO UART0 Controller - Method (_HID) - { - If (\ISWP ()) { - // WildcatPoint - Return ("INT3434") - } - - // LynxPoint-LP - Return ("INT33C4") - } - Name (_UID, 1) + Name (_DDN, "Serial IO UART0 Controller") Name (_ADR, 0x00150005) // BAR0 is assigned during PCI enumeration and saved into NVS @@ -527,18 +470,7 @@ Device (UAR1) { - // Serial IO UART1 Controller - Method (_HID) - { - If (\ISWP ()) { - // WildcatPoint - Return ("INT3435") - } - - // LynxPoint-LP - Return ("INT33C5") - } - Name (_UID, 1) + Name (_DDN, "Serial IO UART1 Controller") Name (_ADR, 0x00150006) // BAR0 is assigned during PCI enumeration and saved into NVS -- To view, visit https://review.coreboot.org/c/coreboot/+/38053 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I46a3acc3a56bdc34079fa7eb256801baa7f778b9 Gerrit-Change-Number: 38053 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/skylake/fsp: enable PCIe Advanced Error Reporting (AER) by default
by Michael Niewöhner (Code Review) 01 Jan '20

01 Jan '20

Michael Niewöhner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35745 ) Change subject: soc/skylake/fsp: enable PCIe Advanced Error Reporting (AER) by default ...................................................................... soc/skylake/fsp: enable PCIe Advanced Error Reporting (AER) by default PCIe Advanced Error Reporting (AER) povides better error reporting for PCIe devices/buses. This is enabled on most modern machines, so we should do the same and enable it by default. Tested on X11SSM-F Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Change-Id: I172329d8d42c3be02e64300675d646edfbee8b72 --- M src/mainboard/asrock/h110m/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/soc/intel/skylake/chip_fsp20.c 11 files changed, 3 insertions(+), 41 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/35745/1 diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 572cd6a..ed3cef8 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -222,8 +222,6 @@ register "PcieRpClkReqSupport[5]" = "1" # Use SRCCLKREQ1# register "PcieRpClkReqNumber[5]" = "1" - # Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[5]" = "1" # Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[5]" = "1" # Use CLK SRC 1 @@ -235,8 +233,6 @@ register "PcieRpClkReqSupport[4]" = "1" # Use SRCCLKREQ2# register "PcieRpClkReqNumber[4]" = "2" - # Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[4]" = "1" # Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[4]" = "1" # Use CLK SRC 2 @@ -250,8 +246,6 @@ register "PcieRpClkReqSupport[6]" = "1" # Use SRCCLKREQ3# register "PcieRpClkReqNumber[6]" = "3" - # Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[6]" = "1" # Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[6]" = "1" # Use CLK SRC 3 diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index 50f9114..4669034 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -148,7 +148,6 @@ register "PcieRpEnable[0]" = "1" register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqNumber[0]" = "1" - register "PcieRpAdvancedErrorReporting[0]" = "1" register "PcieRpLtrEnable[0]" = "1" register "PcieRpHotPlug[0]" = "1" #RP 1 uses CLK SRC 1 @@ -158,7 +157,6 @@ register "PcieRpEnable[4]" = "1" register "PcieRpClkReqSupport[4]" = "1" register "PcieRpClkReqNumber[4]" = "4" - register "PcieRpAdvancedErrorReporting[4]" = "1" register "PcieRpLtrEnable[4]" = "1" #RP 5 uses CLK SRC 4 register "PcieRpClkSrcNumber[4]" = "4" diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index c1afe3d..7a5ca10 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -187,8 +187,6 @@ register "PcieRpClkReqSupport[2]" = "1" # RP 3 uses SRCCLKREQ0# register "PcieRpClkReqNumber[2]" = "0" - # RP 3, Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[2]" = "1" # RP 3, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[2]" = "1" # RP 3 uses uses CLK SRC 0 @@ -200,8 +198,6 @@ register "PcieRpClkReqSupport[3]" = "1" # RP 4 uses SRCCLKREQ5# register "PcieRpClkReqNumber[3]" = "5" - # RP 4, Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[3]" = "1" # RP 4, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[3]" = "1" # RP 4 uses uses CLK SRC 5 @@ -213,8 +209,6 @@ register "PcieRpClkReqSupport[4]" = "1" # RP 5 uses SRCCLKREQ1# register "PcieRpClkReqNumber[4]" = "1" - # RP 5, Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[4]" = "1" # RP 5, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[4]" = "1" # RP 5 uses CLK SRC 1 @@ -226,8 +220,6 @@ register "PcieRpClkReqSupport[8]" = "1" # RP 9 uses SRCCLKREQ2# register "PcieRpClkReqNumber[8]" = "2" - # RP 9, Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[8]" = "1" # RP 9, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[8]" = "1" # RP 9 uses uses CLK SRC 2 @@ -239,8 +231,6 @@ register "PcieRpClkReqSupport[10]" = "1" # RP 11 uses SRCCLKREQ2# register "PcieRpClkReqNumber[10]" = "2" - # RP 11, Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[10]" = "1" # RP 11, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[10]" = "1" # RP 11 uses uses CLK SRC 2 @@ -252,8 +242,6 @@ register "PcieRpClkReqSupport[11]" = "1" # RP 12 uses SRCCLKREQ2# register "PcieRpClkReqNumber[11]" = "2" - # RP 12, Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[11]" = "1" # RP 12, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[11]" = "1" # RP 12 uses uses CLK SRC 2 diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index ac86e79..27e9f48 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -151,7 +151,6 @@ register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqNumber[0]" = "1" register "PcieRpClkSrcNumber[0]" = "1" - register "PcieRpAdvancedErrorReporting[0]" = "1" register "PcieRpLtrEnable[0]" = "1" # USB 2.0 diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index d960474..81c751a 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -147,8 +147,6 @@ register "PcieRpClkReqSupport[0]" = "1" # RP 1 uses SRCCLKREQ1# register "PcieRpClkReqNumber[0]" = "1" - # RP 1, Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[0]" = "1" # RP 1, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[0]" = "1" # RP 1 uses uses CLK SRC 1 diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index 3d37eda..6656896 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -144,13 +144,11 @@ # PcieRpClkReqSupport: Enable CLKREQ# # PcieRpClkReqNumber: Uses SRCCLKREQ1# # PcieRpClkSrcNumber: Uses 1 - # PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting # PcieRpLtrEnable: Enable Latency Tolerance Reporting Mechanism register "PcieRpEnable[3]" = "1" register "PcieRpClkReqSupport[3]" = "1" register "PcieRpClkReqNumber[3]" = "1" register "PcieRpClkSrcNumber[3]" = "1" - register "PcieRpAdvancedErrorReporting[3]" = "1" register "PcieRpLtrEnable[3]" = "1" # Root port 5 (x4) @@ -158,13 +156,11 @@ # PcieRpClkReqSupport: Enable CLKREQ# # PcieRpClkReqNumber: Uses SRCCLKREQ3# # PcieRpClkSrcNumber: Uses 3 - # PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting # PcieRpLtrEnable: Enable Latency Tolerance Reporting Mechanism register "PcieRpEnable[4]" = "1" register "PcieRpClkReqSupport[4]" = "1" register "PcieRpClkReqNumber[4]" = "3" register "PcieRpClkSrcNumber[4]" = "3" - register "PcieRpAdvancedErrorReporting[4]" = "1" register "PcieRpLtrEnable[4]" = "1" # Root port 9 (x2) @@ -172,13 +168,11 @@ # PcieRpClkReqSupport: Enable CLKREQ# # PcieRpClkReqNumber: Uses SRCCLKREQ2# # PcieRpClkSrcNumber: Uses 2 - # PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting # PcieRpLtrEnable: Enable Latency Tolerance Reporting Mechanism register "PcieRpEnable[8]" = "1" register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "2" register "PcieRpClkSrcNumber[8]" = "2" - register "PcieRpAdvancedErrorReporting[8]" = "1" register "PcieRpLtrEnable[8]" = "1" register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 0 diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index ef5e8ad..f6212da 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -158,8 +158,6 @@ register "PcieRpClkReqNumber[0]" = "1" # RP 1 uses uses CLK SRC 1 register "PcieRpClkSrcNumber[0]" = "1" - # RP 1, Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[0]" = "1" # RP 1, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[0]" = "1" diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 75fcf9c..2bf4441 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -154,7 +154,6 @@ register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqNumber[0]" = "1" register "PcieRpClkSrcNumber[0]" = "1" - register "PcieRpAdvancedErrorReporting[0]" = "1" register "PcieRpLtrEnable[0]" = "1" # Root port 9 (x2) @@ -162,13 +161,11 @@ # PcieRpClkReqSupport: Enable CLKREQ# # PcieRpClkReqNumber: Uses SRCCLKREQ2# # PcieRpClkSrcNumber: Uses 3 - # PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting # PcieRpLtrEnable: Enable Latency Tolerance Reporting Mechanism register "PcieRpEnable[8]" = "1" register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "2" register "PcieRpClkSrcNumber[8]" = "3" - register "PcieRpAdvancedErrorReporting[8]" = "1" register "PcieRpLtrEnable[8]" = "1" # USB 2.0 diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index 70a4667..2517282 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -147,8 +147,6 @@ register "PcieRpClkReqNumber[0]" = "1" # RP 1 uses uses CLK SRC 1 register "PcieRpClkSrcNumber[0]" = "1" - # RP 1, Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[0]" = "1" # RP 1, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[0]" = "1" diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index 4711b1f..3067849 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -147,8 +147,6 @@ register "PcieRpClkReqSupport[0]" = "1" # RP 1 uses SRCCLKREQ1# register "PcieRpClkReqNumber[0]" = "1" - # RP 1, Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[0]" = "1" # RP 1, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[0]" = "1" # RP 1 uses uses CLK SRC 1 diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index e46e52c..cb5f0e7 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -291,14 +291,14 @@ sizeof(params->PcieRpClkReqSupport)); memcpy(params->PcieRpClkReqNumber, config->PcieRpClkReqNumber, sizeof(params->PcieRpClkReqNumber)); - memcpy(params->PcieRpAdvancedErrorReporting, - config->PcieRpAdvancedErrorReporting, - sizeof(params->PcieRpAdvancedErrorReporting)); memcpy(params->PcieRpLtrEnable, config->PcieRpLtrEnable, sizeof(params->PcieRpLtrEnable)); memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug, sizeof(params->PcieRpHotPlug)); + /* Enable PCIe Advanced Error Reporting for all root ports */ + memset(params->PcieRpAdvancedErrorReporting, 1, CONFIG_MAX_ROOT_PORTS); + /* * PcieRpClkSrcNumber UPD is set to clock source number(0-6) for * all the enabled PCIe root ports, invalid(0x1F) is set for -- To view, visit https://review.coreboot.org/c/coreboot/+/35745 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I172329d8d42c3be02e64300675d646edfbee8b72 Gerrit-Change-Number: 35745 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-MessageType: newchange

2 17

Change in coreboot[master]: nb/intel/sandybridge: replace .val_4028 with .io_latency
by Felix Held (Code Review) 01 Jan '20

01 Jan '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38027 ) Change subject: nb/intel/sandybridge: replace .val_4028 with .io_latency ...................................................................... nb/intel/sandybridge: replace .val_4028 with .io_latency Change-Id: Id584028e99975f18c97780ca6b3c7988d9e84f45 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/raminit_common.h 2 files changed, 14 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/38027/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 3cc9d29..7da5ad6 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1026,7 +1026,7 @@ shift_402x = -1; reg_io_latency |= - (ctrl->timings[channel][slotrank].val_4028 + shift_402x - + (ctrl->timings[channel][slotrank].io_latency + shift_402x - post_timA_min_high) << (4 * slotrank); reg_4024 |= (ctrl->timings[channel][slotrank].val_4024 + @@ -1260,9 +1260,9 @@ printram("4024 -= 2;\n"); continue; } - ctrl->timings[channel][slotrank].val_4028 += 2; + ctrl->timings[channel][slotrank].io_latency += 2; printram("4028 += 2;\n"); - if (ctrl->timings[channel][slotrank].val_4028 >= 0x10) { + if (ctrl->timings[channel][slotrank].io_latency >= 0x10) { printk(BIOS_EMERG, "402x discovery failed (2): %d, %d\n", channel, slotrank); return MAKE_ERR; @@ -1321,7 +1321,7 @@ else shift_402x = 0; - ctrl->timings[channel][slotrank].val_4028 += shift_402x; + ctrl->timings[channel][slotrank].io_latency += shift_402x; ctrl->timings[channel][slotrank].val_4024 += shift_402x; printram("4024 += %d;\n", shift_402x); printram("4028 += %d;\n", shift_402x); @@ -1367,7 +1367,7 @@ MCHBAR32(0x3400) = (slotrank << 2) | 0x8001; - ctrl->timings[channel][slotrank].val_4028 = 4; + ctrl->timings[channel][slotrank].io_latency = 4; ctrl->timings[channel][slotrank].val_4024 = 55; program_timings(ctrl, channel); @@ -1384,7 +1384,7 @@ } if (all_high) { - ctrl->timings[channel][slotrank].val_4028--; + ctrl->timings[channel][slotrank].io_latency--; printram("4028--;\n"); FOR_ALL_LANES { ctrl->timings[channel][slotrank].lanes[lane]. @@ -1394,7 +1394,7 @@ } } else if (some_high) { ctrl->timings[channel][slotrank].val_4024++; - ctrl->timings[channel][slotrank].val_4028++; + ctrl->timings[channel][slotrank].io_latency++; printram("4024++;\n"); printram("4028++;\n"); } @@ -1418,14 +1418,14 @@ FOR_ALL_LANES { ctrl->timings[channel][slotrank].lanes[lane].timA -= mnmx.timA_min_high * 0x40; } - ctrl->timings[channel][slotrank].val_4028 -= mnmx.timA_min_high; + ctrl->timings[channel][slotrank].io_latency -= mnmx.timA_min_high; printram("4028 -= %d;\n", mnmx.timA_min_high); post_timA_change(ctrl, channel, slotrank, &mnmx); printram("4/8: %d, %d, %x, %x\n", channel, slotrank, ctrl->timings[channel][slotrank].val_4024, - ctrl->timings[channel][slotrank].val_4028); + ctrl->timings[channel][slotrank].io_latency); printram("final results:\n"); FOR_ALL_LANES @@ -1913,7 +1913,7 @@ MCHBAR32(0x4228 + 0x400 * channel) = 0x3f105; MCHBAR32(0x4238 + 0x400 * channel) = 0x4000c01 | ((ctrl->tRP + ctrl->timings[channel][slotrank].val_4024 + - ctrl->timings[channel][slotrank].val_4028) << 16); + ctrl->timings[channel][slotrank].io_latency) << 16); MCHBAR32(0x4208 + 0x400 * channel) = (slotrank << 24) | 0x60008; MCHBAR32(0x4218 + 0x400 * channel) = 0; @@ -2931,12 +2931,12 @@ printram("normalize %d, %d, %d: mat %d\n", channel, slotrank, lane, mat); - delta = (mat >> 6) - ctrl->timings[channel][slotrank].val_4028; + delta = (mat >> 6) - ctrl->timings[channel][slotrank].io_latency; printram("normalize %d, %d, %d: delta %d\n", channel, slotrank, lane, delta); ctrl->timings[channel][slotrank].val_4024 += delta; - ctrl->timings[channel][slotrank].val_4028 += delta; + ctrl->timings[channel][slotrank].io_latency += delta; } FOR_ALL_POPULATED_CHANNELS { diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index 6bbc8b3..d11c044 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -54,8 +54,8 @@ struct ram_rank_timings { /* Register 4024. One byte per slotrank. */ u8 val_4024; - /* Register 4028. One nibble per slotrank. */ - u8 val_4028; + /* IO_LATENCY register. One nibble per slotrank. */ + u8 io_latency; int val_320c; -- To view, visit https://review.coreboot.org/c/coreboot/+/38027 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id584028e99975f18c97780ca6b3c7988d9e84f45 Gerrit-Change-Number: 38027 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: nb/intel/sandybridge/sandybridge.h: Do cosmetic fixes
by Angel Pons (Code Review) 01 Jan '20

01 Jan '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38030 ) Change subject: nb/intel/sandybridge/sandybridge.h: Do cosmetic fixes ...................................................................... nb/intel/sandybridge/sandybridge.h: Do cosmetic fixes Change-Id: I212f58bdaee538ad8f0197c0aec742aace1c7921 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/sandybridge.h 1 file changed, 16 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/38030/1 diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 3e09fd9..48a9e2c 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -1,4 +1,4 @@ -/* +:/* * This file is part of the coreboot project. * * Copyright (C) 2007-2008 coresystems GmbH @@ -125,25 +125,24 @@ #define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x)))) #define MCHBAR32_OR(x, or) (MCHBAR32(x) = (MCHBAR32(x) | (or))) #define MCHBAR32_AND(x, and) (MCHBAR32(x) = (MCHBAR32(x) & (and))) -#define MCHBAR32_AND_OR(x, and, or) \ - (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or)) +#define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or)) -#define TC_DBP_C0 0x4000 /* Timing of DDR - bin parameters */ -#define TC_RAP_C0 0x4004 /* Timing of DDR - regular access parameters */ -#define SC_IO_LATENCY_C0 0x4028 /* IO Latency Configuration */ -#define TC_RFP_C0 0x4294 /* Refresh Parameters */ -#define TC_RFTP_C0 0x4298 /* Refresh Timing Parameters */ -#define PM_PDWN_CONFIG 0x4cb0 -#define MAD_CHNL 0x5000 /* Address Decoder Channel Configuration */ -#define MAD_DIMM_CH0 0x5004 /* Address Decode Channel 0 */ -#define MAD_DIMM_CH1 0x5008 /* Address Decode Channel 1 */ +#define TC_DBP_C0 0x4000 /* Timing of DDR - bin parameters */ +#define TC_RAP_C0 0x4004 /* Timing of DDR - regular access parameters */ +#define SC_IO_LATENCY_C0 0x4028 /* IO Latency Configuration */ +#define TC_RFP_C0 0x4294 /* Refresh Parameters */ +#define TC_RFTP_C0 0x4298 /* Refresh Timing Parameters */ +#define PM_PDWN_CONFIG 0x4cb0 +#define MAD_CHNL 0x5000 /* Address Decoder Channel Configuration */ +#define MAD_DIMM_CH0 0x5004 /* Address Decode Channel 0 */ +#define MAD_DIMM_CH1 0x5008 /* Address Decode Channel 1 */ #define MEM_TRML_ESTIMATION_CONFIG 0x5880 #define MEM_TRML_THRESHOLDS_CONFIG 0x5888 -#define MEM_TRML_INTERRUPT 0x58a8 -#define MC_BIOS_REQ 0x5e00 -#define MC_BIOS_DATA 0x5e04 -#define SSKPD 0x5d14 /* 16bit (scratchpad) */ -#define BIOS_RESET_CPL 0x5da8 /* 8bit */ +#define MEM_TRML_INTERRUPT 0x58a8 +#define MC_BIOS_REQ 0x5e00 +#define MC_BIOS_DATA 0x5e04 +#define SSKPD 0x5d14 /* 16bit (scratchpad) */ +#define BIOS_RESET_CPL 0x5da8 /* 8bit */ /* * EPBAR - Egress Port Root Complex Register Block -- To view, visit https://review.coreboot.org/c/coreboot/+/38030 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I212f58bdaee538ad8f0197c0aec742aace1c7921 Gerrit-Change-Number: 38030 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: nb/intel/sandybridge: Use the MC_BIOS_DATA define
by Angel Pons (Code Review) 01 Jan '20

01 Jan '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38029 ) Change subject: nb/intel/sandybridge: Use the MC_BIOS_DATA define ...................................................................... nb/intel/sandybridge: Use the MC_BIOS_DATA define Change-Id: I177f419d2675ebda5c231a257bed8baf56e13291 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_mrc.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/38029/1 diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index cab5588..aa166c9 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -154,7 +154,7 @@ addr_decode_ch[1] = MCHBAR32(MAD_DIMM_CH1); printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", - (MCHBAR32(0x5e04) * 13333 * 2 + 50)/100); + (MCHBAR32(MC_BIOS_DATA) * 13333 * 2 + 50)/100); printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n", addr_decoder_common & 3, (addr_decoder_common >> 2) & 3, -- To view, visit https://review.coreboot.org/c/coreboot/+/38029 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I177f419d2675ebda5c231a257bed8baf56e13291 Gerrit-Change-Number: 38029 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: nb/intel/sandybridge: Make `PM_PDWN_Config` uppercase
by Angel Pons (Code Review) 01 Jan '20

01 Jan '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38028 ) Change subject: nb/intel/sandybridge: Make `PM_PDWN_Config` uppercase ...................................................................... nb/intel/sandybridge: Make `PM_PDWN_Config` uppercase Change-Id: Id37d2367d57ff925476c53bb0edab927c1c768f6 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/sandybridge.h 2 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/38028/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 3cc9d29..644c415 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -3134,10 +3134,10 @@ if (is_mobile) /* APD - DLL Off, 64 DCLKs until idle, decision per rank */ - MCHBAR32(PM_PDWN_Config) = 0x00000740; + MCHBAR32(PM_PDWN_CONFIG) = 0x00000740; else /* APD - PPD, 64 DCLKs until idle, decision per rank */ - MCHBAR32(PM_PDWN_Config) = 0x00000340; + MCHBAR32(PM_PDWN_CONFIG) = 0x00000340; FOR_ALL_CHANNELS MCHBAR32(0x4380 + 0x400 * channel) = 0x00000aaa; diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 725cc04..3e09fd9 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -133,7 +133,7 @@ #define SC_IO_LATENCY_C0 0x4028 /* IO Latency Configuration */ #define TC_RFP_C0 0x4294 /* Refresh Parameters */ #define TC_RFTP_C0 0x4298 /* Refresh Timing Parameters */ -#define PM_PDWN_Config 0x4cb0 +#define PM_PDWN_CONFIG 0x4cb0 #define MAD_CHNL 0x5000 /* Address Decoder Channel Configuration */ #define MAD_DIMM_CH0 0x5004 /* Address Decode Channel 0 */ #define MAD_DIMM_CH1 0x5008 /* Address Decode Channel 1 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/38028 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id37d2367d57ff925476c53bb0edab927c1c768f6 Gerrit-Change-Number: 38028 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: nb/intel/sandybridge: add and use memory thermal configuration registers
by Felix Held (Code Review) 01 Jan '20

01 Jan '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38015 ) Change subject: nb/intel/sandybridge: add and use memory thermal configuration registers ...................................................................... nb/intel/sandybridge: add and use memory thermal configuration registers Change-Id: I96efeadcc7d22bc8453645f6a0884d82edf3aec6 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/sandybridge.h 2 files changed, 6 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/38015/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 4e42c71..3cc9d29 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -3164,9 +3164,9 @@ } } - MCHBAR32(0x5880) = 0xca9171e5; - MCHBAR32_AND_OR(0x5888, ~0xffffff, 0xe4d5d0); - MCHBAR32_AND(0x58a8, ~0x1f); + MCHBAR32(MEM_TRML_ESTIMATION_CONFIG) = 0xca9171e5; + MCHBAR32_AND_OR(MEM_TRML_THRESHOLDS_CONFIG, ~0xffffff, 0xe4d5d0); + MCHBAR32_AND(MEM_TRML_INTERRUPT, ~0x1f); FOR_ALL_CHANNELS MCHBAR32_AND_OR(TC_RFP_C0 + 0x400 * channel, ~0x30000, 1 << 16); diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 6dcb3ce..7646e66 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -137,6 +137,9 @@ #define MAD_CHNL 0x5000 /* Address Decoder Channel Configuration */ #define MAD_DIMM_CH0 0x5004 /* Address Decode Channel 0 */ #define MAD_DIMM_CH1 0x5008 /* Address Decode Channel 1 */ +#define MEM_TRML_ESTIMATION_CONFIG 0x5880 +#define MEM_TRML_THRESHOLDS_CONFIG 0x5888 +#define MEM_TRML_INTERRUPT 0x58a8 #define MC_BIOS_REQ 0x5e00 #define MC_BIOS_DATA 0x5e04 #define SSKPD 0x5d14 /* 16bit (scratchpad) */ -- To view, visit https://review.coreboot.org/c/coreboot/+/38015 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96efeadcc7d22bc8453645f6a0884d82edf3aec6 Gerrit-Change-Number: 38015 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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coreboot-gerrit January 2020