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Change in coreboot[master]: mb/bap/ode_e20XX: Drop boards with ROMCC_BOOTBLOCK
by HAOUAS Elyes (Code Review) Jan. 7, 2020

Jan. 7, 2020

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38106 ) Change subject: mb/bap/ode_e20XX: Drop boards with ROMCC_BOOTBLOCK ...................................................................... mb/bap/ode_e20XX: Drop boards with ROMCC_BOOTBLOCK ROMCC_BOOTBLOCK is no more. Drop unsupported, unmaintained boards. Change-Id: Ie02997772dbc1b3a36fa0873e1f51790b5e326ab Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- D src/mainboard/bap/ode_e20XX/BAP_Q7_1066.spd.hex D src/mainboard/bap/ode_e20XX/BAP_Q7_800.spd.hex D src/mainboard/bap/ode_e20XX/BiosCallOuts.c D src/mainboard/bap/ode_e20XX/Kconfig D src/mainboard/bap/ode_e20XX/Kconfig.name D src/mainboard/bap/ode_e20XX/Makefile.inc D src/mainboard/bap/ode_e20XX/OemCustomize.c D src/mainboard/bap/ode_e20XX/OptionsIds.h D src/mainboard/bap/ode_e20XX/acpi/gpe.asl D src/mainboard/bap/ode_e20XX/acpi/ide.asl D src/mainboard/bap/ode_e20XX/acpi/mainboard.asl D src/mainboard/bap/ode_e20XX/acpi/routing.asl D src/mainboard/bap/ode_e20XX/acpi/sata.asl D src/mainboard/bap/ode_e20XX/acpi/si.asl D src/mainboard/bap/ode_e20XX/acpi/sleep.asl D src/mainboard/bap/ode_e20XX/acpi/superio.asl D src/mainboard/bap/ode_e20XX/acpi/thermal.asl D src/mainboard/bap/ode_e20XX/acpi/usb_oc.asl D src/mainboard/bap/ode_e20XX/acpi_tables.c D src/mainboard/bap/ode_e20XX/board_info.txt D src/mainboard/bap/ode_e20XX/buildOpts.c D src/mainboard/bap/ode_e20XX/cmos.layout D src/mainboard/bap/ode_e20XX/devicetree.cb D src/mainboard/bap/ode_e20XX/dsdt.asl D src/mainboard/bap/ode_e20XX/irq_tables.c D src/mainboard/bap/ode_e20XX/mainboard.c D src/mainboard/bap/ode_e20XX/mptable.c D src/mainboard/bap/ode_e20XX/romstage.c 28 files changed, 0 insertions(+), 2,936 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/38106/1 diff --git a/src/mainboard/bap/ode_e20XX/BAP_Q7_1066.spd.hex b/src/mainboard/bap/ode_e20XX/BAP_Q7_1066.spd.hex deleted file mode 100644 index 111310a..0000000 --- a/src/mainboard/bap/ode_e20XX/BAP_Q7_1066.spd.hex +++ /dev/null @@ -1,231 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2014 Sage Electronic Engineering, LLC. -# Copyright (C) 2015 BAP - Bruhnspace Advanced Projects -# (Written by Fabian Kunkel <fabi(a)adv.bruhnspace.com> for BAP) -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. - -# Memory chip: Hynix H5TQ4G63MFR-PBC with ECC -# BAP ODE E20XX has 2GB ram soldered down on the Q7 -# Memory setting for DDR-1066 - -# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage -# bits[3:0]: 1 = 128 SPD Bytes Used -# bits[6:4]: 1 = 256 SPD Bytes Total -# bit7 : 0 = CRC covers bytes 0 ~ 125 -11 - -# 1 SPD Revision - -# 0x12 = Revision 1.2 -12 - -# 2 Key Byte / DRAM Device Type -# bits[7:0]: 0x0b = DDR3 SDRAM -0B - -# 3 Key Byte / Module Type -# bits[3:0]: 3 = SO-DIMM -# bits[7:4]: reserved -03 - -# 4 SDRAM CHIP Density and Banks -# bits[3:0]: 4 = 4 Gigabits Total SDRAM capacity per chip -# bits[6:4]: 0 = 3 (8 banks) -# bit7 : reserved -04 - -# 5 SDRAM Addressing -# bits[2:0]: 1 = 10 Column Address Bits -# bits[5:3]: 3 = 15 Row Address Bits -# bits[7:6]: reserved -19 - -# 6 Module Nominal Voltage, VDD -# bit0 : 0 = 1.5 V operable -# bit1 : 0 = NOT 1.35 V operable -# bit2 : 0 = NOT 1.25 V operable -# bits[7:3]: reserved -00 - -# 7 Module Organization -# bits[2:0]: 2 = 16 bits -# bits[5:3]: 0 = 1 Rank -# bits[7:6]: reserved -02 - -# 8 Module Memory Bus Width -# bits[2:0]: 3 = Primary bus width is 64 bits -# bits[4:3]: 1 = 1 bit (bus width extension ECC) -# bits[7:5]: reserved -0B - -# 9 Fine Timebase (FTB) Dividend / Divisor -# bits[3:0]: 0x01 divisor -# bits[7:4]: 0x01 dividend -# 1/1 = 1ps -11 - -# 10 Medium Timebase (MTB) Dividend -# 11 Medium Timebase (MTB) Divisor -# 1 / 8 = .125 ns - used for DDR3 -01 08 - -# 12 SDRAM Minimum Cycle Time (tCKmin) -# 0x0F = tCKmin of 1.875 ns = DDR3-1066 (533 MHz clock) -0F - -# 13 Reserved -00 - -# 14 CAS Latencies Supported, Least Significant Byte -# 15 CAS Latencies Supported, Most Significant Byte -# Cas Latencies of 8 - 5 are supported -1E 00 - -# 16 Minimum CAS Latency Time (tAAmin) -# 0x69 = 13.125ns - DDR3-1066F -69 - -# 17 Minimum Write Recovery Time (tWRmin) -# 0x78 = tWR of 15ns - All DDR3 speed grades -78 - -# 18 Minimum RAS# to CAS# Delay Time (tRCDmin) -# 0x69 = 13.125ns - DDR3-1066F -69 - -# 19 Minimum Row Active to Row Active Delay Time (tRRDmin) -# 0x3C = 7.5ns -3C - -# 20 Minimum Row Precharge Delay Time (tRPmin) -# 0x69 = 13.125ns - DDR3-1066F -69 - -# 21 Upper Nibbles for tRAS and tRC -# bits[3:0]: tRAS most significant nibble = 1 (see byte 22) -# bits[7:4]: tRC most significant nibble = 1 (see byte 23) -11 - -# 22 Minimum Active to Precharge Delay Time (tRASmin), LSB -# 0x12C = 37.5ns - DDR3-1066 (see byte 21) -2C - -# 23 Minimum Active to Active/Refresh Delay Time (tRCmin), LSB -# 0x195 = 50.625ns - DDR3-1066F (see byte 21) -95 - -# 24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB -# 25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB -# 0x500 = 160ns - for 2 Gigabit chips -80 07 - -# 26 Minimum Internal Write to Read Command Delay Time (tWTRmin) -# 0x3c = 7.5 ns - All DDR3 SDRAM speed bins -3C - -# 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin) -# 0x3c = 7.5ns - All DDR3 SDRAM speed bins -3C - -# 28 Upper Nibble for tFAWmin -# 29 Minimum Four Activate Window Delay Time (tFAWmin) -# 0x0190 = 50ns - DDR3-1066, 2 KB page size -01 90 - -# 30 SDRAM Optional Feature -# bit0 : 1= RZQ/6 supported -# bit1 : 1 = RZQ/7 supported -# bits[6:2]: reserved -# bit7 : 0 = DLL Off mode supported -03 - -# 31 SDRAM Thermal and Refresh Options -# bit0 : 0 = Temp up to 95c supported -# bit1 : 0 = 85-95c uses 2x refresh rate -# bit2 : 1 = Auto Self Refresh supported -# bit3 : 0 = no on die thermal sensor -# bits[6:4]: reserved -# bit7 : 0 = partial self refresh supported -04 - -# 32 Module Thermal Sensor -# 0 = Thermal sensor not incorporated onto this assembly -00 - -# 33 SDRAM Device Type -# bits[1:0]: 0 = Signal Loading not specified -# bits[3:2]: reserved -# bits[6:4]: 0 = Die count not specified -# bit7 : 0 = Standard Monolithic DRAM Device -00 - -# 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin) -# 35 Fine Offset for Minimum CAS Latency Time (tAAmin) -# 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin) -# 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin) -# 38 Fine Offset for Minimum Active to Active/Refresh Delay (tRCmin) -00 00 00 00 00 - -# 39 - 59 (reserved) -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 - -# 60 Raw Card Extension, Module Nominal Height -# bits[4:0]: 0 = <= 15mm tall -# bits[7:5]: 0 = raw card revision 0-3 -00 - -# 61 Module Maximum Thickness -# bits[3:0]: 0 = thickness front <= 1mm -# bits[7:4]: 0 = thinkness back <= 1mm -00 - -# 62 Reference Raw Card Used -# bits[4:0]: 0 = Reference Raw card A used -# bits[6:5]: 0 = revision 0 -# bit7 : 0 = Reference raw cards A through AL -00 - -# 63 Address Mapping from Edge Connector to DRAM -# bit0 : 0 = standard mapping (not mirrored) -# bits[7:1]: reserved -00 - -# 64 - 116 (reserved) -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 - -# 117 - 118 Module ID: Module Manufacturers JEDEC ID Code -# 0x80AD = Hynix -80 AD - -# 119 Module ID: Module Manufacturing Location - oem specified -# 120 Module ID: Module Manufacture Year in BCD -# 0x00 = 2000 -00 00 - -# 121 Module ID: Module Manufacture week -# 0x00 = 0th week -00 - -# 122 - 125: Module Serial Number -00 00 00 00 - -# 126 - 127: Cyclical Redundancy Code -E9 40 diff --git a/src/mainboard/bap/ode_e20XX/BAP_Q7_800.spd.hex b/src/mainboard/bap/ode_e20XX/BAP_Q7_800.spd.hex deleted file mode 100644 index ba3d5ac..0000000 --- a/src/mainboard/bap/ode_e20XX/BAP_Q7_800.spd.hex +++ /dev/null @@ -1,231 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2014 Sage Electronic Engineering, LLC. -# Copyright (C) 2015 BAP - Bruhnspace Advanced Projects -# (Written by Fabian Kunkel <fabi(a)adv.bruhnspace.com> for BAP) -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. - -# Memory chip: Hynix H5TQ4G63MFR-PBC with ECC -# BAP ODE E20XX has 2GB ram soldered down on the Q7 -# Memory setting for DDR-800 - -# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage -# bits[3:0]: 1 = 128 SPD Bytes Used -# bits[6:4]: 1 = 256 SPD Bytes Total -# bit7 : 0 = CRC covers bytes 0 ~ 125 -11 - -# 1 SPD Revision - -# 0x11 = Revision 1.1 -11 - -# 2 Key Byte / DRAM Device Type -# bits[7:0]: 0x0b = DDR3 SDRAM -0B - -# 3 Key Byte / Module Type -# bits[3:0]: 3 = SO-DIMM -# bits[7:4]: reserved -03 - -# 4 SDRAM CHIP Density and Banks -# bits[3:0]: 4 = 4 Gigabits Total SDRAM capacity per chip -# bits[6:4]: 0 = 3 (8 banks) -# bit7 : reserved -04 - -# 5 SDRAM Addressing -# bits[2:0]: 1 = 10 Column Address Bits -# bits[5:3]: 3 = 15 Row Address Bits -# bits[7:6]: reserved -19 - -# 6 Module Nominal Voltage, VDD -# bit0 : 0 = 1.5 V operable -# bit1 : 0 = NOT 1.35 V operable -# bit2 : 0 = NOT 1.25 V operable -# bits[7:3]: reserved -00 - -# 7 Module Organization -# bits[2:0]: 2 = 16 bits -# bits[5:3]: 0 = 1 Rank -# bits[7:6]: reserved -02 - -# 8 Module Memory Bus Width -# bits[2:0]: 3 = Primary bus width is 64 bits -# bits[4:3]: 1 = 1 bit (bus width extension ECC) -# bits[7:5]: reserved -0B - -# 9 Fine Timebase (FTB) Dividend / Divisor -# bits[3:0]: 0x01 divisor -# bits[7:4]: 0x01 dividend -# 1/1 = 1ps -11 - -# 10 Medium Timebase (MTB) Dividend -# 11 Medium Timebase (MTB) Divisor -# 1 / 8 = .125 ns - used for DDR3 -01 08 - -# 12 SDRAM Minimum Cycle Time (tCKmin) -# 0x14 = tCKmin of 2.5 ns = DDR3-800 (400 MHz clock) -14 - -# 13 Reserved -00 - -# 14 CAS Latencies Supported, Least Significant Byte -# 15 CAS Latencies Supported, Most Significant Byte -# CAS Latencies of 6 - 5 are supported -06 00 - -# 16 Minimum CAS Latency Time (tAAmin) -# 0x78 = 15ns - DDR3-800E -78 - -# 17 Minimum Write Recovery Time (tWRmin) -# 0x78 = tWR of 15ns - All DDR3 speed grades -78 - -# 18 Minimum RAS# to CAS# Delay Time (tRCDmin) -# 0x6E = 15ns - DDR3-800E -78 - -# 19 Minimum Row Active to Row Active Delay Time (tRRDmin) -# 0x3C = 7.5ns -3C - -# 20 Minimum Row Precharge Delay Time (tRPmin) -# 0x6E = 15ns - DDR3-800E -78 - -# 21 Upper Nibbles for tRAS and tRC -# bits[3:0]: tRAS most significant nibble = 1 (see byte 22) -# bits[7:4]: tRC most significant nibble = 1 (see byte 23) -11 - -# 22 Minimum Active to Precharge Delay Time (tRASmin), LSB -# 0x12C = 37.5ns - DDR3-800E (see byte 21) -2C - -# 23 Minimum Active to Active/Refresh Delay Time (tRCmin), LSB -# 0x1A4 = 52.5ns - DDR3-800E (see byte 21) -A4 - -# 24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB -# 25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB -# 0x780 = 208ns - for 4 Gigabit chips -80 07 - -# 26 Minimum Internal Write to Read Command Delay Time (tWTRmin) -# 0x3c = 7.5 ns - All DDR3 SDRAM speed bins -3C - -# 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin) -# 0x3c = 7.5ns - All DDR3 SDRAM speed bins -3C - -# 28 Upper Nibble for tFAWmin -# 29 Minimum Four Activate Window Delay Time (tFAWmin) -# 0x0190 = 50ns - DDR3-800, 2 KB page size -01 90 - -# 30 SDRAM Optional Feature -# bit0 : 1= RZQ/6 supported -# bit1 : 1 = RZQ/7 supported -# bits[6:2]: reserved -# bit7 : 0 = DLL Off mode supported -03 - -# 31 SDRAM Thermal and Refresh Options -# bit0 : 0 = Temp up to 95c supported -# bit1 : 0 = 85-95c uses 2x refresh rate -# bit2 : 1 = Auto Self Refresh supported -# bit3 : 0 = no on die thermal sensor -# bits[6:4]: reserved -# bit7 : 0 = partial self refresh supported -04 - -# 32 Module Thermal Sensor -# 0 = Thermal sensor not incorporated onto this assembly -00 - -# 33 SDRAM Device Type -# bits[1:0]: 0 = Signal Loading not specified -# bits[3:2]: reserved -# bits[6:4]: 0 = Die count not specified -# bit7 : 0 = Standard Monolithic DRAM Device -00 - -# 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin) -# 35 Fine Offset for Minimum CAS Latency Time (tAAmin) -# 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin) -# 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin) -# 38 Fine Offset for Minimum Active to Active/Refresh Delay (tRCmin) -00 00 00 00 00 - -# 39 - 59 (reserved) -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 - -# 60 Raw Card Extension, Module Nominal Height -# bits[4:0]: 0 = <= 15mm tall -# bits[7:5]: 0 = raw card revision 0-3 -00 - -# 61 Module Maximum Thickness -# bits[3:0]: 0 = thickness front <= 1mm -# bits[7:4]: 0 = thinkness back <= 1mm -00 - -# 62 Reference Raw Card Used -# bits[4:0]: 0 = Reference Raw card A used -# bits[6:5]: 0 = revision 0 -# bit7 : 0 = Reference raw cards A through AL -00 - -# 63 Address Mapping from Edge Connector to DRAM -# bit0 : 0 = standard mapping (not mirrored) -# bits[7:1]: reserved -00 - -# 64 - 116 (reserved) -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 - -# 117 - 118 Module ID: Module Manufacturers JEDEC ID Code -# 0x80AD = Hynix -80 AD - -# 119 Module ID: Module Manufacturing Location - oem specified -# 120 Module ID: Module Manufacture Year in BCD -# 0x00 = 2000 -00 00 - -# 121 Module ID: Module Manufacture week -# 0x00 = 0th week -00 - -# 122 - 125: Module Serial Number -00 00 00 00 - -# 126 - 127: Cyclical Redundancy Code -48 91 diff --git a/src/mainboard/bap/ode_e20XX/BiosCallOuts.c b/src/mainboard/bap/ode_e20XX/BiosCallOuts.c deleted file mode 100644 index abe300e..0000000 --- a/src/mainboard/bap/ode_e20XX/BiosCallOuts.c +++ /dev/null @@ -1,217 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <AGESA.h> -#include <northbridge/amd/agesa/BiosCallOuts.h> -#include <northbridge/amd/agesa/state_machine.h> -#include <FchPlatform.h> -#include <stdlib.h> -#include <spd_bin.h> - -#include "imc.h" - -static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr); - -const BIOS_CALLOUT_STRUCT BiosCallouts[] = -{ - {AGESA_DO_RESET, agesa_Reset }, - {AGESA_READ_SPD, board_ReadSpd_from_cbfs }, - {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, - {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, - {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData }, - {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, - {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, - {AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage } -}; -const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); - -/** - * ALC272 Verb Table - */ -const CODEC_ENTRY Alc272_VerbTbl[] = { - {0x11, 0x411111F0}, // - SPDIF_OUT2 - {0x12, 0x411111F0}, // - DMIC_1/2 - {0x13, 0x411111F0}, // - DMIC_3/4 - {0x14, 0x411111F0}, // Port D - LOUT1 - {0x15, 0x01011050}, // Port A - LOUT2 Explorer 2x DAC - {0x16, 0x411111F0}, // - {0x17, 0x411111F0}, // Port H - MONO - {0x18, 0x01a11840}, // Port B - MIC1 - {0x19, 0x411111F0}, // Port F - MIC2 - {0x1a, 0x01811030}, // Port C - LINE1 - {0x1b, 0x01811020}, // Port E - LINE2 Explorer 2x ADC - {0x1d, 0x40130605}, // - PCBEEP - {0x1e, 0x411111F0}, // - SPDIF_OUT1 - {0x21, 0x01211010}, // Port I - HPOUT - {0xff, 0xffffffff} -}; - -static const CODEC_TBL_LIST CodecTableList[] = -{ - {0x10ec0272, (CODEC_ENTRY*)&Alc272_VerbTbl[0]}, - {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL} -}; - -#define FAN_INPUT_INTERNAL_DIODE 0 -#define FAN_INPUT_TEMP0 1 -#define FAN_INPUT_TEMP1 2 -#define FAN_INPUT_TEMP2 3 -#define FAN_INPUT_TEMP3 4 -#define FAN_INPUT_TEMP0_FILTER 5 -#define FAN_INPUT_ZERO 6 -#define FAN_INPUT_DISABLED 7 - -#define FAN_AUTOMODE (1 << 0) -#define FAN_LINEARMODE (1 << 1) -#define FAN_STEPMODE ~(1 << 1) -#define FAN_POLARITY_HIGH (1 << 2) -#define FAN_POLARITY_LOW ~(1 << 2) - -/* Normally, 4-wire fan runs at 25KHz and 3-wire fan runs at 100Hz */ -#define FREQ_28KHZ 0x0 -#define FREQ_25KHZ 0x1 -#define FREQ_23KHZ 0x2 -#define FREQ_21KHZ 0x3 -#define FREQ_29KHZ 0x4 -#define FREQ_18KHZ 0x5 -#define FREQ_100HZ 0xF7 -#define FREQ_87HZ 0xF8 -#define FREQ_58HZ 0xF9 -#define FREQ_44HZ 0xFA -#define FREQ_35HZ 0xFB -#define FREQ_29HZ 0xFC -#define FREQ_22HZ 0xFD -#define FREQ_14HZ 0xFE -#define FREQ_11HZ 0xFF - -/* Hardware Monitor Fan Control - * Hardware limitation: - * HWM failed to read the input temperture vi I2C, - * if other software switch the I2C switch by mistake or intention. - * We recommend to using IMC to control Fans, instead of HWM. - */ -static void oem_fan_control(FCH_DATA_BLOCK *FchParams) -{ - /* Enable IMC fan control. the recommand way */ - if (CONFIG(HUDSON_IMC_FWM)) { - imc_reg_init(); - - /* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */ - FchParams->Hwm.HwMonitorEnable = TRUE; - FchParams->Hwm.HwmFchtsiAutoPoll = FALSE;/* 0 disable, 1 enable TSI Auto Polling */ - - FchParams->Imc.ImcEnable = TRUE; - FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */ - FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ - - LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader); - - /* Thermal Zone Parameter */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; //BIT0 | BIT2 | BIT5; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x4e;//6 | BIT3; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x04; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x9a; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg7 = 0x01; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg8 = 0x01; /* PWM steping rate in unit of PWM level percentage */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg9 = 0x00; - - /* IMC Fan Policy temperature thresholds */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 50; /*AC0 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 45; /*AC1 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 40; /*AC2 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff; /*AC3 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0xff; /*AC4 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0xff; /*AC5 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0xff; /*AC6 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0xff; /*AC7 lowest threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegA = 0x4b; /*critical threshold* in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegB = 0x00; - - /* IMC Fan Policy PWM Settings */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg2 = 100; /* AL0 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg3 = 99; /* AL1 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg4 = 98; /* AL2 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg5 = 0xff; /* AL3 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg6 = 0xff; /* AL4 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg7 = 0xff; /* AL5 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0xff; /* AL6 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0xff; /* AL7 percentage */ - - FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x111;//BIT0 | BIT4 |BIT8; - - /* NOTE: - * FchInitLateHwm will overwrite the EcStruct with EcDefaultMassege, - * AGESA put EcDefaultMassege as global data in ROM, so we can't overwride it. - * so we remove it from AGESA code. Please Seee FchInitLateHwm. - */ - } else { - /* HWM fan control, the way not recommand */ - FchParams->Imc.ImcEnable = FALSE; - FchParams->Hwm.HwMonitorEnable = TRUE; - FchParams->Hwm.HwmFchtsiAutoPoll = TRUE;/* 1 enable, 0 disable TSI Auto Polling */ - } -} - -void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset) -{ -} - -void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env) -{ - /* Azalia Controller OEM Codec Table Pointer */ - FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&CodecTableList[0]); - - /* Fan Control */ - oem_fan_control(FchParams_env); - - /* sata configuration */ - /* disable GEN2 limitation */ - FchParams_env->Sata.SataMode.SataSetMaxGen2 = FALSE; -} - -static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr) -{ - AGESA_READ_SPD_PARAMS *info = ConfigPtr; - u8 index; - - if (!ENV_ROMSTAGE) - return AGESA_UNSUPPORTED; - - if (CONFIG(BAP_E20_DDR3_1066)) - index = 1; - else /* CONFIG_BAP_E20_DDR3_800 */ - index = 0; - - if (info->MemChannelId > 0) - return AGESA_UNSUPPORTED; - if (info->SocketId != 0) - return AGESA_UNSUPPORTED; - if (info->DimmId != 0) - return AGESA_UNSUPPORTED; - - /* Read index 0, first SPD_SIZE bytes of spd.bin file. */ - if (read_ddr3_spd_from_cbfs((u8 *)info->Buffer, index) < 0) - die("No SPD data\n"); - - return AGESA_SUCCESS; -} diff --git a/src/mainboard/bap/ode_e20XX/Kconfig b/src/mainboard/bap/ode_e20XX/Kconfig deleted file mode 100644 index 2a72deb..0000000 --- a/src/mainboard/bap/ode_e20XX/Kconfig +++ /dev/null @@ -1,87 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2012 Advanced Micro Devices, Inc. -# Copyright (C) 2013-2014 Sage Electronic Engineering -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -config BOARD_ODE_E20XX - def_bool n - -if BOARD_ODE_E20XX - -config BOARD_SPECIFIC_OPTIONS - def_bool y - #select ROMCC_BOOTBLOCK - select CPU_AMD_AGESA_FAMILY16_KB - select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB - select SOUTHBRIDGE_AMD_AGESA_YANGTZE - select DEFAULT_POST_ON_LPC - select HAVE_OPTION_TABLE - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select HAVE_ACPI_TABLES - select BOARD_ROMSIZE_KB_4096 - select GFXUMA - select SUPERIO_FINTEK_F81866D - -config MAINBOARD_DIR - string - default "bap/ode_e20XX" - -config MAINBOARD_PART_NUMBER - string - default "ODE_E20XX" - -config HW_MEM_HOLE_SIZEK - hex - default 0x200000 - -config MAX_CPUS - int - default 4 - -config IRQ_SLOT_COUNT - int - default 11 - -config ONBOARD_VGA_IS_PRIMARY - bool - default y - -config HUDSON_LEGACY_FREE - bool - default y - -choice - prompt "Select DDR3 clock" - default BAP_E20_DDR3_1066 - help - Select your preferred DDR3 clock setting. - - Note: This option changes the total power consumption. - - If unsure, use DDR3-1066. - -config BAP_E20_DDR3_800 - bool "Select DDR3-800" - -config BAP_E20_DDR3_1066 - bool "Select DDR3-1066" - -endchoice - -config DIMM_SPD_SIZE - int - default 128 - -endif # BOARD_ODE_E20XX diff --git a/src/mainboard/bap/ode_e20XX/Kconfig.name b/src/mainboard/bap/ode_e20XX/Kconfig.name deleted file mode 100644 index 54ddcac..0000000 --- a/src/mainboard/bap/ode_e20XX/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -#config BOARD_ODE_E20XX -# bool"ODE_e20xx" diff --git a/src/mainboard/bap/ode_e20XX/Makefile.inc b/src/mainboard/bap/ode_e20XX/Makefile.inc deleted file mode 100644 index 4d8eb8d..0000000 --- a/src/mainboard/bap/ode_e20XX/Makefile.inc +++ /dev/null @@ -1,43 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2012 Advanced Micro Devices, Inc. -# Copyright (C) 2014 Sage Electronic Engineering, LLC -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -romstage-y += buildOpts.c -romstage-y += BiosCallOuts.c -romstage-y += OemCustomize.c - -ramstage-y += buildOpts.c -ramstage-y += BiosCallOuts.c -ramstage-y += OemCustomize.c - -## DIMM SPD for on-board memory -SPD_BIN = $(obj)/spd.bin - -# Order of names in SPD_SOURCES is important! -SPD_SOURCES = BAP_Q7_800 BAP_Q7_1066 - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex) - -# Include spd rom data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/bap/ode_e20XX/OemCustomize.c b/src/mainboard/bap/ode_e20XX/OemCustomize.c deleted file mode 100644 index 29d01d6..0000000 --- a/src/mainboard/bap/ode_e20XX/OemCustomize.c +++ /dev/null @@ -1,145 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <AGESA.h> -#include <PlatformMemoryConfiguration.h> - -#include <northbridge/amd/agesa/state_machine.h> - - -static const PCIe_PORT_DESCRIPTOR PortList[] = { - /* Initialize Port descriptor (PCIe port, Lanes 2-3, PCI Device Number 2, Function 4) */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 3), - PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 4, - HotplugBasic, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 0x02, 0) - }, - /* Initialize Port descriptor (PCIe port, Lane 1, PCI Device Number 2, Function 3) */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 1, 1), - PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 3, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 0x03, 0) - }, - /* Initialize Port descriptor (PCIe port, Lane 0, PCI Device Number 2, Function 2) */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 0), - PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 2, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 0x04, 0) - }, - /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 2, Function 1) */ - { - DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7), - PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 1, - HotplugBasic, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 0x05, 0) - } -}; - -static const PCIe_DDI_DESCRIPTOR DdiList[] = { - /* eDP0 to LVDS connector*/ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1) - }, - /* DP1 to HDMI */ - { - DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux2, Hdp2) - }, -}; - -static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { - .Flags = DESCRIPTOR_TERMINATE_LIST, - .SocketId = 0, - .PciePortList = PortList, - .DdiLinkList = DdiList -}; - -void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) -{ - FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface; - FchReset->Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); - FchReset->Xhci1Enable = FALSE; -} - -void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) -{ - InitEarly->GnbConfig.PcieComplexList = &PcieComplex; -} - -/*---------------------------------------------------------------------------------------- - * CUSTOMER OVERIDES MEMORY TABLE - *---------------------------------------------------------------------------------------- - */ - -/* - * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA - * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable - * is populated, AGESA will base its settings on the data from the table. Otherwise, it will - * use its default conservative settings. - */ -static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { - - #define SEED_WL 0x0E - WRITE_LEVELING_SEED( - ANY_SOCKET, CHANNEL_A, ALL_DIMMS, - SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL, - SEED_WL), - - #define SEED_A 0x12 - HW_RXEN_SEED( - ANY_SOCKET, CHANNEL_A, ALL_DIMMS, - SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, - SEED_A), - - NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1), - NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1), - MOTHER_BOARD_LAYERS(LAYERS_6), - - MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), - CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */ - ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), - CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00), - - PSO_END -}; - -void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) -{ - InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; -} - -void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) -{ - /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ - InitMid->GnbMidConfiguration.iGpuVgaMode = 0; -} diff --git a/src/mainboard/bap/ode_e20XX/OptionsIds.h b/src/mainboard/bap/ode_e20XX/OptionsIds.h deleted file mode 100644 index eaf2442..0000000 --- a/src/mainboard/bap/ode_e20XX/OptionsIds.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDS_DEBUG_PORT - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_CONTROL_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE -#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE -//#define IDSOPT_PERF_ANALYSIS TRUE -#define IDSOPT_ASSERT_ENABLED TRUE -//#undef IDSOPT_DEBUG_ENABLED -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - -#endif diff --git a/src/mainboard/bap/ode_e20XX/acpi/gpe.asl b/src/mainboard/bap/ode_e20XX/acpi/gpe.asl deleted file mode 100644 index 87b0d21..0000000 --- a/src/mainboard/bap/ode_e20XX/acpi/gpe.asl +++ /dev/null @@ -1,74 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Scope(\_GPE) { /* Start Scope GPE */ - - /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* Legacy PM event */ - Method(_L08) { - /* DBGO("\\_GPE\\_L08\n") */ - } - - /* Temp warning (TWarn) event */ - Method(_L09) { - /* DBGO("\\_GPE\\_L09\n") */ - /* Notify (\_TZ.TZ00, 0x80) */ - } - - /* USB controller PME# */ - Method(_L0B) { - /* DBGO("\\_GPE\\_L0B\n") */ - Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* ExtEvent0 SCI event */ - Method(_L10) { - /* DBGO("\\_GPE\\_L10\n") */ - } - - /* ExtEvent1 SCI event */ - Method(_L11) { - /* DBGO("\\_GPE\\_L11\n") */ - } - - /* GPIO0 or GEvent8 event */ - Method(_L18) { - /* DBGO("\\_GPE\\_L18\n") */ - Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* Azalia SCI event */ - Method(_L1B) { - /* DBGO("\\_GPE\\_L1B\n") */ - Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } -} /* End Scope GPE */ diff --git a/src/mainboard/bap/ode_e20XX/acpi/ide.asl b/src/mainboard/bap/ode_e20XX/acpi/ide.asl deleted file mode 100644 index e7f4625..0000000 --- a/src/mainboard/bap/ode_e20XX/acpi/ide.asl +++ /dev/null @@ -1,246 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012-2013 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* No IDE functionality */ - -#if 0 -/* -Scope (_SB) { - Device(PCI0) { - Device(IDEC) { - Name(_ADR, 0x00140001) - #include "ide.asl" - } - } -} -*/ - -/* Some timing tables */ -Name(UDTT, Package(){ /* Udma timing table */ - 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */ -}) - -Name(MDTT, Package(){ /* MWDma timing table */ - 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */ -}) - -Name(POTT, Package(){ /* Pio timing table */ - 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */ -}) - -/* Some timing register value tables */ -Name(MDRT, Package(){ /* MWDma timing register table */ - 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */ -}) - -Name(PORT, Package(){ - 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */ -}) - -OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */ - Field(ICRG, AnyAcc, NoLock, Preserve) -{ - PPTS, 8, /* Primary PIO Slave Timing */ - PPTM, 8, /* Primary PIO Master Timing */ - OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */ - PMTM, 8, /* Primary MWDMA Master Timing */ - OFFSET(0x08), PPCR, 8, /* Primary PIO Control */ - OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */ - PPSM, 4, /* Primary PIO slave Mode */ - OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */ - OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */ - PDSM, 4, /* Primary UltraDMA Mode */ -} - -Method(GTTM, 1) /* get total time*/ -{ - Store(And(Arg0, 0x0F), Local0) /* Recovery Width */ - Increment(Local0) - Store(ShiftRight(Arg0, 4), Local1) /* Command Width */ - Increment(Local1) - Return(Multiply(30, Add(Local0, Local1))) -} - -Device(PRID) -{ - Name (_ADR, Zero) - Method(_GTM, 0) - { - NAME(OTBF, Buffer(20) { /* out buffer */ - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 - }) - - CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */ - CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */ - CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */ - CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */ - CreateDwordField(OTBF, 16, BFFG) /* buffer flags */ - - /* Just return if the channel is disabled */ - If(And(PPCR, 0x01)) { /* primary PIO control */ - Return(OTBF) - } - - /* Always tell them independent timing available and IOChannelReady used on both drives */ - Or(BFFG, 0x1A, BFFG) - - /* save total time of primary PIO master timing to PIO spd0 */ - Store(GTTM(PPTM), PSD0) - /* save total time of primary PIO slave Timing to PIO spd1 */ - Store(GTTM(PPTS), PSD1) - - If(And(PDCR, 0x01)) { /* It's under UDMA mode */ - Or(BFFG, 0x01, BFFG) - Store(DerefOf(Index(UDTT, PDMM)), DSD0) - } - Else { - Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */ - } - - If(And(PDCR, 0x02)) { /* It's under UDMA mode */ - Or(BFFG, 0x04, BFFG) - Store(DerefOf(Index(UDTT, PDSM)), DSD1) - } - Else { - Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */ - } - - Return(OTBF) /* out buffer */ - } /* End Method(_GTM) */ - - Method(_STM, 3, NotSerialized) - { - NAME(INBF, Buffer(20) { /* in buffer */ - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 - }) - - CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */ - CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */ - CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */ - CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */ - CreateDwordField(INBF, 16, BFFG) /*buffer flag */ - - Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0) - Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */ - Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1) - Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */ - - Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */ - Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */ - - If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0) - Divide(Local0, 7, PDMM,) - Or(PDCR, 0x01, PDCR) - } - Else { - If(LNotEqual(DSD0, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTM) - } - } - - If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0) - Divide(Local0, 7, PDSM,) - Or(PDCR, 0x02, PDCR) - } - Else { - If(LNotEqual(DSD1, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTS) - } - } - /* Return(INBF) */ - } /*End Method(_STM) */ - Device(MST) - { - Name(_ADR, 0) - Method(_GTF) { - Name(CMBF, Buffer(21) { - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 - }) - CreateByteField(CMBF, 1, POMD) - CreateByteField(CMBF, 8, DMMD) - CreateByteField(CMBF, 5, CMDA) - CreateByteField(CMBF, 12, CMDB) - CreateByteField(CMBF, 19, CMDC) - - Store(0xA0, CMDA) - Store(0xA0, CMDB) - Store(0xA0, CMDC) - - Or(PPMM, 0x08, POMD) - - If(And(PDCR, 0x01)) { - Or(PDMM, 0x40, DMMD) - } - Else { - Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) - } - } - Return(CMBF) - } - } /* End Device(MST) */ - - Device(SLAV) - { - Name(_ADR, 1) - Method(_GTF) { - Name(CMBF, Buffer(21) { - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 - }) - CreateByteField(CMBF, 1, POMD) - CreateByteField(CMBF, 8, DMMD) - CreateByteField(CMBF, 5, CMDA) - CreateByteField(CMBF, 12, CMDB) - CreateByteField(CMBF, 19, CMDC) - - Store(0xB0, CMDA) - Store(0xB0, CMDB) - Store(0xB0, CMDC) - - Or(PPSM, 0x08, POMD) - - If(And(PDCR, 0x02)) { - Or(PDSM, 0x40, DMMD) - } - Else { - Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) - } - } - Return(CMBF) - } - } /* End Device(SLAV) */ -} -#endif diff --git a/src/mainboard/bap/ode_e20XX/acpi/mainboard.asl b/src/mainboard/bap/ode_e20XX/acpi/mainboard.asl deleted file mode 100644 index 68609d8..0000000 --- a/src/mainboard/bap/ode_e20XX/acpi/mainboard.asl +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Memory related values */ -Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ -Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ -Name(PBLN, 0x0) /* Length of BIOS area */ - -Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ -Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */ -Name(HPBA, 0xFED00000) /* Base address of HPET table */ - -/* Some global data */ -Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ -Name(OSV, Ones) /* Assume nothing */ -Name(PMOD, One) /* Assume APIC */ - -/* AcpiGpe0Blk */ -OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04) - Field(GP0B, ByteAcc, NoLock, Preserve) { - , 11, - USBS, 1, -} diff --git a/src/mainboard/bap/ode_e20XX/acpi/routing.asl b/src/mainboard/bap/ode_e20XX/acpi/routing.asl deleted file mode 100644 index 1fb4c1d..0000000 --- a/src/mainboard/bap/ode_e20XX/acpi/routing.asl +++ /dev/null @@ -1,194 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* -#include <arch/acpi.h> -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 - ) - { - #include "routing.asl" - } -*/ - -/* Routing is in System Bus scope */ -Name(PR0, Package(){ - /* NB devices */ - /* Bus 0, Dev 0 - F16 Host Controller */ - - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ - /* Bus 0, Dev 1, Func 1 - HDMI Audio Controller */ - Package(){0x0001FFFF, 0, INTB, 0 }, - Package(){0x0001FFFF, 1, INTC, 0 }, - - - /* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */ - Package(){0x0002FFFF, 0, INTC, 0 }, - Package(){0x0002FFFF, 1, INTD, 0 }, - Package(){0x0002FFFF, 2, INTA, 0 }, - Package(){0x0002FFFF, 3, INTB, 0 }, - - /* FCH devices */ - /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */ - Package(){0x0014FFFF, 0, INTA, 0 }, - Package(){0x0014FFFF, 1, INTB, 0 }, - Package(){0x0014FFFF, 2, INTC, 0 }, - Package(){0x0014FFFF, 3, INTD, 0 }, - - /* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */ - /* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */ - Package(){0x0012FFFF, 0, INTC, 0 }, - Package(){0x0012FFFF, 1, INTB, 0 }, - - Package(){0x0013FFFF, 0, INTC, 0 }, - Package(){0x0013FFFF, 1, INTB, 0 }, - - Package(){0x0016FFFF, 0, INTC, 0 }, - Package(){0x0016FFFF, 1, INTB, 0 }, - - /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */ - Package(){0x0010FFFF, 0, INTC, 0 }, - Package(){0x0010FFFF, 1, INTB, 0 }, - - /* Bus 0, Dev 17 - SATA controller */ - Package(){0x0011FFFF, 0, INTD, 0 }, - -}) - -Name(APR0, Package(){ - /* NB devices in APIC mode */ - /* Bus 0, Dev 0 - F15 Host Controller */ - - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ - Package(){0x0001FFFF, 0, 0, 44 }, - Package(){0x0001FFFF, 1, 0, 45 }, - - /* Bus 0, Dev 2 - PCIe Bridges */ - Package(){0x0002FFFF, 0, 0, 24 }, - Package(){0x0002FFFF, 1, 0, 25 }, - Package(){0x0002FFFF, 2, 0, 26 }, - Package(){0x0002FFFF, 3, 0, 27 }, - - - /* SB devices in APIC mode */ - /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */ - Package(){0x0014FFFF, 0, 0, 16 }, - Package(){0x0014FFFF, 1, 0, 17 }, - Package(){0x0014FFFF, 2, 0, 18 }, - Package(){0x0014FFFF, 3, 0, 19 }, - - /* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */ - /* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */ - Package(){0x0012FFFF, 0, 0, 18 }, - Package(){0x0012FFFF, 1, 0, 17 }, - - Package(){0x0013FFFF, 0, 0, 18 }, - Package(){0x0013FFFF, 1, 0, 17 }, - - Package(){0x0016FFFF, 0, 0, 18 }, - Package(){0x0016FFFF, 1, 0, 17 }, - - /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */ - Package(){0x0010FFFF, 0, 0, 0x12}, - Package(){0x0010FFFF, 1, 0, 0x11}, - - /* Bus 0, Dev 17 - SATA controller */ - Package(){0x0011FFFF, 0, 0, 19 }, - -}) - -Name(PS2, Package(){ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, -}) -Name(APS2, Package(){ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, -}) - -/* GFX */ -Name(PS4, Package(){ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, -}) -Name(APS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, 0, 24 }, - Package(){0x0000FFFF, 1, 0, 25 }, - Package(){0x0000FFFF, 2, 0, 26 }, - Package(){0x0000FFFF, 3, 0, 27 }, -}) - -/* GPP 0 */ -Name(PS5, Package(){ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, -}) -Name(APS5, Package(){ - Package(){0x0000FFFF, 0, 0, 28 }, - Package(){0x0000FFFF, 1, 0, 29 }, - Package(){0x0000FFFF, 2, 0, 30 }, - Package(){0x0000FFFF, 3, 0, 31 }, -}) - -/* GPP 1 */ -Name(PS6, Package(){ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, -}) -Name(APS6, Package(){ - Package(){0x0000FFFF, 0, 0, 32 }, - Package(){0x0000FFFF, 1, 0, 33 }, - Package(){0x0000FFFF, 2, 0, 34 }, - Package(){0x0000FFFF, 3, 0, 35 }, -}) - -/* GPP 2 */ -Name(PS7, Package(){ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, -}) -Name(APS7, Package(){ - Package(){0x0000FFFF, 0, 0, 36 }, - Package(){0x0000FFFF, 1, 0, 37 }, - Package(){0x0000FFFF, 2, 0, 38 }, - Package(){0x0000FFFF, 3, 0, 39 }, -}) - -/* GPP 3 */ -Name(PS8, Package(){ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, -}) -Name(APS8, Package(){ - Package(){0x0000FFFF, 0, 0, 40 }, - Package(){0x0000FFFF, 1, 0, 41 }, - Package(){0x0000FFFF, 2, 0, 42 }, - Package(){0x0000FFFF, 3, 0, 43 }, -}) diff --git a/src/mainboard/bap/ode_e20XX/acpi/sata.asl b/src/mainboard/bap/ode_e20XX/acpi/sata.asl deleted file mode 100644 index f675323..0000000 --- a/src/mainboard/bap/ode_e20XX/acpi/sata.asl +++ /dev/null @@ -1 +0,0 @@ -/* No SATA functionality */ diff --git a/src/mainboard/bap/ode_e20XX/acpi/si.asl b/src/mainboard/bap/ode_e20XX/acpi/si.asl deleted file mode 100644 index 2923471..0000000 --- a/src/mainboard/bap/ode_e20XX/acpi/si.asl +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Scope(\_SI) { - Method(_SST, 1) { - /* DBGO("\\_SI\\_SST\n") */ - /* DBGO(" New Indicator state: ") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - } -} /* End Scope SI */ diff --git a/src/mainboard/bap/ode_e20XX/acpi/sleep.asl b/src/mainboard/bap/ode_e20XX/acpi/sleep.asl deleted file mode 100644 index 1225a62..0000000 --- a/src/mainboard/bap/ode_e20XX/acpi/sleep.asl +++ /dev/null @@ -1,93 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Wake status package */ -Name(WKST,Package(){Zero, Zero}) - -/* -* \_PTS - Prepare to Sleep method -* -* Entry: -* Arg0=The value of the sleeping state S1=1, S2=2, etc -* -* Exit: -* -none- -* -* The _PTS control method is executed at the beginning of the sleep process -* for S1-S5. The sleeping value is passed to the _PTS control method. This -* control method may be executed a relatively long time before entering the -* sleep state and the OS may abort the operation without notification to -* the ACPI driver. This method cannot modify the configuration or power -* state of any device in the system. -*/ - -External(\_SB.APTS, MethodObj) -External(\_SB.AWAK, MethodObj) - -Method(_PTS, 1) { - /* DBGO("\\_PTS\n") */ - /* DBGO("From S0 to S") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - - /* Clear wake status structure. */ - Store(0, Index(WKST,0)) - Store(0, Index(WKST,1)) - Store(7, UPWS) - \_SB.APTS(Arg0) -} /* End Method(\_PTS) */ - -/* -* \_BFS OEM Back From Sleep method -* -* Entry: -* Arg0=The value of the sleeping state S1=1, S2=2 -* -* Exit: -* -none- -*/ -Method(\_BFS, 1) { - /* DBGO("\\_BFS\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ -} - -/* -* \_WAK System Wake method -* -* Entry: -* Arg0=The value of the sleeping state S1=1, S2=2 -* -* Exit: -* Return package of 2 DWords -* Dword 1 - Status -* 0x00000000 wake succeeded -* 0x00000001 Wake was signaled but failed due to lack of power -* 0x00000002 Wake was signaled but failed due to thermal condition -* Dword 2 - Power Supply state -* if non-zero the effective S-state the power supply entered -*/ -Method(\_WAK, 1) { - /* DBGO("\\_WAK\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - Store(1,USBS) - - \_SB.AWAK(Arg0) - - Return(WKST) -} /* End Method(\_WAK) */ diff --git a/src/mainboard/bap/ode_e20XX/acpi/superio.asl b/src/mainboard/bap/ode_e20XX/acpi/superio.asl deleted file mode 100644 index 92bd106..0000000 --- a/src/mainboard/bap/ode_e20XX/acpi/superio.asl +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * Copyright (C) 2015 BAP - Bruhnspace Advanced Projects - * (Written by Fabian Kunkel <fabi(a)adv.bruhnspace.com> for BAP) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* SuperIO support for Windows */ - -Device (UAR1) { - Name (_HID, EISAID ("PNP0501")) - Name (_UID, 1) - Name (_CRS, ResourceTemplate () - { - IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08) - IRQNoFlags () {4} - }) - Name (_PRS, ResourceTemplate () - { - IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08) - IRQNoFlags () {4} - }) -} - -Device (UAR2) { - Name (_HID, EISAID ("PNP0501")) - Name (_UID, 2) - Name (_CRS, ResourceTemplate () - { - IO (Decode16, 0x02F8, 0x02F8, 0x08, 0x08) - IRQNoFlags () {3} - }) - Name (_PRS, ResourceTemplate () - { - IO (Decode16, 0x02F8, 0x02F8, 0x08, 0x08) - IRQNoFlags () {3} - }) -} diff --git a/src/mainboard/bap/ode_e20XX/acpi/thermal.asl b/src/mainboard/bap/ode_e20XX/acpi/thermal.asl deleted file mode 100644 index e69de29..0000000 --- a/src/mainboard/bap/ode_e20XX/acpi/thermal.asl +++ /dev/null diff --git a/src/mainboard/bap/ode_e20XX/acpi/usb_oc.asl b/src/mainboard/bap/ode_e20XX/acpi/usb_oc.asl deleted file mode 100644 index c020216..0000000 --- a/src/mainboard/bap/ode_e20XX/acpi/usb_oc.asl +++ /dev/null @@ -1,129 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* simple name description */ -/* -#include <arch/acpi.h> -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 - ) - { - #include "usb.asl" - } -*/ - -/* USB overcurrent mapping pins. */ -Name(UOM0, 0) -Name(UOM1, 2) -Name(UOM2, 0) -Name(UOM3, 7) -Name(UOM4, 2) -Name(UOM5, 2) -Name(UOM6, 6) -Name(UOM7, 2) -Name(UOM8, 6) -Name(UOM9, 6) - -/* USB Overcurrent GPEs */ - -#if 0 /* TODO: Update */ -Method(UCOC, 0) { - Sleep(20) - Store(0x13,CMTI) - Store(0,GPSL) -} - -/* USB Port 0 overcurrent uses Gpm 0 */ -If(LLessEqual(UOM0,9)) { - Scope (\_GPE) { - Method (_L13) { - } - } -} - -/* USB Port 1 overcurrent uses Gpm 1 */ -If (LLessEqual(UOM1,9)) { - Scope (\_GPE) { - Method (_L14) { - } - } -} - -/* USB Port 2 overcurrent uses Gpm 2 */ -If (LLessEqual(UOM2,9)) { - Scope (\_GPE) { - Method (_L15) { - } - } -} - -/* USB Port 3 overcurrent uses Gpm 3 */ -If (LLessEqual(UOM3,9)) { - Scope (\_GPE) { - Method (_L16) { - } - } -} - -/* USB Port 4 overcurrent uses Gpm 4 */ -If (LLessEqual(UOM4,9)) { - Scope (\_GPE) { - Method (_L19) { - } - } -} - -/* USB Port 5 overcurrent uses Gpm 5 */ -If (LLessEqual(UOM5,9)) { - Scope (\_GPE) { - Method (_L1A) { - } - } -} - -/* USB Port 6 overcurrent uses Gpm 6 */ -If (LLessEqual(UOM6,9)) { - Scope (\_GPE) { - /* Method (_L1C) { */ - Method (_L06) { - } - } -} - -/* USB Port 7 overcurrent uses Gpm 7 */ -If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { - /* Method (_L1D) { */ - Method (_L07) { - } - } -} - -/* USB Port 8 overcurrent uses Gpm 8 */ -If (LLessEqual(UOM8,9)) { - Scope (\_GPE) { - Method (_L17) { - } - } -} - -/* USB Port 9 overcurrent uses Gpm 9 */ -If (LLessEqual(UOM9,9)) { - Scope (\_GPE) { - Method (_L0E) { - } - } -} -#endif diff --git a/src/mainboard/bap/ode_e20XX/acpi_tables.c b/src/mainboard/bap/ode_e20XX/acpi_tables.c deleted file mode 100644 index 20509e9..0000000 --- a/src/mainboard/bap/ode_e20XX/acpi_tables.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/acpi.h> -#include <arch/ioapic.h> - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); - - /* Write SB800 IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, - IO_APIC_ADDR, 0); - - /* TODO: Remove the hardcode */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS+1, - 0xFEC20000, 24); - - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xF); - /* 0: mean bus 0--->ISA */ - /* 0: PIC 0 */ - /* 2: APIC 2 */ - /* 5 mean: 0101 --> Edge-triggered, Active high */ - - /* create all subtables for processors */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1); - /* 1: LINT1 connect to NMI */ - - return current; -} diff --git a/src/mainboard/bap/ode_e20XX/board_info.txt b/src/mainboard/bap/ode_e20XX/board_info.txt deleted file mode 100644 index b351b8e..0000000 --- a/src/mainboard/bap/ode_e20XX/board_info.txt +++ /dev/null @@ -1 +0,0 @@ -Category: eval diff --git a/src/mainboard/bap/ode_e20XX/buildOpts.c b/src/mainboard/bap/ode_e20XX/buildOpts.c deleted file mode 100644 index 6c405cc..0000000 --- a/src/mainboard/bap/ode_e20XX/buildOpts.c +++ /dev/null @@ -1,341 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/** - * @file - * - * AMD User options selection for a Brazos platform solution system - * - * This file is placed in the user's platform directory and contains the - * build option selections desired for that platform. - * - * For Information about this file, see @ref platforminstall. - * - */ - -#include <stdlib.h> -#include <AGESA.h> - -#define INSTALL_FT3_SOCKET_SUPPORT TRUE -#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE - -#define INSTALL_G34_SOCKET_SUPPORT FALSE -#define INSTALL_C32_SOCKET_SUPPORT FALSE -#define INSTALL_S1G3_SOCKET_SUPPORT FALSE -#define INSTALL_S1G4_SOCKET_SUPPORT FALSE -#define INSTALL_ASB2_SOCKET_SUPPORT FALSE -#define INSTALL_FS1_SOCKET_SUPPORT FALSE -#define INSTALL_FM1_SOCKET_SUPPORT FALSE -#define INSTALL_FP2_SOCKET_SUPPORT FALSE -#define INSTALL_FT1_SOCKET_SUPPORT FALSE -#define INSTALL_AM3_SOCKET_SUPPORT FALSE -#define INSTALL_FM2_SOCKET_SUPPORT FALSE - - -#ifdef BLDOPT_REMOVE_FT3_SOCKET_SUPPORT - #if BLDOPT_REMOVE_FT3_SOCKET_SUPPORT == TRUE - #undef INSTALL_FT3_SOCKET_SUPPORT - #define INSTALL_FT3_SOCKET_SUPPORT FALSE - #endif -#endif - -//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE -//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE -#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE -#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE -#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE -//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE -#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE -//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE -#define BLDOPT_REMOVE_SRAT FALSE //TRUE -#define BLDOPT_REMOVE_SLIT FALSE //TRUE -#define BLDOPT_REMOVE_WHEA FALSE //TRUE -#define BLDOPT_REMOVE_CRAT TRUE -#define BLDOPT_REMOVE_CDIT TRUE -#define BLDOPT_REMOVE_DMI TRUE -//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE - -//This element selects whether P-States should be forced to be independent, -// as reported by the ACPI _PSD object. For single-link processors, -// setting TRUE for OS to support this feature. - -//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE - -#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER -/* Build configuration values here. - */ -#define BLDCFG_VRM_CURRENT_LIMIT 15000 -#define BLDCFG_VRM_NB_CURRENT_LIMIT 13000 -#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 21000 -#define BLDCFG_VRM_SVI_OCP_LEVEL BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT -#define BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT 17000 -#define BLDCFG_VRM_NB_SVI_OCP_LEVEL BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT -#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0 -#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 0 -#define BLDCFG_VRM_SLEW_RATE 10000 -#define BLDCFG_VRM_NB_SLEW_RATE BLDCFG_VRM_SLEW_RATE -#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE - -#define BLDCFG_PLAT_NUM_IO_APICS 3 -#define BLDCFG_GNB_IOAPIC_ADDRESS 0xFEC20000 -#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST -#define BLDCFG_MEM_INIT_PSTATE 0 -#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 // Specifies the IO addresses trapped by the - // core for C-state entry requests. A value - // of 0 in this field specifies that the core - // does not trap any IO addresses for C-state entry. - // Values greater than 0xFFF8 results in undefined behavior. -#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770 - -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE - -#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY -#define BLDCFG_MEMORY_MODE_UNGANGED TRUE -#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE -#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE -#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE -#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE -#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE -#define BLDCFG_MEMORY_POWER_DOWN TRUE -#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT -#define BLDCFG_ONLINE_SPARE FALSE -#define BLDCFG_BANK_SWIZZLE TRUE -#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#define BLDCFG_MEMORY_CLOCK_SELECT DDR1866_FREQUENCY -#define BLDCFG_DQS_TRAINING_CONTROL TRUE -#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE -#define BLDCFG_USE_BURST_MODE FALSE -#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE -#define BLDCFG_ENABLE_ECC_FEATURE TRUE -#define BLDCFG_ECC_REDIRECTION FALSE -#define BLDCFG_SCRUB_DRAM_RATE 0 -#define BLDCFG_SCRUB_L2_RATE 0 -#define BLDCFG_SCRUB_L3_RATE 0 -#define BLDCFG_SCRUB_IC_RATE 0 -#define BLDCFG_SCRUB_DC_RATE 0 -#define BLDCFG_ECC_SYNC_FLOOD TRUE -#define BLDCFG_ECC_SYMBOL_SIZE 4 -#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000ul -#define BLDCFG_1GB_ALIGN FALSE -#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED -#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO -#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeDisabled -#define BLDCFG_IOMMU_SUPPORT FALSE -#define OPTION_GFX_INIT_SVIEW FALSE -//#define BLDCFG_PLATFORM_POWER_POLICY_MODE BatteryLife - -//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL OEM_LCD_BACK_LIGHT_CONTROL -#define BLDCFG_CFG_ABM_SUPPORT TRUE - -#define BLDCFG_CFG_GNB_HD_AUDIO TRUE -//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID -//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID -//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID - -#ifdef PCIEX_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_BASE PCIEX_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_SIZE (PCIEX_LENGTH >> 20) -#endif - -#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P' -#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' -#define BLDCFG_PCIE_TRAINING_ALGORITHM PcieTrainingDistributed - -/* Process the options... - * This file include MUST occur AFTER the user option selection settings - */ -/* - * Customized OEM build configurations for FCH component - */ -// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00 -// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20 -// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00 -// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400 -// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404 -// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408 -// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410 -// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420 -// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000 -// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000 -// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000 -// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0 -// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00 -// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000 -// #define BLDCFG_AZALIA_SSID 0x780D1022 -// #define BLDCFG_SMBUS_SSID 0x780B1022 -// #define BLDCFG_IDE_SSID 0x780C1022 -// #define BLDCFG_SATA_AHCI_SSID 0x78011022 -// #define BLDCFG_SATA_IDE_SSID 0x78001022 -// #define BLDCFG_SATA_RAID5_SSID 0x78031022 -// #define BLDCFG_SATA_RAID_SSID 0x78021022 -// #define BLDCFG_EHCI_SSID 0x78081022 -// #define BLDCFG_OHCI_SSID 0x78071022 -// #define BLDCFG_LPC_SSID 0x780E1022 -// #define BLDCFG_SD_SSID 0x78061022 -// #define BLDCFG_XHCI_SSID 0x78121022 -// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE -// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE -// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4 -// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE - -CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = -{ - { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 }, - { CPU_LIST_TERMINAL } -}; - -#define BLDCFG_AP_MTRR_SETTINGS_LIST &KabiniApMtrrSettingsList - -/* Include the files that instantiate the configuration definitions. */ -#include "cpuRegisters.h" -#include "cpuFamRegisters.h" -#include "cpuFamilyTranslation.h" -#include "AdvancedApi.h" -#include "heapManager.h" -#include "CreateStruct.h" -#include "cpuFeatures.h" -#include "Table.h" -#include "cpuEarlyInit.h" -#include "cpuLateInit.h" -#include "GnbInterface.h" - - // This is the delivery package title, "BrazosPI" - // This string MUST be exactly 8 characters long -#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} - - // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long -#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} - -/* MEMORY_BUS_SPEED */ -//#define DDR400_FREQUENCY 200 ///< DDR 400 -//#define DDR533_FREQUENCY 266 ///< DDR 533 -//#define DDR667_FREQUENCY 333 ///< DDR 667 -//#define DDR800_FREQUENCY 400 ///< DDR 800 -//#define DDR1066_FREQUENCY 533 ///< DDR 1066 -//#define DDR1333_FREQUENCY 667 ///< DDR 1333 -//#define DDR1600_FREQUENCY 800 ///< DDR 1600 -//#define DDR1866_FREQUENCY 933 ///< DDR 1866 -//#define DDR2100_FREQUENCY 1050 ///< DDR 2100 -//#define DDR2133_FREQUENCY 1066 ///< DDR 2133 -//#define DDR2400_FREQUENCY 1200 ///< DDR 2400 -//#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency -// -///* QUANDRANK_TYPE*/ -//#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -//#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM -// -///* USER_MEMORY_TIMING_MODE */ -//#define TIMING_MODE_AUTO 0 ///< Use best rate possible -//#define TIMING_MODE_LIMITED 1 ///< Set user top limit -//#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed -// -///* POWER_DOWN_MODE */ -//#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -//#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode - -/* - * Agesa optional capabilities selection. - * Uncomment and mark FALSE those features you wish to include in the build. - * Comment out or mark TRUE those features you want to REMOVE from the build. - */ - -#define DFLT_SMBUS0_BASE_ADDRESS 0xB00 -#define DFLT_SMBUS1_BASE_ADDRESS 0xB20 -#define DFLT_SIO_PME_BASE_ADDRESS 0xE00 -#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800 -#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804 -#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808 -#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810 -#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820 -#define DFLT_SPI_BASE_ADDRESS 0xFEC10000 -#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 -#define DFLT_HPET_BASE_ADDRESS 0xFED00000 -#define DFLT_SMI_CMD_PORT 0xB0 -#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 -#define DFLT_GEC_BASE_ADDRESS 0xFED61000 -#define DFLT_AZALIA_SSID 0x780D1022 -#define DFLT_SMBUS_SSID 0x780B1022 -#define DFLT_IDE_SSID 0x780C1022 -#define DFLT_SATA_AHCI_SSID 0x78011022 -#define DFLT_SATA_IDE_SSID 0x78001022 -#define DFLT_SATA_RAID5_SSID 0x78031022 -#define DFLT_SATA_RAID_SSID 0x78021022 -#define DFLT_EHCI_SSID 0x78081022 -#define DFLT_OHCI_SSID 0x78071022 -#define DFLT_LPC_SSID 0x780E1022 -#define DFLT_SD_SSID 0x78061022 -#define DFLT_XHCI_SSID 0x78121022 -#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE -#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE -#define DFLT_FCH_GPP_LINK_CONFIG PortA4 -#define DFLT_FCH_GPP_PORT0_PRESENT FALSE -#define DFLT_FCH_GPP_PORT1_PRESENT FALSE -#define DFLT_FCH_GPP_PORT2_PRESENT FALSE -#define DFLT_FCH_GPP_PORT3_PRESENT FALSE -#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE -//#define BLDCFG_IR_PIN_CONTROL 0x33 - -GPIO_CONTROL gizmo2_gpio[] = { - {183, Function1, GpioIn | GpioOutEnB | PullUpB}, - {-1} -}; -//#define BLDCFG_FCH_GPIO_CONTROL_LIST (&gizmo2_gpio[0]) - -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. -#define DFLT_SCRUB_DRAM_RATE (0) -#define DFLT_SCRUB_L2_RATE (0) -#define DFLT_SCRUB_L3_RATE (0) -#define DFLT_SCRUB_IC_RATE (0) -#define DFLT_SCRUB_DC_RATE (0) -#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define DFLT_VRM_SLEW_RATE (5000) - -#include <PlatformInstall.h> diff --git a/src/mainboard/bap/ode_e20XX/cmos.layout b/src/mainboard/bap/ode_e20XX/cmos.layout deleted file mode 100644 index e1dbd9a..0000000 --- a/src/mainboard/bap/ode_e20XX/cmos.layout +++ /dev/null @@ -1,66 +0,0 @@ -#***************************************************************************** -# -# This file is part of the coreboot project. -# -# Copyright (C) 2012 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -#***************************************************************************** - -entries - -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#392 3 r 0 unused -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum -# Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% - -checksums - -checksum 392 983 984 diff --git a/src/mainboard/bap/ode_e20XX/devicetree.cb b/src/mainboard/bap/ode_e20XX/devicetree.cb deleted file mode 100644 index 893d323..0000000 --- a/src/mainboard/bap/ode_e20XX/devicetree.cb +++ /dev/null @@ -1,115 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2013 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -chip northbridge/amd/agesa/family16kb/root_complex - device cpu_cluster 0 on - chip cpu/amd/agesa/family16kb - device lapic 0 on end - end - end - - device domain 0 on - subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/agesa/family16kb - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x9835 - device pci 1.1 on end # Internal Multimedia - device pci 2.0 on end # PCIe Host Bridge - device pci 2.1 on end # x4 PCIe Slot - device pci 2.2 on end # PCIe Q7 Realtek GBit LAN - device pci 2.3 on end # PCIe CB Realtek GBit LAN - device pci 2.4 on end # x2 PCIe Microsemi FPGA - end #chip northbridge/amd/agesa/family16kb - - chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus - device pci 10.0 on end # XHCI HC0 - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on end # SM - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/fintek/f81866d - register "hwm_amd_tsi_addr" = "0x98" # Set to AMD - register "hwm_amd_tsi_control" = "0x02" # Set to AMD - register "hwm_fan_select" = "0xC0" # Sets Fan2 to PWM - register "hwm_fan_mode" = "0xD5" # Sets FAN1-3 to Auto RPM mode - register "hwm_fan3_control" = "0x00" # Fan control 23kHz - register "hwm_fan2_temp_map_select" = "0x1E" # Fan control 23kHz - register "hwm_fan2_bound1" = "0x3C" # 60°C - register "hwm_fan2_bound2" = "0x32" # 50°C - register "hwm_fan2_bound3" = "0x28" # 40°C - register "hwm_fan2_bound4" = "0x1E" # 30°C - register "hwm_fan2_seg1_speed" = "0xFF" # 100% - register "hwm_fan2_seg2_speed" = "0xD9" # 85% - register "hwm_fan2_seg3_speed" = "0xB2" # 70% - register "hwm_fan2_seg4_speed" = "0x99" # 60% - register "hwm_fan2_seg5_speed" = "0x80" # 50% - register "hwm_temp_sens_type" = "0x04" # Sets temp sensor 1 type to to thermistor - device pnp 4e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 4e.3 off end # Parallel Port - device pnp 4e.4 on # Hardware Monitor - io 0x60 = 0x295 - irq 0x70 = 0 - end - device pnp 4e.5 off # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 4e.6 off end # GPIO - device pnp 4e.7 on end # WDT - device pnp 4e.a off end # PME - device pnp 4e.10 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 4e.11 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 4e.12 on # COM3 - io 0x60 = 0x3e8 - irq 0x70 = 4 - end - device pnp 4e.13 on # COM4 - io 0x60 = 0x2e8 - irq 0x70 = 3 - end - device pnp 4e.14 off # COM5 - end - device pnp 4e.15 off # COM6 - end - end # f81866d - end #LPC - device pci 14.7 on end # SD - end #chip southbridge/amd/agesa/hudson - - chip northbridge/amd/agesa/family16kb - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - end - - end #domain -end #northbridge/amd/agesa/family16kb/root_complex diff --git a/src/mainboard/bap/ode_e20XX/dsdt.asl b/src/mainboard/bap/ode_e20XX/dsdt.asl deleted file mode 100644 index c4fc934..0000000 --- a/src/mainboard/bap/ode_e20XX/dsdt.asl +++ /dev/null @@ -1,88 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* DefinitionBlock Statement */ -#include <arch/acpi.h> -DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - OEM_ID, - ACPI_TABLE_CREATOR, - 0x00010001 /* OEM Revision */ - ) -{ /* Start of ASL file */ - /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ - - /* Globals for the platform */ - #include "acpi/mainboard.asl" - - /* Describe the USB Overcurrent pins */ - #include "acpi/usb_oc.asl" - - /* PCI IRQ mapping for the Southbridge */ - #include <southbridge/amd/agesa/hudson/acpi/pcie.asl> - - /* Describe the processor tree (\_PR) */ - #include <cpu/amd/agesa/family16kb/acpi/cpu.asl> - - /* Contains the supported sleep states for this chipset */ - #include <southbridge/amd/common/acpi/sleepstates.asl> - - /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */ - #include "acpi/sleep.asl" - - /* System Bus */ - Scope(\_SB) { /* Start \_SB scope */ - /* global utility methods expected within the \_SB scope */ - #include <arch/x86/acpi/globutil.asl> - - /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ - #include "acpi/routing.asl" - - Device(PWRB) { - Name(_HID, EISAID("PNP0C0C")) - Name(_UID, 0xAA) - Name(_PRW, Package () {3, 0x04}) - Name(_STA, 0x0B) - } - - Device(PCI0) { - /* Describe the AMD Northbridge */ - #include <northbridge/amd/agesa/family16kb/acpi/northbridge.asl> - - /* Describe the AMD Fusion Controller Hub Southbridge */ - #include <southbridge/amd/agesa/hudson/acpi/fch.asl> - } - - /* Describe PCI INT[A-H] for the Southbridge */ - #include <southbridge/amd/agesa/hudson/acpi/pci_int.asl> - - } /* End \_SB scope */ - - /* Describe SMBUS for the Southbridge */ - #include <southbridge/amd/agesa/hudson/acpi/smbus.asl> - - /* Define the General Purpose Events for the platform */ - #include "acpi/gpe.asl" - - /* Define the Thermal zones and methods for the platform */ - #include "acpi/thermal.asl" - - /* Define the System Indicators for the platform */ - #include "acpi/si.asl" -} -/* End of ASL file */ diff --git a/src/mainboard/bap/ode_e20XX/irq_tables.c b/src/mainboard/bap/ode_e20XX/irq_tables.c deleted file mode 100644 index 530c132..0000000 --- a/src/mainboard/bap/ode_e20XX/irq_tables.c +++ /dev/null @@ -1,100 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <string.h> -#include <stdint.h> -#include <arch/pirq_routing.h> - -static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, - u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, - u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, - u8 slot, u8 rfu) -{ - pirq_info->bus = bus; - pirq_info->devfn = devfn; - pirq_info->irq[0].link = link0; - pirq_info->irq[0].bitmap = bitmap0; - pirq_info->irq[1].link = link1; - pirq_info->irq[1].bitmap = bitmap1; - pirq_info->irq[2].link = link2; - pirq_info->irq[2].bitmap = bitmap2; - pirq_info->irq[3].link = link3; - pirq_info->irq[3].bitmap = bitmap3; - pirq_info->slot = slot; - pirq_info->rfu = rfu; -} - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - struct irq_routing_table *pirq; - struct irq_info *pirq_info; - u32 slot_num; - u8 *v; - - u8 sum = 0; - int i; - - /* Align the table to be 16 byte aligned. */ - addr += 15; - addr &= ~15; - - /* This table must be between 0xf0000 & 0x100000 */ - printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); - - pirq = (void *)(addr); - v = (u8 *) (addr); - - pirq->signature = PIRQ_SIGNATURE; - pirq->version = PIRQ_VERSION; - - pirq->rtr_bus = 0; - pirq->rtr_devfn = PCI_DEVFN(0x14, 4); - - pirq->exclusive_irqs = 0; - - pirq->rtr_vendor = 0x1002; - pirq->rtr_device = 0x4384; - - pirq->miniport_data = 0; - - memset(pirq->rfu, 0, sizeof(pirq->rfu)); - - pirq_info = (void *)(&pirq->checksum + 1); - slot_num = 0; - - /* pci bridge */ - write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), - 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, - 0); - pirq_info++; - - slot_num++; - - pirq->size = 32 + 16 * slot_num; - - for (i = 0; i < pirq->size; i++) - sum += v[i]; - - sum = pirq->checksum - sum; - - if (sum != pirq->checksum) { - pirq->checksum = sum; - } - - printk(BIOS_INFO, "write_pirq_routing_table done.\n"); - - return (unsigned long)pirq_info; -} diff --git a/src/mainboard/bap/ode_e20XX/mainboard.c b/src/mainboard/bap/ode_e20XX/mainboard.c deleted file mode 100644 index 6bd9445..0000000 --- a/src/mainboard/bap/ode_e20XX/mainboard.c +++ /dev/null @@ -1,122 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC - * All Rights Reserved - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/device.h> - -#include <southbridge/amd/agesa/hudson/pci_devs.h> -#include <southbridge/amd/agesa/hudson/amd_pci_int_defs.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <northbridge/amd/agesa/family16kb/pci_devs.h> - -/*********************************************************** - * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. - * This table is responsible for physically routing the PIC and - * IOAPIC IRQs to the different PCI devices on the system. It - * is read and written via registers 0xC00/0xC01 as an - * Index/Data pair. These values are chipset and mainboard - * dependent and should be updated accordingly. - * - * These values are used by the PCI configuration space, - * MP Tables. TODO: Make ACPI use these values too. - */ -const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = { - /* INTA# - INTH# */ - [0x00] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B, - /* Misc-nil,0,1,2, INT from Serial irq */ - [0x08] = 0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - /* SCI, SMBUS0, ASF, HDA, FC, RSVD, PerMon, SD */ - [0x10] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, - /* IMC INT0 - 5 */ - [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, - /* USB Devs 18/19/22 INTA-C */ - [0x30] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B, - /* SATA */ - [0x41] = 0x0F, -}; - -const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = { - /* INTA# - INTH# */ - [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, - /* Misc-nil,0,1,2, INT from Serial irq */ - [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon, SD */ - [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F, - /* IMC INT0 - 5 */ - [0x20] = 0x05,0x1F,0x1F,0x1F,0x1F,0x1F, - /* USB Devs 18/19/20/22 INTA-C */ - [0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12, - /* SATA */ - [0x41] = 0x13 -}; - -/* - * This table defines the index into the picr/intr_data - * tables for each device. Any enabled device and slot - * that uses hardware interrupts should have an entry - * in this table to define its index into the FCH - * PCI_INTR register 0xC00/0xC01. This index will define - * the interrupt that it should use. Putting PIRQ_A into - * the PIN A index for a device will tell that device to - * use PIC IRQ 10 if it uses PIN A for its hardware INT. - */ -static const struct pirq_struct mainboard_pirq_data[] = { - /* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D}}, */ - {GFX_DEVFN, {PIRQ_A, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* VGA: 01.0 */ - {ACTL_DEVFN,{PIRQ_NC, PIRQ_B, PIRQ_NC, PIRQ_NC}}, /* Audio: 01.1 */ - {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* x4 PCIe: 02.1 */ - {NB_PCIE_PORT2_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A}}, /* mPCIe: 02.2 */ - {NB_PCIE_PORT3_DEVFN, {PIRQ_C, PIRQ_D, PIRQ_A, PIRQ_B}}, /* NIC: 02.3 */ - {NB_PCIE_PORT4_DEVFN, {PIRQ_D, PIRQ_A, PIRQ_B, PIRQ_C}}, /* Edge: 02.4 */ - {NB_PCIE_PORT5_DEVFN, {PIRQ_E, PIRQ_F, PIRQ_G, PIRQ_H}}, /* Edge: 02.5 */ - {XHCI_DEVFN, {PIRQ_C, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* XHCI: 10.0 */ - {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SATA: 11.0 */ - {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1: 12.0 */ - {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1: 12.2 */ - {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2: 13.0 */ - {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2: 13.2 */ - {SMBUS_DEVFN, {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SMBUS: 14.0 */ - {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* HDA: 14.2 */ - {SD_DEVFN, {PIRQ_SD, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SD: 14.7 */ -}; - -const u8 *picr_data = mainboard_picr_data; -const u8 *intr_data = mainboard_intr_data; - -/* PIRQ Setup */ -static void pirq_setup(void) -{ - pirq_data_ptr = mainboard_pirq_data; - pirq_data_size = sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct); - intr_data_ptr = mainboard_intr_data; - picr_data_ptr = mainboard_picr_data; -} - -/********************************************** - * enable the dedicated function in mainboard. - **********************************************/ -static void mainboard_enable(struct device *dev) -{ - printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - - /* Initialize the PIRQ data structures for consumption */ - pirq_setup(); -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/bap/ode_e20XX/mptable.c b/src/mainboard/bap/ode_e20XX/mptable.c deleted file mode 100644 index e4edc5f..0000000 --- a/src/mainboard/bap/ode_e20XX/mptable.c +++ /dev/null @@ -1,159 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <stdint.h> -#include <cpu/x86/lapic.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <drivers/generic/ioapic/chip.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - /* Initialize the MP_Table */ - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - /* - * Type 0: Processor Entries: - * LAPIC ID, LAPIC Version, CPU Flags:EN/BP, - * CPU Signature (Stepping, Model, Family), - * Feature Flags - */ - smp_write_processors(mc); - - /* - * Type 1: Bus Entries: - * Bus ID, Bus Type - */ - mptable_write_buses(mc, NULL, &bus_isa); - - /* - * Type 2: I/O APICs: - * APIC ID, Version, APIC Flags:EN, Address - */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* - * Type 3: I/O Interrupt Table Entries: - * Int Type, Int Polarity, Int Level, Source Bus ID, - * Source Bus IRQ, Dest APIC ID, Dest PIN# - */ - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) - - /* APU Internal Graphic Device */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]); - - /* SMBUS / ACPI */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]); - - /* Southbridge HD Audio */ - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]); - - /* LPC */ - PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]); - PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]); - PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]); - PCI_INT(0x0, 0x16, 0x2, intr_data_ptr[PIRQ_EHCI3]); - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_OHCI4]); - - /* SATA */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]); - - /* on board NIC & Slot PCIE */ - PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); - PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]); - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0 */ - PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); - PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); - PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]); - PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]); - - /* PCI_SLOT 1 */ - PCI_INT(bus_pci, 0x6, 0x0, intr_data_ptr[PIRQ_F]); - PCI_INT(bus_pci, 0x6, 0x1, intr_data_ptr[PIRQ_G]); - PCI_INT(bus_pci, 0x6, 0x2, intr_data_ptr[PIRQ_H]); - PCI_INT(bus_pci, 0x6, 0x3, intr_data_ptr[PIRQ_E]); - - /* PCI_SLOT 2 */ - PCI_INT(bus_pci, 0x7, 0x0, intr_data_ptr[PIRQ_G]); - PCI_INT(bus_pci, 0x7, 0x1, intr_data_ptr[PIRQ_H]); - PCI_INT(bus_pci, 0x7, 0x2, intr_data_ptr[PIRQ_E]); - PCI_INT(bus_pci, 0x7, 0x3, intr_data_ptr[PIRQ_F]); - - PCI_INT(bus_pci, 0x0, 0x0, intr_data_ptr[PIRQ_C]); - PCI_INT(bus_pci, 0x0, 0x1, intr_data_ptr[PIRQ_D]); - PCI_INT(bus_pci, 0x0, 0x2, intr_data_ptr[PIRQ_E]); - } - - /* PCIe Lan*/ - PCI_INT(0x0, 0x06, 0x0, intr_data_ptr[PIRQ_D]); - - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_A]); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_B]); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_C]); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_D]); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/bap/ode_e20XX/romstage.c b/src/mainboard/bap/ode_e20XX/romstage.c deleted file mode 100644 index 505de38..0000000 --- a/src/mainboard/bap/ode_e20XX/romstage.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2015 BAP - Bruhnspace Advanced Projects - * (Written by Fabian Kunkel <fabi(a)adv.bruhnspace.com> for BAP) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <device/pci_ops.h> -#include <southbridge/amd/agesa/hudson/hudson.h> - -#include <northbridge/amd/agesa/state_machine.h> -#include <superio/fintek/common/fintek.h> -#include <superio/fintek/f81866d/f81866d.h> - - -#define SERIAL_DEV1 PNP_DEV(0x4e, F81866D_SP1) - -void board_BeforeAgesa(struct sysinfo *cb) -{ - /* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */ - outb(0xea, 0xcd6); - outb(0x1, 0xcd7); - - /* Set LPC decode enables. */ - pci_devfn_t dev = PCI_DEV(0, 0x14, 3); - pci_write_config32(dev, 0x44, 0xff03ffd5); - - fintek_enable_serial(SERIAL_DEV1, CONFIG_TTYS0_BASE); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/38106 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie02997772dbc1b3a36fa0873e1f51790b5e326ab Gerrit-Change-Number: 38106 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/gizmosphere/gizmo2: Drop boards with ROMCC_BOOTBLOCK
by HAOUAS Elyes (Code Review) Jan. 7, 2020

Jan. 7, 2020

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38107 ) Change subject: mb/gizmosphere/gizmo2: Drop boards with ROMCC_BOOTBLOCK ...................................................................... mb/gizmosphere/gizmo2: Drop boards with ROMCC_BOOTBLOCK ROMCC_BOOTBLOCK is no more. Drop unsupported, unmaintained boards. Change-Id: I1947638f80a1de498b8a34c5099283d658f2b8d5 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- D src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c D src/mainboard/gizmosphere/gizmo2/Kconfig D src/mainboard/gizmosphere/gizmo2/Kconfig.name D src/mainboard/gizmosphere/gizmo2/Makefile.inc D src/mainboard/gizmosphere/gizmo2/Micron_MT41J128M16JT.spd.hex D src/mainboard/gizmosphere/gizmo2/OemCustomize.c D src/mainboard/gizmosphere/gizmo2/OptionsIds.h D src/mainboard/gizmosphere/gizmo2/acpi/gpe.asl D src/mainboard/gizmosphere/gizmo2/acpi/ide.asl D src/mainboard/gizmosphere/gizmo2/acpi/mainboard.asl D src/mainboard/gizmosphere/gizmo2/acpi/routing.asl D src/mainboard/gizmosphere/gizmo2/acpi/sata.asl D src/mainboard/gizmosphere/gizmo2/acpi/si.asl D src/mainboard/gizmosphere/gizmo2/acpi/sleep.asl D src/mainboard/gizmosphere/gizmo2/acpi/superio.asl D src/mainboard/gizmosphere/gizmo2/acpi/thermal.asl D src/mainboard/gizmosphere/gizmo2/acpi/usb_oc.asl D src/mainboard/gizmosphere/gizmo2/acpi_tables.c D src/mainboard/gizmosphere/gizmo2/board_info.txt D src/mainboard/gizmosphere/gizmo2/buildOpts.c D src/mainboard/gizmosphere/gizmo2/cmos.layout D src/mainboard/gizmosphere/gizmo2/devicetree.cb D src/mainboard/gizmosphere/gizmo2/dsdt.asl D src/mainboard/gizmosphere/gizmo2/irq_tables.c D src/mainboard/gizmosphere/gizmo2/mainboard.c D src/mainboard/gizmosphere/gizmo2/mptable.c D src/mainboard/gizmosphere/gizmo2/romstage.c 27 files changed, 0 insertions(+), 2,713 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/38107/1 diff --git a/src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c b/src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c deleted file mode 100644 index 99162d8..0000000 --- a/src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c +++ /dev/null @@ -1,186 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <AGESA.h> -#include <northbridge/amd/agesa/BiosCallOuts.h> -#include <northbridge/amd/agesa/state_machine.h> -#include <FchPlatform.h> -#include <stdlib.h> - -#include "imc.h" - -const BIOS_CALLOUT_STRUCT BiosCallouts[] = -{ - {AGESA_DO_RESET, agesa_Reset }, - {AGESA_READ_SPD, agesa_ReadSpd_from_cbfs }, - {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, - {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, - {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData }, - {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, - {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, - {AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage } -}; -const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); - -/** - * ALC272 Verb Table - */ -const CODEC_ENTRY Alc272_VerbTbl[] = { - {0x11, 0x411111F0}, // - SPDIF_OUT2 - {0x12, 0x411111F0}, // - DMIC_1/2 - {0x13, 0x411111F0}, // - DMIC_3/4 - {0x14, 0x411111F0}, // Port D - LOUT1 - {0x15, 0x01011050}, // Port A - LOUT2 Explorer 2x DAC - {0x16, 0x411111F0}, // - {0x17, 0x411111F0}, // Port H - MONO - {0x18, 0x01a11840}, // Port B - MIC1 - {0x19, 0x411111F0}, // Port F - MIC2 - {0x1a, 0x01811030}, // Port C - LINE1 - {0x1b, 0x01811020}, // Port E - LINE2 Explorer 2x ADC - {0x1d, 0x40130605}, // - PCBEEP - {0x1e, 0x411111F0}, // - SPDIF_OUT1 - {0x21, 0x01211010}, // Port I - HPOUT - {0xff, 0xffffffff} -}; - -static const CODEC_TBL_LIST CodecTableList[] = -{ - {0x10ec0272, (CODEC_ENTRY*)&Alc272_VerbTbl[0]}, - {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL} -}; - -#define FAN_INPUT_INTERNAL_DIODE 0 -#define FAN_INPUT_TEMP0 1 -#define FAN_INPUT_TEMP1 2 -#define FAN_INPUT_TEMP2 3 -#define FAN_INPUT_TEMP3 4 -#define FAN_INPUT_TEMP0_FILTER 5 -#define FAN_INPUT_ZERO 6 -#define FAN_INPUT_DISABLED 7 - -#define FAN_AUTOMODE (1 << 0) -#define FAN_LINEARMODE (1 << 1) -#define FAN_STEPMODE ~(1 << 1) -#define FAN_POLARITY_HIGH (1 << 2) -#define FAN_POLARITY_LOW ~(1 << 2) - -/* Normally, 4-wire fan runs at 25KHz and 3-wire fan runs at 100Hz */ -#define FREQ_28KHZ 0x0 -#define FREQ_25KHZ 0x1 -#define FREQ_23KHZ 0x2 -#define FREQ_21KHZ 0x3 -#define FREQ_29KHZ 0x4 -#define FREQ_18KHZ 0x5 -#define FREQ_100HZ 0xF7 -#define FREQ_87HZ 0xF8 -#define FREQ_58HZ 0xF9 -#define FREQ_44HZ 0xFA -#define FREQ_35HZ 0xFB -#define FREQ_29HZ 0xFC -#define FREQ_22HZ 0xFD -#define FREQ_14HZ 0xFE -#define FREQ_11HZ 0xFF - -/* Hardware Monitor Fan Control - * Hardware limitation: - * HWM failed to read the input temperture vi I2C, - * if other software switch the I2C switch by mistake or intention. - * We recommend to using IMC to control Fans, instead of HWM. - */ -static void oem_fan_control(FCH_DATA_BLOCK *FchParams) -{ - /* Enable IMC fan control. the recommand way */ - if (CONFIG(HUDSON_IMC_FWM)) { - imc_reg_init(); - - /* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */ - FchParams->Hwm.HwMonitorEnable = TRUE; - FchParams->Hwm.HwmFchtsiAutoPoll = FALSE;/* 0 disable, 1 enable TSI Auto Polling */ - - FchParams->Imc.ImcEnable = TRUE; - FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */ - FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ - - LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader); - - /* Thermal Zone Parameter */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; //BIT0 | BIT2 | BIT5; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x4e;//6 | BIT3; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x04; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x9a; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg7 = 0x01; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg8 = 0x01; /* PWM steping rate in unit of PWM level percentage */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg9 = 0x00; - - /* IMC Fan Policy temperature thresholds */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 50; /*AC0 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 45; /*AC1 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 40; /*AC2 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff; /*AC3 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0xff; /*AC4 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0xff; /*AC5 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0xff; /*AC6 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0xff; /*AC7 lowest threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegA = 0x4b; /*critical threshold* in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegB = 0x00; - - /* IMC Fan Policy PWM Settings */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg2 = 100; /* AL0 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg3 = 99; /* AL1 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg4 = 98; /* AL2 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg5 = 0xff; /* AL3 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg6 = 0xff; /* AL4 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg7 = 0xff; /* AL5 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0xff; /* AL6 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0xff; /* AL7 percentage */ - - FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x111;//BIT0 | BIT4 |BIT8; - - /* NOTE: - * FchInitLateHwm will overwrite the EcStruct with EcDefaultMassege, - * AGESA put EcDefaultMassege as global data in ROM, so we can't overwride it. - * so we remove it from AGESA code. Please Seee FchInitLateHwm. - */ - } else { - /* HWM fan control, the way not recommand */ - FchParams->Imc.ImcEnable = FALSE; - FchParams->Hwm.HwMonitorEnable = TRUE; - FchParams->Hwm.HwmFchtsiAutoPoll = TRUE;/* 1 enable, 0 disable TSI Auto Polling */ - } -} - -void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset) -{ -} - -void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env) -{ - /* Azalia Controller OEM Codec Table Pointer */ - FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&CodecTableList[0]); - - FchParams_env->Imc.ImcEnable = FALSE; - FchParams_env->Hwm.HwMonitorEnable = FALSE; - FchParams_env->Hwm.HwmFchtsiAutoPoll = FALSE;/* 1 enable, 0 disable TSI Auto Polling */ - - /* Fan Control */ - oem_fan_control(FchParams_env); -} diff --git a/src/mainboard/gizmosphere/gizmo2/Kconfig b/src/mainboard/gizmosphere/gizmo2/Kconfig deleted file mode 100644 index 685e271..0000000 --- a/src/mainboard/gizmosphere/gizmo2/Kconfig +++ /dev/null @@ -1,70 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2012 Advanced Micro Devices, Inc. -# Copyright (C) 2013-2014 Sage Electronic Engineering -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -config BOARD_GIZMOSPHERE_GIZMO2 - def_bool n - -if BOARD_GIZMOSPHERE_GIZMO2 - -config BOARD_SPECIFIC_OPTIONS - def_bool y - #select ROMCC_BOOTBLOCK - select CPU_AMD_AGESA_FAMILY16_KB - select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB - select SOUTHBRIDGE_AMD_AGESA_YANGTZE - select DEFAULT_POST_ON_LPC - select HAVE_OPTION_TABLE - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select HAVE_ACPI_RESUME - select HAVE_ACPI_TABLES - select BOARD_ROMSIZE_KB_4096 - select GFXUMA - select HUDSON_IMC_ENABLE - -config MAINBOARD_DIR - string - default "gizmosphere/gizmo2" - -config MAINBOARD_PART_NUMBER - string - default "Gizmo2" - -config HW_MEM_HOLE_SIZEK - hex - default 0x200000 - -config MAX_CPUS - int - default 4 - -config IRQ_SLOT_COUNT - int - default 11 - -config ONBOARD_VGA_IS_PRIMARY - bool - default y - -config HUDSON_LEGACY_FREE - bool - default y - -config DIMM_SPD_SIZE - int - default 128 - -endif # BOARD_GIZMOSPHERE_GIZMO2 diff --git a/src/mainboard/gizmosphere/gizmo2/Kconfig.name b/src/mainboard/gizmosphere/gizmo2/Kconfig.name deleted file mode 100644 index 29688e2..0000000 --- a/src/mainboard/gizmosphere/gizmo2/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -#config BOARD_GIZMOSPHERE_GIZMO2 -# bool"Gizmo2" diff --git a/src/mainboard/gizmosphere/gizmo2/Makefile.inc b/src/mainboard/gizmosphere/gizmo2/Makefile.inc deleted file mode 100644 index 8a24bea..0000000 --- a/src/mainboard/gizmosphere/gizmo2/Makefile.inc +++ /dev/null @@ -1,43 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2012 Advanced Micro Devices, Inc. -# Copyright (C) 2014 Sage Electronic Engineering, LLC -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -romstage-y += buildOpts.c -romstage-y += BiosCallOuts.c -romstage-y += OemCustomize.c - -ramstage-y += buildOpts.c -ramstage-y += BiosCallOuts.c -ramstage-y += OemCustomize.c - -## DIMM SPD for on-board memory -SPD_BIN = $(obj)/spd.bin - -# Order of names in SPD_SOURCES is important! -SPD_SOURCES = Micron_MT41J128M16JT - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/gizmosphere/gizmo2/Micron_MT41J128M16JT.spd.hex b/src/mainboard/gizmosphere/gizmo2/Micron_MT41J128M16JT.spd.hex deleted file mode 100644 index 510f690..0000000 --- a/src/mainboard/gizmosphere/gizmo2/Micron_MT41J128M16JT.spd.hex +++ /dev/null @@ -1,231 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2014 Sage Electronic Engineering, LLC. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. - -# Gizmo2 has 1GB using 4 Micron_MT41J128M16JT-125 chips -# The datasheet is available at: -# http://download.micron.com/pdf/datasheets/dram/ddr3/2Gb_DDR3_SDRAM.pdf - -# SPD contents for Gizmo2 2GB DDR3 (1600MHz PC3-12800) soldered down - -# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage -# bits[3:0]: 1 = 128 SPD Bytes Used -# bits[6:4]: 1 = 256 SPD Bytes Total -# bit7 : 0 = CRC covers bytes 0 ~ 125 -11 - -# 1 SPD Revision - -# 0x10 = Revision 1.0 -10 - -# 2 Key Byte / DRAM Device Type -# bits[7:0]: 0x0b = DDR3 SDRAM -0B - -# 3 Key Byte / Module Type -# bits[3:0]: 3 = SO-DIMM -# bits[7:4]: reserved -03 - -# 4 SDRAM CHIP Density and Banks -# bits[3:0]: 3 = 2 Gigabits Total SDRAM capacity per chip -# bits[6:4]: 0 = 3 (8 banks) -# bit7 : reserved -03 - -# 5 SDRAM Addressing -# bits[2:0]: 1 = 10 Column Address Bits -# bits[5:3]: 2 = 14 Row Address Bits -# bits[7:6]: reserved -11 - -# 6 Module Nominal Voltage, VDD -# bit0 : 0 = 1.5 V operable -# bit1 : 0 = NOT 1.35 V operable -# bit2 : 0 = NOT 1.25 V operable -# bits[7:3]: reserved -00 - -# 7 Module Organization -# bits[2:0]: 2 = 16 bits -# bits[5:3]: 0 = 1 Rank -# bits[7:6]: reserved -02 - -# 8 Module Memory Bus Width -# bits[2:0]: 3 = Primary bus width is 64 bits -# bits[4:3]: 0 = 0 bits (no bus width extension) -# bits[7:5]: reserved -03 - -# 9 Fine Timebase (FTB) Dividend / Divisor -# bits[3:0]: 0x02 divisor -# bits[7:4]: 0x05 dividend -# 5/2 = 2.5ps -52 - -# 10 Medium Timebase (MTB) Dividend -# 11 Medium Timebase (MTB) Divisor -# 1 / 8 = .125 ns - used for clock freq of 400 through 1066 MHz -01 08 - -# 12 SDRAM Minimum Cycle Time (tCKmin) -# 0x0a = tCKmin of 1.25 ns = DDR3-1600 (800 MHz clock) -0A - -# 13 Reserved -00 - -# 14 CAS Latencies Supported, Least Significant Byte -# 15 CAS Latencies Supported, Most Significant Byte -# Cas Latencies of 11 - 5 are supported -FE 00 - -# 16 Minimum CAS Latency Time (tAAmin) -# 0x6E = 13.75ns - DDR3-1600K -6E - -# 17 Minimum Write Recovery Time (tWRmin) -# 0x78 = tWR of 15ns - All DDR3 speed grades -78 - -# 18 Minimum RAS# to CAS# Delay Time (tRCDmin) -# 0x6E = 13.75ns - DDR3-1600K -6E - -# 19 Minimum Row Active to Row Active Delay Time (tRRDmin) -# 0x3C = 7.5ns -3C - -# 20 Minimum Row Precharge Delay Time (tRPmin) -# 0x6E = 13.75ns - DDR3-1600K -6E - -# 21 Upper Nibbles for tRAS and tRC -# bits[3:0]: tRAS most significant nibble = 1 (see byte 22) -# bits[7:4]: tRC most significant nibble = 1 (see byte 23) -11 - -# 22 Minimum Active to Precharge Delay Time (tRASmin), LSB -# 0x118 = 35ns - DDR3-1600 (see byte 21) -18 - -# 23 Minimum Active to Active/Refresh Delay Time (tRCmin), LSB -# 0x186 = 48.75ns - DDR3-1600K -86 - -# 24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB -# 25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB -# 0x500 = 160ns - for 2 Gigabit chips -00 05 - -# 26 Minimum Internal Write to Read Command Delay Time (tWTRmin) -# 0x3c = 7.5 ns - All DDR3 SDRAM speed bins -3C - -# 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin) -# 0x3c = 7.5ns - All DDR3 SDRAM speed bins -3C - -# 28 Upper Nibble for tFAWmin -# 29 Minimum Four Activate Window Delay Time (tFAWmin) -# 0x0140 = 40ns - DDR3-1600, 2 KB page size -01 40 - -# 30 SDRAM Optional Feature -# bit0 : 1= RZQ/6 supported -# bit1 : 1 = RZQ/7 supported -# bits[6:2]: reserved -# bit7 : 1 = DLL Off mode supported -83 - -# 31 SDRAM Thermal and Refresh Options -# bit0 : 1 = Temp up to 95c supported -# bit1 : 0 = 85-95c uses 2x refresh rate -# bit2 : 1 = Auto Self Refresh supported -# bit3 : 0 = no on die thermal sensor -# bits[6:4]: reserved -# bit7 : 0 = partial self refresh supported -05 - -# 32 Module Thermal Sensor -# 0 = Thermal sensor not incorporated onto this assembly -00 - -# 33 SDRAM Device Type -# bits[1:0]: 0 = Signal Loading not specified -# bits[3:2]: reserved -# bits[6:4]: 0 = Die count not specified -# bit7 : 0 = Standard Monolithic DRAM Device -00 - -# 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin) -# 35 Fine Offset for Minimum CAS Latency Time (tAAmin) -# 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin) -# 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin) -# 38 Fine Offset for Minimum Active to Active/Refresh Delay (tRCmin) -00 00 00 00 00 - -# 39 - 59 (reserved) -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 - -# 60 Raw Card Extension, Module Nominal Height -# bits[4:0]: 0 = <= 15mm tall -# bits[7:5]: 0 = raw card revision 0-3 -00 - -# 61 Module Maximum Thickness -# bits[3:0]: 0 = thickness front <= 1mm -# bits[7:4]: 0 = thinkness back <= 1mm -00 - -# 62 Reference Raw Card Used -# bits[4:0]: 0 = Reference Raw card A used -# bits[6:5]: 0 = revision 0 -# bit7 : 0 = Reference raw cards A through AL -00 - -# 63 Address Mapping from Edge Connector to DRAM -# bit0 : 0 = standard mapping (not mirrored) -# bits[7:1]: reserved -00 - -# 64 - 116 (reserved) -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 - -# 117 - 118 Module ID: Module Manufacturers JEDEC ID Code -# 0x0001 = AMD -00 01 - -# 119 Module ID: Module Manufacturing Location - oem specified -# 120 Module ID: Module Manufacture Year in BCD -# 0x13 = 2013 -00 13 - -# 121 Module ID: Module Manufacture week -# 0x12 = 12th week -12 - -# 122 - 125: Module Serial Number -53 41 47 45 - -# 126 - 127: Cyclical Redundancy Code -00 00 diff --git a/src/mainboard/gizmosphere/gizmo2/OemCustomize.c b/src/mainboard/gizmosphere/gizmo2/OemCustomize.c deleted file mode 100644 index 6b21f0c..0000000 --- a/src/mainboard/gizmosphere/gizmo2/OemCustomize.c +++ /dev/null @@ -1,153 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <AGESA.h> -#include <PlatformMemoryConfiguration.h> - -#include <northbridge/amd/agesa/state_machine.h> - -static const PCIe_PORT_DESCRIPTOR PortList[] = { - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 3, 3), - PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 5, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 0x01, 0) - }, - /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 2), - PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 4, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 0x02, 0) - }, - /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 1, 1), - PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 3, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 0x03, 0) - }, - /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 0), - PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 2, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 0x04, 0) - }, - /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */ - { - DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7), - PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 1, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 0x05, 0) - } -}; - -static const PCIe_DDI_DESCRIPTOR DdiList[] = { - /* DP0 to HDMI0/DP */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux1, Hdp1) - }, - /* DP1 to high-speed edge connector */ - { - DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2) - }, -}; - -static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { - .Flags = DESCRIPTOR_TERMINATE_LIST, - .SocketId = 0, - .PciePortList = PortList, - .DdiLinkList = DdiList -}; - -void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) -{ - FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface; - FchReset->Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); - FchReset->Xhci1Enable = FALSE; -} - -void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) -{ - InitEarly->GnbConfig.PcieComplexList = &PcieComplex; -} - -/*---------------------------------------------------------------------------------------- - * CUSTOMER OVERIDES MEMORY TABLE - *---------------------------------------------------------------------------------------- - */ - -/* - * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA - * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable - * is populated, AGESA will base its settings on the data from the table. Otherwise, it will - * use its default conservative settings. - */ -static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { - - #define SEED_WL 0x0E - WRITE_LEVELING_SEED( - ANY_SOCKET, CHANNEL_A, ALL_DIMMS, - SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL, - SEED_WL), - - #define SEED_A 0x12 - HW_RXEN_SEED( - ANY_SOCKET, CHANNEL_A, ALL_DIMMS, - SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, - SEED_A), - - NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1), - NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1), - MOTHER_BOARD_LAYERS(LAYERS_6), - - MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), - CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */ - ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), - CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00), - - PSO_END -}; - -void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) -{ - InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; -} - -void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) -{ - /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ - InitMid->GnbMidConfiguration.iGpuVgaMode = 0; -} diff --git a/src/mainboard/gizmosphere/gizmo2/OptionsIds.h b/src/mainboard/gizmosphere/gizmo2/OptionsIds.h deleted file mode 100644 index eaf2442..0000000 --- a/src/mainboard/gizmosphere/gizmo2/OptionsIds.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDS_DEBUG_PORT - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_CONTROL_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE -#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE -//#define IDSOPT_PERF_ANALYSIS TRUE -#define IDSOPT_ASSERT_ENABLED TRUE -//#undef IDSOPT_DEBUG_ENABLED -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - -#endif diff --git a/src/mainboard/gizmosphere/gizmo2/acpi/gpe.asl b/src/mainboard/gizmosphere/gizmo2/acpi/gpe.asl deleted file mode 100644 index 87b0d21..0000000 --- a/src/mainboard/gizmosphere/gizmo2/acpi/gpe.asl +++ /dev/null @@ -1,74 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Scope(\_GPE) { /* Start Scope GPE */ - - /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* Legacy PM event */ - Method(_L08) { - /* DBGO("\\_GPE\\_L08\n") */ - } - - /* Temp warning (TWarn) event */ - Method(_L09) { - /* DBGO("\\_GPE\\_L09\n") */ - /* Notify (\_TZ.TZ00, 0x80) */ - } - - /* USB controller PME# */ - Method(_L0B) { - /* DBGO("\\_GPE\\_L0B\n") */ - Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* ExtEvent0 SCI event */ - Method(_L10) { - /* DBGO("\\_GPE\\_L10\n") */ - } - - /* ExtEvent1 SCI event */ - Method(_L11) { - /* DBGO("\\_GPE\\_L11\n") */ - } - - /* GPIO0 or GEvent8 event */ - Method(_L18) { - /* DBGO("\\_GPE\\_L18\n") */ - Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* Azalia SCI event */ - Method(_L1B) { - /* DBGO("\\_GPE\\_L1B\n") */ - Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } -} /* End Scope GPE */ diff --git a/src/mainboard/gizmosphere/gizmo2/acpi/ide.asl b/src/mainboard/gizmosphere/gizmo2/acpi/ide.asl deleted file mode 100644 index e7f4625..0000000 --- a/src/mainboard/gizmosphere/gizmo2/acpi/ide.asl +++ /dev/null @@ -1,246 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012-2013 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* No IDE functionality */ - -#if 0 -/* -Scope (_SB) { - Device(PCI0) { - Device(IDEC) { - Name(_ADR, 0x00140001) - #include "ide.asl" - } - } -} -*/ - -/* Some timing tables */ -Name(UDTT, Package(){ /* Udma timing table */ - 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */ -}) - -Name(MDTT, Package(){ /* MWDma timing table */ - 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */ -}) - -Name(POTT, Package(){ /* Pio timing table */ - 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */ -}) - -/* Some timing register value tables */ -Name(MDRT, Package(){ /* MWDma timing register table */ - 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */ -}) - -Name(PORT, Package(){ - 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */ -}) - -OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */ - Field(ICRG, AnyAcc, NoLock, Preserve) -{ - PPTS, 8, /* Primary PIO Slave Timing */ - PPTM, 8, /* Primary PIO Master Timing */ - OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */ - PMTM, 8, /* Primary MWDMA Master Timing */ - OFFSET(0x08), PPCR, 8, /* Primary PIO Control */ - OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */ - PPSM, 4, /* Primary PIO slave Mode */ - OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */ - OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */ - PDSM, 4, /* Primary UltraDMA Mode */ -} - -Method(GTTM, 1) /* get total time*/ -{ - Store(And(Arg0, 0x0F), Local0) /* Recovery Width */ - Increment(Local0) - Store(ShiftRight(Arg0, 4), Local1) /* Command Width */ - Increment(Local1) - Return(Multiply(30, Add(Local0, Local1))) -} - -Device(PRID) -{ - Name (_ADR, Zero) - Method(_GTM, 0) - { - NAME(OTBF, Buffer(20) { /* out buffer */ - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 - }) - - CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */ - CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */ - CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */ - CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */ - CreateDwordField(OTBF, 16, BFFG) /* buffer flags */ - - /* Just return if the channel is disabled */ - If(And(PPCR, 0x01)) { /* primary PIO control */ - Return(OTBF) - } - - /* Always tell them independent timing available and IOChannelReady used on both drives */ - Or(BFFG, 0x1A, BFFG) - - /* save total time of primary PIO master timing to PIO spd0 */ - Store(GTTM(PPTM), PSD0) - /* save total time of primary PIO slave Timing to PIO spd1 */ - Store(GTTM(PPTS), PSD1) - - If(And(PDCR, 0x01)) { /* It's under UDMA mode */ - Or(BFFG, 0x01, BFFG) - Store(DerefOf(Index(UDTT, PDMM)), DSD0) - } - Else { - Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */ - } - - If(And(PDCR, 0x02)) { /* It's under UDMA mode */ - Or(BFFG, 0x04, BFFG) - Store(DerefOf(Index(UDTT, PDSM)), DSD1) - } - Else { - Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */ - } - - Return(OTBF) /* out buffer */ - } /* End Method(_GTM) */ - - Method(_STM, 3, NotSerialized) - { - NAME(INBF, Buffer(20) { /* in buffer */ - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 - }) - - CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */ - CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */ - CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */ - CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */ - CreateDwordField(INBF, 16, BFFG) /*buffer flag */ - - Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0) - Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */ - Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1) - Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */ - - Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */ - Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */ - - If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0) - Divide(Local0, 7, PDMM,) - Or(PDCR, 0x01, PDCR) - } - Else { - If(LNotEqual(DSD0, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTM) - } - } - - If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0) - Divide(Local0, 7, PDSM,) - Or(PDCR, 0x02, PDCR) - } - Else { - If(LNotEqual(DSD1, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTS) - } - } - /* Return(INBF) */ - } /*End Method(_STM) */ - Device(MST) - { - Name(_ADR, 0) - Method(_GTF) { - Name(CMBF, Buffer(21) { - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 - }) - CreateByteField(CMBF, 1, POMD) - CreateByteField(CMBF, 8, DMMD) - CreateByteField(CMBF, 5, CMDA) - CreateByteField(CMBF, 12, CMDB) - CreateByteField(CMBF, 19, CMDC) - - Store(0xA0, CMDA) - Store(0xA0, CMDB) - Store(0xA0, CMDC) - - Or(PPMM, 0x08, POMD) - - If(And(PDCR, 0x01)) { - Or(PDMM, 0x40, DMMD) - } - Else { - Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) - } - } - Return(CMBF) - } - } /* End Device(MST) */ - - Device(SLAV) - { - Name(_ADR, 1) - Method(_GTF) { - Name(CMBF, Buffer(21) { - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 - }) - CreateByteField(CMBF, 1, POMD) - CreateByteField(CMBF, 8, DMMD) - CreateByteField(CMBF, 5, CMDA) - CreateByteField(CMBF, 12, CMDB) - CreateByteField(CMBF, 19, CMDC) - - Store(0xB0, CMDA) - Store(0xB0, CMDB) - Store(0xB0, CMDC) - - Or(PPSM, 0x08, POMD) - - If(And(PDCR, 0x02)) { - Or(PDSM, 0x40, DMMD) - } - Else { - Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) - } - } - Return(CMBF) - } - } /* End Device(SLAV) */ -} -#endif diff --git a/src/mainboard/gizmosphere/gizmo2/acpi/mainboard.asl b/src/mainboard/gizmosphere/gizmo2/acpi/mainboard.asl deleted file mode 100644 index 68609d8..0000000 --- a/src/mainboard/gizmosphere/gizmo2/acpi/mainboard.asl +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Memory related values */ -Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ -Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ -Name(PBLN, 0x0) /* Length of BIOS area */ - -Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ -Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */ -Name(HPBA, 0xFED00000) /* Base address of HPET table */ - -/* Some global data */ -Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ -Name(OSV, Ones) /* Assume nothing */ -Name(PMOD, One) /* Assume APIC */ - -/* AcpiGpe0Blk */ -OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04) - Field(GP0B, ByteAcc, NoLock, Preserve) { - , 11, - USBS, 1, -} diff --git a/src/mainboard/gizmosphere/gizmo2/acpi/routing.asl b/src/mainboard/gizmosphere/gizmo2/acpi/routing.asl deleted file mode 100644 index 1fb4c1d..0000000 --- a/src/mainboard/gizmosphere/gizmo2/acpi/routing.asl +++ /dev/null @@ -1,194 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* -#include <arch/acpi.h> -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 - ) - { - #include "routing.asl" - } -*/ - -/* Routing is in System Bus scope */ -Name(PR0, Package(){ - /* NB devices */ - /* Bus 0, Dev 0 - F16 Host Controller */ - - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ - /* Bus 0, Dev 1, Func 1 - HDMI Audio Controller */ - Package(){0x0001FFFF, 0, INTB, 0 }, - Package(){0x0001FFFF, 1, INTC, 0 }, - - - /* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */ - Package(){0x0002FFFF, 0, INTC, 0 }, - Package(){0x0002FFFF, 1, INTD, 0 }, - Package(){0x0002FFFF, 2, INTA, 0 }, - Package(){0x0002FFFF, 3, INTB, 0 }, - - /* FCH devices */ - /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */ - Package(){0x0014FFFF, 0, INTA, 0 }, - Package(){0x0014FFFF, 1, INTB, 0 }, - Package(){0x0014FFFF, 2, INTC, 0 }, - Package(){0x0014FFFF, 3, INTD, 0 }, - - /* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */ - /* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */ - Package(){0x0012FFFF, 0, INTC, 0 }, - Package(){0x0012FFFF, 1, INTB, 0 }, - - Package(){0x0013FFFF, 0, INTC, 0 }, - Package(){0x0013FFFF, 1, INTB, 0 }, - - Package(){0x0016FFFF, 0, INTC, 0 }, - Package(){0x0016FFFF, 1, INTB, 0 }, - - /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */ - Package(){0x0010FFFF, 0, INTC, 0 }, - Package(){0x0010FFFF, 1, INTB, 0 }, - - /* Bus 0, Dev 17 - SATA controller */ - Package(){0x0011FFFF, 0, INTD, 0 }, - -}) - -Name(APR0, Package(){ - /* NB devices in APIC mode */ - /* Bus 0, Dev 0 - F15 Host Controller */ - - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ - Package(){0x0001FFFF, 0, 0, 44 }, - Package(){0x0001FFFF, 1, 0, 45 }, - - /* Bus 0, Dev 2 - PCIe Bridges */ - Package(){0x0002FFFF, 0, 0, 24 }, - Package(){0x0002FFFF, 1, 0, 25 }, - Package(){0x0002FFFF, 2, 0, 26 }, - Package(){0x0002FFFF, 3, 0, 27 }, - - - /* SB devices in APIC mode */ - /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */ - Package(){0x0014FFFF, 0, 0, 16 }, - Package(){0x0014FFFF, 1, 0, 17 }, - Package(){0x0014FFFF, 2, 0, 18 }, - Package(){0x0014FFFF, 3, 0, 19 }, - - /* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */ - /* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */ - Package(){0x0012FFFF, 0, 0, 18 }, - Package(){0x0012FFFF, 1, 0, 17 }, - - Package(){0x0013FFFF, 0, 0, 18 }, - Package(){0x0013FFFF, 1, 0, 17 }, - - Package(){0x0016FFFF, 0, 0, 18 }, - Package(){0x0016FFFF, 1, 0, 17 }, - - /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */ - Package(){0x0010FFFF, 0, 0, 0x12}, - Package(){0x0010FFFF, 1, 0, 0x11}, - - /* Bus 0, Dev 17 - SATA controller */ - Package(){0x0011FFFF, 0, 0, 19 }, - -}) - -Name(PS2, Package(){ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, -}) -Name(APS2, Package(){ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, -}) - -/* GFX */ -Name(PS4, Package(){ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, -}) -Name(APS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, 0, 24 }, - Package(){0x0000FFFF, 1, 0, 25 }, - Package(){0x0000FFFF, 2, 0, 26 }, - Package(){0x0000FFFF, 3, 0, 27 }, -}) - -/* GPP 0 */ -Name(PS5, Package(){ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, -}) -Name(APS5, Package(){ - Package(){0x0000FFFF, 0, 0, 28 }, - Package(){0x0000FFFF, 1, 0, 29 }, - Package(){0x0000FFFF, 2, 0, 30 }, - Package(){0x0000FFFF, 3, 0, 31 }, -}) - -/* GPP 1 */ -Name(PS6, Package(){ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, -}) -Name(APS6, Package(){ - Package(){0x0000FFFF, 0, 0, 32 }, - Package(){0x0000FFFF, 1, 0, 33 }, - Package(){0x0000FFFF, 2, 0, 34 }, - Package(){0x0000FFFF, 3, 0, 35 }, -}) - -/* GPP 2 */ -Name(PS7, Package(){ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, -}) -Name(APS7, Package(){ - Package(){0x0000FFFF, 0, 0, 36 }, - Package(){0x0000FFFF, 1, 0, 37 }, - Package(){0x0000FFFF, 2, 0, 38 }, - Package(){0x0000FFFF, 3, 0, 39 }, -}) - -/* GPP 3 */ -Name(PS8, Package(){ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, -}) -Name(APS8, Package(){ - Package(){0x0000FFFF, 0, 0, 40 }, - Package(){0x0000FFFF, 1, 0, 41 }, - Package(){0x0000FFFF, 2, 0, 42 }, - Package(){0x0000FFFF, 3, 0, 43 }, -}) diff --git a/src/mainboard/gizmosphere/gizmo2/acpi/sata.asl b/src/mainboard/gizmosphere/gizmo2/acpi/sata.asl deleted file mode 100644 index 6755258..0000000 --- a/src/mainboard/gizmosphere/gizmo2/acpi/sata.asl +++ /dev/null @@ -1,146 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012-2013 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* No SATA functionality */ - -#if 0 -/* -Scope (_SB) { - Device(PCI0) { - Device(SATA) { - Name(_ADR, 0x00110000) - #include "sata.asl" - } - } -} -*/ - -Name(STTM, Buffer(20) { - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x1f, 0x00, 0x00, 0x00 -}) - -/* Start by clearing the PhyRdyChg bits */ -Method(_INI) { - \_GPE._L1F() -} - -Device(PMRY) -{ - Name(_ADR, 0) - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(PMST) { - Name(_ADR, 0) - Method(_STA,0) { - if (LGreater(P0IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - }/* end of PMST */ - - Device(PSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (LGreater(P1IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of PSLA */ -} /* end of PMRY */ - -Device(SEDY) -{ - Name(_ADR, 1) /* IDE Scondary Channel */ - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(SMST) - { - Name(_ADR, 0) - Method(_STA,0) { - if (LGreater(P2IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SMST */ - - Device(SSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (LGreater(P3IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SSLA */ -} /* end of SEDY */ - -/* SATA Hot Plug Support */ -Scope(\_GPE) { - Method(_L1F,0x0,NotSerialized) { - if (\_SB.P0PR) { - if (LGreater(\_SB.P0IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P0PR) - } - - if (\_SB.P1PR) { - if (LGreater(\_SB.P1IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P1PR) - } - - if (\_SB.P2PR) { - if (LGreater(\_SB.P2IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P2PR) - } - - if (\_SB.P3PR) { - if (LGreater(\_SB.P3IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P3PR) - } - } -} -#endif diff --git a/src/mainboard/gizmosphere/gizmo2/acpi/si.asl b/src/mainboard/gizmosphere/gizmo2/acpi/si.asl deleted file mode 100644 index 2923471..0000000 --- a/src/mainboard/gizmosphere/gizmo2/acpi/si.asl +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Scope(\_SI) { - Method(_SST, 1) { - /* DBGO("\\_SI\\_SST\n") */ - /* DBGO(" New Indicator state: ") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - } -} /* End Scope SI */ diff --git a/src/mainboard/gizmosphere/gizmo2/acpi/sleep.asl b/src/mainboard/gizmosphere/gizmo2/acpi/sleep.asl deleted file mode 100644 index 1225a62..0000000 --- a/src/mainboard/gizmosphere/gizmo2/acpi/sleep.asl +++ /dev/null @@ -1,93 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Wake status package */ -Name(WKST,Package(){Zero, Zero}) - -/* -* \_PTS - Prepare to Sleep method -* -* Entry: -* Arg0=The value of the sleeping state S1=1, S2=2, etc -* -* Exit: -* -none- -* -* The _PTS control method is executed at the beginning of the sleep process -* for S1-S5. The sleeping value is passed to the _PTS control method. This -* control method may be executed a relatively long time before entering the -* sleep state and the OS may abort the operation without notification to -* the ACPI driver. This method cannot modify the configuration or power -* state of any device in the system. -*/ - -External(\_SB.APTS, MethodObj) -External(\_SB.AWAK, MethodObj) - -Method(_PTS, 1) { - /* DBGO("\\_PTS\n") */ - /* DBGO("From S0 to S") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - - /* Clear wake status structure. */ - Store(0, Index(WKST,0)) - Store(0, Index(WKST,1)) - Store(7, UPWS) - \_SB.APTS(Arg0) -} /* End Method(\_PTS) */ - -/* -* \_BFS OEM Back From Sleep method -* -* Entry: -* Arg0=The value of the sleeping state S1=1, S2=2 -* -* Exit: -* -none- -*/ -Method(\_BFS, 1) { - /* DBGO("\\_BFS\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ -} - -/* -* \_WAK System Wake method -* -* Entry: -* Arg0=The value of the sleeping state S1=1, S2=2 -* -* Exit: -* Return package of 2 DWords -* Dword 1 - Status -* 0x00000000 wake succeeded -* 0x00000001 Wake was signaled but failed due to lack of power -* 0x00000002 Wake was signaled but failed due to thermal condition -* Dword 2 - Power Supply state -* if non-zero the effective S-state the power supply entered -*/ -Method(\_WAK, 1) { - /* DBGO("\\_WAK\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - Store(1,USBS) - - \_SB.AWAK(Arg0) - - Return(WKST) -} /* End Method(\_WAK) */ diff --git a/src/mainboard/gizmosphere/gizmo2/acpi/superio.asl b/src/mainboard/gizmosphere/gizmo2/acpi/superio.asl deleted file mode 100644 index e69de29..0000000 --- a/src/mainboard/gizmosphere/gizmo2/acpi/superio.asl +++ /dev/null diff --git a/src/mainboard/gizmosphere/gizmo2/acpi/thermal.asl b/src/mainboard/gizmosphere/gizmo2/acpi/thermal.asl deleted file mode 100644 index e69de29..0000000 --- a/src/mainboard/gizmosphere/gizmo2/acpi/thermal.asl +++ /dev/null diff --git a/src/mainboard/gizmosphere/gizmo2/acpi/usb_oc.asl b/src/mainboard/gizmosphere/gizmo2/acpi/usb_oc.asl deleted file mode 100644 index c020216..0000000 --- a/src/mainboard/gizmosphere/gizmo2/acpi/usb_oc.asl +++ /dev/null @@ -1,129 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* simple name description */ -/* -#include <arch/acpi.h> -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 - ) - { - #include "usb.asl" - } -*/ - -/* USB overcurrent mapping pins. */ -Name(UOM0, 0) -Name(UOM1, 2) -Name(UOM2, 0) -Name(UOM3, 7) -Name(UOM4, 2) -Name(UOM5, 2) -Name(UOM6, 6) -Name(UOM7, 2) -Name(UOM8, 6) -Name(UOM9, 6) - -/* USB Overcurrent GPEs */ - -#if 0 /* TODO: Update */ -Method(UCOC, 0) { - Sleep(20) - Store(0x13,CMTI) - Store(0,GPSL) -} - -/* USB Port 0 overcurrent uses Gpm 0 */ -If(LLessEqual(UOM0,9)) { - Scope (\_GPE) { - Method (_L13) { - } - } -} - -/* USB Port 1 overcurrent uses Gpm 1 */ -If (LLessEqual(UOM1,9)) { - Scope (\_GPE) { - Method (_L14) { - } - } -} - -/* USB Port 2 overcurrent uses Gpm 2 */ -If (LLessEqual(UOM2,9)) { - Scope (\_GPE) { - Method (_L15) { - } - } -} - -/* USB Port 3 overcurrent uses Gpm 3 */ -If (LLessEqual(UOM3,9)) { - Scope (\_GPE) { - Method (_L16) { - } - } -} - -/* USB Port 4 overcurrent uses Gpm 4 */ -If (LLessEqual(UOM4,9)) { - Scope (\_GPE) { - Method (_L19) { - } - } -} - -/* USB Port 5 overcurrent uses Gpm 5 */ -If (LLessEqual(UOM5,9)) { - Scope (\_GPE) { - Method (_L1A) { - } - } -} - -/* USB Port 6 overcurrent uses Gpm 6 */ -If (LLessEqual(UOM6,9)) { - Scope (\_GPE) { - /* Method (_L1C) { */ - Method (_L06) { - } - } -} - -/* USB Port 7 overcurrent uses Gpm 7 */ -If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { - /* Method (_L1D) { */ - Method (_L07) { - } - } -} - -/* USB Port 8 overcurrent uses Gpm 8 */ -If (LLessEqual(UOM8,9)) { - Scope (\_GPE) { - Method (_L17) { - } - } -} - -/* USB Port 9 overcurrent uses Gpm 9 */ -If (LLessEqual(UOM9,9)) { - Scope (\_GPE) { - Method (_L0E) { - } - } -} -#endif diff --git a/src/mainboard/gizmosphere/gizmo2/acpi_tables.c b/src/mainboard/gizmosphere/gizmo2/acpi_tables.c deleted file mode 100644 index 20509e9..0000000 --- a/src/mainboard/gizmosphere/gizmo2/acpi_tables.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/acpi.h> -#include <arch/ioapic.h> - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); - - /* Write SB800 IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, - IO_APIC_ADDR, 0); - - /* TODO: Remove the hardcode */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS+1, - 0xFEC20000, 24); - - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xF); - /* 0: mean bus 0--->ISA */ - /* 0: PIC 0 */ - /* 2: APIC 2 */ - /* 5 mean: 0101 --> Edge-triggered, Active high */ - - /* create all subtables for processors */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1); - /* 1: LINT1 connect to NMI */ - - return current; -} diff --git a/src/mainboard/gizmosphere/gizmo2/board_info.txt b/src/mainboard/gizmosphere/gizmo2/board_info.txt deleted file mode 100644 index b351b8e..0000000 --- a/src/mainboard/gizmosphere/gizmo2/board_info.txt +++ /dev/null @@ -1 +0,0 @@ -Category: eval diff --git a/src/mainboard/gizmosphere/gizmo2/buildOpts.c b/src/mainboard/gizmosphere/gizmo2/buildOpts.c deleted file mode 100644 index 6c405cc..0000000 --- a/src/mainboard/gizmosphere/gizmo2/buildOpts.c +++ /dev/null @@ -1,341 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/** - * @file - * - * AMD User options selection for a Brazos platform solution system - * - * This file is placed in the user's platform directory and contains the - * build option selections desired for that platform. - * - * For Information about this file, see @ref platforminstall. - * - */ - -#include <stdlib.h> -#include <AGESA.h> - -#define INSTALL_FT3_SOCKET_SUPPORT TRUE -#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE - -#define INSTALL_G34_SOCKET_SUPPORT FALSE -#define INSTALL_C32_SOCKET_SUPPORT FALSE -#define INSTALL_S1G3_SOCKET_SUPPORT FALSE -#define INSTALL_S1G4_SOCKET_SUPPORT FALSE -#define INSTALL_ASB2_SOCKET_SUPPORT FALSE -#define INSTALL_FS1_SOCKET_SUPPORT FALSE -#define INSTALL_FM1_SOCKET_SUPPORT FALSE -#define INSTALL_FP2_SOCKET_SUPPORT FALSE -#define INSTALL_FT1_SOCKET_SUPPORT FALSE -#define INSTALL_AM3_SOCKET_SUPPORT FALSE -#define INSTALL_FM2_SOCKET_SUPPORT FALSE - - -#ifdef BLDOPT_REMOVE_FT3_SOCKET_SUPPORT - #if BLDOPT_REMOVE_FT3_SOCKET_SUPPORT == TRUE - #undef INSTALL_FT3_SOCKET_SUPPORT - #define INSTALL_FT3_SOCKET_SUPPORT FALSE - #endif -#endif - -//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE -//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE -#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE -#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE -#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE -//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE -#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE -//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE -#define BLDOPT_REMOVE_SRAT FALSE //TRUE -#define BLDOPT_REMOVE_SLIT FALSE //TRUE -#define BLDOPT_REMOVE_WHEA FALSE //TRUE -#define BLDOPT_REMOVE_CRAT TRUE -#define BLDOPT_REMOVE_CDIT TRUE -#define BLDOPT_REMOVE_DMI TRUE -//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE - -//This element selects whether P-States should be forced to be independent, -// as reported by the ACPI _PSD object. For single-link processors, -// setting TRUE for OS to support this feature. - -//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE - -#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER -/* Build configuration values here. - */ -#define BLDCFG_VRM_CURRENT_LIMIT 15000 -#define BLDCFG_VRM_NB_CURRENT_LIMIT 13000 -#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 21000 -#define BLDCFG_VRM_SVI_OCP_LEVEL BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT -#define BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT 17000 -#define BLDCFG_VRM_NB_SVI_OCP_LEVEL BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT -#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0 -#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 0 -#define BLDCFG_VRM_SLEW_RATE 10000 -#define BLDCFG_VRM_NB_SLEW_RATE BLDCFG_VRM_SLEW_RATE -#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE - -#define BLDCFG_PLAT_NUM_IO_APICS 3 -#define BLDCFG_GNB_IOAPIC_ADDRESS 0xFEC20000 -#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST -#define BLDCFG_MEM_INIT_PSTATE 0 -#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 // Specifies the IO addresses trapped by the - // core for C-state entry requests. A value - // of 0 in this field specifies that the core - // does not trap any IO addresses for C-state entry. - // Values greater than 0xFFF8 results in undefined behavior. -#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770 - -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE - -#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY -#define BLDCFG_MEMORY_MODE_UNGANGED TRUE -#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE -#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE -#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE -#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE -#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE -#define BLDCFG_MEMORY_POWER_DOWN TRUE -#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT -#define BLDCFG_ONLINE_SPARE FALSE -#define BLDCFG_BANK_SWIZZLE TRUE -#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#define BLDCFG_MEMORY_CLOCK_SELECT DDR1866_FREQUENCY -#define BLDCFG_DQS_TRAINING_CONTROL TRUE -#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE -#define BLDCFG_USE_BURST_MODE FALSE -#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE -#define BLDCFG_ENABLE_ECC_FEATURE TRUE -#define BLDCFG_ECC_REDIRECTION FALSE -#define BLDCFG_SCRUB_DRAM_RATE 0 -#define BLDCFG_SCRUB_L2_RATE 0 -#define BLDCFG_SCRUB_L3_RATE 0 -#define BLDCFG_SCRUB_IC_RATE 0 -#define BLDCFG_SCRUB_DC_RATE 0 -#define BLDCFG_ECC_SYNC_FLOOD TRUE -#define BLDCFG_ECC_SYMBOL_SIZE 4 -#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000ul -#define BLDCFG_1GB_ALIGN FALSE -#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED -#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO -#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeDisabled -#define BLDCFG_IOMMU_SUPPORT FALSE -#define OPTION_GFX_INIT_SVIEW FALSE -//#define BLDCFG_PLATFORM_POWER_POLICY_MODE BatteryLife - -//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL OEM_LCD_BACK_LIGHT_CONTROL -#define BLDCFG_CFG_ABM_SUPPORT TRUE - -#define BLDCFG_CFG_GNB_HD_AUDIO TRUE -//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID -//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID -//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID - -#ifdef PCIEX_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_BASE PCIEX_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_SIZE (PCIEX_LENGTH >> 20) -#endif - -#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P' -#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' -#define BLDCFG_PCIE_TRAINING_ALGORITHM PcieTrainingDistributed - -/* Process the options... - * This file include MUST occur AFTER the user option selection settings - */ -/* - * Customized OEM build configurations for FCH component - */ -// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00 -// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20 -// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00 -// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400 -// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404 -// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408 -// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410 -// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420 -// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000 -// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000 -// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000 -// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0 -// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00 -// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000 -// #define BLDCFG_AZALIA_SSID 0x780D1022 -// #define BLDCFG_SMBUS_SSID 0x780B1022 -// #define BLDCFG_IDE_SSID 0x780C1022 -// #define BLDCFG_SATA_AHCI_SSID 0x78011022 -// #define BLDCFG_SATA_IDE_SSID 0x78001022 -// #define BLDCFG_SATA_RAID5_SSID 0x78031022 -// #define BLDCFG_SATA_RAID_SSID 0x78021022 -// #define BLDCFG_EHCI_SSID 0x78081022 -// #define BLDCFG_OHCI_SSID 0x78071022 -// #define BLDCFG_LPC_SSID 0x780E1022 -// #define BLDCFG_SD_SSID 0x78061022 -// #define BLDCFG_XHCI_SSID 0x78121022 -// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE -// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE -// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4 -// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE - -CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = -{ - { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 }, - { CPU_LIST_TERMINAL } -}; - -#define BLDCFG_AP_MTRR_SETTINGS_LIST &KabiniApMtrrSettingsList - -/* Include the files that instantiate the configuration definitions. */ -#include "cpuRegisters.h" -#include "cpuFamRegisters.h" -#include "cpuFamilyTranslation.h" -#include "AdvancedApi.h" -#include "heapManager.h" -#include "CreateStruct.h" -#include "cpuFeatures.h" -#include "Table.h" -#include "cpuEarlyInit.h" -#include "cpuLateInit.h" -#include "GnbInterface.h" - - // This is the delivery package title, "BrazosPI" - // This string MUST be exactly 8 characters long -#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} - - // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long -#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} - -/* MEMORY_BUS_SPEED */ -//#define DDR400_FREQUENCY 200 ///< DDR 400 -//#define DDR533_FREQUENCY 266 ///< DDR 533 -//#define DDR667_FREQUENCY 333 ///< DDR 667 -//#define DDR800_FREQUENCY 400 ///< DDR 800 -//#define DDR1066_FREQUENCY 533 ///< DDR 1066 -//#define DDR1333_FREQUENCY 667 ///< DDR 1333 -//#define DDR1600_FREQUENCY 800 ///< DDR 1600 -//#define DDR1866_FREQUENCY 933 ///< DDR 1866 -//#define DDR2100_FREQUENCY 1050 ///< DDR 2100 -//#define DDR2133_FREQUENCY 1066 ///< DDR 2133 -//#define DDR2400_FREQUENCY 1200 ///< DDR 2400 -//#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency -// -///* QUANDRANK_TYPE*/ -//#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -//#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM -// -///* USER_MEMORY_TIMING_MODE */ -//#define TIMING_MODE_AUTO 0 ///< Use best rate possible -//#define TIMING_MODE_LIMITED 1 ///< Set user top limit -//#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed -// -///* POWER_DOWN_MODE */ -//#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -//#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode - -/* - * Agesa optional capabilities selection. - * Uncomment and mark FALSE those features you wish to include in the build. - * Comment out or mark TRUE those features you want to REMOVE from the build. - */ - -#define DFLT_SMBUS0_BASE_ADDRESS 0xB00 -#define DFLT_SMBUS1_BASE_ADDRESS 0xB20 -#define DFLT_SIO_PME_BASE_ADDRESS 0xE00 -#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800 -#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804 -#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808 -#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810 -#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820 -#define DFLT_SPI_BASE_ADDRESS 0xFEC10000 -#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 -#define DFLT_HPET_BASE_ADDRESS 0xFED00000 -#define DFLT_SMI_CMD_PORT 0xB0 -#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 -#define DFLT_GEC_BASE_ADDRESS 0xFED61000 -#define DFLT_AZALIA_SSID 0x780D1022 -#define DFLT_SMBUS_SSID 0x780B1022 -#define DFLT_IDE_SSID 0x780C1022 -#define DFLT_SATA_AHCI_SSID 0x78011022 -#define DFLT_SATA_IDE_SSID 0x78001022 -#define DFLT_SATA_RAID5_SSID 0x78031022 -#define DFLT_SATA_RAID_SSID 0x78021022 -#define DFLT_EHCI_SSID 0x78081022 -#define DFLT_OHCI_SSID 0x78071022 -#define DFLT_LPC_SSID 0x780E1022 -#define DFLT_SD_SSID 0x78061022 -#define DFLT_XHCI_SSID 0x78121022 -#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE -#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE -#define DFLT_FCH_GPP_LINK_CONFIG PortA4 -#define DFLT_FCH_GPP_PORT0_PRESENT FALSE -#define DFLT_FCH_GPP_PORT1_PRESENT FALSE -#define DFLT_FCH_GPP_PORT2_PRESENT FALSE -#define DFLT_FCH_GPP_PORT3_PRESENT FALSE -#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE -//#define BLDCFG_IR_PIN_CONTROL 0x33 - -GPIO_CONTROL gizmo2_gpio[] = { - {183, Function1, GpioIn | GpioOutEnB | PullUpB}, - {-1} -}; -//#define BLDCFG_FCH_GPIO_CONTROL_LIST (&gizmo2_gpio[0]) - -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. -#define DFLT_SCRUB_DRAM_RATE (0) -#define DFLT_SCRUB_L2_RATE (0) -#define DFLT_SCRUB_L3_RATE (0) -#define DFLT_SCRUB_IC_RATE (0) -#define DFLT_SCRUB_DC_RATE (0) -#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define DFLT_VRM_SLEW_RATE (5000) - -#include <PlatformInstall.h> diff --git a/src/mainboard/gizmosphere/gizmo2/cmos.layout b/src/mainboard/gizmosphere/gizmo2/cmos.layout deleted file mode 100644 index e1dbd9a..0000000 --- a/src/mainboard/gizmosphere/gizmo2/cmos.layout +++ /dev/null @@ -1,66 +0,0 @@ -#***************************************************************************** -# -# This file is part of the coreboot project. -# -# Copyright (C) 2012 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -#***************************************************************************** - -entries - -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#392 3 r 0 unused -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum -# Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% - -checksums - -checksum 392 983 984 diff --git a/src/mainboard/gizmosphere/gizmo2/devicetree.cb b/src/mainboard/gizmosphere/gizmo2/devicetree.cb deleted file mode 100644 index e35249e..0000000 --- a/src/mainboard/gizmosphere/gizmo2/devicetree.cb +++ /dev/null @@ -1,59 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2013 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -chip northbridge/amd/agesa/family16kb/root_complex - device cpu_cluster 0 on - chip cpu/amd/agesa/family16kb - device lapic 0 on end - end - end - - device domain 0 on - subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/agesa/family16kb - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x9835 - device pci 1.1 on end # Internal Multimedia - device pci 2.0 on end # PCIe Host Bridge - device pci 2.1 on end # PCIe GFX Bridge - device pci 2.2 on end # PCIe GPP mini PCIe - device pci 2.3 on end # PCIe LAN - device pci 2.4 on end # PCIe x2 to high speed edge connector - device pci 2.5 on end # PCIe x2 to high speed edge connector - end #chip northbridge/amd/agesa/family16kb - - chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus - device pci 10.0 on end # XHCI HC0 - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on end # SM - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on end # LPC 0x439d - device pci 14.7 on end # SD - end #chip southbridge/amd/agesa/hudson - - chip northbridge/amd/agesa/family16kb - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - end - - end #domain -end #northbridge/amd/agesa/family16kb/root_complex diff --git a/src/mainboard/gizmosphere/gizmo2/dsdt.asl b/src/mainboard/gizmosphere/gizmo2/dsdt.asl deleted file mode 100644 index c4fc934..0000000 --- a/src/mainboard/gizmosphere/gizmo2/dsdt.asl +++ /dev/null @@ -1,88 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* DefinitionBlock Statement */ -#include <arch/acpi.h> -DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - OEM_ID, - ACPI_TABLE_CREATOR, - 0x00010001 /* OEM Revision */ - ) -{ /* Start of ASL file */ - /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ - - /* Globals for the platform */ - #include "acpi/mainboard.asl" - - /* Describe the USB Overcurrent pins */ - #include "acpi/usb_oc.asl" - - /* PCI IRQ mapping for the Southbridge */ - #include <southbridge/amd/agesa/hudson/acpi/pcie.asl> - - /* Describe the processor tree (\_PR) */ - #include <cpu/amd/agesa/family16kb/acpi/cpu.asl> - - /* Contains the supported sleep states for this chipset */ - #include <southbridge/amd/common/acpi/sleepstates.asl> - - /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */ - #include "acpi/sleep.asl" - - /* System Bus */ - Scope(\_SB) { /* Start \_SB scope */ - /* global utility methods expected within the \_SB scope */ - #include <arch/x86/acpi/globutil.asl> - - /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ - #include "acpi/routing.asl" - - Device(PWRB) { - Name(_HID, EISAID("PNP0C0C")) - Name(_UID, 0xAA) - Name(_PRW, Package () {3, 0x04}) - Name(_STA, 0x0B) - } - - Device(PCI0) { - /* Describe the AMD Northbridge */ - #include <northbridge/amd/agesa/family16kb/acpi/northbridge.asl> - - /* Describe the AMD Fusion Controller Hub Southbridge */ - #include <southbridge/amd/agesa/hudson/acpi/fch.asl> - } - - /* Describe PCI INT[A-H] for the Southbridge */ - #include <southbridge/amd/agesa/hudson/acpi/pci_int.asl> - - } /* End \_SB scope */ - - /* Describe SMBUS for the Southbridge */ - #include <southbridge/amd/agesa/hudson/acpi/smbus.asl> - - /* Define the General Purpose Events for the platform */ - #include "acpi/gpe.asl" - - /* Define the Thermal zones and methods for the platform */ - #include "acpi/thermal.asl" - - /* Define the System Indicators for the platform */ - #include "acpi/si.asl" -} -/* End of ASL file */ diff --git a/src/mainboard/gizmosphere/gizmo2/irq_tables.c b/src/mainboard/gizmosphere/gizmo2/irq_tables.c deleted file mode 100644 index 530c132..0000000 --- a/src/mainboard/gizmosphere/gizmo2/irq_tables.c +++ /dev/null @@ -1,100 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <string.h> -#include <stdint.h> -#include <arch/pirq_routing.h> - -static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, - u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, - u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, - u8 slot, u8 rfu) -{ - pirq_info->bus = bus; - pirq_info->devfn = devfn; - pirq_info->irq[0].link = link0; - pirq_info->irq[0].bitmap = bitmap0; - pirq_info->irq[1].link = link1; - pirq_info->irq[1].bitmap = bitmap1; - pirq_info->irq[2].link = link2; - pirq_info->irq[2].bitmap = bitmap2; - pirq_info->irq[3].link = link3; - pirq_info->irq[3].bitmap = bitmap3; - pirq_info->slot = slot; - pirq_info->rfu = rfu; -} - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - struct irq_routing_table *pirq; - struct irq_info *pirq_info; - u32 slot_num; - u8 *v; - - u8 sum = 0; - int i; - - /* Align the table to be 16 byte aligned. */ - addr += 15; - addr &= ~15; - - /* This table must be between 0xf0000 & 0x100000 */ - printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); - - pirq = (void *)(addr); - v = (u8 *) (addr); - - pirq->signature = PIRQ_SIGNATURE; - pirq->version = PIRQ_VERSION; - - pirq->rtr_bus = 0; - pirq->rtr_devfn = PCI_DEVFN(0x14, 4); - - pirq->exclusive_irqs = 0; - - pirq->rtr_vendor = 0x1002; - pirq->rtr_device = 0x4384; - - pirq->miniport_data = 0; - - memset(pirq->rfu, 0, sizeof(pirq->rfu)); - - pirq_info = (void *)(&pirq->checksum + 1); - slot_num = 0; - - /* pci bridge */ - write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), - 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, - 0); - pirq_info++; - - slot_num++; - - pirq->size = 32 + 16 * slot_num; - - for (i = 0; i < pirq->size; i++) - sum += v[i]; - - sum = pirq->checksum - sum; - - if (sum != pirq->checksum) { - pirq->checksum = sum; - } - - printk(BIOS_INFO, "write_pirq_routing_table done.\n"); - - return (unsigned long)pirq_info; -} diff --git a/src/mainboard/gizmosphere/gizmo2/mainboard.c b/src/mainboard/gizmosphere/gizmo2/mainboard.c deleted file mode 100644 index f856df9..0000000 --- a/src/mainboard/gizmosphere/gizmo2/mainboard.c +++ /dev/null @@ -1,120 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC - * All Rights Reserved - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/device.h> -#include <southbridge/amd/agesa/hudson/pci_devs.h> -#include <southbridge/amd/agesa/hudson/amd_pci_int_defs.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <northbridge/amd/agesa/family16kb/pci_devs.h> - -/*********************************************************** - * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. - * This table is responsible for physically routing the PIC and - * IOAPIC IRQs to the different PCI devices on the system. It - * is read and written via registers 0xC00/0xC01 as an - * Index/Data pair. These values are chipset and mainboard - * dependent and should be updated accordingly. - * - * These values are used by the PCI configuration space, - * MP Tables. TODO: Make ACPI use these values too. - */ -const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = { - /* INTA# - INTH# */ - [0x00] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B, - /* Misc-nil,0,1,2, INT from Serial irq */ - [0x08] = 0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - /* SCI, SMBUS0, ASF, HDA, FC, RSVD, PerMon, SD */ - [0x10] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, - /* IMC INT0 - 5 */ - [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, - /* USB Devs 18/19/22 INTA-C */ - [0x30] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B, - /* SATA */ - [0x41] = 0x0F, -}; - -const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = { - /* INTA# - INTH# */ - [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, - /* Misc-nil,0,1,2, INT from Serial irq */ - [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon, SD */ - [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F, - /* IMC INT0 - 5 */ - [0x20] = 0x05,0x1F,0x1F,0x1F,0x1F,0x1F, - /* USB Devs 18/19/20/22 INTA-C */ - [0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12, - /* SATA */ - [0x41] = 0x13 -}; - -/* - * This table defines the index into the picr/intr_data - * tables for each device. Any enabled device and slot - * that uses hardware interrupts should have an entry - * in this table to define its index into the FCH - * PCI_INTR register 0xC00/0xC01. This index will define - * the interrupt that it should use. Putting PIRQ_A into - * the PIN A index for a device will tell that device to - * use PIC IRQ 10 if it uses PIN A for its hardware INT. - */ -static const struct pirq_struct mainboard_pirq_data[] = { - /* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D}}, */ - {GFX_DEVFN, {PIRQ_A, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* VGA: 01.0 */ - {ACTL_DEVFN,{PIRQ_NC, PIRQ_B, PIRQ_NC, PIRQ_NC}}, /* Audio: 01.1 */ - {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* x4 PCIe: 02.1 */ - {NB_PCIE_PORT2_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A}}, /* mPCIe: 02.2 */ - {NB_PCIE_PORT3_DEVFN, {PIRQ_C, PIRQ_D, PIRQ_A, PIRQ_B}}, /* NIC: 02.3 */ - {NB_PCIE_PORT4_DEVFN, {PIRQ_D, PIRQ_A, PIRQ_B, PIRQ_C}}, /* Edge: 02.4 */ - {NB_PCIE_PORT5_DEVFN, {PIRQ_E, PIRQ_F, PIRQ_G, PIRQ_H}}, /* Edge: 02.5 */ - {XHCI_DEVFN, {PIRQ_C, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* XHCI: 10.0 */ - {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SATA: 11.0 */ - {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1: 12.0 */ - {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1: 12.2 */ - {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2: 13.0 */ - {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2: 13.2 */ - {SMBUS_DEVFN, {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SMBUS: 14.0 */ - {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* HDA: 14.2 */ - {SD_DEVFN, {PIRQ_SD, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SD: 14.7 */ -}; - -const u8 *picr_data = mainboard_picr_data; -const u8 *intr_data = mainboard_intr_data; - -/* PIRQ Setup */ -static void pirq_setup(void) -{ - pirq_data_ptr = mainboard_pirq_data; - pirq_data_size = sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct); - intr_data_ptr = mainboard_intr_data; - picr_data_ptr = mainboard_picr_data; -} - -/********************************************** - * enable the dedicated function in mainboard. - **********************************************/ -static void mainboard_enable(struct device *dev) -{ - printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - /* Initialize the PIRQ data structures for consumption */ - pirq_setup(); -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/gizmosphere/gizmo2/mptable.c b/src/mainboard/gizmosphere/gizmo2/mptable.c deleted file mode 100644 index e4edc5f..0000000 --- a/src/mainboard/gizmosphere/gizmo2/mptable.c +++ /dev/null @@ -1,159 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <stdint.h> -#include <cpu/x86/lapic.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <drivers/generic/ioapic/chip.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - /* Initialize the MP_Table */ - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - /* - * Type 0: Processor Entries: - * LAPIC ID, LAPIC Version, CPU Flags:EN/BP, - * CPU Signature (Stepping, Model, Family), - * Feature Flags - */ - smp_write_processors(mc); - - /* - * Type 1: Bus Entries: - * Bus ID, Bus Type - */ - mptable_write_buses(mc, NULL, &bus_isa); - - /* - * Type 2: I/O APICs: - * APIC ID, Version, APIC Flags:EN, Address - */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* - * Type 3: I/O Interrupt Table Entries: - * Int Type, Int Polarity, Int Level, Source Bus ID, - * Source Bus IRQ, Dest APIC ID, Dest PIN# - */ - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) - - /* APU Internal Graphic Device */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]); - - /* SMBUS / ACPI */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]); - - /* Southbridge HD Audio */ - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]); - - /* LPC */ - PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]); - PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]); - PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]); - PCI_INT(0x0, 0x16, 0x2, intr_data_ptr[PIRQ_EHCI3]); - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_OHCI4]); - - /* SATA */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]); - - /* on board NIC & Slot PCIE */ - PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); - PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]); - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0 */ - PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); - PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); - PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]); - PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]); - - /* PCI_SLOT 1 */ - PCI_INT(bus_pci, 0x6, 0x0, intr_data_ptr[PIRQ_F]); - PCI_INT(bus_pci, 0x6, 0x1, intr_data_ptr[PIRQ_G]); - PCI_INT(bus_pci, 0x6, 0x2, intr_data_ptr[PIRQ_H]); - PCI_INT(bus_pci, 0x6, 0x3, intr_data_ptr[PIRQ_E]); - - /* PCI_SLOT 2 */ - PCI_INT(bus_pci, 0x7, 0x0, intr_data_ptr[PIRQ_G]); - PCI_INT(bus_pci, 0x7, 0x1, intr_data_ptr[PIRQ_H]); - PCI_INT(bus_pci, 0x7, 0x2, intr_data_ptr[PIRQ_E]); - PCI_INT(bus_pci, 0x7, 0x3, intr_data_ptr[PIRQ_F]); - - PCI_INT(bus_pci, 0x0, 0x0, intr_data_ptr[PIRQ_C]); - PCI_INT(bus_pci, 0x0, 0x1, intr_data_ptr[PIRQ_D]); - PCI_INT(bus_pci, 0x0, 0x2, intr_data_ptr[PIRQ_E]); - } - - /* PCIe Lan*/ - PCI_INT(0x0, 0x06, 0x0, intr_data_ptr[PIRQ_D]); - - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_A]); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_B]); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_C]); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_D]); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/gizmosphere/gizmo2/romstage.c b/src/mainboard/gizmosphere/gizmo2/romstage.c deleted file mode 100644 index 4676199..0000000 --- a/src/mainboard/gizmosphere/gizmo2/romstage.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <device/pci_ops.h> -#include <northbridge/amd/agesa/state_machine.h> -#include <southbridge/amd/agesa/hudson/hudson.h> - -void board_BeforeAgesa(struct sysinfo *cb) -{ - /* For serial port option, plug-in card on LPC. */ - pci_devfn_t dev = PCI_DEV(0, 0x14, 3); - pci_write_config32(dev, 0x44, 0xff03ffd5); - - /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for - * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA - * even though the register is not documented in the Kabini BKDG. - * Otherwise the serial output is bad code. - */ - outb(0xD2, 0xcd6); - outb(0x00, 0xcd7); -} - -#if 0 - /* LPC clock? Should happen before enable_serial. */ - - /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */ - int i; - for(i = 0; i < 200000; i++) - val = inb(0xcd6); -#endif - -#if 0 - /* Was before copy_and_run. */ - outb(0xEA, 0xCD6); - outb(0x1, 0xcd7); -#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/38107 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1947638f80a1de498b8a34c5099283d658f2b8d5 Gerrit-Change-Number: 38107 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: mb/elmex/pcm205400: Drop boards with ROMCC_BOOTBLOCK
by HAOUAS Elyes (Code Review) Jan. 7, 2020

Jan. 7, 2020

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38108 ) Change subject: mb/elmex/pcm205400: Drop boards with ROMCC_BOOTBLOCK ...................................................................... mb/elmex/pcm205400: Drop boards with ROMCC_BOOTBLOCK ROMCC_BOOTBLOCK is no more. Drop unsupported, unmaintained boards. Change-Id: I75f4ae75a42656891447eec5d7055945016d9e90 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- D src/mainboard/elmex/pcm205400/BiosCallOuts.c D src/mainboard/elmex/pcm205400/Kconfig D src/mainboard/elmex/pcm205400/Kconfig.name D src/mainboard/elmex/pcm205400/Makefile.inc D src/mainboard/elmex/pcm205400/OemCustomize.c D src/mainboard/elmex/pcm205400/OptionsIds.h D src/mainboard/elmex/pcm205400/acpi/gpe.asl D src/mainboard/elmex/pcm205400/acpi/ide.asl D src/mainboard/elmex/pcm205400/acpi/mainboard.asl D src/mainboard/elmex/pcm205400/acpi/routing.asl D src/mainboard/elmex/pcm205400/acpi/sata.asl D src/mainboard/elmex/pcm205400/acpi/sleep.asl D src/mainboard/elmex/pcm205400/acpi/superio.asl D src/mainboard/elmex/pcm205400/acpi/usb_oc.asl D src/mainboard/elmex/pcm205400/acpi_tables.c D src/mainboard/elmex/pcm205400/board_info.txt D src/mainboard/elmex/pcm205400/buildOpts.c D src/mainboard/elmex/pcm205400/cmos.layout D src/mainboard/elmex/pcm205400/devicetree.cb D src/mainboard/elmex/pcm205400/dsdt.asl D src/mainboard/elmex/pcm205400/irq_tables.c D src/mainboard/elmex/pcm205400/mainboard.c D src/mainboard/elmex/pcm205400/mptable.c D src/mainboard/elmex/pcm205400/platform_cfg.h D src/mainboard/elmex/pcm205400/romstage.c 25 files changed, 0 insertions(+), 2,834 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/38108/1 diff --git a/src/mainboard/elmex/pcm205400/BiosCallOuts.c b/src/mainboard/elmex/pcm205400/BiosCallOuts.c deleted file mode 100644 index 6e2eaed..0000000 --- a/src/mainboard/elmex/pcm205400/BiosCallOuts.c +++ /dev/null @@ -1,92 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <AGESA.h> -#include <amdlib.h> -#include <northbridge/amd/agesa/BiosCallOuts.h> -#include <SB800.h> -#include <stdlib.h> - -static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr); -static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr); - -const BIOS_CALLOUT_STRUCT BiosCallouts[] = -{ - {AGESA_DO_RESET, agesa_Reset }, - {AGESA_READ_SPD, agesa_ReadSpd }, - {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, - {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, - {AGESA_GNB_PCIE_SLOT_RESET, board_GnbPcieSlotReset }, - {AGESA_HOOKBEFORE_DRAM_INIT, board_BeforeDramInit }, - {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, agesa_NoopSuccess }, - {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, - {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, -}; -const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); - -/* Call the host environment interface to provide a user hook opportunity. */ -static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr) -{ - // Unlike e.g. AMD Inagua, Persimmon is unable to vary the RAM voltage. - // Make sure the right speed settings are selected. - ((MEM_DATA_STRUCT*)ConfigPtr)->ParameterListPtr->DDR3Voltage = VOLT1_5; - return AGESA_SUCCESS; -} - -/* PCIE slot reset control */ -static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr) -{ - AGESA_STATUS Status; - UINTN FcnData; - PCIe_SLOT_RESET_INFO *ResetInfo; - - UINT32 GpioMmioAddr; - UINT32 AcpiMmioAddr; - UINT8 Data8; - UINT16 Data16; - - FcnData = Data; - ResetInfo = ConfigPtr; - // Get SB800 MMIO Base (AcpiMmioAddr) - WriteIo8(0xCD6, 0x27); - Data8 = ReadIo8(0xCD7); - Data16=Data8<<8; - WriteIo8(0xCD6, 0x26); - Data8 = ReadIo8(0xCD7); - Data16|=Data8; - AcpiMmioAddr = (UINT32)Data16 << 16; - Status = AGESA_UNSUPPORTED; - GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; - switch (ResetInfo->ResetId) - { - case 46: // GPIO50 = SBGPIO_PCIE_RST# affects LAN0, LAN1, PCIe slot - switch (ResetInfo->ResetControl) { - case AssertSlotReset: - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50); - Data8 &= ~(UINT8)BIT6; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG50, Data8); - Status = AGESA_SUCCESS; - break; - case DeassertSlotReset: - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50); - Data8 |= BIT6; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG50, Data8); - Status = AGESA_SUCCESS; - break; - } - break; - } - return Status; -} diff --git a/src/mainboard/elmex/pcm205400/Kconfig b/src/mainboard/elmex/pcm205400/Kconfig deleted file mode 100644 index e94a6d8..0000000 --- a/src/mainboard/elmex/pcm205400/Kconfig +++ /dev/null @@ -1,76 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2011 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -config BOARD_ELMEX_PCM205400 - def_bool n - -if BOARD_ELMEX_PCM205400 - -config MAINBOARD_PART_NUMBER - string - default "pcm205400" - -config VGA_BIOS_ID - string - default "1002,9806" # FUSION_G_T56N - -endif # BOARD_ELMEX_PCM205400 - -if BOARD_ELMEX_PCM205400 || BOARD_ELMEX_PCM205401 - -config BOARD_SPECIFIC_OPTIONS - def_bool y - #select ROMCC_BOOTBLOCK - select CPU_AMD_AGESA_FAMILY14 - select NORTHBRIDGE_AMD_AGESA_FAMILY14 - select SOUTHBRIDGE_AMD_CIMX_SB800 - select SUPERIO_FINTEK_F81865F - select HAVE_OPTION_TABLE - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select HAVE_ACPI_RESUME - select HAVE_ACPI_TABLES - select BOARD_ROMSIZE_KB_4096 - select GFXUMA - -config MAINBOARD_DIR - string - default "elmex/pcm205400" - -config HW_MEM_HOLE_SIZEK - hex - default 0x200000 - -config MAX_CPUS - int - default 2 - -config IRQ_SLOT_COUNT - int - default 11 - -config ONBOARD_VGA_IS_PRIMARY - bool - default y - -config VGA_BIOS - bool - default n - -config SB800_AHCI_ROM - bool - default n - -endif # BOARD_ELMEX_PCM205400 | BOARD_ELMEX_PCM205401 diff --git a/src/mainboard/elmex/pcm205400/Kconfig.name b/src/mainboard/elmex/pcm205400/Kconfig.name deleted file mode 100644 index 6488992..0000000 --- a/src/mainboard/elmex/pcm205400/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -#config BOARD_ELMEX_PCM205400 -# bool"pcm205400" diff --git a/src/mainboard/elmex/pcm205400/Makefile.inc b/src/mainboard/elmex/pcm205400/Makefile.inc deleted file mode 100644 index ba56286..0000000 --- a/src/mainboard/elmex/pcm205400/Makefile.inc +++ /dev/null @@ -1,29 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2011 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -ifeq ($(CONFIG_AHCI_BIOS),y) -stripped_ahcibios_id = $(call strip_quotes,$(CONFIG_AHCI_BIOS_ID)) -cbfs-files-$(CONFIG_AHCI_BIOS) += pci$(stripped_ahcibios_id).rom -pci$(stripped_ahcibios_id).rom-file := $(call strip_quotes,$(CONFIG_AHCI_BIOS_FILE)) -pci$(stripped_ahcibios_id).rom-type := optionrom -endif - -romstage-y += buildOpts.c -romstage-y += BiosCallOuts.c -romstage-y += OemCustomize.c - -ramstage-y += buildOpts.c -ramstage-y += BiosCallOuts.c -ramstage-y += OemCustomize.c diff --git a/src/mainboard/elmex/pcm205400/OemCustomize.c b/src/mainboard/elmex/pcm205400/OemCustomize.c deleted file mode 100644 index f8a2613..0000000 --- a/src/mainboard/elmex/pcm205400/OemCustomize.c +++ /dev/null @@ -1,122 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -#include <AGESA.h> -#include <northbridge/amd/agesa/state_machine.h> -#include <PlatformMemoryConfiguration.h> - -static const PCIe_PORT_DESCRIPTOR PortList[] = { - // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, - HotplugDisabled, - PcieGen2, - PcieGen2, - AspmL0sL1, 46) - }, - // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5), - PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 5, - HotplugDisabled, - PcieGen2, - PcieGen2, - AspmL0sL1, 46) - }, - // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6), - PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 6, - HotplugDisabled, - PcieGen2, - PcieGen2, - AspmL0sL1, 46) - }, - // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7), - PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 7, - HotplugDisabled, - PcieGen2, - PcieGen2, - AspmL0sL1, 0) - }, - // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) - { - DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, - HotplugDisabled, - PcieGen2, - PcieGen2, - AspmL0sL1, 0) - } -}; - -static const PCIe_DDI_DESCRIPTOR DdiList[] = { - // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeLvds, Aux1, Hdp1) - }, - // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) - { - DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2) - } -}; - -static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { - .Flags = DESCRIPTOR_TERMINATE_LIST, - .SocketId = 0, - .PciePortList = PortList, - .DdiLinkList = DdiList, -}; - -void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) -{ - InitEarly->GnbConfig.PcieComplexList = &PcieComplex; - InitEarly->GnbConfig.PsppPolicy = 0; -} - -/*---------------------------------------------------------------------------------------- - * CUSTOMER OVERIDES MEMORY TABLE - *---------------------------------------------------------------------------------------- - */ - -/* - * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA - * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable - * is populated, AGESA will base its settings on the data from the table. Otherwise, it will - * use its default conservative settings. - */ -static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { - NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2), - NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1), - PSO_END -}; - -void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) -{ - InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; -} diff --git a/src/mainboard/elmex/pcm205400/OptionsIds.h b/src/mainboard/elmex/pcm205400/OptionsIds.h deleted file mode 100644 index 2d8381b..0000000 --- a/src/mainboard/elmex/pcm205400/OptionsIds.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDS_DEBUG_PORT - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE -#define IDSOPT_ASSERT_ENABLED TRUE - -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - -#endif diff --git a/src/mainboard/elmex/pcm205400/acpi/gpe.asl b/src/mainboard/elmex/pcm205400/acpi/gpe.asl deleted file mode 100644 index 3cf38c0..0000000 --- a/src/mainboard/elmex/pcm205400/acpi/gpe.asl +++ /dev/null @@ -1,69 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Scope(\_GPE) { /* Start Scope GPE */ - - /* Legacy PM event */ - Method(_L08) { - /* DBGO("\\_GPE\\_L08\n") */ - } - - /* Temp warning (TWarn) event */ - Method(_L09) { - /* DBGO("\\_GPE\\_L09\n") */ - /* Notify (\_TZ.TZ00, 0x80) */ - } - - /* USB controller PME# */ - Method(_L0B) { - /* DBGO("\\_GPE\\_L0B\n") */ - Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* ExtEvent0 SCI event */ - Method(_L10) { - /* DBGO("\\_GPE\\_L10\n") */ - } - - - /* ExtEvent1 SCI event */ - Method(_L11) { - /* DBGO("\\_GPE\\_L11\n") */ - } - - /* GPIO0 or GEvent8 event */ - Method(_L18) { - /* DBGO("\\_GPE\\_L18\n") */ - Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* Azalia SCI event */ - Method(_L1B) { - /* DBGO("\\_GPE\\_L1B\n") */ - Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - } -} /* End Scope GPE */ - -/* Contains the GPEs for USB overcurrent */ -#include "usb_oc.asl" diff --git a/src/mainboard/elmex/pcm205400/acpi/ide.asl b/src/mainboard/elmex/pcm205400/acpi/ide.asl deleted file mode 100644 index 59ea078..0000000 --- a/src/mainboard/elmex/pcm205400/acpi/ide.asl +++ /dev/null @@ -1,240 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* -Scope (_SB) { - Device(PCI0) { - Device(IDEC) { - Name(_ADR, 0x00140001) - #include "ide.asl" - } - } -} -*/ - -/* Some timing tables */ -Name(UDTT, Package(){ /* Udma timing table */ - 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */ -}) - -Name(MDTT, Package(){ /* MWDma timing table */ - 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */ -}) - -Name(POTT, Package(){ /* Pio timing table */ - 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */ -}) - -/* Some timing register value tables */ -Name(MDRT, Package(){ /* MWDma timing register table */ - 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */ -}) - -Name(PORT, Package(){ - 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */ -}) - -OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */ - Field(ICRG, AnyAcc, NoLock, Preserve) -{ - PPTS, 8, /* Primary PIO Slave Timing */ - PPTM, 8, /* Primary PIO Master Timing */ - OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */ - PMTM, 8, /* Primary MWDMA Master Timing */ - OFFSET(0x08), PPCR, 8, /* Primary PIO Control */ - OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */ - PPSM, 4, /* Primary PIO slave Mode */ - OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */ - OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */ - PDSM, 4, /* Primary UltraDMA Mode */ -} - -Method(GTTM, 1) /* get total time*/ -{ - Store(And(Arg0, 0x0F), Local0) /* Recovery Width */ - Increment(Local0) - Store(ShiftRight(Arg0, 4), Local1) /* Command Width */ - Increment(Local1) - Return(Multiply(30, Add(Local0, Local1))) -} - -Device(PRID) -{ - Name (_ADR, Zero) - Method(_GTM, 0, Serialized) - { - NAME(OTBF, Buffer(20) { /* out buffer */ - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 - }) - - CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */ - CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */ - CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */ - CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */ - CreateDwordField(OTBF, 16, BFFG) /* buffer flags */ - - /* Just return if the channel is disabled */ - If(And(PPCR, 0x01)) { /* primary PIO control */ - Return(OTBF) - } - - /* Always tell them independent timing available and IOChannelReady used on both drives */ - Or(BFFG, 0x1A, BFFG) - - Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */ - Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */ - - If(And(PDCR, 0x01)) { /* It's under UDMA mode */ - Or(BFFG, 0x01, BFFG) - Store(DerefOf(Index(UDTT, PDMM)), DSD0) - } - Else { - Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */ - } - - If(And(PDCR, 0x02)) { /* It's under UDMA mode */ - Or(BFFG, 0x04, BFFG) - Store(DerefOf(Index(UDTT, PDSM)), DSD1) - } - Else { - Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */ - } - - Return(OTBF) /* out buffer */ - } /* End Method(_GTM) */ - - Method(_STM, 3, Serialized) - { - NAME(INBF, Buffer(20) { /* in buffer */ - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 - }) - - CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */ - CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */ - CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */ - CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */ - CreateDwordField(INBF, 16, BFFG) /*buffer flag */ - - Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0) - Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */ - Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1) - Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */ - - Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */ - Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */ - - If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0) - Divide(Local0, 7, PDMM,) - Or(PDCR, 0x01, PDCR) - } - Else { - If(LNotEqual(DSD0, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTM) - } - } - - If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0) - Divide(Local0, 7, PDSM,) - Or(PDCR, 0x02, PDCR) - } - Else { - If(LNotEqual(DSD1, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTS) - } - } - /* Return(INBF) */ - } /*End Method(_STM) */ - Device(MST) - { - Name(_ADR, 0) - Method(_GTF, 0, Serialized) { - Name(CMBF, Buffer(21) { - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 - }) - CreateByteField(CMBF, 1, POMD) - CreateByteField(CMBF, 8, DMMD) - CreateByteField(CMBF, 5, CMDA) - CreateByteField(CMBF, 12, CMDB) - CreateByteField(CMBF, 19, CMDC) - - Store(0xA0, CMDA) - Store(0xA0, CMDB) - Store(0xA0, CMDC) - - Or(PPMM, 0x08, POMD) - - If(And(PDCR, 0x01)) { - Or(PDMM, 0x40, DMMD) - } - Else { - Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) - } - } - Return(CMBF) - } - } /* End Device(MST) */ - - Device(SLAV) - { - Name(_ADR, 1) - Method(_GTF, 0, Serialized) { - Name(CMBF, Buffer(21) { - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 - }) - CreateByteField(CMBF, 1, POMD) - CreateByteField(CMBF, 8, DMMD) - CreateByteField(CMBF, 5, CMDA) - CreateByteField(CMBF, 12, CMDB) - CreateByteField(CMBF, 19, CMDC) - - Store(0xB0, CMDA) - Store(0xB0, CMDB) - Store(0xB0, CMDC) - - Or(PPSM, 0x08, POMD) - - If(And(PDCR, 0x02)) { - Or(PDSM, 0x40, DMMD) - } - Else { - Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) - } - } - Return(CMBF) - } - } /* End Device(SLAV) */ -} diff --git a/src/mainboard/elmex/pcm205400/acpi/mainboard.asl b/src/mainboard/elmex/pcm205400/acpi/mainboard.asl deleted file mode 100644 index 702cb92..0000000 --- a/src/mainboard/elmex/pcm205400/acpi/mainboard.asl +++ /dev/null @@ -1,61 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Data to be patched by the BIOS during POST */ -/* FIXME the patching is not done yet! */ -/* Memory related values */ -Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ -Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ -Name(PBLN, 0x0) /* Length of BIOS area */ - -Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ -Name(HPBA, 0xFED00000) /* Base address of HPET table */ - -/* Some global data */ -Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ -Name(OSV, Ones) /* Assume nothing */ -Name(PMOD, One) /* Assume APIC */ - -Scope(\_SB) { - Method(OSFL, 0){ - - if(LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */ - - if(CondRefOf(\_OSI)) - { - Store(1, OSVR) /* Assume some form of XP */ - if (\_OSI("Windows 2006")) /* Vista */ - { - Store(2, OSVR) - } - } else { - If(WCMP(\_OS,"Linux")) { - Store(3, OSVR) /* Linux */ - } Else { - Store(4, OSVR) /* Gotta be WinCE */ - } - } - Return(OSVR) - } -} - -Scope(\_SI) { - Method(_SST, 1) { - /* DBGO("\\_SI\\_SST\n") */ - /* DBGO(" New Indicator state: ") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - } -} /* End Scope SI */ diff --git a/src/mainboard/elmex/pcm205400/acpi/routing.asl b/src/mainboard/elmex/pcm205400/acpi/routing.asl deleted file mode 100644 index 2cf17a7..0000000 --- a/src/mainboard/elmex/pcm205400/acpi/routing.asl +++ /dev/null @@ -1,337 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* -#include <arch/acpi.h> -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 - ) - { - #include "routing.asl" - } -*/ - -/* Routing is in System Bus scope */ -Scope(\_SB) { - Name(PR0, Package(){ - /* NB devices */ - /* Bus 0, Dev 0 - RS780 Host Controller */ - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ - Package(){0x0001FFFF, 0, INTC, 0 }, - Package(){0x0001FFFF, 1, INTD, 0 }, - /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){0x0002FFFF, 0, INTC, 0 }, - Package(){0x0002FFFF, 1, INTD, 0 }, - Package(){0x0002FFFF, 2, INTA, 0 }, - Package(){0x0002FFFF, 3, INTB, 0 }, - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - Package(){0x0003FFFF, 0, INTD, 0 }, - Package(){0x0003FFFF, 1, INTA, 0 }, - Package(){0x0003FFFF, 2, INTB, 0 }, - Package(){0x0003FFFF, 3, INTC, 0 }, - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, INTA, 0 }, - Package(){0x0004FFFF, 1, INTB, 0 }, - Package(){0x0004FFFF, 2, INTC, 0 }, - Package(){0x0004FFFF, 3, INTD, 0 }, - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - Package(){0x0005FFFF, 0, INTB, 0 }, - Package(){0x0005FFFF, 1, INTC, 0 }, - Package(){0x0005FFFF, 2, INTD, 0 }, - Package(){0x0005FFFF, 3, INTA, 0 }, - /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ - Package(){0x0006FFFF, 0, INTC, 0 }, - Package(){0x0006FFFF, 1, INTD, 0 }, - Package(){0x0006FFFF, 2, INTA, 0 }, - Package(){0x0006FFFF, 3, INTB, 0 }, - /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ - Package(){0x0007FFFF, 0, INTD, 0 }, - Package(){0x0007FFFF, 1, INTA, 0 }, - Package(){0x0007FFFF, 2, INTB, 0 }, - Package(){0x0007FFFF, 3, INTC, 0 }, - - /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ - - - /* SB devices */ - /* Bus 0, Dev 17 - SATA controller */ - Package(){0x0011FFFF, 0, INTD, 0 }, - - /* OHCI, dev 18, 19, 22 func 0 - * EHCI, dev 18, 19, 22 func 2 */ - Package(){0x0012FFFF, 0, INTC, 0 }, /* Dev 12, INTA, handled by INTC device, Global */ - Package(){0x0012FFFF, 1, INTB, 0 }, /* Dev 12, INTB, handled by INTB device, Global */ - - Package(){0x0013FFFF, 0, INTC, 0 }, - Package(){0x0013FFFF, 1, INTB, 0 }, - - Package(){0x0016FFFF, 0, INTC, 0 }, - Package(){0x0016FFFF, 1, INTB, 0 }, - - /* Bus 0, Dev 20 - F0:SMBus/ACPI; F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ - Package(){0x0014FFFF, 0, INTA, 0 }, - Package(){0x0014FFFF, 1, INTB, 0 }, - Package(){0x0014FFFF, 2, INTC, 0 }, - Package(){0x0014FFFF, 3, INTD, 0 }, - - Package(){0x0015FFFF, 0, INTA, 0 }, - Package(){0x0015FFFF, 1, INTB, 0 }, - Package(){0x0015FFFF, 2, INTC, 0 }, - Package(){0x0015FFFF, 3, INTD, 0 }, - }) - - Name(APR0, Package(){ - /* NB devices in APIC mode */ - /* Bus 0, Dev 0 - RS780 Host Controller */ - - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ - Package(){0x0001FFFF, 0, 0, 18 }, - Package(){0x0001FFFF, 1, 0, 19 }, - - /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){0x0002FFFF, 0, 0, 18 }, - /* Package(){0x0002FFFF, 1, 0, 19 }, */ - /* Package(){0x0002FFFF, 2, 0, 16 }, */ - /* Package(){0x0002FFFF, 3, 0, 17 }, */ - - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - Package(){0x0003FFFF, 0, 0, 19 }, - Package(){0x0003FFFF, 1, 0, 16 }, - Package(){0x0003FFFF, 2, 0, 17 }, - Package(){0x0003FFFF, 3, 0, 18 }, - - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, 0, 16 }, - Package(){0x0004FFFF, 1, 0, 17 }, - Package(){0x0004FFFF, 2, 0, 18 }, - Package(){0x0004FFFF, 3, 0, 19 }, - - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - Package(){0x0005FFFF, 0, 0, 17 }, - Package(){0x0005FFFF, 1, 0, 18 }, - Package(){0x0005FFFF, 2, 0, 19 }, - Package(){0x0005FFFF, 3, 0, 16 }, - - /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ - Package(){0x0006FFFF, 0, 0, 18 }, - Package(){0x0006FFFF, 1, 0, 19 }, - Package(){0x0006FFFF, 2, 0, 16 }, - Package(){0x0006FFFF, 3, 0, 17 }, - - /* Bus 0, Dev 7 - PCIe Bridge for network card */ - Package(){0x0007FFFF, 0, 0, 19 }, - Package(){0x0007FFFF, 1, 0, 16 }, - Package(){0x0007FFFF, 2, 0, 17 }, - Package(){0x0007FFFF, 3, 0, 18 }, - - /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ - - /* SB devices in APIC mode */ - /* Bus 0, Dev 17 - SATA controller */ - Package(){0x0011FFFF, 0, 0, 19 }, - - /* OHCI, dev 18, 19, 22 func 0 - * EHCI, dev 18, 19, 22 func 2 */ - Package(){0x0012FFFF, 0, 0, 18 }, - Package(){0x0012FFFF, 1, 0, 17 }, - - Package(){0x0013FFFF, 0, 0, 18 }, - Package(){0x0013FFFF, 1, 0, 17 }, - - Package(){0x0016FFFF, 0, 0, 18 }, - Package(){0x0016FFFF, 1, 0, 17 }, - - /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ - Package(){0x0014FFFF, 0, 0, 16 }, - Package(){0x0014FFFF, 1, 0, 17 }, - Package(){0x0014FFFF, 2, 0, 18 }, - Package(){0x0014FFFF, 3, 0, 19 }, - /* Package(){0x00140004, 2, 0, 18 }, */ - /* Package(){0x00140004, 3, 0, 19 }, */ - /* Package(){0x00140005, 1, 0, 17 }, */ - /* Package(){0x00140006, 1, 0, 17 }, */ - - /* TODO: pcie */ - Package(){0x0015FFFF, 0, 0, 16 }, - Package(){0x0015FFFF, 1, 0, 17 }, - Package(){0x0015FFFF, 2, 0, 18 }, - Package(){0x0015FFFF, 3, 0, 19 }, - }) - - Name(PR1, Package(){ - /* Internal graphics - RS780 VGA, Bus1, Dev5 */ - Package(){0x0005FFFF, 0, INTA, 0 }, - Package(){0x0005FFFF, 1, INTB, 0 }, - Package(){0x0005FFFF, 2, INTC, 0 }, - Package(){0x0005FFFF, 3, INTD, 0 }, - }) - Name(APR1, Package(){ - /* Internal graphics - RS780 VGA, Bus1, Dev5 */ - Package(){0x0005FFFF, 0, 0, 18 }, - Package(){0x0005FFFF, 1, 0, 19 }, - /* Package(){0x0005FFFF, 2, 0, 20 }, */ - /* Package(){0x0005FFFF, 3, 0, 17 }, */ - }) - - Name(PS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - Name(APS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, - }) - Name(APS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, - }) - - Name(PS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, - }) - Name(APS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - - Name(PS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - Name(APS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PS7, Package(){ - /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - Name(APS7, Package(){ - /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, - }) - - Name(PE0, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, - }) - Name(APE0, Package(){ - /* PCIe slot - Hooked to PCIe */ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, - }) - - Name(PE1, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, - }) - Name(APE1, Package(){ - /* PCIe slot - Hooked to PCIe */ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - - Name(PE2, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - Name(APE2, Package(){ - /* PCIe slot - Hooked to PCIe */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PE3, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - Name(APE3, Package(){ - /* PCIe slot - Hooked to PCIe */ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, - }) - - Name(PCIB, Package(){ - /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Func 4. */ - Package(){0x0003FFFF, 0, 0, 0x14 }, - Package(){0x0003FFFF, 1, 0, 0x15 }, - Package(){0x0003FFFF, 2, 0, 0x16 }, - Package(){0x0003FFFF, 3, 0, 0x17 }, - Package(){0x0004FFFF, 0, 0, 0x15 }, - Package(){0x0004FFFF, 1, 0, 0x16 }, - Package(){0x0004FFFF, 2, 0, 0x17 }, - Package(){0x0004FFFF, 3, 0, 0x14 }, - Package(){0x0005FFFF, 0, 0, 0x16 }, - Package(){0x0005FFFF, 1, 0, 0x17 }, - Package(){0x0005FFFF, 2, 0, 0x14 }, - Package(){0x0005FFFF, 3, 0, 0x15 }, - }) -} diff --git a/src/mainboard/elmex/pcm205400/acpi/sata.asl b/src/mainboard/elmex/pcm205400/acpi/sata.asl deleted file mode 100644 index 9e0e535..0000000 --- a/src/mainboard/elmex/pcm205400/acpi/sata.asl +++ /dev/null @@ -1,145 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* simple name description */ - -/* -Scope (_SB) { - Device(PCI0) { - Device(SATA) { - Name(_ADR, 0x00110000) - #include "sata.asl" - } - } -} -*/ - -Name(STTM, Buffer(20) { - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x1f, 0x00, 0x00, 0x00 -}) - -/* Start by clearing the PhyRdyChg bits */ -Method(_INI) { - \_GPE._L1F() -} - -Device(PMRY) -{ - Name(_ADR, 0) - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(PMST) { - Name(_ADR, 0) - Method(_STA,0) { - if (LGreater(P0IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - }/* end of PMST */ - - Device(PSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (LGreater(P1IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of PSLA */ -} /* end of PMRY */ - - -Device(SEDY) -{ - Name(_ADR, 1) /* IDE Scondary Channel */ - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(SMST) - { - Name(_ADR, 0) - Method(_STA,0) { - if (LGreater(P2IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SMST */ - - Device(SSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (LGreater(P3IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SSLA */ -} /* end of SEDY */ - -/* SATA Hot Plug Support */ -Scope(\_GPE) { - Method(_L1F,0x0,NotSerialized) { - if (\_SB.P0PR) { - if (LGreater(\_SB.P0IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P0PR) - } - - if (\_SB.P1PR) { - if (LGreater(\_SB.P1IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P1PR) - } - - if (\_SB.P2PR) { - if (LGreater(\_SB.P2IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P2PR) - } - - if (\_SB.P3PR) { - if (LGreater(\_SB.P3IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P3PR) - } - } -} diff --git a/src/mainboard/elmex/pcm205400/acpi/sleep.asl b/src/mainboard/elmex/pcm205400/acpi/sleep.asl deleted file mode 100644 index 47de049..0000000 --- a/src/mainboard/elmex/pcm205400/acpi/sleep.asl +++ /dev/null @@ -1,117 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Wake status package */ -Name(WKST,Package(){Zero, Zero}) - -/* -* \_PTS - Prepare to Sleep method -* -* Entry: -* Arg0=The value of the sleeping state S1=1, S2=2, etc -* -* Exit: -* -none- -* -* The _PTS control method is executed at the beginning of the sleep process -* for S1-S5. The sleeping value is passed to the _PTS control method. This -* control method may be executed a relatively long time before entering the -* sleep state and the OS may abort the operation without notification to -* the ACPI driver. This method cannot modify the configuration or power -* state of any device in the system. -*/ -Method(\_PTS, 1) { - /* DBGO("\\_PTS\n") */ - /* DBGO("From S0 to S") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - - /* Don't allow PCIRST# to reset USB */ - if (LEqual(Arg0,3)){ - Store(0,URRE) - } - - /* Clear sleep SMI status flag and enable sleep SMI trap. */ - /*Store(One, CSSM) - Store(One, SSEN)*/ - - /* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(\_SB.SBRI, 0x13)) { - * Store(0,\_SB.PWDE) - *} - */ - - /* Clear wake status structure. */ - Store(0, Index(WKST,0)) - Store(0, Index(WKST,1)) -} /* End Method(\_PTS) */ - -/* -* \_BFS OEM Back From Sleep method -* -* Entry: -* Arg0=The value of the sleeping state S1=1, S2=2 -* -* Exit: -* -none- -*/ -Method(\_BFS, 1) { - /* DBGO("\\_BFS\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ -} - -/* -* \_WAK System Wake method -* -* Entry: -* Arg0=The value of the sleeping state S1=1, S2=2 -* -* Exit: -* Return package of 2 DWords -* Dword 1 - Status -* 0x00000000 wake succeeded -* 0x00000001 Wake was signaled but failed due to lack of power -* 0x00000002 Wake was signaled but failed due to thermal condition -* Dword 2 - Power Supply state -* if non-zero the effective S-state the power supply entered -*/ -Method(\_WAK, 1) { - /* DBGO("\\_WAK\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - - /* Re-enable HPET */ - Store(1,HPDE) - - /* Restore PCIRST# so it resets USB */ - if (LEqual(Arg0,3)){ - Store(1,URRE) - } - - /* Arbitrarily clear PciExpWakeStatus */ - Store(PWST, Local1) - Store(Local1, PWST) - - /* if (DeRefOf(Index(WKST,0))) { - * Store(0, Index(WKST,1)) - * } else { - * Store(Arg0, Index(WKST,1)) - * } - */ - Return(WKST) -} /* End Method(\_WAK) */ diff --git a/src/mainboard/elmex/pcm205400/acpi/superio.asl b/src/mainboard/elmex/pcm205400/acpi/superio.asl deleted file mode 100644 index daf6e91..0000000 --- a/src/mainboard/elmex/pcm205400/acpi/superio.asl +++ /dev/null @@ -1,14 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* No Super I/O device or functionality yet */ diff --git a/src/mainboard/elmex/pcm205400/acpi/usb_oc.asl b/src/mainboard/elmex/pcm205400/acpi/usb_oc.asl deleted file mode 100644 index a209909..0000000 --- a/src/mainboard/elmex/pcm205400/acpi/usb_oc.asl +++ /dev/null @@ -1,171 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* simple name description */ -/* -#include <arch/acpi.h> -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 - ) - { - #include "usb.asl" - } -*/ - -/* USB overcurrent mapping pins. */ -Name(UOM0, 0) -Name(UOM1, 2) -Name(UOM2, 0) -Name(UOM3, 7) -Name(UOM4, 2) -Name(UOM5, 2) -Name(UOM6, 6) -Name(UOM7, 2) -Name(UOM8, 6) -Name(UOM9, 6) - -Method(UCOC, 0) { - Sleep(20) - Store(0x13,CMTI) - Store(0,GPSL) -} - -/* USB Port 0 overcurrent uses Gpm 0 */ -If(LLessEqual(UOM0,9)) { - Scope (\_GPE) { - Method (_L13) { - UCOC() - if(LEqual(GPB0,PLC0)) { - Not(PLC0,PLC0) - Store(PLC0, \_SB.PT0D) - } - } - } -} - -/* USB Port 1 overcurrent uses Gpm 1 */ -If (LLessEqual(UOM1,9)) { - Scope (\_GPE) { - Method (_L14) { - UCOC() - if (LEqual(GPB1,PLC1)) { - Not(PLC1,PLC1) - Store(PLC1, \_SB.PT1D) - } - } - } -} - -/* USB Port 2 overcurrent uses Gpm 2 */ -If (LLessEqual(UOM2,9)) { - Scope (\_GPE) { - Method (_L15) { - UCOC() - if (LEqual(GPB2,PLC2)) { - Not(PLC2,PLC2) - Store(PLC2, \_SB.PT2D) - } - } - } -} - -/* USB Port 3 overcurrent uses Gpm 3 */ -If (LLessEqual(UOM3,9)) { - Scope (\_GPE) { - Method (_L16) { - UCOC() - if (LEqual(GPB3,PLC3)) { - Not(PLC3,PLC3) - Store(PLC3, \_SB.PT3D) - } - } - } -} - -/* USB Port 4 overcurrent uses Gpm 4 */ -If (LLessEqual(UOM4,9)) { - Scope (\_GPE) { - Method (_L19) { - UCOC() - if (LEqual(GPB4,PLC4)) { - Not(PLC4,PLC4) - Store(PLC4, \_SB.PT4D) - } - } - } -} - -/* USB Port 5 overcurrent uses Gpm 5 */ -If (LLessEqual(UOM5,9)) { - Scope (\_GPE) { - Method (_L1A) { - UCOC() - if (LEqual(GPB5,PLC5)) { - Not(PLC5,PLC5) - Store(PLC5, \_SB.PT5D) - } - } - } -} - -/* USB Port 6 overcurrent uses Gpm 6 */ -If (LLessEqual(UOM6,9)) { - Scope (\_GPE) { - /* Method (_L1C) { */ - Method (_L06) { - UCOC() - if (LEqual(GPB6,PLC6)) { - Not(PLC6,PLC6) - Store(PLC6, \_SB.PT6D) - } - } - } -} - -/* USB Port 7 overcurrent uses Gpm 7 */ -If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { - /* Method (_L1D) { */ - Method (_L07) { - UCOC() - if (LEqual(GPB7,PLC7)) { - Not(PLC7,PLC7) - Store(PLC7, \_SB.PT7D) - } - } - } -} - -/* USB Port 8 overcurrent uses Gpm 8 */ -If (LLessEqual(UOM8,9)) { - Scope (\_GPE) { - Method (_L17) { - if (LEqual(G8IS,PLC8)) { - Not(PLC8,PLC8) - Store(PLC8, \_SB.PT8D) - } - } - } -} - -/* USB Port 9 overcurrent uses Gpm 9 */ -If (LLessEqual(UOM9,9)) { - Scope (\_GPE) { - Method (_L0E) { - if (LEqual(G9IS,0)) { - Store(1,\_SB.PT9D) - } - } - } -} diff --git a/src/mainboard/elmex/pcm205400/acpi_tables.c b/src/mainboard/elmex/pcm205400/acpi_tables.c deleted file mode 100644 index 97ea649..0000000 --- a/src/mainboard/elmex/pcm205400/acpi_tables.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/acpi.h> -#include <arch/ioapic.h> - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); - - /* Write SB800 IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - CONFIG_MAX_CPUS, IO_APIC_ADDR, 0); - - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xF); - - /* 0: mean bus 0--->ISA */ - /* 0: PIC 0 */ - /* 2: APIC 2 */ - /* 5 mean: 0101 --> Edge-triggered, Active high */ - - /* create all subtables for processors */ - /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */ - /* 1: LINT1 connect to NMI */ - - return current; -} diff --git a/src/mainboard/elmex/pcm205400/board_info.txt b/src/mainboard/elmex/pcm205400/board_info.txt deleted file mode 100644 index e73423f..0000000 --- a/src/mainboard/elmex/pcm205400/board_info.txt +++ /dev/null @@ -1,5 +0,0 @@ -Board name: PCM205400 -Category: sbc -ROM protocol: SPI -ROM socketed: n -Flashrom support: y diff --git a/src/mainboard/elmex/pcm205400/buildOpts.c b/src/mainboard/elmex/pcm205400/buildOpts.c deleted file mode 100644 index 863a552..0000000 --- a/src/mainboard/elmex/pcm205400/buildOpts.c +++ /dev/null @@ -1,294 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/** - * @file - * - * AMD User options selection for a Brazos platform solution system - * - * This file is placed in the user's platform directory and contains the - * build option selections desired for that platform. - * - * For Information about this file, see @ref platforminstall. - * - */ - -#include <stdlib.h> - - -/* Select the cpu family. */ -#define INSTALL_FAMILY_10_SUPPORT FALSE -#define INSTALL_FAMILY_12_SUPPORT FALSE -#define INSTALL_FAMILY_14_SUPPORT TRUE -#define INSTALL_FAMILY_15_SUPPORT FALSE - -/* Select the cpu socket type. */ -#define INSTALL_G34_SOCKET_SUPPORT FALSE -#define INSTALL_C32_SOCKET_SUPPORT FALSE -#define INSTALL_S1G3_SOCKET_SUPPORT FALSE -#define INSTALL_S1G4_SOCKET_SUPPORT FALSE -#define INSTALL_ASB2_SOCKET_SUPPORT FALSE -#define INSTALL_FS1_SOCKET_SUPPORT FALSE -#define INSTALL_FM1_SOCKET_SUPPORT FALSE -#define INSTALL_FP1_SOCKET_SUPPORT FALSE -#define INSTALL_FT1_SOCKET_SUPPORT TRUE -#define INSTALL_AM3_SOCKET_SUPPORT FALSE - -/* - * Agesa optional capabilities selection. - * Uncomment and mark FALSE those features you wish to include in the build. - * Comment out or mark TRUE those features you want to REMOVE from the build. - */ - -#define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE -#define BLDOPT_REMOVE_FAMILY_12_SUPPORT TRUE -#define BLDOPT_REMOVE_FAMILY_14_SUPPORT FALSE -#define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE - -#define BLDOPT_REMOVE_AM3_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_C32_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FM1_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FP1_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FS1_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FT1_SOCKET_SUPPORT FALSE -#define BLDOPT_REMOVE_G34_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT TRUE - -#define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE -#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE -#define BLDOPT_REMOVE_ECC_SUPPORT FALSE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE -#define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE -#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE -#define BLDOPT_REMOVE_PARALLEL_TRAINING FALSE -#define BLDOPT_REMOVE_DQS_TRAINING FALSE -#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE -#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_ACPI_PSTATES FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PSD FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE - #define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT FALSE -#define BLDOPT_REMOVE_SRAT FALSE -#define BLDOPT_REMOVE_SLIT FALSE -#define BLDOPT_REMOVE_WHEA FALSE -#define BLDOPT_REMOVE_DMI TRUE -#define BLDOPT_REMOVE_HT_ASSIST TRUE -#define BLDOPT_REMOVE_ATM_MODE TRUE -//#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE -//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE -#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE -//#define BLDOPT_REMOVE_C6_STATE TRUE -#define BLDOPT_REMOVE_GFX_RECOVERY TRUE -#define BLDOPT_REMOVE_EARLY_SAMPLES TRUE - - -#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER - -#define BLDCFG_VRM_CURRENT_LIMIT 24000 -//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 -#define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000 -#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 -#define BLDCFG_VRM_SLEW_RATE 5000 -//#define BLDCFG_VRM_NB_SLEW_RATE 5000 -//#define BLDCFG_VRM_ADDITIONAL_DELAY 0 -//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 -#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE -//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE FALSE -#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 6000 -//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 - -//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C' -//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' -//#define BLDCFG_PROCESSOR_SCOPE_IN_SB FALSE -#define BLDCFG_PLAT_NUM_IO_APICS 3 -//#define BLDCFG_PLATFORM_C1E_MODE C1eModeDisabled -//#define BLDCFG_PLATFORM_C1E_OPDATA 0 -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0 -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0 -#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 -#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 -#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 -//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto -#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST -#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE -//#define BLDCFG_STARTING_BUSNUM 0 -//#define BLDCFG_MAXIMUM_BUSNUM 0xf8 -//#define BLDCFG_ALLOCATED_BUSNUMS 0x20 -//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST 0 -//#define BLDCFG_BUID_SWAP_LIST 0 -//#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST 0 -//#define BLDCFG_HTFABRIC_LIMITS_LIST 0 -//#define BLDCFG_HTCHAIN_LIMITS_LIST 0 -//#define BLDCFG_BUS_NUMBERS_LIST 0 -//#define BLDCFG_IGNORE_LINK_LIST 0 -//#define BLDCFG_LINK_SKIP_REGANG_LIST 0 -//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST 0 -//#define BLDCFG_USE_HT_ASSIST TRUE -//#define BLDCFG_USE_ATM_MODE TRUE -//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm -#define BLDCFG_S3_LATE_RESTORE TRUE -//#define BLDCFG_USE_32_BYTE_REFRESH FALSE -//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE -//#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance -//#define BLDCFG_SET_HTCRC_SYNC_FLOOD FALSE -//#define BLDCFG_USE_UNIT_ID_CLUMPING FALSE -//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP 0 -#define BLDCFG_CFG_GNB_HD_AUDIO FALSE -//#define BLDCFG_CFG_ABM_SUPPORT FALSE -//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE 0 -//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 0 -//#define BLDCFG_MEM_INIT_PSTATE 0 -//#define BLDCFG_AMD_PSTATE_CAP_VALUE 0 -#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY -#define BLDCFG_MEMORY_MODE_UNGANGED TRUE -//#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE -//#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE -#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE -#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE -#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE -#define BLDCFG_MEMORY_POWER_DOWN TRUE -#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT -//#define BLDCFG_ONLINE_SPARE FALSE -//#define BLDCFG_MEMORY_PARITY_ENABLE FALSE -#define BLDCFG_BANK_SWIZZLE TRUE -#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY -#define BLDCFG_DQS_TRAINING_CONTROL TRUE -#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE -#define BLDCFG_USE_BURST_MODE FALSE -#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE -//#define BLDCFG_ENABLE_ECC_FEATURE TRUE -//#define BLDCFG_ECC_REDIRECTION FALSE -//#define BLDCFG_SCRUB_DRAM_RATE 0 -//#define BLDCFG_SCRUB_L2_RATE 0 -//#define BLDCFG_SCRUB_L3_RATE 0 -//#define BLDCFG_SCRUB_IC_RATE 0 -//#define BLDCFG_SCRUB_DC_RATE 0 -//#define BLDCFG_ECC_SYNC_FLOOD 0 -//#define BLDCFG_ECC_SYMBOL_SIZE 0 -//#define BLDCFG_1GB_ALIGN FALSE -#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO -#define BLDCFG_UMA_ALLOCATION_SIZE 0 -#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE -#define BLDCFG_UMA_ALIGNMENT NO_UMA_ALIGNED -#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 -#define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000 - -/* - * Agesa configuration values selection. - * Uncomment and specify the value for the configuration options - * needed by the system. - */ -#include <AGESA.h> - -/* The fixed MTRR values to be set after memory initialization. */ -CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = -{ - { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull }, - { AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull }, - { CPU_LIST_TERMINAL } -}; - -/* Include the files that instantiate the configuration definitions. */ - -#include "cpuRegisters.h" -#include "cpuFamRegisters.h" -#include "cpuFamilyTranslation.h" -#include "AdvancedApi.h" -#include "heapManager.h" -#include "CreateStruct.h" -#include "cpuFeatures.h" -#include "Table.h" -#include "cpuEarlyInit.h" -#include "cpuLateInit.h" -#include "GnbInterface.h" - -/***************************************************************************** - * Define the RELEASE VERSION string - * - * The Release Version string should identify the next planned release. - * When a branch is made in preparation for a release, the release manager - * should change/confirm that the branch version of this file contains the - * string matching the desired version for the release. The trunk version of - * the file should always contain a trailing 'X'. This will make sure that a - * development build from trunk will not be confused for a released version. - * The release manager will need to remove the trailing 'X' and update the - * version string as appropriate for the release. The trunk copy of this file - * should also be updated/incremented for the next expected version, + trailing 'X' - ****************************************************************************/ -// This is the delivery package title, "BrazosPI" -// This string MUST be exactly 8 characters long -#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} - -// This is the release version number of the AGESA component -// This string MUST be exactly 12 characters long -#define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '} - -/* MEMORY_BUS_SPEED */ -#define DDR400_FREQUENCY 200 ///< DDR 400 -#define DDR533_FREQUENCY 266 ///< DDR 533 -#define DDR667_FREQUENCY 333 ///< DDR 667 -#define DDR800_FREQUENCY 400 ///< DDR 800 -#define DDR1066_FREQUENCY 533 ///< DDR 1066 -#define DDR1333_FREQUENCY 667 ///< DDR 1333 -#define DDR1600_FREQUENCY 800 ///< DDR 1600 -#define DDR1866_FREQUENCY 933 ///< DDR 1866 -#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency - -/* QUANDRANK_TYPE*/ -#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM - -/* USER_MEMORY_TIMING_MODE */ -#define TIMING_MODE_AUTO 0 ///< Use best rate possible -#define TIMING_MODE_LIMITED 1 ///< Set user top limit -#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed - -/* POWER_DOWN_MODE */ -#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode - -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. -#define DFLT_SCRUB_DRAM_RATE (0) -#define DFLT_SCRUB_L2_RATE (0) -#define DFLT_SCRUB_L3_RATE (0) -#define DFLT_SCRUB_IC_RATE (0) -#define DFLT_SCRUB_DC_RATE (0) -#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define DFLT_VRM_SLEW_RATE (5000) - -// Instantiate all solution relevant data. -#include <PlatformInstall.h> diff --git a/src/mainboard/elmex/pcm205400/cmos.layout b/src/mainboard/elmex/pcm205400/cmos.layout deleted file mode 100644 index 1144223..0000000 --- a/src/mainboard/elmex/pcm205400/cmos.layout +++ /dev/null @@ -1,68 +0,0 @@ -#***************************************************************************** -# -# This file is part of the coreboot project. -# -# Copyright (C) 2011 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -#***************************************************************************** - -entries - -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 r 0 reboot_bits -#392 3 r 0 unused -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum -# Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - - - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% - -checksums - -checksum 392 983 984 diff --git a/src/mainboard/elmex/pcm205400/devicetree.cb b/src/mainboard/elmex/pcm205400/devicetree.cb deleted file mode 100644 index 902b892..0000000 --- a/src/mainboard/elmex/pcm205400/devicetree.cb +++ /dev/null @@ -1,148 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2011 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -chip northbridge/amd/agesa/family14/root_complex - device cpu_cluster 0 on - chip cpu/amd/agesa/family14 - device lapic 0 on end - end - end - device domain 0 on - subsystemid 0x1022 0x1510 inherit - chip northbridge/amd/agesa/family14 - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456] - device pci 4.0 on end # PCIE P2P bridge on-board NIC - device pci 5.0 off end # PCIE P2P bridge - device pci 6.0 on end # PCIE P2P bridge PCIe slot - device pci 7.0 off end # PCIE P2P bridge - device pci 8.0 off end # NB/SB Link P2P bridge - end # agesa northbridge - - chip southbridge/amd/cimx/sb800 - device pci 11.0 on end # SATA - device pci 12.0 on end # OHCI USB 0-4 - device pci 12.2 on end # EHCI USB 0-4 - device pci 13.0 on end # OHCI USB 5-9 - device pci 13.2 on end # EHCI USB 5-9 - device pci 14.0 on end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 off end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/fintek/f81865f - device pnp 4e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 4e.3 off end # Parallel Port - device pnp 4e.4 off end # Hardware Monitor - device pnp 4e.5 off end # Keyboard - device pnp 4e.6 off end # GPIO - device pnp 4e.a off end # PME - device pnp 4e.10 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 4e.11 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - end # f81865f - end #LPC - device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} - device pci 14.5 off end # OHCI FS/LS USB - device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699) - device pci 15.0 off end # PCIe PortA - device pci 15.1 off end # PCIe PortB - device pci 15.2 off end # PCIe PortC - device pci 15.3 off end # PCIe PortD - device pci 16.0 off end # OHCI USB 10-13 - device pci 16.2 off end # EHCI USB 10-13 - - register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow) - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - - #set up SB800 Fan control registers and IMC fan controls - register "imc_port_address" = "0x6E" # 0x2E and 0x6E are common - register "fan0_enabled" = "1" - register "fan1_enabled" = "1" - register "imc_fan_zone0_enabled" = "1" - register "imc_fan_zone1_enabled" = "1" - - register "fan0_config_vals" = "{ \ - FAN_INPUT_INTERNAL_DIODE, FAN_POLARITY_HIGH, \ - FREQ_25KHZ, 0x08, 0x00, 0x00, 0x00, 0x00,\ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }" - register "fan1_config_vals" = "{ \ - FAN_INPUT_INTERNAL_DIODE, FAN_POLARITY_HIGH, \ - FREQ_25KHZ, 0x10, 0x00, 0x00, 0x00, 0x00, \ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }" - - register "imc_zone0_mode1" = " \ - IMC_MODE1_FAN_ENABLED | IMC_MODE1_FAN_IMC_CONTROLLED | \ - IMC_MODE1_FAN_STEP_MODE | IMC_MODE1_FANOUT0" - register "imc_zone0_mode2" = " IMC_MODE2_TEMPIN_SB_TSI | \ - IMC_MODE2_FANIN0 | IMC_MODE2_TEMP_AVERAGING_DISABLED" - register "imc_zone0_temp_offset" = "0x00" # No temp offset - register "imc_zone0_hysteresis" = "0x05" # Degrees C Hysteresis - register "imc_zone0_smbus_addr" = "0x98" # Temp Sensor SMBus address - register "imc_zone0_smbus_num" = "IMC_TEMP_SENSOR_ON_SMBUS_3" # SMBUS number - register "imc_zone0_pwm_step" = "0x01" # Fan PWM stepping rate - register "imc_zone0_ramping" = "0x00" # Disable Fan PWM ramping and stepping - - register "imc_zone1_mode1" = " \ - IMC_MODE1_FAN_ENABLED | IMC_MODE1_FAN_IMC_CONTROLLED | \ - IMC_MODE1_FAN_STEP_MODE | IMC_MODE1_FANOUT1" - register "imc_zone1_mode2" = " IMC_MODE2_TEMPIN_SB_TSI | \ - IMC_MODE2_FANIN1 | IMC_MODE2_TEMP_AVERAGING_DISABLED" - register "imc_zone1_temp_offset" = "0x00" # No temp offset - register "imc_zone1_hysteresis" = "0x05" # Degrees C Hysteresis - register "imc_zone1_smbus_addr" = "0x98" # Temp Sensor SMBus address - register "imc_zone1_smbus_num" = "IMC_TEMP_SENSOR_ON_SMBUS_3" # SMBUS number - register "imc_zone1_pwm_step" = "0x01" # Fan PWM stepping rate - register "imc_zone1_ramping" = "0x00" # Disable Fan PWM ramping and stepping - - # T56N has a Maximum operating temperature of 90C - # ZONEX_THRESHOLDS - _AC0 - _AC7, _CRT - Temp Threshold in degrees C - # ZONEX_FANSPEEDS - Fan speeds as a "percentage" - register "imc_zone0_thresholds" = "{ 87, 82, 77, 72, 65, 1, 0, 0, 90 }" - register "imc_zone0_fanspeeds" = "{100, 7, 5, 4, 3, 2, 0, 0 }" - register "imc_zone1_thresholds" = "{ 85, 80, 75, 65, 1, 0, 0, 0, 90 }" - register "imc_zone1_fanspeeds" = "{100, 10, 6, 4, 3, 0, 0, 0 }" - - end #southbridge/amd/cimx/sb800 - - chip northbridge/amd/agesa/family14 - - # These seem unnecessary - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - device pci 18.6 on end - device pci 18.7 on end - - register "spdAddrLookup" = " - { - { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses - { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses - }" - - end # agesa northbridge - - end #domain -end #northbridge/amd/agesa/family14/root_complex diff --git a/src/mainboard/elmex/pcm205400/dsdt.asl b/src/mainboard/elmex/pcm205400/dsdt.asl deleted file mode 100644 index 5496288..0000000 --- a/src/mainboard/elmex/pcm205400/dsdt.asl +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* DefinitionBlock Statement */ -#include <arch/acpi.h> -DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - OEM_ID, - ACPI_TABLE_CREATOR, - 0x00010001 /* OEM Revision */ - ) -{ /* Start of ASL file */ - /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ - - #include "acpi/mainboard.asl" - - #include <cpu/amd/agesa/family14/acpi/cpu.asl> - - #include "acpi/routing.asl" - - Scope(\_SB) { - /* global utility methods expected within the \_SB scope */ - #include <arch/x86/acpi/globutil.asl> - - Device(PCI0) { - - /* Describe the AMD Northbridge */ - #include <northbridge/amd/agesa/family14/acpi/northbridge.asl> - - /* Describe the AMD Fusion Controller Hub Southbridge */ - #include <southbridge/amd/cimx/sb800/acpi/fch.asl> - - /* Primary (and only) IDE channel */ - Device(IDEC) { - Name(_ADR, 0x00140001) - #include "acpi/ide.asl" - } /* end IDEC */ - - } - } /* End Scope(_SB) */ - - /* Contains the supported sleep states for this chipset */ - #include <southbridge/amd/common/acpi/sleepstates.asl> - - /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */ - #include "acpi/sleep.asl" - - #include "acpi/gpe.asl" -} -/* End of ASL file */ diff --git a/src/mainboard/elmex/pcm205400/irq_tables.c b/src/mainboard/elmex/pcm205400/irq_tables.c deleted file mode 100644 index 804f52d..0000000 --- a/src/mainboard/elmex/pcm205400/irq_tables.c +++ /dev/null @@ -1,109 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -#include <console/console.h> -#include <string.h> -#include <stdint.h> -#include <arch/pirq_routing.h> - - -static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, - u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, - u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, - u8 slot, u8 rfu) -{ - pirq_info->bus = bus; - pirq_info->devfn = devfn; - pirq_info->irq[0].link = link0; - pirq_info->irq[0].bitmap = bitmap0; - pirq_info->irq[1].link = link1; - pirq_info->irq[1].bitmap = bitmap1; - pirq_info->irq[2].link = link2; - pirq_info->irq[2].bitmap = bitmap2; - pirq_info->irq[3].link = link3; - pirq_info->irq[3].bitmap = bitmap3; - pirq_info->slot = slot; - pirq_info->rfu = rfu; -} - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - - struct irq_routing_table *pirq; - struct irq_info *pirq_info; - u32 slot_num; - u8 *v; - - u8 sum = 0; - int i; - - /* Align the table to be 16 byte aligned. */ - addr += 15; - addr &= ~15; - - /* This table must be between 0xf0000 & 0x100000 */ - printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); - - pirq = (void *)(addr); - v = (u8 *) (addr); - - pirq->signature = PIRQ_SIGNATURE; - pirq->version = PIRQ_VERSION; - - pirq->rtr_bus = 0; - pirq->rtr_devfn = PCI_DEVFN(0x14, 4); - - pirq->exclusive_irqs = 0; - - pirq->rtr_vendor = 0x1002; - pirq->rtr_device = 0x4384; - - pirq->miniport_data = 0; - - memset(pirq->rfu, 0, sizeof(pirq->rfu)); - - pirq_info = (void *)(&pirq->checksum + 1); - slot_num = 0; - - - /* pci bridge */ - write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), - 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, - 0); - pirq_info++; - - - - slot_num++; - - - - pirq->size = 32 + 16 * slot_num; - - for (i = 0; i < pirq->size; i++) - sum += v[i]; - - sum = pirq->checksum - sum; - - if (sum != pirq->checksum) { - pirq->checksum = sum; - } - - printk(BIOS_INFO, "write_pirq_routing_table done.\n"); - - return (unsigned long)pirq_info; - -} diff --git a/src/mainboard/elmex/pcm205400/mainboard.c b/src/mainboard/elmex/pcm205400/mainboard.c deleted file mode 100644 index 0e89ffd..0000000 --- a/src/mainboard/elmex/pcm205400/mainboard.c +++ /dev/null @@ -1,151 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <amdblocks/acpimmio.h> -#include <console/console.h> -#include <device/device.h> -#include <device/mmio.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> -#include <southbridge/amd/cimx/sb800/pci_devs.h> -#include <northbridge/amd/agesa/family14/pci_devs.h> - -/*********************************************************** - * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. - * This table is responsible for physically routing the PIC and - * IOAPIC IRQs to the different PCI devices on the system. It - * is read and written via registers 0xC00/0xC01 as an - * Index/Data pair. These values are chipset and mainboard - * dependent and should be updated accordingly. - * - * These values are used by the PCI configuration space, - * MP Tables. TODO: Make ACPI use these values too. - * - * The Persimmon PCI INTA/B/C/D pins are connected to - * FCH pins INTE/F/G/H on the schematic so these need - * to be routed as well. - */ -static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = { - /* INTA# - INTH# */ - [0x00] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B, - /* Misc-nil,0,1,2, INT from Serial irq */ - [0x08] = 0x00,0xF0,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerfMon */ - [0x10] = 0x1F,0x1F,0x1F,0x0A,0x1F,0x1F,0x1F, - /* IMC INT0 - 5 */ - [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, - /* USB Devs 18/19/20/22 INTA-C */ - [0x30] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A, - /* IDE, SATA */ - [0x40] = 0x0B,0x0B, - /* GPPInt0 - 3 */ - [0x50] = 0x0A,0x0B,0x0A,0x0B -}; - -static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = { - /* INTA# - INTH# */ - [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, - /* Misc-nil,0,1,2, INT from Serial irq */ - [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon */ - [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F, - /* IMC INT0 - 5 */ - [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, - /* USB Devs 18/19/22/20 INTA-C */ - [0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12, - /* IDE, SATA */ - [0x40] = 0x11,0x13, - /* GPPInt0 - 3 */ - [0x50] = 0x10,0x11,0x12,0x13 -}; - -/* - * This table defines the index into the picr/intr_data - * tables for each device. Any enabled device and slot - * that uses hardware interrupts should have an entry - * in this table to define its index into the FCH - * PCI_INTR register 0xC00/0xC01. This index will define - * the interrupt that it should use. Putting PIRQ_A into - * the PIN A index for a device will tell that device to - * use PIC IRQ 10 if it uses PIN A for its hardware INT. - */ -/* - * Persimmon has PCI slot INTA/B/C/D connected to PIRQE/F/G/H - * but because PCI INT_PIN swizzling isn't implemented to match - * the IDSEL (dev 3) of the slot, the table is adjusted for the - * swizzle and INTA is connected to PIRQH so PINA/B/C/D on - * off-chip devices should get mapped to PIRQH/E/F/G. - */ -static const struct pirq_struct mainboard_pirq_data[] = { - /* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D}}, */ - {GFX_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_NC, PIRQ_NC}}, /* VGA: 01.0 */ - {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* NIC: 04.0 */ - {NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* PCIe bdg: 06.0 */ - {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SATA: 11.0 */ - {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1: 12.0 */ - {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1: 12.2 */ - {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2: 13.0 */ - {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2: 13.2 */ - {SMBUS_DEVFN, {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SMBUS: 14.0 */ - {IDE_DEVFN, {PIRQ_NC, PIRQ_IDE, PIRQ_NC, PIRQ_NC}}, /* IDE: 14.1 */ - {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* HDA: 14.2 */ - {SB_PCI_PORT_DEVFN, {PIRQ_H, PIRQ_E, PIRQ_F, PIRQ_G}}, /* PCI bdg: 14.4 */ - {OHCI4_DEVFN, {PIRQ_NC, PIRQ_NC, PIRQ_OHCI4, PIRQ_NC}}, /* OHCI4: 14.5 */ - {OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI3: 16.0 */ - {EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}}, /* EHCI3: 16.2 */ -}; - -/* PIRQ Setup */ -static void pirq_setup(void) -{ - pirq_data_ptr = mainboard_pirq_data; - pirq_data_size = sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct); - intr_data_ptr = mainboard_intr_data; - picr_data_ptr = mainboard_picr_data; -} - -/********************************************** - * Enable the dedicated functions of the board. - **********************************************/ -static void mainboard_enable(struct device *dev) -{ - printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - - /* enable GPP CLK0 thru CLK1 */ - /* disable GPP CLK2 thru SLT_GFX_CLK */ - u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE); - write8(misc_mem_clk_cntrl + 0, 0xFF); - write8(misc_mem_clk_cntrl + 1, 0x00); - write8(misc_mem_clk_cntrl + 2, 0x00); - write8(misc_mem_clk_cntrl + 3, 0x00); - write8(misc_mem_clk_cntrl + 4, 0x00); - - /* - * Initialize ASF registers to an arbitrary address because someone - * long ago set things up this way inside the SPD read code. The - * SPD read code has been made generic and moved out of the board - * directory, so the ASF init is being done here. - */ - pm_write8(0x29, 0x80); - pm_write8(0x28, 0x61); - - /* Initialize the PIRQ data structures for consumption */ - pirq_setup(); -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/elmex/pcm205400/mptable.c b/src/mainboard/elmex/pcm205400/mptable.c deleted file mode 100644 index bc7a3ac..0000000 --- a/src/mainboard/elmex/pcm205400/mptable.c +++ /dev/null @@ -1,142 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/smp/mpspec.h> -#include <stdint.h> -#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <drivers/generic/ioapic/chip.h> -#include <arch/ioapic.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - /* Initialize the MP_Table */ - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - /* - * Type 0: Processor Entries: - * LAPIC ID, LAPIC Version, CPU Flags:EN/BP, - * CPU Signature (Stepping, Model, Family), - * Feature Flags - */ - smp_write_processors(mc); - - /* - * Type 1: Bus Entries: - * Bus ID, Bus Type - */ - mptable_write_buses(mc, NULL, &bus_isa); - - /* - * Type 2: I/O APICs: - * APIC ID, Version, APIC Flags:EN, Address - */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* - * Type 3: I/O Interrupt Table Entries: - * Int Type, Int Polarity, Int Level, Source Bus ID, - * Source Bus IRQ, Dest APIC ID, Dest PIN# - */ - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) - - /* APU Internal Graphic Device */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]); - - /* SMBUS / ACPI */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]); - - /* Southbridge HD Audio */ - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]); - - /* LPC */ - PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]); - PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]); - PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]); - PCI_INT(0x0, 0x14, 0x5, intr_data_ptr[PIRQ_OHCI4]); - - /* IDE */ - PCI_INT(0x0, 0x14, 0x1, intr_data_ptr[PIRQ_IDE]); - - /* SATA */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]); - - /* on board NIC & Slot PCIE */ - PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ - PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0 */ - PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */ - PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */ - PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */ - PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */ - } - - /* PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */ - /* PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */ - /* PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */ - /* PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */ - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */ - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/elmex/pcm205400/platform_cfg.h b/src/mainboard/elmex/pcm205400/platform_cfg.h deleted file mode 100644 index 593ccc7..0000000 --- a/src/mainboard/elmex/pcm205400/platform_cfg.h +++ /dev/null @@ -1,252 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -#ifndef _PLATFORM_CFG_H_ -#define _PLATFORM_CFG_H_ - -/** - * @def BIOS_SIZE - * BIOS_SIZE_{1,2,4,8,16}M - * - * In SB800, default ROM size is 1M Bytes, if your platform ROM - * bigger than 1M you have to set the ROM size outside CIMx module and - * before AGESA module get call. - */ -#ifndef BIOS_SIZE -#define BIOS_SIZE ((CONFIG_COREBOOT_ROMSIZE_KB >> 10) - 1) -#endif /* BIOS_SIZE */ - -/** - * @def SPREAD_SPECTRUM - * @brief - * 0 - Disable Spread Spectrum function - * 1 - Enable Spread Spectrum function - */ -#define SPREAD_SPECTRUM 0 - -/** - * @def SB_HPET_TIMER - * @brief - * 0 - Disable hpet - * 1 - Enable hpet - */ -#define HPET_TIMER 1 - -/** - * @def USB_CONFIG - * @brief bit[0-6] used to control USB - * 0 - Disable - * 1 - Enable - * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is define at BIT0 - * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is define at BIT1 - * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is define at BIT2 - * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is define at BIT3 - * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is define at BIT4 - * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is define at BIT5 - * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is define at BIT6 - */ -#define USB_CONFIG 0x7F - -/** - * @def PCI_CLOCK_CTRL - * @brief bit[0-4] used for PCI Slots Clock Control, - * 0 - disable - * 1 - enable - * PCI SLOT 0 define at BIT0 - * PCI SLOT 1 define at BIT1 - * PCI SLOT 2 define at BIT2 - * PCI SLOT 3 define at BIT3 - * PCI SLOT 4 define at BIT4 - */ -#define PCI_CLOCK_CTRL 0x07 - -/** - * @def SATA_CONTROLLER - * @brief INCHIP Sata Controller - */ -#define SATA_CONTROLLER CIMX_OPTION_ENABLED - -/** - * @def SATA_MODE - * @brief INCHIP Sata Controller Mode - * NOTE: DO NOT ALLOW SATA & IDE use same mode - */ -#define SATA_MODE CONFIG_SB800_SATA_MODE - -/** - * @brief INCHIP Sata IDE Controller Mode - */ -#define IDE_LEGACY_MODE 0 -#define IDE_NATIVE_MODE 1 - -/** - * @def SATA_IDE_MODE - * @brief INCHIP Sata IDE Controller Mode - * NOTE: DO NOT ALLOW SATA & IDE use same mode - */ -#define SATA_IDE_MODE IDE_LEGACY_MODE - -/** - * @def EXTERNAL_CLOCK - * @brief 00/10: Reference clock from crystal oscillator via - * PAD_XTALI and PAD_XTALO - * - * @def INTERNAL_CLOCK - * @brief 01/11: Reference clock from internal clock through - * CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL - */ -#define EXTERNAL_CLOCK 0x00 -#define INTERNAL_CLOCK 0x01 - -/* NOTE: inagua have to using internal clock, - * otherwise can not detect sata drive - */ -#define SATA_CLOCK_SOURCE INTERNAL_CLOCK - -/** - * @def SATA_PORT_MULT_CAP_RESERVED - * @brief 1 ON, 0 0FF - */ -#define SATA_PORT_MULT_CAP_RESERVED 1 - - -/** - * @def AZALIA_AUTO - * @brief Detect Azalia controller automatically. - * - * @def AZALIA_DISABLE - * @brief Disable Azalia controller. - - * @def AZALIA_ENABLE - * @brief Enable Azalia controller. - */ -#define AZALIA_AUTO 0 -#define AZALIA_DISABLE 1 -#define AZALIA_ENABLE 2 - -/** - * @brief INCHIP HDA controller - */ -#define AZALIA_CONTROLLER AZALIA_AUTO - -/** - * @def AZALIA_PIN_CONFIG - * @brief - * 0 - disable - * 1 - enable - */ -#define AZALIA_PIN_CONFIG 1 - -/** - * @def AZALIA_SDIN_PIN - * @brief - * SDIN0 is define at BIT0 & BIT1 - * 00 - GPIO PIN - * 01 - Reserved - * 10 - As a Azalia SDIN pin - * SDIN1 is define at BIT2 & BIT3 - * SDIN2 is define at BIT4 & BIT5 - * SDIN3 is define at BIT6 & BIT7 - */ -//#define AZALIA_SDIN_PIN 0xAA -#define AZALIA_SDIN_PIN 0x2A - -/** - * @def GPP_CONTROLLER - */ -#define GPP_CONTROLLER CIMX_OPTION_ENABLED - -/** - * @def GPP_CFGMODE - * @brief GPP Link Configuration - * four possible configuration: - * GPP_CFGMODE_X4000 - * GPP_CFGMODE_X2200 - * GPP_CFGMODE_X2110 - * GPP_CFGMODE_X1111 - */ -#define GPP_CFGMODE GPP_CFGMODE_X1111 - -/** - * @def NB_SB_GEN2 - * 0 - Disable - * 1 - Enable - */ -#define NB_SB_GEN2 TRUE - -/** - * @def SB_GPP_GEN2 - * 0 - Disable - * 1 - Enable - */ -#define SB_GPP_GEN2 TRUE - -/** - * @def SB_GPP_UNHIDE_PORTS - * TRUE - ports visible always, even port empty - * FALSE - ports invisible if port empty - */ -#define SB_GPP_UNHIDE_PORTS FALSE - -/** - * @def GEC_CONFIG - * 0 - Enable - * 1 - Disable - */ -#define GEC_CONFIG 0 - -static const CODECENTRY persimmon_codec_alc269[] = { - /* NID, PinConfig */ - {0x12, 0x411111F0}, - {0x14, 0x99130110}, - {0x21, 0x0121401F}, - {0x17, 0x411111F0}, - {0x18, 0x01A19820}, - {0x19, 0x411111F0}, - {0x1A, 0x0181302F}, - {0x1B, 0x411111F0}, - {0x1D, 0x40069E05}, - {0x1E, 0x411111F0}, - {0x20, 0x0001FFFF}, - {0xff, 0xffffffff} /* end of table */ -}; - -static const CODECTBLLIST codec_tablelist[] = { - {0x010ec0269, (CODECENTRY *)&persimmon_codec_alc269[0]}, - {0x0FFFFFFFFUL, (CODECENTRY *)0x0FFFFFFFFUL} -}; - -/** - * @def AZALIA_OEM_VERB_TABLE - * Mainboard specific codec verb table list - */ -//#define AZALIA_OEM_VERB_TABLE (&codec_tablelist[0]) - -/* set up an ACPI preferred power management profile */ -/* from acpi.h - * PM_UNSPECIFIED = 0, - * PM_DESKTOP = 1, - * PM_MOBILE = 2, - * PM_WORKSTATION = 3, - * PM_ENTERPRISE_SERVER = 4, - * PM_SOHO_SERVER = 5, - * PM_APPLIANCE_PC = 6, - * PM_PERFORMANCE_SERVER = 7, - * PM_TABLET = 8 - */ -#define FADT_PM_PROFILE 1 - -#endif /* _PLATFORM_CFG_H_ */ diff --git a/src/mainboard/elmex/pcm205400/romstage.c b/src/mainboard/elmex/pcm205400/romstage.c deleted file mode 100644 index 7ccf167..0000000 --- a/src/mainboard/elmex/pcm205400/romstage.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <northbridge/amd/agesa/state_machine.h> -#include <superio/fintek/common/fintek.h> -#include <superio/fintek/f81865f/f81865f.h> -#include <sb_cimx.h> - -#define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) - -void board_BeforeAgesa(struct sysinfo *cb) -{ - sb_Poweron_Init(); - fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/38108 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I75f4ae75a42656891447eec5d7055945016d9e90 Gerrit-Change-Number: 38108 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/biostar/a68n_5200: Drop boards with ROMCC_BOOTBLOCK
by HAOUAS Elyes (Code Review) Jan. 7, 2020

Jan. 7, 2020

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38109 ) Change subject: mb/biostar/a68n_5200: Drop boards with ROMCC_BOOTBLOCK ...................................................................... mb/biostar/a68n_5200: Drop boards with ROMCC_BOOTBLOCK ROMCC_BOOTBLOCK is no more. Drop unsupported, unmaintained boards. Change-Id: I77f1975910969ecaa1c37b2c4f0bf6c4745988f6 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- D src/mainboard/biostar/a68n_5200/BiosCallOuts.c D src/mainboard/biostar/a68n_5200/Kconfig D src/mainboard/biostar/a68n_5200/Kconfig.name D src/mainboard/biostar/a68n_5200/Makefile.inc D src/mainboard/biostar/a68n_5200/OemCustomize.c D src/mainboard/biostar/a68n_5200/OptionsIds.h D src/mainboard/biostar/a68n_5200/acpi/AmdImc.asl D src/mainboard/biostar/a68n_5200/acpi/gpe.asl D src/mainboard/biostar/a68n_5200/acpi/ide.asl D src/mainboard/biostar/a68n_5200/acpi/mainboard.asl D src/mainboard/biostar/a68n_5200/acpi/routing.asl D src/mainboard/biostar/a68n_5200/acpi/sata.asl D src/mainboard/biostar/a68n_5200/acpi/si.asl D src/mainboard/biostar/a68n_5200/acpi/sleep.asl D src/mainboard/biostar/a68n_5200/acpi/superio.asl D src/mainboard/biostar/a68n_5200/acpi/thermal.asl D src/mainboard/biostar/a68n_5200/acpi/usb_oc.asl D src/mainboard/biostar/a68n_5200/acpi_tables.c D src/mainboard/biostar/a68n_5200/board_info.txt D src/mainboard/biostar/a68n_5200/buildOpts.c D src/mainboard/biostar/a68n_5200/cmos.layout D src/mainboard/biostar/a68n_5200/devicetree.cb D src/mainboard/biostar/a68n_5200/dsdt.asl D src/mainboard/biostar/a68n_5200/irq_tables.c D src/mainboard/biostar/a68n_5200/mainboard.c D src/mainboard/biostar/a68n_5200/mptable.c D src/mainboard/biostar/a68n_5200/romstage.c 27 files changed, 0 insertions(+), 2,576 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/38109/1 diff --git a/src/mainboard/biostar/a68n_5200/BiosCallOuts.c b/src/mainboard/biostar/a68n_5200/BiosCallOuts.c deleted file mode 100644 index 8f55fb6..0000000 --- a/src/mainboard/biostar/a68n_5200/BiosCallOuts.c +++ /dev/null @@ -1,184 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <AGESA.h> -#include <northbridge/amd/agesa/BiosCallOuts.h> -#include <northbridge/amd/agesa/state_machine.h> -#include <FchPlatform.h> -#include <stdlib.h> - -#include "imc.h" - -const BIOS_CALLOUT_STRUCT BiosCallouts[] = -{ - {AGESA_DO_RESET, agesa_Reset }, - {AGESA_READ_SPD, agesa_ReadSpd }, - {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, - {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, - {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData }, - {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, - {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, - {AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage } -}; -const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); - -/** - * AMD Olivehill Platform ALC272 Verb Table - */ -static const CODEC_ENTRY Olivehill_Alc272_VerbTbl[] = { - {0x11, 0x411111F0}, // - SPDIF_OUT2 - {0x12, 0x411111F0}, // - DMIC_1/2 - {0x13, 0x411111F0}, // - DMIC_3/4 - {0x14, 0x411111F0}, // Port D - LOUT1 - {0x15, 0x411111F0}, // Port A - LOUT2 - {0x16, 0x411111F0}, // - {0x17, 0x411111F0}, // Port H - MONO - {0x18, 0x01a19840}, // Port B - MIC1 - {0x19, 0x411111F0}, // Port F - MIC2 - {0x1a, 0x01813030}, // Port C - LINE1 - {0x1b, 0x411111F0}, // Port E - LINE2 - {0x1d, 0x40130605}, // - PCBEEP - {0x1e, 0x01441120}, // - SPDIF_OUT1 - {0x21, 0x01214010}, // Port I - HPOUT - {0xff, 0xffffffff} -}; - -static const CODEC_TBL_LIST OlivehillCodecTableList[] = -{ - {0x10ec0272, (CODEC_ENTRY*)&Olivehill_Alc272_VerbTbl[0]}, - {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL} -}; - -#define FAN_INPUT_INTERNAL_DIODE 0 -#define FAN_INPUT_TEMP0 1 -#define FAN_INPUT_TEMP1 2 -#define FAN_INPUT_TEMP2 3 -#define FAN_INPUT_TEMP3 4 -#define FAN_INPUT_TEMP0_FILTER 5 -#define FAN_INPUT_ZERO 6 -#define FAN_INPUT_DISABLED 7 - -#define FAN_AUTOMODE (1 << 0) -#define FAN_LINEARMODE (1 << 1) -#define FAN_STEPMODE ~(1 << 1) -#define FAN_POLARITY_HIGH (1 << 2) -#define FAN_POLARITY_LOW ~(1 << 2) - -/* Normally, 4-wire fan runs at 25KHz and 3-wire fan runs at 100Hz */ -#define FREQ_28KHZ 0x0 -#define FREQ_25KHZ 0x1 -#define FREQ_23KHZ 0x2 -#define FREQ_21KHZ 0x3 -#define FREQ_29KHZ 0x4 -#define FREQ_18KHZ 0x5 -#define FREQ_100HZ 0xF7 -#define FREQ_87HZ 0xF8 -#define FREQ_58HZ 0xF9 -#define FREQ_44HZ 0xFA -#define FREQ_35HZ 0xFB -#define FREQ_29HZ 0xFC -#define FREQ_22HZ 0xFD -#define FREQ_14HZ 0xFE -#define FREQ_11HZ 0xFF - -/* Olivehill Hardware Monitor Fan Control - * Hardware limitation: - * HWM failed to read the input temperture vi I2C, - * if other software switch the I2C switch by mistake or intention. - * We recommend to using IMC to control Fans, instead of HWM. - */ -static void oem_fan_control(FCH_DATA_BLOCK *FchParams) -{ - /* Enable IMC fan control. the recommand way */ - if (CONFIG(HUDSON_IMC_FWM)) { - imc_reg_init(); - - /* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */ - FchParams->Hwm.HwMonitorEnable = TRUE; - FchParams->Hwm.HwmFchtsiAutoPoll = FALSE;/* 0 disable, 1 enable TSI Auto Polling */ - - FchParams->Imc.ImcEnable = TRUE; - FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */ - FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ - - LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader); - - /* Thermal Zone Parameter */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; //BIT0 | BIT2 | BIT5; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x4e;//6 | BIT3; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x04; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x9a; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg7 = 0x01; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg8 = 0x01; /* PWM steping rate in unit of PWM level percentage */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg9 = 0x00; - - /* IMC Fan Policy temperature thresholds */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x46;///80; /*AC0 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0x3c; /*AC1 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0x32; /*AC2 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff; /*AC3 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0xff; /*AC4 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0xff; /*AC5 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0xff; /*AC6 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0xff; /*AC7 lowest threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegA = 0x4b; /*critical threshold* in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegB = 0x00; - - /* IMC Fan Policy PWM Settings */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg2 = 0x5a; /* AL0 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg3 = 0x46; /* AL1 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg4 = 0x28; /* AL2 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg5 = 0xff; /* AL3 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg6 = 0xff; /* AL4 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg7 = 0xff; /* AL5 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0xff; /* AL6 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0xff; /* AL7 percentage */ - - FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x111;//BIT0 | BIT4 |BIT8; - - /* NOTE: - * FchInitLateHwm will overwrite the EcStruct with EcDefaultMassege, - * AGESA put EcDefaultMassege as global data in ROM, so we can't overwride it. - * so we remove it from AGESA code. Please Seee FchInitLateHwm. - */ - } else { - /* HWM fan control, the way not recommand */ - FchParams->Imc.ImcEnable = FALSE; - FchParams->Hwm.HwMonitorEnable = TRUE; - FchParams->Hwm.HwmFchtsiAutoPoll = TRUE;/* 1 enable, 0 disable TSI Auto Polling */ - } -} - -void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset) -{ - FchParams_reset->Mode = FCH_SPI_MODE_NORMAL; - FchParams_reset->QeEnabled = FALSE; -} - -void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env) -{ - /* Azalia Controller OEM Codec Table Pointer */ - FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&OlivehillCodecTableList[0]); - - /* Fan Control */ - oem_fan_control(FchParams_env); -} diff --git a/src/mainboard/biostar/a68n_5200/Kconfig b/src/mainboard/biostar/a68n_5200/Kconfig deleted file mode 100644 index f608513..0000000 --- a/src/mainboard/biostar/a68n_5200/Kconfig +++ /dev/null @@ -1,65 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2012 Advanced Micro Devices, Inc. -# Copyright (C) 2016 Edward O'Callaghan <funfunctor(a)folklore1984.net> -# Copyright (C) 2017 Damien Zammit <damien(a)zamaudio.com> -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -config BOARD_BIOSTAR_A68N5200 - def_bool n - -if BOARD_BIOSTAR_A68N5200 - -config BOARD_SPECIFIC_OPTIONS - def_bool y - #select ROMCC_BOOTBLOCK - select CPU_AMD_AGESA_FAMILY16_KB - select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB - select SOUTHBRIDGE_AMD_AGESA_YANGTZE - select SUPERIO_ITE_IT8728F - select HAVE_OPTION_TABLE - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select HAVE_ACPI_TABLES - select BOARD_ROMSIZE_KB_4096 - select GFXUMA - -config MAINBOARD_DIR - string - default "biostar/a68n_5200" - -config MAINBOARD_PART_NUMBER - string - default "A68N5200" - -config HW_MEM_HOLE_SIZEK - hex - default 0x200000 - -config MAX_CPUS - int - default 4 - -config IRQ_SLOT_COUNT - int - default 11 - -config ONBOARD_VGA_IS_PRIMARY - bool - default y - -config HUDSON_LEGACY_FREE - bool - default n - -endif # BOARD_BIOSTAR_A68N5200 diff --git a/src/mainboard/biostar/a68n_5200/Kconfig.name b/src/mainboard/biostar/a68n_5200/Kconfig.name deleted file mode 100644 index 6d765d2..0000000 --- a/src/mainboard/biostar/a68n_5200/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -#config BOARD_BIOSTAR_A68N5200 -# bool"A68N-5200" diff --git a/src/mainboard/biostar/a68n_5200/Makefile.inc b/src/mainboard/biostar/a68n_5200/Makefile.inc deleted file mode 100644 index f8895fa..0000000 --- a/src/mainboard/biostar/a68n_5200/Makefile.inc +++ /dev/null @@ -1,22 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2012 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -romstage-y += buildOpts.c -romstage-y += BiosCallOuts.c -romstage-y += OemCustomize.c - -ramstage-y += buildOpts.c -ramstage-y += BiosCallOuts.c -ramstage-y += OemCustomize.c diff --git a/src/mainboard/biostar/a68n_5200/OemCustomize.c b/src/mainboard/biostar/a68n_5200/OemCustomize.c deleted file mode 100644 index df13fa5..0000000 --- a/src/mainboard/biostar/a68n_5200/OemCustomize.c +++ /dev/null @@ -1,152 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <AGESA.h> -#include <PlatformMemoryConfiguration.h> - -#include <northbridge/amd/agesa/state_machine.h> - -static const PCIe_PORT_DESCRIPTOR PortList[] = { - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 3, 3), - PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 5, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 0x01, 0) - }, - /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 2), - PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 4, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 0x02, 0) - }, - /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 1, 1), - PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 3, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 0x03, 0) - }, - /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 0), - PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 2, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 0x04, 0) - }, - /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */ - { - DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7), - PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 1, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 0x05, 0) - } -}; - -static const PCIe_DDI_DESCRIPTOR DdiList[] = { - /* DP0 to HDMI0/DP */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1) - }, - /* DP1 to FCH */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2) - }, - /* DP2 to HDMI1/DP */ - { - DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 16, 19), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeCrt, Aux3, Hdp3) - }, -}; - -static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { - .Flags = DESCRIPTOR_TERMINATE_LIST, - .SocketId = 0, - .PciePortList = PortList, - .DdiLinkList = DdiList -}; - -void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) -{ - FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface; - FchReset->Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); - FchReset->Xhci1Enable = FALSE; -} - -void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) -{ - InitEarly->GnbConfig.PcieComplexList = &PcieComplex; -} - -/*---------------------------------------------------------------------------------------- - * CUSTOMER OVERIDES MEMORY TABLE - *---------------------------------------------------------------------------------------- - */ - -/* - * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA - * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable - * is populated, AGESA will base its settings on the data from the table. Otherwise, it will - * use its default conservative settings. - */ -static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { - #define SEED_A 0x12 - HW_RXEN_SEED( - ANY_SOCKET, CHANNEL_A, ALL_DIMMS, - SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, - SEED_A), - - NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2), - NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1), - MOTHER_BOARD_LAYERS(LAYERS_4), - - MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00), - CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */ - ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), - CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00), - - PSO_END -}; - -void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) -{ - InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; -} - -void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) -{ - /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ - InitMid->GnbMidConfiguration.iGpuVgaMode = 0; -} diff --git a/src/mainboard/biostar/a68n_5200/OptionsIds.h b/src/mainboard/biostar/a68n_5200/OptionsIds.h deleted file mode 100644 index eaf2442..0000000 --- a/src/mainboard/biostar/a68n_5200/OptionsIds.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDS_DEBUG_PORT - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_CONTROL_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE -#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE -//#define IDSOPT_PERF_ANALYSIS TRUE -#define IDSOPT_ASSERT_ENABLED TRUE -//#undef IDSOPT_DEBUG_ENABLED -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - -#endif diff --git a/src/mainboard/biostar/a68n_5200/acpi/AmdImc.asl b/src/mainboard/biostar/a68n_5200/acpi/AmdImc.asl deleted file mode 100644 index aa941ba..0000000 --- a/src/mainboard/biostar/a68n_5200/acpi/AmdImc.asl +++ /dev/null @@ -1,110 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -//BTDC Due to IMC Fan, ACPI control codes -OperationRegion(IMIO, SystemIO, 0x3E, 0x02) -Field(IMIO , ByteAcc, NoLock, Preserve) { - IMCX,8, - IMCA,8 -} - -IndexField(IMCX, IMCA, ByteAcc, NoLock, Preserve) { - Offset(0x80), - MSTI, 8, - MITS, 8, - MRG0, 8, - MRG1, 8, - MRG2, 8, - MRG3, 8, -} - -Method(WACK, 0) -{ - Store(0, Local0) - While (LNotEqual(Local0, 0xFA)) { - Store(MRG0, Local0) - Sleep(10) - } -} - -//Init -Method (ITZE, 0) -{ - Store(0, MRG0) - Store(0xB5, MRG1) - Store(0, MRG2) - Store(0x96, MSTI) - WACK() - - Store(0, MRG0) - Store(0, MRG1) - Store(0, MRG2) - Store(0x80, MSTI) - WACK() - - Or(MRG2, 0x01, Local0) - - Store(0, MRG0) - Store(0, MRG1) - Store(Local0, MRG2) - Store(0x81, MSTI) - WACK() -} - -//Sleep -Method (IMSP, 0) -{ - Store(0, MRG0) - Store(0xB5, MRG1) - Store(0, MRG2) - Store(0x96, MSTI) - WACK() - - Store(0, MRG0) - Store(1, MRG1) - Store(0, MRG2) - Store(0x98, MSTI) - WACK() - - Store(0, MRG0) - Store(0xB4, MRG1) - Store(0, MRG2) - Store(0x96, MSTI) - WACK() -} - -//Wake -Method (IMWK, 0) -{ - Store(0, MRG0) - Store(0xB5, MRG1) - Store(0, MRG2) - Store(0x96, MSTI) - WACK() - - Store(0, MRG0) - Store(0, MRG1) - Store(0, MRG2) - Store(0x80, MSTI) - WACK() - - Or(MRG2, 0x01, Local0) - - Store(0, MRG0) - Store(0, MRG1) - Store(Local0, MRG2) - Store(0x81, MSTI) - WACK() -} diff --git a/src/mainboard/biostar/a68n_5200/acpi/gpe.asl b/src/mainboard/biostar/a68n_5200/acpi/gpe.asl deleted file mode 100644 index 87b0d21..0000000 --- a/src/mainboard/biostar/a68n_5200/acpi/gpe.asl +++ /dev/null @@ -1,74 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Scope(\_GPE) { /* Start Scope GPE */ - - /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* Legacy PM event */ - Method(_L08) { - /* DBGO("\\_GPE\\_L08\n") */ - } - - /* Temp warning (TWarn) event */ - Method(_L09) { - /* DBGO("\\_GPE\\_L09\n") */ - /* Notify (\_TZ.TZ00, 0x80) */ - } - - /* USB controller PME# */ - Method(_L0B) { - /* DBGO("\\_GPE\\_L0B\n") */ - Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* ExtEvent0 SCI event */ - Method(_L10) { - /* DBGO("\\_GPE\\_L10\n") */ - } - - /* ExtEvent1 SCI event */ - Method(_L11) { - /* DBGO("\\_GPE\\_L11\n") */ - } - - /* GPIO0 or GEvent8 event */ - Method(_L18) { - /* DBGO("\\_GPE\\_L18\n") */ - Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* Azalia SCI event */ - Method(_L1B) { - /* DBGO("\\_GPE\\_L1B\n") */ - Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } -} /* End Scope GPE */ diff --git a/src/mainboard/biostar/a68n_5200/acpi/ide.asl b/src/mainboard/biostar/a68n_5200/acpi/ide.asl deleted file mode 100644 index e7f4625..0000000 --- a/src/mainboard/biostar/a68n_5200/acpi/ide.asl +++ /dev/null @@ -1,246 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012-2013 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* No IDE functionality */ - -#if 0 -/* -Scope (_SB) { - Device(PCI0) { - Device(IDEC) { - Name(_ADR, 0x00140001) - #include "ide.asl" - } - } -} -*/ - -/* Some timing tables */ -Name(UDTT, Package(){ /* Udma timing table */ - 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */ -}) - -Name(MDTT, Package(){ /* MWDma timing table */ - 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */ -}) - -Name(POTT, Package(){ /* Pio timing table */ - 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */ -}) - -/* Some timing register value tables */ -Name(MDRT, Package(){ /* MWDma timing register table */ - 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */ -}) - -Name(PORT, Package(){ - 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */ -}) - -OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */ - Field(ICRG, AnyAcc, NoLock, Preserve) -{ - PPTS, 8, /* Primary PIO Slave Timing */ - PPTM, 8, /* Primary PIO Master Timing */ - OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */ - PMTM, 8, /* Primary MWDMA Master Timing */ - OFFSET(0x08), PPCR, 8, /* Primary PIO Control */ - OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */ - PPSM, 4, /* Primary PIO slave Mode */ - OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */ - OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */ - PDSM, 4, /* Primary UltraDMA Mode */ -} - -Method(GTTM, 1) /* get total time*/ -{ - Store(And(Arg0, 0x0F), Local0) /* Recovery Width */ - Increment(Local0) - Store(ShiftRight(Arg0, 4), Local1) /* Command Width */ - Increment(Local1) - Return(Multiply(30, Add(Local0, Local1))) -} - -Device(PRID) -{ - Name (_ADR, Zero) - Method(_GTM, 0) - { - NAME(OTBF, Buffer(20) { /* out buffer */ - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 - }) - - CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */ - CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */ - CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */ - CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */ - CreateDwordField(OTBF, 16, BFFG) /* buffer flags */ - - /* Just return if the channel is disabled */ - If(And(PPCR, 0x01)) { /* primary PIO control */ - Return(OTBF) - } - - /* Always tell them independent timing available and IOChannelReady used on both drives */ - Or(BFFG, 0x1A, BFFG) - - /* save total time of primary PIO master timing to PIO spd0 */ - Store(GTTM(PPTM), PSD0) - /* save total time of primary PIO slave Timing to PIO spd1 */ - Store(GTTM(PPTS), PSD1) - - If(And(PDCR, 0x01)) { /* It's under UDMA mode */ - Or(BFFG, 0x01, BFFG) - Store(DerefOf(Index(UDTT, PDMM)), DSD0) - } - Else { - Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */ - } - - If(And(PDCR, 0x02)) { /* It's under UDMA mode */ - Or(BFFG, 0x04, BFFG) - Store(DerefOf(Index(UDTT, PDSM)), DSD1) - } - Else { - Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */ - } - - Return(OTBF) /* out buffer */ - } /* End Method(_GTM) */ - - Method(_STM, 3, NotSerialized) - { - NAME(INBF, Buffer(20) { /* in buffer */ - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 - }) - - CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */ - CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */ - CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */ - CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */ - CreateDwordField(INBF, 16, BFFG) /*buffer flag */ - - Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0) - Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */ - Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1) - Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */ - - Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */ - Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */ - - If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0) - Divide(Local0, 7, PDMM,) - Or(PDCR, 0x01, PDCR) - } - Else { - If(LNotEqual(DSD0, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTM) - } - } - - If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0) - Divide(Local0, 7, PDSM,) - Or(PDCR, 0x02, PDCR) - } - Else { - If(LNotEqual(DSD1, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTS) - } - } - /* Return(INBF) */ - } /*End Method(_STM) */ - Device(MST) - { - Name(_ADR, 0) - Method(_GTF) { - Name(CMBF, Buffer(21) { - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 - }) - CreateByteField(CMBF, 1, POMD) - CreateByteField(CMBF, 8, DMMD) - CreateByteField(CMBF, 5, CMDA) - CreateByteField(CMBF, 12, CMDB) - CreateByteField(CMBF, 19, CMDC) - - Store(0xA0, CMDA) - Store(0xA0, CMDB) - Store(0xA0, CMDC) - - Or(PPMM, 0x08, POMD) - - If(And(PDCR, 0x01)) { - Or(PDMM, 0x40, DMMD) - } - Else { - Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) - } - } - Return(CMBF) - } - } /* End Device(MST) */ - - Device(SLAV) - { - Name(_ADR, 1) - Method(_GTF) { - Name(CMBF, Buffer(21) { - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 - }) - CreateByteField(CMBF, 1, POMD) - CreateByteField(CMBF, 8, DMMD) - CreateByteField(CMBF, 5, CMDA) - CreateByteField(CMBF, 12, CMDB) - CreateByteField(CMBF, 19, CMDC) - - Store(0xB0, CMDA) - Store(0xB0, CMDB) - Store(0xB0, CMDC) - - Or(PPSM, 0x08, POMD) - - If(And(PDCR, 0x02)) { - Or(PDSM, 0x40, DMMD) - } - Else { - Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) - } - } - Return(CMBF) - } - } /* End Device(SLAV) */ -} -#endif diff --git a/src/mainboard/biostar/a68n_5200/acpi/mainboard.asl b/src/mainboard/biostar/a68n_5200/acpi/mainboard.asl deleted file mode 100644 index 68609d8..0000000 --- a/src/mainboard/biostar/a68n_5200/acpi/mainboard.asl +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Memory related values */ -Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ -Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ -Name(PBLN, 0x0) /* Length of BIOS area */ - -Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ -Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */ -Name(HPBA, 0xFED00000) /* Base address of HPET table */ - -/* Some global data */ -Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ -Name(OSV, Ones) /* Assume nothing */ -Name(PMOD, One) /* Assume APIC */ - -/* AcpiGpe0Blk */ -OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04) - Field(GP0B, ByteAcc, NoLock, Preserve) { - , 11, - USBS, 1, -} diff --git a/src/mainboard/biostar/a68n_5200/acpi/routing.asl b/src/mainboard/biostar/a68n_5200/acpi/routing.asl deleted file mode 100644 index 1fb4c1d..0000000 --- a/src/mainboard/biostar/a68n_5200/acpi/routing.asl +++ /dev/null @@ -1,194 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* -#include <arch/acpi.h> -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 - ) - { - #include "routing.asl" - } -*/ - -/* Routing is in System Bus scope */ -Name(PR0, Package(){ - /* NB devices */ - /* Bus 0, Dev 0 - F16 Host Controller */ - - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ - /* Bus 0, Dev 1, Func 1 - HDMI Audio Controller */ - Package(){0x0001FFFF, 0, INTB, 0 }, - Package(){0x0001FFFF, 1, INTC, 0 }, - - - /* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */ - Package(){0x0002FFFF, 0, INTC, 0 }, - Package(){0x0002FFFF, 1, INTD, 0 }, - Package(){0x0002FFFF, 2, INTA, 0 }, - Package(){0x0002FFFF, 3, INTB, 0 }, - - /* FCH devices */ - /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */ - Package(){0x0014FFFF, 0, INTA, 0 }, - Package(){0x0014FFFF, 1, INTB, 0 }, - Package(){0x0014FFFF, 2, INTC, 0 }, - Package(){0x0014FFFF, 3, INTD, 0 }, - - /* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */ - /* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */ - Package(){0x0012FFFF, 0, INTC, 0 }, - Package(){0x0012FFFF, 1, INTB, 0 }, - - Package(){0x0013FFFF, 0, INTC, 0 }, - Package(){0x0013FFFF, 1, INTB, 0 }, - - Package(){0x0016FFFF, 0, INTC, 0 }, - Package(){0x0016FFFF, 1, INTB, 0 }, - - /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */ - Package(){0x0010FFFF, 0, INTC, 0 }, - Package(){0x0010FFFF, 1, INTB, 0 }, - - /* Bus 0, Dev 17 - SATA controller */ - Package(){0x0011FFFF, 0, INTD, 0 }, - -}) - -Name(APR0, Package(){ - /* NB devices in APIC mode */ - /* Bus 0, Dev 0 - F15 Host Controller */ - - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ - Package(){0x0001FFFF, 0, 0, 44 }, - Package(){0x0001FFFF, 1, 0, 45 }, - - /* Bus 0, Dev 2 - PCIe Bridges */ - Package(){0x0002FFFF, 0, 0, 24 }, - Package(){0x0002FFFF, 1, 0, 25 }, - Package(){0x0002FFFF, 2, 0, 26 }, - Package(){0x0002FFFF, 3, 0, 27 }, - - - /* SB devices in APIC mode */ - /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */ - Package(){0x0014FFFF, 0, 0, 16 }, - Package(){0x0014FFFF, 1, 0, 17 }, - Package(){0x0014FFFF, 2, 0, 18 }, - Package(){0x0014FFFF, 3, 0, 19 }, - - /* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */ - /* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */ - Package(){0x0012FFFF, 0, 0, 18 }, - Package(){0x0012FFFF, 1, 0, 17 }, - - Package(){0x0013FFFF, 0, 0, 18 }, - Package(){0x0013FFFF, 1, 0, 17 }, - - Package(){0x0016FFFF, 0, 0, 18 }, - Package(){0x0016FFFF, 1, 0, 17 }, - - /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */ - Package(){0x0010FFFF, 0, 0, 0x12}, - Package(){0x0010FFFF, 1, 0, 0x11}, - - /* Bus 0, Dev 17 - SATA controller */ - Package(){0x0011FFFF, 0, 0, 19 }, - -}) - -Name(PS2, Package(){ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, -}) -Name(APS2, Package(){ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, -}) - -/* GFX */ -Name(PS4, Package(){ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, -}) -Name(APS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, 0, 24 }, - Package(){0x0000FFFF, 1, 0, 25 }, - Package(){0x0000FFFF, 2, 0, 26 }, - Package(){0x0000FFFF, 3, 0, 27 }, -}) - -/* GPP 0 */ -Name(PS5, Package(){ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, -}) -Name(APS5, Package(){ - Package(){0x0000FFFF, 0, 0, 28 }, - Package(){0x0000FFFF, 1, 0, 29 }, - Package(){0x0000FFFF, 2, 0, 30 }, - Package(){0x0000FFFF, 3, 0, 31 }, -}) - -/* GPP 1 */ -Name(PS6, Package(){ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, -}) -Name(APS6, Package(){ - Package(){0x0000FFFF, 0, 0, 32 }, - Package(){0x0000FFFF, 1, 0, 33 }, - Package(){0x0000FFFF, 2, 0, 34 }, - Package(){0x0000FFFF, 3, 0, 35 }, -}) - -/* GPP 2 */ -Name(PS7, Package(){ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, -}) -Name(APS7, Package(){ - Package(){0x0000FFFF, 0, 0, 36 }, - Package(){0x0000FFFF, 1, 0, 37 }, - Package(){0x0000FFFF, 2, 0, 38 }, - Package(){0x0000FFFF, 3, 0, 39 }, -}) - -/* GPP 3 */ -Name(PS8, Package(){ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, -}) -Name(APS8, Package(){ - Package(){0x0000FFFF, 0, 0, 40 }, - Package(){0x0000FFFF, 1, 0, 41 }, - Package(){0x0000FFFF, 2, 0, 42 }, - Package(){0x0000FFFF, 3, 0, 43 }, -}) diff --git a/src/mainboard/biostar/a68n_5200/acpi/sata.asl b/src/mainboard/biostar/a68n_5200/acpi/sata.asl deleted file mode 100644 index 6755258..0000000 --- a/src/mainboard/biostar/a68n_5200/acpi/sata.asl +++ /dev/null @@ -1,146 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012-2013 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* No SATA functionality */ - -#if 0 -/* -Scope (_SB) { - Device(PCI0) { - Device(SATA) { - Name(_ADR, 0x00110000) - #include "sata.asl" - } - } -} -*/ - -Name(STTM, Buffer(20) { - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x1f, 0x00, 0x00, 0x00 -}) - -/* Start by clearing the PhyRdyChg bits */ -Method(_INI) { - \_GPE._L1F() -} - -Device(PMRY) -{ - Name(_ADR, 0) - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(PMST) { - Name(_ADR, 0) - Method(_STA,0) { - if (LGreater(P0IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - }/* end of PMST */ - - Device(PSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (LGreater(P1IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of PSLA */ -} /* end of PMRY */ - -Device(SEDY) -{ - Name(_ADR, 1) /* IDE Scondary Channel */ - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(SMST) - { - Name(_ADR, 0) - Method(_STA,0) { - if (LGreater(P2IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SMST */ - - Device(SSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (LGreater(P3IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SSLA */ -} /* end of SEDY */ - -/* SATA Hot Plug Support */ -Scope(\_GPE) { - Method(_L1F,0x0,NotSerialized) { - if (\_SB.P0PR) { - if (LGreater(\_SB.P0IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P0PR) - } - - if (\_SB.P1PR) { - if (LGreater(\_SB.P1IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P1PR) - } - - if (\_SB.P2PR) { - if (LGreater(\_SB.P2IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P2PR) - } - - if (\_SB.P3PR) { - if (LGreater(\_SB.P3IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P3PR) - } - } -} -#endif diff --git a/src/mainboard/biostar/a68n_5200/acpi/si.asl b/src/mainboard/biostar/a68n_5200/acpi/si.asl deleted file mode 100644 index 2923471..0000000 --- a/src/mainboard/biostar/a68n_5200/acpi/si.asl +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Scope(\_SI) { - Method(_SST, 1) { - /* DBGO("\\_SI\\_SST\n") */ - /* DBGO(" New Indicator state: ") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - } -} /* End Scope SI */ diff --git a/src/mainboard/biostar/a68n_5200/acpi/sleep.asl b/src/mainboard/biostar/a68n_5200/acpi/sleep.asl deleted file mode 100644 index 1225a62..0000000 --- a/src/mainboard/biostar/a68n_5200/acpi/sleep.asl +++ /dev/null @@ -1,93 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Wake status package */ -Name(WKST,Package(){Zero, Zero}) - -/* -* \_PTS - Prepare to Sleep method -* -* Entry: -* Arg0=The value of the sleeping state S1=1, S2=2, etc -* -* Exit: -* -none- -* -* The _PTS control method is executed at the beginning of the sleep process -* for S1-S5. The sleeping value is passed to the _PTS control method. This -* control method may be executed a relatively long time before entering the -* sleep state and the OS may abort the operation without notification to -* the ACPI driver. This method cannot modify the configuration or power -* state of any device in the system. -*/ - -External(\_SB.APTS, MethodObj) -External(\_SB.AWAK, MethodObj) - -Method(_PTS, 1) { - /* DBGO("\\_PTS\n") */ - /* DBGO("From S0 to S") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - - /* Clear wake status structure. */ - Store(0, Index(WKST,0)) - Store(0, Index(WKST,1)) - Store(7, UPWS) - \_SB.APTS(Arg0) -} /* End Method(\_PTS) */ - -/* -* \_BFS OEM Back From Sleep method -* -* Entry: -* Arg0=The value of the sleeping state S1=1, S2=2 -* -* Exit: -* -none- -*/ -Method(\_BFS, 1) { - /* DBGO("\\_BFS\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ -} - -/* -* \_WAK System Wake method -* -* Entry: -* Arg0=The value of the sleeping state S1=1, S2=2 -* -* Exit: -* Return package of 2 DWords -* Dword 1 - Status -* 0x00000000 wake succeeded -* 0x00000001 Wake was signaled but failed due to lack of power -* 0x00000002 Wake was signaled but failed due to thermal condition -* Dword 2 - Power Supply state -* if non-zero the effective S-state the power supply entered -*/ -Method(\_WAK, 1) { - /* DBGO("\\_WAK\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - Store(1,USBS) - - \_SB.AWAK(Arg0) - - Return(WKST) -} /* End Method(\_WAK) */ diff --git a/src/mainboard/biostar/a68n_5200/acpi/superio.asl b/src/mainboard/biostar/a68n_5200/acpi/superio.asl deleted file mode 100644 index e69de29..0000000 --- a/src/mainboard/biostar/a68n_5200/acpi/superio.asl +++ /dev/null diff --git a/src/mainboard/biostar/a68n_5200/acpi/thermal.asl b/src/mainboard/biostar/a68n_5200/acpi/thermal.asl deleted file mode 100644 index e69de29..0000000 --- a/src/mainboard/biostar/a68n_5200/acpi/thermal.asl +++ /dev/null diff --git a/src/mainboard/biostar/a68n_5200/acpi/usb_oc.asl b/src/mainboard/biostar/a68n_5200/acpi/usb_oc.asl deleted file mode 100644 index 513d66d..0000000 --- a/src/mainboard/biostar/a68n_5200/acpi/usb_oc.asl +++ /dev/null @@ -1,129 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* simple name description */ -/* -#include <arch/acpi.h> -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 - ) - { - #include "usb.asl" - } -*/ - -/* USB overcurrent mapping pins. */ -Name(UOM0, 0) -Name(UOM1, 2) -Name(UOM2, 0) -Name(UOM3, 7) -Name(UOM4, 2) -Name(UOM5, 2) -Name(UOM6, 6) -Name(UOM7, 2) -Name(UOM8, 6) -Name(UOM9, 6) - -/* USB Overcurrent GPEs */ - -#if 0 /* TODO: Update for Olivehill */ -Method(UCOC, 0) { - Sleep(20) - Store(0x13,CMTI) - Store(0,GPSL) -} - -/* USB Port 0 overcurrent uses Gpm 0 */ -If(LLessEqual(UOM0,9)) { - Scope (\_GPE) { - Method (_L13) { - } - } -} - -/* USB Port 1 overcurrent uses Gpm 1 */ -If (LLessEqual(UOM1,9)) { - Scope (\_GPE) { - Method (_L14) { - } - } -} - -/* USB Port 2 overcurrent uses Gpm 2 */ -If (LLessEqual(UOM2,9)) { - Scope (\_GPE) { - Method (_L15) { - } - } -} - -/* USB Port 3 overcurrent uses Gpm 3 */ -If (LLessEqual(UOM3,9)) { - Scope (\_GPE) { - Method (_L16) { - } - } -} - -/* USB Port 4 overcurrent uses Gpm 4 */ -If (LLessEqual(UOM4,9)) { - Scope (\_GPE) { - Method (_L19) { - } - } -} - -/* USB Port 5 overcurrent uses Gpm 5 */ -If (LLessEqual(UOM5,9)) { - Scope (\_GPE) { - Method (_L1A) { - } - } -} - -/* USB Port 6 overcurrent uses Gpm 6 */ -If (LLessEqual(UOM6,9)) { - Scope (\_GPE) { - /* Method (_L1C) { */ - Method (_L06) { - } - } -} - -/* USB Port 7 overcurrent uses Gpm 7 */ -If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { - /* Method (_L1D) { */ - Method (_L07) { - } - } -} - -/* USB Port 8 overcurrent uses Gpm 8 */ -If (LLessEqual(UOM8,9)) { - Scope (\_GPE) { - Method (_L17) { - } - } -} - -/* USB Port 9 overcurrent uses Gpm 9 */ -If (LLessEqual(UOM9,9)) { - Scope (\_GPE) { - Method (_L0E) { - } - } -} -#endif diff --git a/src/mainboard/biostar/a68n_5200/acpi_tables.c b/src/mainboard/biostar/a68n_5200/acpi_tables.c deleted file mode 100644 index 20509e9..0000000 --- a/src/mainboard/biostar/a68n_5200/acpi_tables.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/acpi.h> -#include <arch/ioapic.h> - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); - - /* Write SB800 IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, - IO_APIC_ADDR, 0); - - /* TODO: Remove the hardcode */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS+1, - 0xFEC20000, 24); - - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xF); - /* 0: mean bus 0--->ISA */ - /* 0: PIC 0 */ - /* 2: APIC 2 */ - /* 5 mean: 0101 --> Edge-triggered, Active high */ - - /* create all subtables for processors */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1); - /* 1: LINT1 connect to NMI */ - - return current; -} diff --git a/src/mainboard/biostar/a68n_5200/board_info.txt b/src/mainboard/biostar/a68n_5200/board_info.txt deleted file mode 100644 index b351b8e..0000000 --- a/src/mainboard/biostar/a68n_5200/board_info.txt +++ /dev/null @@ -1 +0,0 @@ -Category: eval diff --git a/src/mainboard/biostar/a68n_5200/buildOpts.c b/src/mainboard/biostar/a68n_5200/buildOpts.c deleted file mode 100644 index 65b86b8..0000000 --- a/src/mainboard/biostar/a68n_5200/buildOpts.c +++ /dev/null @@ -1,342 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/** - * @file - * - * AMD User options selection for a Brazos platform solution system - * - * This file is placed in the user's platform directory and contains the - * build option selections desired for that platform. - * - * For Information about this file, see @ref platforminstall. - * - */ - -#include <stdlib.h> -#include <AGESA.h> - -#define INSTALL_FT3_SOCKET_SUPPORT TRUE -#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE - -#define INSTALL_G34_SOCKET_SUPPORT FALSE -#define INSTALL_C32_SOCKET_SUPPORT FALSE -#define INSTALL_S1G3_SOCKET_SUPPORT FALSE -#define INSTALL_S1G4_SOCKET_SUPPORT FALSE -#define INSTALL_ASB2_SOCKET_SUPPORT FALSE -#define INSTALL_FS1_SOCKET_SUPPORT FALSE -#define INSTALL_FM1_SOCKET_SUPPORT FALSE -#define INSTALL_FP2_SOCKET_SUPPORT FALSE -#define INSTALL_FT1_SOCKET_SUPPORT FALSE -#define INSTALL_AM3_SOCKET_SUPPORT FALSE -#define INSTALL_FM2_SOCKET_SUPPORT FALSE - - -#ifdef BLDOPT_REMOVE_FT3_SOCKET_SUPPORT - #if BLDOPT_REMOVE_FT3_SOCKET_SUPPORT == TRUE - #undef INSTALL_FT3_SOCKET_SUPPORT - #define INSTALL_FT3_SOCKET_SUPPORT FALSE - #endif -#endif - -//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE -//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE -#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE -#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE -#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE -//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE -#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE -//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE -#define BLDOPT_REMOVE_SRAT FALSE //TRUE -#define BLDOPT_REMOVE_SLIT FALSE //TRUE -#define BLDOPT_REMOVE_WHEA FALSE //TRUE -#define BLDOPT_REMOVE_CRAT TRUE -#define BLDOPT_REMOVE_CDIT TRUE -#define BLDOPT_REMOVE_DMI TRUE -//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE - -//This element selects whether P-States should be forced to be independent, -// as reported by the ACPI _PSD object. For single-link processors, -// setting TRUE for OS to support this feature. - -//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE - -#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER -/* Build configuration values here. - */ -#define BLDCFG_VRM_CURRENT_LIMIT 15000 -#define BLDCFG_VRM_NB_CURRENT_LIMIT 13000 -#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 21000 -#define BLDCFG_VRM_SVI_OCP_LEVEL BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT -#define BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT 17000 -#define BLDCFG_VRM_NB_SVI_OCP_LEVEL BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT -#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0 -#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 0 -#define BLDCFG_VRM_SLEW_RATE 10000 -#define BLDCFG_VRM_NB_SLEW_RATE BLDCFG_VRM_SLEW_RATE -#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE - -#define BLDCFG_PLAT_NUM_IO_APICS 3 -#define BLDCFG_GNB_IOAPIC_ADDRESS 0xFEC20000 -#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST -#define BLDCFG_MEM_INIT_PSTATE 0 -#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 // Specifies the IO addresses trapped by the - // core for C-state entry requests. A value - // of 0 in this field specifies that the core - // does not trap any IO addresses for C-state entry. - // Values greater than 0xFFF8 results in undefined behavior. -#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770 - -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE - -#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY -#define BLDCFG_MEMORY_MODE_UNGANGED TRUE -#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE -#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE -#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE -#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE -#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE -#define BLDCFG_MEMORY_POWER_DOWN TRUE -#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT -#define BLDCFG_ONLINE_SPARE FALSE -#define BLDCFG_BANK_SWIZZLE TRUE -#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#define BLDCFG_MEMORY_CLOCK_SELECT DDR1866_FREQUENCY -#define BLDCFG_DQS_TRAINING_CONTROL TRUE -#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE -#define BLDCFG_USE_BURST_MODE FALSE -#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE -#define BLDCFG_ENABLE_ECC_FEATURE TRUE -#define BLDCFG_ECC_REDIRECTION FALSE -#define BLDCFG_SCRUB_DRAM_RATE 0 -#define BLDCFG_SCRUB_L2_RATE 0 -#define BLDCFG_SCRUB_L3_RATE 0 -#define BLDCFG_SCRUB_IC_RATE 0 -#define BLDCFG_SCRUB_DC_RATE 0 -#define BLDCFG_ECC_SYNC_FLOOD TRUE -#define BLDCFG_ECC_SYMBOL_SIZE 4 -#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000ul -#define BLDCFG_1GB_ALIGN FALSE -#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED -#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO -#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeDisabled -#define BLDCFG_IOMMU_SUPPORT FALSE -#define OPTION_GFX_INIT_SVIEW FALSE -//#define BLDCFG_PLATFORM_POWER_POLICY_MODE BatteryLife - -//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL OEM_LCD_BACK_LIGHT_CONTROL -#define BLDCFG_CFG_ABM_SUPPORT TRUE - -#define BLDCFG_CFG_GNB_HD_AUDIO TRUE -//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID -//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID -//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID - -#ifdef PCIEX_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_BASE PCIEX_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_SIZE (PCIEX_LENGTH >> 20) -#endif - -#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P' -#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' -#define BLDCFG_PCIE_TRAINING_ALGORITHM PcieTrainingDistributed - -/* Process the options... - * This file include MUST occur AFTER the user option selection settings - */ -/* - * Customized OEM build configurations for FCH component - */ -// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00 -// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20 -// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00 -// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400 -// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404 -// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408 -// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410 -// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420 -// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000 -// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000 -// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000 -// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0 -// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00 -// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000 -// #define BLDCFG_AZALIA_SSID 0x780D1022 -// #define BLDCFG_SMBUS_SSID 0x780B1022 -// #define BLDCFG_IDE_SSID 0x780C1022 -// #define BLDCFG_SATA_AHCI_SSID 0x78011022 -// #define BLDCFG_SATA_IDE_SSID 0x78001022 -// #define BLDCFG_SATA_RAID5_SSID 0x78031022 -// #define BLDCFG_SATA_RAID_SSID 0x78021022 -// #define BLDCFG_EHCI_SSID 0x78081022 -// #define BLDCFG_OHCI_SSID 0x78071022 -// #define BLDCFG_LPC_SSID 0x780E1022 -// #define BLDCFG_SD_SSID 0x78061022 -// #define BLDCFG_XHCI_SSID 0x78121022 -// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE -// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE -// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4 -// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE - -CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = -{ - { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 }, - { CPU_LIST_TERMINAL } -}; - -#define BLDCFG_AP_MTRR_SETTINGS_LIST &KabiniApMtrrSettingsList - - -/* Include the files that instantiate the configuration definitions. */ -#include "cpuRegisters.h" -#include "cpuFamRegisters.h" -#include "cpuFamilyTranslation.h" -#include "AdvancedApi.h" -#include "heapManager.h" -#include "CreateStruct.h" -#include "cpuFeatures.h" -#include "Table.h" -#include "cpuEarlyInit.h" -#include "cpuLateInit.h" -#include "GnbInterface.h" - - // This is the delivery package title, "BrazosPI" - // This string MUST be exactly 8 characters long -#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} - - // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long -#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} - -/* MEMORY_BUS_SPEED */ -//#define DDR400_FREQUENCY 200 ///< DDR 400 -//#define DDR533_FREQUENCY 266 ///< DDR 533 -//#define DDR667_FREQUENCY 333 ///< DDR 667 -//#define DDR800_FREQUENCY 400 ///< DDR 800 -//#define DDR1066_FREQUENCY 533 ///< DDR 1066 -//#define DDR1333_FREQUENCY 667 ///< DDR 1333 -//#define DDR1600_FREQUENCY 800 ///< DDR 1600 -//#define DDR1866_FREQUENCY 933 ///< DDR 1866 -//#define DDR2100_FREQUENCY 1050 ///< DDR 2100 -//#define DDR2133_FREQUENCY 1066 ///< DDR 2133 -//#define DDR2400_FREQUENCY 1200 ///< DDR 2400 -//#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency -// -///* QUANDRANK_TYPE*/ -//#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -//#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM -// -///* USER_MEMORY_TIMING_MODE */ -//#define TIMING_MODE_AUTO 0 ///< Use best rate possible -//#define TIMING_MODE_LIMITED 1 ///< Set user top limit -//#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed -// -///* POWER_DOWN_MODE */ -//#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -//#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode - -/* - * Agesa optional capabilities selection. - * Uncomment and mark FALSE those features you wish to include in the build. - * Comment out or mark TRUE those features you want to REMOVE from the build. - */ - -#define DFLT_SMBUS0_BASE_ADDRESS 0xB00 -#define DFLT_SMBUS1_BASE_ADDRESS 0xB20 -#define DFLT_SIO_PME_BASE_ADDRESS 0xE00 -#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800 -#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804 -#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808 -#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810 -#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820 -#define DFLT_SPI_BASE_ADDRESS 0xFEC10000 -#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 -#define DFLT_HPET_BASE_ADDRESS 0xFED00000 -#define DFLT_SMI_CMD_PORT 0xB0 -#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 -#define DFLT_GEC_BASE_ADDRESS 0xFED61000 -#define DFLT_AZALIA_SSID 0x780D1022 -#define DFLT_SMBUS_SSID 0x780B1022 -#define DFLT_IDE_SSID 0x780C1022 -#define DFLT_SATA_AHCI_SSID 0x78011022 -#define DFLT_SATA_IDE_SSID 0x78001022 -#define DFLT_SATA_RAID5_SSID 0x78031022 -#define DFLT_SATA_RAID_SSID 0x78021022 -#define DFLT_EHCI_SSID 0x78081022 -#define DFLT_OHCI_SSID 0x78071022 -#define DFLT_LPC_SSID 0x780E1022 -#define DFLT_SD_SSID 0x78061022 -#define DFLT_XHCI_SSID 0x78121022 -#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE -#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE -#define DFLT_FCH_GPP_LINK_CONFIG PortA4 -#define DFLT_FCH_GPP_PORT0_PRESENT FALSE -#define DFLT_FCH_GPP_PORT1_PRESENT FALSE -#define DFLT_FCH_GPP_PORT2_PRESENT FALSE -#define DFLT_FCH_GPP_PORT3_PRESENT FALSE -#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE -//#define BLDCFG_IR_PIN_CONTROL 0x33 - -GPIO_CONTROL olivehill_gpio[] = { - {183, Function1, GpioIn | GpioOutEnB | PullUpB}, - {-1} -}; -//#define BLDCFG_FCH_GPIO_CONTROL_LIST (&olivehill_gpio[0]) - -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. -#define DFLT_SCRUB_DRAM_RATE (0) -#define DFLT_SCRUB_L2_RATE (0) -#define DFLT_SCRUB_L3_RATE (0) -#define DFLT_SCRUB_IC_RATE (0) -#define DFLT_SCRUB_DC_RATE (0) -#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define DFLT_VRM_SLEW_RATE (5000) - -#include <PlatformInstall.h> diff --git a/src/mainboard/biostar/a68n_5200/cmos.layout b/src/mainboard/biostar/a68n_5200/cmos.layout deleted file mode 100644 index e1dbd9a..0000000 --- a/src/mainboard/biostar/a68n_5200/cmos.layout +++ /dev/null @@ -1,66 +0,0 @@ -#***************************************************************************** -# -# This file is part of the coreboot project. -# -# Copyright (C) 2012 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -#***************************************************************************** - -entries - -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#392 3 r 0 unused -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum -# Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% - -checksums - -checksum 392 983 984 diff --git a/src/mainboard/biostar/a68n_5200/devicetree.cb b/src/mainboard/biostar/a68n_5200/devicetree.cb deleted file mode 100644 index fd9b6ed..0000000 --- a/src/mainboard/biostar/a68n_5200/devicetree.cb +++ /dev/null @@ -1,107 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2013 Advanced Micro Devices, Inc. -# Copyright (C) 2016 Edward O'Callaghan <funfunctor(a)folklore1984.net> -# Copyright (C) 2017 Damien Zammit <damien(a)zamaudio.com> -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -chip northbridge/amd/agesa/family16kb/root_complex - device cpu_cluster 0 on - chip cpu/amd/agesa/family16kb - device lapic 0 on end - end - end - - device domain 0 on - subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/agesa/family16kb - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 - device pci 1.1 on end # Internal Multimedia - device pci 2.0 on end # PCIe Host Bridge - device pci 2.1 on end # x4 PCIe slot - device pci 2.2 off end # mPCIe slot - device pci 2.3 off end # Realtek NIC - device pci 2.4 off end # Edge Connector - device pci 2.5 off end # Edge Connector - end #chip northbridge/amd/agesa/family16kb - - chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus - device pci 10.0 on end # XHCI HC0 - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - end # SM - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/ite/it8728f - #register "multi_function_register_1" = "0x01" - device pnp 2e.0 off end # Floppy - device pnp 2e.1 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 off end # COM2 - device pnp 2e.3 on # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 5 - drq 0x74 = 4 - end - device pnp 2e.4 on # Hardware Monitor - io 0x60 = 0xa00 - io 0x62 = 0xa20 - irq 0x70 = 0 - irq 0xf1 = 0x00 - irq 0xf2 = 0x04 - irq 0xf3 = 0xa0 - irq 0xf5 = 0x0f - irq 0xf9 = 0xa0 - irq 0xfa = 0x04 - end - device pnp 2e.5 on # KBC - io 0x60 = 0x60 - end - device pnp 2e.6 off end # KBC? - device pnp 2e.7 off end # GPIO - device pnp 2e.8 off end - device pnp 2e.9 off end - device pnp 2e.a off end # IR - end # ITE IT8728F - end #LPC - device pci 14.7 off end # SD - end #chip southbridge/amd/agesa/hudson - - chip northbridge/amd/agesa/family16kb - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - register "spdAddrLookup" = " - { - { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses - { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses - }" - end - - end #domain -end #northbridge/amd/agesa/family16kb/root_complex diff --git a/src/mainboard/biostar/a68n_5200/dsdt.asl b/src/mainboard/biostar/a68n_5200/dsdt.asl deleted file mode 100644 index c4fc934..0000000 --- a/src/mainboard/biostar/a68n_5200/dsdt.asl +++ /dev/null @@ -1,88 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* DefinitionBlock Statement */ -#include <arch/acpi.h> -DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - OEM_ID, - ACPI_TABLE_CREATOR, - 0x00010001 /* OEM Revision */ - ) -{ /* Start of ASL file */ - /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ - - /* Globals for the platform */ - #include "acpi/mainboard.asl" - - /* Describe the USB Overcurrent pins */ - #include "acpi/usb_oc.asl" - - /* PCI IRQ mapping for the Southbridge */ - #include <southbridge/amd/agesa/hudson/acpi/pcie.asl> - - /* Describe the processor tree (\_PR) */ - #include <cpu/amd/agesa/family16kb/acpi/cpu.asl> - - /* Contains the supported sleep states for this chipset */ - #include <southbridge/amd/common/acpi/sleepstates.asl> - - /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */ - #include "acpi/sleep.asl" - - /* System Bus */ - Scope(\_SB) { /* Start \_SB scope */ - /* global utility methods expected within the \_SB scope */ - #include <arch/x86/acpi/globutil.asl> - - /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ - #include "acpi/routing.asl" - - Device(PWRB) { - Name(_HID, EISAID("PNP0C0C")) - Name(_UID, 0xAA) - Name(_PRW, Package () {3, 0x04}) - Name(_STA, 0x0B) - } - - Device(PCI0) { - /* Describe the AMD Northbridge */ - #include <northbridge/amd/agesa/family16kb/acpi/northbridge.asl> - - /* Describe the AMD Fusion Controller Hub Southbridge */ - #include <southbridge/amd/agesa/hudson/acpi/fch.asl> - } - - /* Describe PCI INT[A-H] for the Southbridge */ - #include <southbridge/amd/agesa/hudson/acpi/pci_int.asl> - - } /* End \_SB scope */ - - /* Describe SMBUS for the Southbridge */ - #include <southbridge/amd/agesa/hudson/acpi/smbus.asl> - - /* Define the General Purpose Events for the platform */ - #include "acpi/gpe.asl" - - /* Define the Thermal zones and methods for the platform */ - #include "acpi/thermal.asl" - - /* Define the System Indicators for the platform */ - #include "acpi/si.asl" -} -/* End of ASL file */ diff --git a/src/mainboard/biostar/a68n_5200/irq_tables.c b/src/mainboard/biostar/a68n_5200/irq_tables.c deleted file mode 100644 index 530c132..0000000 --- a/src/mainboard/biostar/a68n_5200/irq_tables.c +++ /dev/null @@ -1,100 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <string.h> -#include <stdint.h> -#include <arch/pirq_routing.h> - -static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, - u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, - u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, - u8 slot, u8 rfu) -{ - pirq_info->bus = bus; - pirq_info->devfn = devfn; - pirq_info->irq[0].link = link0; - pirq_info->irq[0].bitmap = bitmap0; - pirq_info->irq[1].link = link1; - pirq_info->irq[1].bitmap = bitmap1; - pirq_info->irq[2].link = link2; - pirq_info->irq[2].bitmap = bitmap2; - pirq_info->irq[3].link = link3; - pirq_info->irq[3].bitmap = bitmap3; - pirq_info->slot = slot; - pirq_info->rfu = rfu; -} - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - struct irq_routing_table *pirq; - struct irq_info *pirq_info; - u32 slot_num; - u8 *v; - - u8 sum = 0; - int i; - - /* Align the table to be 16 byte aligned. */ - addr += 15; - addr &= ~15; - - /* This table must be between 0xf0000 & 0x100000 */ - printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); - - pirq = (void *)(addr); - v = (u8 *) (addr); - - pirq->signature = PIRQ_SIGNATURE; - pirq->version = PIRQ_VERSION; - - pirq->rtr_bus = 0; - pirq->rtr_devfn = PCI_DEVFN(0x14, 4); - - pirq->exclusive_irqs = 0; - - pirq->rtr_vendor = 0x1002; - pirq->rtr_device = 0x4384; - - pirq->miniport_data = 0; - - memset(pirq->rfu, 0, sizeof(pirq->rfu)); - - pirq_info = (void *)(&pirq->checksum + 1); - slot_num = 0; - - /* pci bridge */ - write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), - 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, - 0); - pirq_info++; - - slot_num++; - - pirq->size = 32 + 16 * slot_num; - - for (i = 0; i < pirq->size; i++) - sum += v[i]; - - sum = pirq->checksum - sum; - - if (sum != pirq->checksum) { - pirq->checksum = sum; - } - - printk(BIOS_INFO, "write_pirq_routing_table done.\n"); - - return (unsigned long)pirq_info; -} diff --git a/src/mainboard/biostar/a68n_5200/mainboard.c b/src/mainboard/biostar/a68n_5200/mainboard.c deleted file mode 100644 index 65e838b..0000000 --- a/src/mainboard/biostar/a68n_5200/mainboard.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/device.h> - -/********************************************** - * enable the dedicated function in mainboard. - **********************************************/ -static void mainboard_enable(struct device *dev) -{ - printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/biostar/a68n_5200/mptable.c b/src/mainboard/biostar/a68n_5200/mptable.c deleted file mode 100644 index 52374f1..0000000 --- a/src/mainboard/biostar/a68n_5200/mptable.c +++ /dev/null @@ -1,187 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/smp/mpspec.h> -#include <arch/io.h> -#include <arch/ioapic.h> -#include <string.h> -#include <stdint.h> -#include <cpu/x86/lapic.h> -#include <southbridge/amd/agesa/hudson/hudson.h> - -u8 picr_data[0x54] = { - 0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - 0x1F,0x1F,0x1F,0x03,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x05,0x04,0x05,0x04,0x04,0x05,0x04,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x04,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x03,0x04,0x05,0x07 -}; -u8 intr_data[0x54] = { - 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x10,0x11,0x12,0x13 -}; - -static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) -{ - mc->mpc_length += length; - mc->mpc_entry_count++; -} - -static void my_smp_write_bus(struct mp_config_table *mc, - unsigned char id, const char *bustype) -{ - struct mpc_config_bus *mpc; - mpc = smp_next_mpc_entry(mc); - memset(mpc, '\0', sizeof(*mpc)); - mpc->mpc_type = MP_BUS; - mpc->mpc_busid = id; - memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); - smp_add_mpc_entry(mc, sizeof(*mpc)); -} - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - u8 byte; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - //mptable_write_buses(mc, NULL, &bus_isa); - my_smp_write_bus(mc, 0, "PCI "); - my_smp_write_bus(mc, 1, "PCI "); - bus_isa = 0x02; - my_smp_write_bus(mc, bus_isa, "ISA "); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000); - /* PIC IRQ routine */ - for (byte = 0x0; byte < sizeof(picr_data); byte ++) { - outb(byte, 0xC00); - outb(picr_data[byte], 0xC01); - } - - /* APIC IRQ routine */ - for (byte = 0x0; byte < sizeof(intr_data); byte ++) { - outb(byte | 0x80, 0xC00); - outb(intr_data[byte], 0xC01); - } - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) - - /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); - - /* SMBUS */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - - /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe Lan*/ - PCI_INT(0x0, 0x06, 0x0, 0x13); - - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/biostar/a68n_5200/romstage.c b/src/mainboard/biostar/a68n_5200/romstage.c deleted file mode 100644 index 5d210fa..0000000 --- a/src/mainboard/biostar/a68n_5200/romstage.c +++ /dev/null @@ -1,76 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2016 Edward O'Callaghan <funfunctor(a)folklore1984.net> - * Copyright (C) 2017 Damien Zammit <damien(a)zamaudio.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <device/pci_def.h> -#include <arch/io.h> -#include <device/pci_ops.h> -#include <northbridge/amd/agesa/state_machine.h> -#include <southbridge/amd/agesa/hudson/hudson.h> -#include <superio/ite/common/ite.h> -#include <superio/ite/it8728f/it8728f.h> - -#define SB_MMIO 0xFED80000 -#define SB_MMIO_MISC32(x) *(volatile u32 *)(SB_MMIO + 0xE00 + (x)) - -#define SERIAL_DEV PNP_DEV(0x2e, IT8728F_SP1) -#define GPIO_DEV PNP_DEV(0x2e, IT8728F_GPIO) -#define CLKIN_DEV PNP_DEV(0x2e, IT8728F_GPIO) - -static void sbxxx_enable_48mhzout(void) -{ - /* most likely programming to 48MHz out signal */ - /* Set auxiliary output clock frequency on OSCOUT1 pin to be 48MHz */ - u32 reg32; - reg32 = SB_MMIO_MISC32(0x28); - reg32 &= 0xfff8ffff; - SB_MMIO_MISC32(0x28) = reg32; - - /* Enable Auxiliary Clock1, disable FCH 14 MHz OscClk */ - reg32 = SB_MMIO_MISC32(0x40); - reg32 &= 0xffffbffb; - SB_MMIO_MISC32(0x40) = reg32; -} - -void board_BeforeAgesa(struct sysinfo *cb) -{ - u8 byte; - - /* Enable the AcpiMmio space */ - outb(0x24, 0xcd6); - outb(0x1, 0xcd7); - - /* Set LPC decode enables. */ - pci_devfn_t dev = PCI_DEV(0, 0x14, 3); - pci_write_config32(dev, 0x44, 0xff03ffd5); - - /* enable SIO LPC decode */ - byte = pci_read_config8(dev, 0x48); - byte |= 3; /* 2e, 2f */ - pci_write_config8(dev, 0x48, byte); - - /* enable serial decode */ - byte = pci_read_config8(dev, 0x44); - byte |= (1 << 6); /* 0x3f8 */ - pci_write_config8(dev, 0x44, byte); - - /* run ite */ - sbxxx_enable_48mhzout(); - ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_48); - ite_kill_watchdog(GPIO_DEV); - ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/38109 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I77f1975910969ecaa1c37b2c4f0bf6c4745988f6 Gerrit-Change-Number: 38109 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: mb/amd/union_station: Drop boards with ROMCC_BOOTBLOCK
by HAOUAS Elyes (Code Review) Jan. 7, 2020

Jan. 7, 2020

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38110 ) Change subject: mb/amd/union_station: Drop boards with ROMCC_BOOTBLOCK ...................................................................... mb/amd/union_station: Drop boards with ROMCC_BOOTBLOCK ROMCC_BOOTBLOCK is no more. Drop unsupported, unmaintained boards. Change-Id: I095814d4f7fad282ab8823007cfdb3dc8900263c Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- D src/mainboard/amd/union_station/BiosCallOuts.c D src/mainboard/amd/union_station/Kconfig D src/mainboard/amd/union_station/Kconfig.name D src/mainboard/amd/union_station/Makefile.inc D src/mainboard/amd/union_station/OemCustomize.c D src/mainboard/amd/union_station/OptionsIds.h D src/mainboard/amd/union_station/acpi/gpe.asl D src/mainboard/amd/union_station/acpi/ide.asl D src/mainboard/amd/union_station/acpi/mainboard.asl D src/mainboard/amd/union_station/acpi/routing.asl D src/mainboard/amd/union_station/acpi/sata.asl D src/mainboard/amd/union_station/acpi/sleep.asl D src/mainboard/amd/union_station/acpi/superio.asl D src/mainboard/amd/union_station/acpi/usb_oc.asl D src/mainboard/amd/union_station/acpi_tables.c D src/mainboard/amd/union_station/board_info.txt D src/mainboard/amd/union_station/buildOpts.c D src/mainboard/amd/union_station/cmos.layout D src/mainboard/amd/union_station/devicetree.cb D src/mainboard/amd/union_station/dsdt.asl D src/mainboard/amd/union_station/irq_tables.c D src/mainboard/amd/union_station/mainboard.c D src/mainboard/amd/union_station/mptable.c D src/mainboard/amd/union_station/platform_cfg.h D src/mainboard/amd/union_station/romstage.c 25 files changed, 0 insertions(+), 2,750 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/38110/1 diff --git a/src/mainboard/amd/union_station/BiosCallOuts.c b/src/mainboard/amd/union_station/BiosCallOuts.c deleted file mode 100644 index ecb7e1c..0000000 --- a/src/mainboard/amd/union_station/BiosCallOuts.c +++ /dev/null @@ -1,202 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <AGESA.h> -#include <amdlib.h> -#include <northbridge/amd/agesa/BiosCallOuts.h> -#include <SB800.h> -#include <southbridge/amd/cimx/sb800/gpio_oem.h> -#include <stdlib.h> - -static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr); -static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr); - -const BIOS_CALLOUT_STRUCT BiosCallouts[] = -{ - {AGESA_DO_RESET, agesa_Reset }, - {AGESA_READ_SPD, agesa_ReadSpd }, - {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, - {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, - {AGESA_GNB_PCIE_SLOT_RESET, board_GnbPcieSlotReset }, - {AGESA_HOOKBEFORE_DRAM_INIT, board_BeforeDramInit }, - {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, agesa_NoopSuccess }, - {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, - {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, -}; -const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); - -/* Call the host environment interface to provide a user hook opportunity. */ -static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr) -{ - AGESA_STATUS Status; - UINTN FcnData; - MEM_DATA_STRUCT *MemData; - UINT32 AcpiMmioAddr; - UINT32 GpioMmioAddr; - UINT8 Data8; - UINT16 Data16; - UINT8 TempData8; - - FcnData = Data; - MemData = ConfigPtr; - - Status = AGESA_SUCCESS; - /* Get SB MMIO Base (AcpiMmioAddr) */ - WriteIo8 (0xCD6, 0x27); - Data8 = ReadIo8(0xCD7); - Data16 = Data8 << 8; - WriteIo8 (0xCD6, 0x26); - Data8 = ReadIo8(0xCD7); - Data16 |= Data8; - AcpiMmioAddr = (UINT32)Data16 << 16; - GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; - - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178); - Data8 &= ~BIT5; - TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); - TempData8 &= 0x03; - TempData8 |= Data8; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8); - - Data8 |= BIT2+BIT3; - Data8 &= ~BIT4; - TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); - TempData8 &= 0x23; - TempData8 |= Data8; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8); - - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179); - Data8 &= ~BIT5; - TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); - TempData8 &= 0x03; - TempData8 |= Data8; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8); - - Data8 |= BIT2+BIT3; - Data8 &= ~BIT4; - TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); - TempData8 &= 0x23; - TempData8 |= Data8; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8); - - switch(MemData->ParameterListPtr->DDR3Voltage){ - case VOLT1_35: - Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); - Data8 &= ~(UINT8)BIT6; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8); - Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); - Data8 |= (UINT8)BIT6; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8); - break; - case VOLT1_25: - Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); - Data8 &= ~(UINT8)BIT6; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8); - Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); - Data8 &= ~(UINT8)BIT6; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8); - break; - case VOLT1_5: - default: - Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); - Data8 |= (UINT8)BIT6; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8); - Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); - Data8 &= ~(UINT8)BIT6; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8); - } - return Status; -} - -/* PCIE slot reset control */ -static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr) -{ - AGESA_STATUS Status; - UINTN FcnData; - PCIe_SLOT_RESET_INFO *ResetInfo; - - UINT32 GpioMmioAddr; - UINT32 AcpiMmioAddr; - UINT8 Data8; - UINT16 Data16; - - FcnData = Data; - ResetInfo = ConfigPtr; - // Get SB800 MMIO Base (AcpiMmioAddr) - WriteIo8(0xCD6, 0x27); - Data8 = ReadIo8(0xCD7); - Data16 = Data8 << 8; - WriteIo8(0xCD6, 0x26); - Data8 = ReadIo8(0xCD7); - Data16 |= Data8; - AcpiMmioAddr = (UINT32)Data16 << 16; - Status = AGESA_UNSUPPORTED; - GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; - switch (ResetInfo->ResetId) - { - case 4: - switch (ResetInfo->ResetControl) - { - case AssertSlotReset: - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); - Data8 &= ~(UINT8)BIT6; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 - Status = AGESA_SUCCESS; - break; - case DeassertSlotReset: - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); - Data8 |= BIT6; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 - Status = AGESA_SUCCESS; - break; - } - break; - case 6: - switch (ResetInfo->ResetControl) - { - case AssertSlotReset: - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); - Data8 &= ~(UINT8)BIT6; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 - Status = AGESA_SUCCESS; - break; - case DeassertSlotReset: - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); - Data8 |= BIT6; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 - Status = AGESA_SUCCESS; - break; - } - break; - case 7: - switch (ResetInfo->ResetControl) - { - case AssertSlotReset: - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); - Data8 &= ~(UINT8)BIT6; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 - Status = AGESA_SUCCESS; - break; - case DeassertSlotReset: - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); - Data8 |= BIT6; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 - Status = AGESA_SUCCESS; - break; - } - break; - } - return Status; -} diff --git a/src/mainboard/amd/union_station/Kconfig b/src/mainboard/amd/union_station/Kconfig deleted file mode 100644 index 1532d34..0000000 --- a/src/mainboard/amd/union_station/Kconfig +++ /dev/null @@ -1,69 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2011 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -config BOARD_AMD_UNIONSTATION - def_bool n - -if BOARD_AMD_UNIONSTATION - -config BOARD_SPECIFIC_OPTIONS - def_bool y - #select ROMCC_BOOTBLOCK - select CPU_AMD_AGESA_FAMILY14 - select NORTHBRIDGE_AMD_AGESA_FAMILY14 - select SOUTHBRIDGE_AMD_CIMX_SB800 - select HAVE_OPTION_TABLE - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select HAVE_ACPI_TABLES - select BOARD_ROMSIZE_KB_2048 - select GFXUMA - -config MAINBOARD_DIR - string - default "amd/union_station" - -config MAINBOARD_PART_NUMBER - string - default "Unionstation" - -config HW_MEM_HOLE_SIZEK - hex - default 0x200000 - -config MAX_CPUS - int - default 4 - -config IRQ_SLOT_COUNT - int - default 11 - -config ONBOARD_VGA_IS_PRIMARY - bool - default y - -config VGA_BIOS - bool - default n -config VGA_BIOS_FILE - string - default "site-local/vgabios.bin" - -config VGA_BIOS_ID - string - default "1002,9802" - -endif # BOARD_AMD_UNIONSTATION diff --git a/src/mainboard/amd/union_station/Kconfig.name b/src/mainboard/amd/union_station/Kconfig.name deleted file mode 100644 index b4dc5365..0000000 --- a/src/mainboard/amd/union_station/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -#config BOARD_AMD_UNIONSTATION -# bool"Unionstation" diff --git a/src/mainboard/amd/union_station/Makefile.inc b/src/mainboard/amd/union_station/Makefile.inc deleted file mode 100644 index 440744c..0000000 --- a/src/mainboard/amd/union_station/Makefile.inc +++ /dev/null @@ -1,22 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2011 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -romstage-y += buildOpts.c -romstage-y += BiosCallOuts.c -romstage-y += OemCustomize.c - -ramstage-y += buildOpts.c -ramstage-y += BiosCallOuts.c -ramstage-y += OemCustomize.c diff --git a/src/mainboard/amd/union_station/OemCustomize.c b/src/mainboard/amd/union_station/OemCustomize.c deleted file mode 100644 index 866be54..0000000 --- a/src/mainboard/amd/union_station/OemCustomize.c +++ /dev/null @@ -1,121 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <AGESA.h> -#include <PlatformMemoryConfiguration.h> -#include <northbridge/amd/agesa/state_machine.h> - -static const PCIe_PORT_DESCRIPTOR PortList[] = { - // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, - HotplugDisabled, - PcieGen2, - PcieGen2, - AspmL0sL1, 4) - }, - // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5, - HotplugDisabled, - PcieGen2, - PcieGen2, - AspmL0sL1, 5) - }, - // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, - HotplugDisabled, - PcieGen2, - PcieGen2, - AspmL0sL1, 6) - }, - // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7, - HotplugDisabled, - PcieGen2, - PcieGen2, - AspmL0sL1, 7) - }, - // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) - { - DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, - HotplugDisabled, - PcieGen2, - PcieGen2, - AspmL0sL1, 0) - } -}; - -static const PCIe_DDI_DESCRIPTOR DdiList[] = { - // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux1, Hdp1) - }, - // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) - { - DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux2, Hdp2) - } -}; - -static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { - .Flags = DESCRIPTOR_TERMINATE_LIST, - .SocketId = 0, - .PciePortList = PortList, - .DdiLinkList = DdiList, -}; - -void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) -{ - InitEarly->GnbConfig.PcieComplexList = &PcieComplex; - InitEarly->GnbConfig.PsppPolicy = 0; -} - -/*---------------------------------------------------------------------------------------- - * CUSTOMER OVERIDES MEMORY TABLE - *---------------------------------------------------------------------------------------- - */ - -/* - * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA - * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable - * is populated, AGESA will base its settings on the data from the table. Otherwise, it will - * use its default conservative settings. - */ -static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { - NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2), - NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1), - PSO_END -}; - -void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) -{ - InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; -} diff --git a/src/mainboard/amd/union_station/OptionsIds.h b/src/mainboard/amd/union_station/OptionsIds.h deleted file mode 100644 index 2d8381b..0000000 --- a/src/mainboard/amd/union_station/OptionsIds.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDS_DEBUG_PORT - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE -#define IDSOPT_ASSERT_ENABLED TRUE - -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - -#endif diff --git a/src/mainboard/amd/union_station/acpi/gpe.asl b/src/mainboard/amd/union_station/acpi/gpe.asl deleted file mode 100644 index e7a320e..0000000 --- a/src/mainboard/amd/union_station/acpi/gpe.asl +++ /dev/null @@ -1,69 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Scope(\_GPE) { /* Start Scope GPE */ - - /* Legacy PM event */ - Method(_L08) { - /* DBGO("\\_GPE\\_L08\n") */ - } - - /* Temp warning (TWarn) event */ - Method(_L09) { - /* DBGO("\\_GPE\\_L09\n") */ - /* Notify (\_TZ.TZ00, 0x80) */ - } - - /* USB controller PME# */ - Method(_L0B) { - /* DBGO("\\_GPE\\_L0B\n") */ - Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* ExtEvent0 SCI event */ - Method(_L10) { - /* DBGO("\\_GPE\\_L10\n") */ - } - - - /* ExtEvent1 SCI event */ - Method(_L11) { - /* DBGO("\\_GPE\\_L11\n") */ - } - - /* GPIO0 or GEvent8 event */ - Method(_L18) { - /* DBGO("\\_GPE\\_L18\n") */ - Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* Azalia SCI event */ - Method(_L1B) { - /* DBGO("\\_GPE\\_L1B\n") */ - Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - } -} /* End Scope GPE */ - -/* Contains the GPEs for USB overcurrent */ -#include "usb_oc.asl" diff --git a/src/mainboard/amd/union_station/acpi/ide.asl b/src/mainboard/amd/union_station/acpi/ide.asl deleted file mode 100644 index 59ea078..0000000 --- a/src/mainboard/amd/union_station/acpi/ide.asl +++ /dev/null @@ -1,240 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* -Scope (_SB) { - Device(PCI0) { - Device(IDEC) { - Name(_ADR, 0x00140001) - #include "ide.asl" - } - } -} -*/ - -/* Some timing tables */ -Name(UDTT, Package(){ /* Udma timing table */ - 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */ -}) - -Name(MDTT, Package(){ /* MWDma timing table */ - 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */ -}) - -Name(POTT, Package(){ /* Pio timing table */ - 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */ -}) - -/* Some timing register value tables */ -Name(MDRT, Package(){ /* MWDma timing register table */ - 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */ -}) - -Name(PORT, Package(){ - 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */ -}) - -OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */ - Field(ICRG, AnyAcc, NoLock, Preserve) -{ - PPTS, 8, /* Primary PIO Slave Timing */ - PPTM, 8, /* Primary PIO Master Timing */ - OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */ - PMTM, 8, /* Primary MWDMA Master Timing */ - OFFSET(0x08), PPCR, 8, /* Primary PIO Control */ - OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */ - PPSM, 4, /* Primary PIO slave Mode */ - OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */ - OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */ - PDSM, 4, /* Primary UltraDMA Mode */ -} - -Method(GTTM, 1) /* get total time*/ -{ - Store(And(Arg0, 0x0F), Local0) /* Recovery Width */ - Increment(Local0) - Store(ShiftRight(Arg0, 4), Local1) /* Command Width */ - Increment(Local1) - Return(Multiply(30, Add(Local0, Local1))) -} - -Device(PRID) -{ - Name (_ADR, Zero) - Method(_GTM, 0, Serialized) - { - NAME(OTBF, Buffer(20) { /* out buffer */ - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 - }) - - CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */ - CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */ - CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */ - CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */ - CreateDwordField(OTBF, 16, BFFG) /* buffer flags */ - - /* Just return if the channel is disabled */ - If(And(PPCR, 0x01)) { /* primary PIO control */ - Return(OTBF) - } - - /* Always tell them independent timing available and IOChannelReady used on both drives */ - Or(BFFG, 0x1A, BFFG) - - Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */ - Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */ - - If(And(PDCR, 0x01)) { /* It's under UDMA mode */ - Or(BFFG, 0x01, BFFG) - Store(DerefOf(Index(UDTT, PDMM)), DSD0) - } - Else { - Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */ - } - - If(And(PDCR, 0x02)) { /* It's under UDMA mode */ - Or(BFFG, 0x04, BFFG) - Store(DerefOf(Index(UDTT, PDSM)), DSD1) - } - Else { - Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */ - } - - Return(OTBF) /* out buffer */ - } /* End Method(_GTM) */ - - Method(_STM, 3, Serialized) - { - NAME(INBF, Buffer(20) { /* in buffer */ - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 - }) - - CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */ - CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */ - CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */ - CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */ - CreateDwordField(INBF, 16, BFFG) /*buffer flag */ - - Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0) - Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */ - Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1) - Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */ - - Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */ - Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */ - - If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0) - Divide(Local0, 7, PDMM,) - Or(PDCR, 0x01, PDCR) - } - Else { - If(LNotEqual(DSD0, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTM) - } - } - - If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0) - Divide(Local0, 7, PDSM,) - Or(PDCR, 0x02, PDCR) - } - Else { - If(LNotEqual(DSD1, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTS) - } - } - /* Return(INBF) */ - } /*End Method(_STM) */ - Device(MST) - { - Name(_ADR, 0) - Method(_GTF, 0, Serialized) { - Name(CMBF, Buffer(21) { - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 - }) - CreateByteField(CMBF, 1, POMD) - CreateByteField(CMBF, 8, DMMD) - CreateByteField(CMBF, 5, CMDA) - CreateByteField(CMBF, 12, CMDB) - CreateByteField(CMBF, 19, CMDC) - - Store(0xA0, CMDA) - Store(0xA0, CMDB) - Store(0xA0, CMDC) - - Or(PPMM, 0x08, POMD) - - If(And(PDCR, 0x01)) { - Or(PDMM, 0x40, DMMD) - } - Else { - Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) - } - } - Return(CMBF) - } - } /* End Device(MST) */ - - Device(SLAV) - { - Name(_ADR, 1) - Method(_GTF, 0, Serialized) { - Name(CMBF, Buffer(21) { - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 - }) - CreateByteField(CMBF, 1, POMD) - CreateByteField(CMBF, 8, DMMD) - CreateByteField(CMBF, 5, CMDA) - CreateByteField(CMBF, 12, CMDB) - CreateByteField(CMBF, 19, CMDC) - - Store(0xB0, CMDA) - Store(0xB0, CMDB) - Store(0xB0, CMDC) - - Or(PPSM, 0x08, POMD) - - If(And(PDCR, 0x02)) { - Or(PDSM, 0x40, DMMD) - } - Else { - Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) - } - } - Return(CMBF) - } - } /* End Device(SLAV) */ -} diff --git a/src/mainboard/amd/union_station/acpi/mainboard.asl b/src/mainboard/amd/union_station/acpi/mainboard.asl deleted file mode 100644 index 702cb92..0000000 --- a/src/mainboard/amd/union_station/acpi/mainboard.asl +++ /dev/null @@ -1,61 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Data to be patched by the BIOS during POST */ -/* FIXME the patching is not done yet! */ -/* Memory related values */ -Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ -Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ -Name(PBLN, 0x0) /* Length of BIOS area */ - -Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ -Name(HPBA, 0xFED00000) /* Base address of HPET table */ - -/* Some global data */ -Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ -Name(OSV, Ones) /* Assume nothing */ -Name(PMOD, One) /* Assume APIC */ - -Scope(\_SB) { - Method(OSFL, 0){ - - if(LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */ - - if(CondRefOf(\_OSI)) - { - Store(1, OSVR) /* Assume some form of XP */ - if (\_OSI("Windows 2006")) /* Vista */ - { - Store(2, OSVR) - } - } else { - If(WCMP(\_OS,"Linux")) { - Store(3, OSVR) /* Linux */ - } Else { - Store(4, OSVR) /* Gotta be WinCE */ - } - } - Return(OSVR) - } -} - -Scope(\_SI) { - Method(_SST, 1) { - /* DBGO("\\_SI\\_SST\n") */ - /* DBGO(" New Indicator state: ") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - } -} /* End Scope SI */ diff --git a/src/mainboard/amd/union_station/acpi/routing.asl b/src/mainboard/amd/union_station/acpi/routing.asl deleted file mode 100644 index 537bcac..0000000 --- a/src/mainboard/amd/union_station/acpi/routing.asl +++ /dev/null @@ -1,404 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* -#include <arch/acpi.h> -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 - ) - { - #include "routing.asl" - } -*/ - -/* Routing is in System Bus scope */ -Scope(\_SB) { - Name(PR0, Package(){ - /* NB devices */ - /* Bus 0, Dev 0 - RS780 Host Controller */ - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ - Package(){0x0001FFFF, 0, INTC, 0 }, - Package(){0x0001FFFF, 1, INTD, 0 }, - /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){0x0002FFFF, 0, INTC, 0 }, - Package(){0x0002FFFF, 1, INTD, 0 }, - Package(){0x0002FFFF, 2, INTA, 0 }, - Package(){0x0002FFFF, 3, INTB, 0 }, - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - Package(){0x0003FFFF, 0, INTD, 0 }, - Package(){0x0003FFFF, 1, INTA, 0 }, - Package(){0x0003FFFF, 2, INTB, 0 }, - Package(){0x0003FFFF, 3, INTC, 0 }, - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, INTA, 0 }, - Package(){0x0004FFFF, 1, INTB, 0 }, - Package(){0x0004FFFF, 2, INTC, 0 }, - Package(){0x0004FFFF, 3, INTD, 0 }, - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - Package(){0x0005FFFF, 0, INTB, 0 }, - Package(){0x0005FFFF, 1, INTC, 0 }, - Package(){0x0005FFFF, 2, INTD, 0 }, - Package(){0x0005FFFF, 3, INTA, 0 }, - /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ - Package(){0x0006FFFF, 0, INTC, 0 }, - Package(){0x0006FFFF, 1, INTD, 0 }, - Package(){0x0006FFFF, 2, INTA, 0 }, - Package(){0x0006FFFF, 3, INTB, 0 }, - /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ - Package(){0x0007FFFF, 0, INTD, 0 }, - Package(){0x0007FFFF, 1, INTA, 0 }, - Package(){0x0007FFFF, 2, INTB, 0 }, - Package(){0x0007FFFF, 3, INTC, 0 }, - - Package(){0x0009FFFF, 0, INTB, 0 }, - Package(){0x0009FFFF, 1, INTC, 0 }, - Package(){0x0009FFFF, 2, INTD, 0 }, - Package(){0x0009FFFF, 3, INTA, 0 }, - - Package(){0x000AFFFF, 0, INTC, 0 }, - Package(){0x000AFFFF, 1, INTD, 0 }, - Package(){0x000AFFFF, 2, INTA, 0 }, - Package(){0x000AFFFF, 3, INTB, 0 }, - - Package(){0x000BFFFF, 0, INTD, 0 }, - Package(){0x000BFFFF, 1, INTA, 0 }, - Package(){0x000BFFFF, 2, INTB, 0 }, - Package(){0x000BFFFF, 3, INTC, 0 }, - - Package(){0x000CFFFF, 0, INTA, 0 }, - Package(){0x000CFFFF, 1, INTB, 0 }, - Package(){0x000CFFFF, 2, INTC, 0 }, - Package(){0x000CFFFF, 3, INTD, 0 }, - - /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ - - /* SB devices */ - /* Bus 0, Dev 17 - SATA controller #2 */ - /* Bus 0, Dev 18 - SATA controller #1 */ - Package(){0x0011FFFF, 0, INTD, 0 }, - - /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5; - * EHCI, dev 18, 19 func 2 */ - Package(){0x0012FFFF, 0, INTC, 0 }, - Package(){0x0012FFFF, 1, INTB, 0 }, - - Package(){0x0013FFFF, 0, INTC, 0 }, - Package(){0x0013FFFF, 1, INTB, 0 }, - - Package(){0x0016FFFF, 0, INTC, 0 }, - Package(){0x0016FFFF, 1, INTB, 0 }, - - /* Package(){0x0014FFFF, 1, INTA, 0 }, */ - - /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */ - Package(){0x0014FFFF, 0, INTA, 0 }, - Package(){0x0014FFFF, 1, INTB, 0 }, - Package(){0x0014FFFF, 2, INTC, 0 }, - Package(){0x0014FFFF, 3, INTD, 0 }, - - Package(){0x0015FFFF, 0, INTA, 0 }, - Package(){0x0015FFFF, 1, INTB, 0 }, - Package(){0x0015FFFF, 2, INTC, 0 }, - Package(){0x0015FFFF, 3, INTD, 0 }, - }) - - Name(APR0, Package(){ - /* NB devices in APIC mode */ - /* Bus 0, Dev 0 - RS780 Host Controller */ - - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ - Package(){0x0001FFFF, 0, 0, 18 }, - Package(){0x0001FFFF, 1, 0, 19 }, - - /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){0x0002FFFF, 0, 0, 18 }, - /* Package(){0x0002FFFF, 1, 0, 19 }, */ - /* Package(){0x0002FFFF, 2, 0, 16 }, */ - /* Package(){0x0002FFFF, 3, 0, 17 }, */ - - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - Package(){0x0003FFFF, 0, 0, 19 }, - Package(){0x0003FFFF, 1, 0, 16 }, - Package(){0x0003FFFF, 2, 0, 17 }, - Package(){0x0003FFFF, 3, 0, 18 }, - - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, 0, 16 }, - Package(){0x0004FFFF, 1, 0, 17 }, - Package(){0x0004FFFF, 2, 0, 18 }, - Package(){0x0004FFFF, 3, 0, 19 }, - - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - Package(){0x0005FFFF, 0, 0, 17 }, - Package(){0x0005FFFF, 1, 0, 18 }, - Package(){0x0005FFFF, 2, 0, 19 }, - Package(){0x0005FFFF, 3, 0, 16 }, - - /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ - Package(){0x0006FFFF, 0, 0, 18 }, - Package(){0x0006FFFF, 1, 0, 19 }, - Package(){0x0006FFFF, 2, 0, 16 }, - Package(){0x0006FFFF, 3, 0, 17 }, - - /* Bus 0, Dev 7 - PCIe Bridge for network card */ - Package(){0x0007FFFF, 0, 0, 19 }, - Package(){0x0007FFFF, 1, 0, 16 }, - Package(){0x0007FFFF, 2, 0, 17 }, - Package(){0x0007FFFF, 3, 0, 18 }, - - /* Bus 0, Dev 9 - PCIe Bridge for network card */ - Package(){0x0009FFFF, 0, 0, 17 }, - Package(){0x0009FFFF, 1, 0, 16 }, - Package(){0x0009FFFF, 2, 0, 17 }, - Package(){0x0009FFFF, 3, 0, 18 }, - /* Bus 0, Dev A - PCIe Bridge for network card */ - Package(){0x000AFFFF, 0, 0, 18 }, - Package(){0x000AFFFF, 1, 0, 16 }, - Package(){0x000AFFFF, 2, 0, 17 }, - Package(){0x000AFFFF, 3, 0, 18 }, - /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ - - /* SB devices in APIC mode */ - /* Bus 0, Dev 17 - SATA controller #2 */ - /* Bus 0, Dev 18 - SATA controller #1 */ - Package(){0x0011FFFF, 0, 0, 19 }, - - /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5; - * EHCI, dev 18, 19 func 2 */ - Package(){0x0012FFFF, 0, 0, 18 }, - Package(){0x0012FFFF, 1, 0, 17 }, - /* Package(){0x0012FFFF, 2, 0, 18 }, */ - - Package(){0x0013FFFF, 0, 0, 18 }, - Package(){0x0013FFFF, 1, 0, 17 }, - /* Package(){0x0013FFFF, 2, 0, 16 }, */ - - /* Package(){0x00140000, 0, 0, 16 }, */ - - Package(){0x0016FFFF, 0, 0, 18 }, - Package(){0x0016FFFF, 1, 0, 17 }, - - /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ - Package(){0x0014FFFF, 0, 0, 16 }, - Package(){0x0014FFFF, 1, 0, 17 }, - Package(){0x0014FFFF, 2, 0, 18 }, - Package(){0x0014FFFF, 3, 0, 19 }, - /* Package(){0x00140004, 2, 0, 18 }, */ - /* Package(){0x00140004, 3, 0, 19 }, */ - /* Package(){0x00140005, 1, 0, 17 }, */ - /* Package(){0x00140006, 1, 0, 17 }, */ - - /* TODO: pcie */ - Package(){0x0015FFFF, 0, 0, 16 }, - Package(){0x0015FFFF, 1, 0, 17 }, - Package(){0x0015FFFF, 2, 0, 18 }, - Package(){0x0015FFFF, 3, 0, 19 }, - }) - - Name(PR1, Package(){ - /* Internal graphics - RS780 VGA, Bus1, Dev5 */ - Package(){0x0005FFFF, 0, INTA, 0 }, - Package(){0x0005FFFF, 1, INTB, 0 }, - Package(){0x0005FFFF, 2, INTC, 0 }, - Package(){0x0005FFFF, 3, INTD, 0 }, - }) - Name(APR1, Package(){ - /* Internal graphics - RS780 VGA, Bus1, Dev5 */ - Package(){0x0005FFFF, 0, 0, 18 }, - Package(){0x0005FFFF, 1, 0, 19 }, - /* Package(){0x0005FFFF, 2, 0, 20 }, */ - /* Package(){0x0005FFFF, 3, 0, 17 }, */ - }) - - Name(PS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - Name(APS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, - }) - Name(APS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, - }) - - Name(PS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, - }) - Name(APS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - - Name(PS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - Name(APS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PS7, Package(){ - /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - Name(APS7, Package(){ - /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, - }) - - Name(PS9, Package(){ - /* PCIe slot - Hooked to PCIe slot 9 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - Name(APS9, Package(){ - /* PCIe slot - Hooked to PCIe slot 9 */ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - - Name(PSa, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - Name(APSa, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PE0, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, - }) - Name(APE0, Package(){ - /* PCIe slot - Hooked to PCIe */ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, - }) - - Name(PE1, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, - }) - Name(APE1, Package(){ - /* PCIe slot - Hooked to PCIe */ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - - Name(PE2, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - Name(APE2, Package(){ - /* PCIe slot - Hooked to PCIe */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PE3, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - Name(APE3, Package(){ - /* PCIe slot - Hooked to PCIe */ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, - }) - - Name(PCIB, Package(){ - /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */ - Package(){0x0005FFFF, 0, 0, 0x14 }, - Package(){0x0005FFFF, 1, 0, 0x15 }, - Package(){0x0005FFFF, 2, 0, 0x16 }, - Package(){0x0005FFFF, 3, 0, 0x17 }, - Package(){0x0006FFFF, 0, 0, 0x15 }, - Package(){0x0006FFFF, 1, 0, 0x16 }, - Package(){0x0006FFFF, 2, 0, 0x17 }, - Package(){0x0006FFFF, 3, 0, 0x14 }, - Package(){0x0007FFFF, 0, 0, 0x16 }, - Package(){0x0007FFFF, 1, 0, 0x17 }, - Package(){0x0007FFFF, 2, 0, 0x14 }, - Package(){0x0007FFFF, 3, 0, 0x15 }, - }) -} diff --git a/src/mainboard/amd/union_station/acpi/sata.asl b/src/mainboard/amd/union_station/acpi/sata.asl deleted file mode 100644 index 9e0e535..0000000 --- a/src/mainboard/amd/union_station/acpi/sata.asl +++ /dev/null @@ -1,145 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* simple name description */ - -/* -Scope (_SB) { - Device(PCI0) { - Device(SATA) { - Name(_ADR, 0x00110000) - #include "sata.asl" - } - } -} -*/ - -Name(STTM, Buffer(20) { - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x1f, 0x00, 0x00, 0x00 -}) - -/* Start by clearing the PhyRdyChg bits */ -Method(_INI) { - \_GPE._L1F() -} - -Device(PMRY) -{ - Name(_ADR, 0) - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(PMST) { - Name(_ADR, 0) - Method(_STA,0) { - if (LGreater(P0IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - }/* end of PMST */ - - Device(PSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (LGreater(P1IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of PSLA */ -} /* end of PMRY */ - - -Device(SEDY) -{ - Name(_ADR, 1) /* IDE Scondary Channel */ - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(SMST) - { - Name(_ADR, 0) - Method(_STA,0) { - if (LGreater(P2IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SMST */ - - Device(SSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (LGreater(P3IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SSLA */ -} /* end of SEDY */ - -/* SATA Hot Plug Support */ -Scope(\_GPE) { - Method(_L1F,0x0,NotSerialized) { - if (\_SB.P0PR) { - if (LGreater(\_SB.P0IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P0PR) - } - - if (\_SB.P1PR) { - if (LGreater(\_SB.P1IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P1PR) - } - - if (\_SB.P2PR) { - if (LGreater(\_SB.P2IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P2PR) - } - - if (\_SB.P3PR) { - if (LGreater(\_SB.P3IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P3PR) - } - } -} diff --git a/src/mainboard/amd/union_station/acpi/sleep.asl b/src/mainboard/amd/union_station/acpi/sleep.asl deleted file mode 100644 index 0069aa9..0000000 --- a/src/mainboard/amd/union_station/acpi/sleep.asl +++ /dev/null @@ -1,117 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Wake status package */ -Name(WKST,Package(){Zero, Zero}) - -/* -* \_PTS - Prepare to Sleep method -* -* Entry: -* Arg0=The value of the sleeping state S1=1, S2=2, etc -* -* Exit: -* -none- -* -* The _PTS control method is executed at the beginning of the sleep process -* for S1-S5. The sleeping value is passed to the _PTS control method. This -* control method may be executed a relatively long time before entering the -* sleep state and the OS may abort the operation without notification to -* the ACPI driver. This method cannot modify the configuration or power -* state of any device in the system. -*/ -Method(\_PTS, 1) { - /* DBGO("\\_PTS\n") */ - /* DBGO("From S0 to S") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - - /* Don't allow PCIRST# to reset USB */ - if (LEqual(Arg0,3)){ - Store(0,URRE) - } - - /* Clear sleep SMI status flag and enable sleep SMI trap. */ - /*Store(One, CSSM) - Store(One, SSEN)*/ - - /* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(\_SB.SBRI, 0x13)) { - * Store(0,\_SB.PWDE) - *} - */ - - /* Clear wake status structure. */ - Store(0, Index(WKST,0)) - Store(0, Index(WKST,1)) -} /* End Method(\_PTS) */ - -/* -* \_BFS OEM Back From Sleep method -* -* Entry: -* Arg0=The value of the sleeping state S1=1, S2=2 -* -* Exit: -* -none- -*/ -Method(\_BFS, 1) { - /* DBGO("\\_BFS\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ -} - -/* -* \_WAK System Wake method -* -* Entry: -* Arg0=The value of the sleeping state S1=1, S2=2 -* -* Exit: -* Return package of 2 DWords -* Dword 1 - Status -* 0x00000000 wake succeeded -* 0x00000001 Wake was signaled but failed due to lack of power -* 0x00000002 Wake was signaled but failed due to thermal condition -* Dword 2 - Power Supply state -* if non-zero the effective S-state the power supply entered -*/ -Method(\_WAK, 1) { - /* DBGO("\\_WAK\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - - /* Re-enable HPET */ - Store(1,HPDE) - - /* Restore PCIRST# so it resets USB */ - if (LEqual(Arg0,3)){ - Store(1,URRE) - } - - /* Arbitrarily clear PciExpWakeStatus */ - Store(PWST, Local1) - Store(Local1, PWST) - - /* if (DeRefOf(Index(WKST,0))) { - * Store(0, Index(WKST,1)) - * } else { - * Store(Arg0, Index(WKST,1)) - * } - */ - Return(WKST) -} /* End Method(\_WAK) */ diff --git a/src/mainboard/amd/union_station/acpi/superio.asl b/src/mainboard/amd/union_station/acpi/superio.asl deleted file mode 100644 index e69de29..0000000 --- a/src/mainboard/amd/union_station/acpi/superio.asl +++ /dev/null diff --git a/src/mainboard/amd/union_station/acpi/usb_oc.asl b/src/mainboard/amd/union_station/acpi/usb_oc.asl deleted file mode 100644 index 13111b7..0000000 --- a/src/mainboard/amd/union_station/acpi/usb_oc.asl +++ /dev/null @@ -1,171 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* simple name description */ -/* -#include <arch/acpi.h> -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 - ) - { - #include "usb.asl" - } -*/ - -/* USB overcurrent mapping pins. */ -Name(UOM0, 0) -Name(UOM1, 2) -Name(UOM2, 0) -Name(UOM3, 7) -Name(UOM4, 2) -Name(UOM5, 2) -Name(UOM6, 6) -Name(UOM7, 2) -Name(UOM8, 6) -Name(UOM9, 6) - -Method(UCOC, 0) { - Sleep(20) - Store(0x13,CMTI) - Store(0,GPSL) -} - -/* USB Port 0 overcurrent uses Gpm 0 */ -If(LLessEqual(UOM0,9)) { - Scope (\_GPE) { - Method (_L13) { - UCOC() - if(LEqual(GPB0,PLC0)) { - Not(PLC0,PLC0) - Store(PLC0, \_SB.PT0D) - } - } - } -} - -/* USB Port 1 overcurrent uses Gpm 1 */ -If (LLessEqual(UOM1,9)) { - Scope (\_GPE) { - Method (_L14) { - UCOC() - if (LEqual(GPB1,PLC1)) { - Not(PLC1,PLC1) - Store(PLC1, \_SB.PT1D) - } - } - } -} - -/* USB Port 2 overcurrent uses Gpm 2 */ -If (LLessEqual(UOM2,9)) { - Scope (\_GPE) { - Method (_L15) { - UCOC() - if (LEqual(GPB2,PLC2)) { - Not(PLC2,PLC2) - Store(PLC2, \_SB.PT2D) - } - } - } -} - -/* USB Port 3 overcurrent uses Gpm 3 */ -If (LLessEqual(UOM3,9)) { - Scope (\_GPE) { - Method (_L16) { - UCOC() - if (LEqual(GPB3,PLC3)) { - Not(PLC3,PLC3) - Store(PLC3, \_SB.PT3D) - } - } - } -} - -/* USB Port 4 overcurrent uses Gpm 4 */ -If (LLessEqual(UOM4,9)) { - Scope (\_GPE) { - Method (_L19) { - UCOC() - if (LEqual(GPB4,PLC4)) { - Not(PLC4,PLC4) - Store(PLC4, \_SB.PT4D) - } - } - } -} - -/* USB Port 5 overcurrent uses Gpm 5 */ -If (LLessEqual(UOM5,9)) { - Scope (\_GPE) { - Method (_L1A) { - UCOC() - if (LEqual(GPB5,PLC5)) { - Not(PLC5,PLC5) - Store(PLC5, \_SB.PT5D) - } - } - } -} - -/* USB Port 6 overcurrent uses Gpm 6 */ -If (LLessEqual(UOM6,9)) { - Scope (\_GPE) { - /* Method (_L1C) { */ - Method (_L06) { - UCOC() - if (LEqual(GPB6,PLC6)) { - Not(PLC6,PLC6) - Store(PLC6, \_SB.PT6D) - } - } - } -} - -/* USB Port 7 overcurrent uses Gpm 7 */ -If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { - /* Method (_L1D) { */ - Method (_L07) { - UCOC() - if (LEqual(GPB7,PLC7)) { - Not(PLC7,PLC7) - Store(PLC7, \_SB.PT7D) - } - } - } -} - -/* USB Port 8 overcurrent uses Gpm 8 */ -If (LLessEqual(UOM8,9)) { - Scope (\_GPE) { - Method (_L17) { - if (LEqual(G8IS,PLC8)) { - Not(PLC8,PLC8) - Store(PLC8, \_SB.PT8D) - } - } - } -} - -/* USB Port 9 overcurrent uses Gpm 9 */ -If (LLessEqual(UOM9,9)) { - Scope (\_GPE) { - Method (_L0E) { - if (LEqual(G9IS,0)) { - Store(1,\_SB.PT9D) - } - } - } -} diff --git a/src/mainboard/amd/union_station/acpi_tables.c b/src/mainboard/amd/union_station/acpi_tables.c deleted file mode 100644 index 97ea649..0000000 --- a/src/mainboard/amd/union_station/acpi_tables.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/acpi.h> -#include <arch/ioapic.h> - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); - - /* Write SB800 IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - CONFIG_MAX_CPUS, IO_APIC_ADDR, 0); - - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xF); - - /* 0: mean bus 0--->ISA */ - /* 0: PIC 0 */ - /* 2: APIC 2 */ - /* 5 mean: 0101 --> Edge-triggered, Active high */ - - /* create all subtables for processors */ - /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */ - /* 1: LINT1 connect to NMI */ - - return current; -} diff --git a/src/mainboard/amd/union_station/board_info.txt b/src/mainboard/amd/union_station/board_info.txt deleted file mode 100644 index 23fc323..0000000 --- a/src/mainboard/amd/union_station/board_info.txt +++ /dev/null @@ -1,6 +0,0 @@ -Board name: Union Station -Category: eval -ROM package: SOIC8 -ROM protocol: SPI -ROM socketed: n -Flashrom support: y diff --git a/src/mainboard/amd/union_station/buildOpts.c b/src/mainboard/amd/union_station/buildOpts.c deleted file mode 100644 index 244229d..0000000 --- a/src/mainboard/amd/union_station/buildOpts.c +++ /dev/null @@ -1,294 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/** - * @file - * - * AMD User options selection for a Brazos platform solution system - * - * This file is placed in the user's platform directory and contains the - * build option selections desired for that platform. - * - * For Information about this file, see @ref platforminstall. - * - */ - -#include <stdlib.h> - - -/* Select the CPU family. */ -#define INSTALL_FAMILY_10_SUPPORT FALSE -#define INSTALL_FAMILY_12_SUPPORT FALSE -#define INSTALL_FAMILY_14_SUPPORT TRUE -#define INSTALL_FAMILY_15_SUPPORT FALSE - -/* Select the CPU socket type. */ -#define INSTALL_G34_SOCKET_SUPPORT FALSE -#define INSTALL_C32_SOCKET_SUPPORT FALSE -#define INSTALL_S1G3_SOCKET_SUPPORT FALSE -#define INSTALL_S1G4_SOCKET_SUPPORT FALSE -#define INSTALL_ASB2_SOCKET_SUPPORT FALSE -#define INSTALL_FS1_SOCKET_SUPPORT FALSE -#define INSTALL_FM1_SOCKET_SUPPORT FALSE -#define INSTALL_FP1_SOCKET_SUPPORT FALSE -#define INSTALL_FT1_SOCKET_SUPPORT TRUE -#define INSTALL_AM3_SOCKET_SUPPORT FALSE - -/* - * Agesa optional capabilities selection. - * Uncomment and mark FALSE those features you wish to include in the build. - * Comment out or mark TRUE those features you want to REMOVE from the build. - */ - -#define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE -#define BLDOPT_REMOVE_FAMILY_12_SUPPORT TRUE -#define BLDOPT_REMOVE_FAMILY_14_SUPPORT FALSE -#define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE - -#define BLDOPT_REMOVE_AM3_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_C32_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FM1_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FP1_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FS1_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FT1_SOCKET_SUPPORT FALSE -#define BLDOPT_REMOVE_G34_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT TRUE - -#define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE -#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE -#define BLDOPT_REMOVE_ECC_SUPPORT FALSE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE -#define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE -#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE -#define BLDOPT_REMOVE_PARALLEL_TRAINING FALSE -#define BLDOPT_REMOVE_DQS_TRAINING FALSE -#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE -#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_ACPI_PSTATES FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PSD FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE - #define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT FALSE -#define BLDOPT_REMOVE_SRAT TRUE -#define BLDOPT_REMOVE_SLIT TRUE -#define BLDOPT_REMOVE_WHEA TRUE -#define BLDOPT_REMOVE_DMI TRUE -#define BLDOPT_REMOVE_HT_ASSIST TRUE -#define BLDOPT_REMOVE_ATM_MODE TRUE -//#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE -//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE -#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE -//#define BLDOPT_REMOVE_C6_STATE TRUE -#define BLDOPT_REMOVE_GFX_RECOVERY TRUE -#define BLDOPT_REMOVE_EARLY_SAMPLES TRUE - - -#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER - -#define BLDCFG_VRM_CURRENT_LIMIT 24000 -//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 -#define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000 -#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 -#define BLDCFG_VRM_SLEW_RATE 5000 -//#define BLDCFG_VRM_NB_SLEW_RATE 5000 -//#define BLDCFG_VRM_ADDITIONAL_DELAY 0 -//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 -#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE -//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE FALSE -#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 6000 -//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 - -//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C' -//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' -//#define BLDCFG_PROCESSOR_SCOPE_IN_SB FALSE -#define BLDCFG_PLAT_NUM_IO_APICS 3 -//#define BLDCFG_PLATFORM_C1E_MODE C1eModeDisabled -//#define BLDCFG_PLATFORM_C1E_OPDATA 0 -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0 -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0 -#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 -#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 -#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 -//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto -#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST -#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE -//#define BLDCFG_STARTING_BUSNUM 0 -//#define BLDCFG_MAXIMUM_BUSNUM 0xf8 -//#define BLDCFG_ALLOCATED_BUSNUMS 0x20 -//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST 0 -//#define BLDCFG_BUID_SWAP_LIST 0 -//#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST 0 -//#define BLDCFG_HTFABRIC_LIMITS_LIST 0 -//#define BLDCFG_HTCHAIN_LIMITS_LIST 0 -//#define BLDCFG_BUS_NUMBERS_LIST 0 -//#define BLDCFG_IGNORE_LINK_LIST 0 -//#define BLDCFG_LINK_SKIP_REGANG_LIST 0 -//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST 0 -//#define BLDCFG_USE_HT_ASSIST TRUE -//#define BLDCFG_USE_ATM_MODE TRUE -//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm -#define BLDCFG_S3_LATE_RESTORE FALSE -//#define BLDCFG_USE_32_BYTE_REFRESH FALSE -//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE -//#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance -//#define BLDCFG_SET_HTCRC_SYNC_FLOOD FALSE -//#define BLDCFG_USE_UNIT_ID_CLUMPING FALSE -//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP 0 -#define BLDCFG_CFG_GNB_HD_AUDIO TRUE -//#define BLDCFG_CFG_ABM_SUPPORT FALSE -//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE 0 -//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 0 -//#define BLDCFG_MEM_INIT_PSTATE 0 -//#define BLDCFG_AMD_PSTATE_CAP_VALUE 0 -#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY -#define BLDCFG_MEMORY_MODE_UNGANGED TRUE -//#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE -//#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE -#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE -#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE -#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE -#define BLDCFG_MEMORY_POWER_DOWN TRUE -#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT -//#define BLDCFG_ONLINE_SPARE FALSE -//#define BLDCFG_MEMORY_PARITY_ENABLE FALSE -#define BLDCFG_BANK_SWIZZLE TRUE -#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY -#define BLDCFG_DQS_TRAINING_CONTROL TRUE -#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE -#define BLDCFG_USE_BURST_MODE FALSE -#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE -//#define BLDCFG_ENABLE_ECC_FEATURE TRUE -//#define BLDCFG_ECC_REDIRECTION FALSE -//#define BLDCFG_SCRUB_DRAM_RATE 0 -//#define BLDCFG_SCRUB_L2_RATE 0 -//#define BLDCFG_SCRUB_L3_RATE 0 -//#define BLDCFG_SCRUB_IC_RATE 0 -//#define BLDCFG_SCRUB_DC_RATE 0 -//#define BLDCFG_ECC_SYNC_FLOOD 0 -//#define BLDCFG_ECC_SYMBOL_SIZE 0 -//#define BLDCFG_1GB_ALIGN FALSE -#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO -#define BLDCFG_UMA_ALLOCATION_SIZE 0 -#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE -#define BLDCFG_UMA_ALIGNMENT NO_UMA_ALIGNED -#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 -#define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000 - -/* - * Agesa configuration values selection. - * Uncomment and specify the value for the configuration options - * needed by the system. - */ -#include <AGESA.h> - -/* The fixed MTRR values to be set after memory initialization. */ -CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = -{ - { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull }, - { AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull }, - { CPU_LIST_TERMINAL } -}; - -/* Include the files that instantiate the configuration definitions. */ - -#include "cpuRegisters.h" -#include "cpuFamRegisters.h" -#include "cpuFamilyTranslation.h" -#include "AdvancedApi.h" -#include "heapManager.h" -#include "CreateStruct.h" -#include "cpuFeatures.h" -#include "Table.h" -#include "cpuEarlyInit.h" -#include "cpuLateInit.h" -#include "GnbInterface.h" - -/***************************************************************************** - * Define the RELEASE VERSION string - * - * The Release Version string should identify the next planned release. - * When a branch is made in preparation for a release, the release manager - * should change/confirm that the branch version of this file contains the - * string matching the desired version for the release. The trunk version of - * the file should always contain a trailing 'X'. This will make sure that a - * development build from trunk will not be confused for a released version. - * The release manager will need to remove the trailing 'X' and update the - * version string as appropriate for the release. The trunk copy of this file - * should also be updated/incremented for the next expected version, + trailing 'X' - ****************************************************************************/ - // This is the delivery package title, "BrazosPI" - // This string MUST be exactly 8 characters long -#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} - - // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long -#define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '} - -/* MEMORY_BUS_SPEED */ -#define DDR400_FREQUENCY 200 ///< DDR 400 -#define DDR533_FREQUENCY 266 ///< DDR 533 -#define DDR667_FREQUENCY 333 ///< DDR 667 -#define DDR800_FREQUENCY 400 ///< DDR 800 -#define DDR1066_FREQUENCY 533 ///< DDR 1066 -#define DDR1333_FREQUENCY 667 ///< DDR 1333 -#define DDR1600_FREQUENCY 800 ///< DDR 1600 -#define DDR1866_FREQUENCY 933 ///< DDR 1866 -#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency - -/* QUANDRANK_TYPE*/ -#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM - -/* USER_MEMORY_TIMING_MODE */ -#define TIMING_MODE_AUTO 0 ///< Use best rate possible -#define TIMING_MODE_LIMITED 1 ///< Set user top limit -#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed - -/* POWER_DOWN_MODE */ -#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode - -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. -#define DFLT_SCRUB_DRAM_RATE (0) -#define DFLT_SCRUB_L2_RATE (0) -#define DFLT_SCRUB_L3_RATE (0) -#define DFLT_SCRUB_IC_RATE (0) -#define DFLT_SCRUB_DC_RATE (0) -#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define DFLT_VRM_SLEW_RATE (5000) - -// Instantiate all solution relevant data. -#include <PlatformInstall.h> diff --git a/src/mainboard/amd/union_station/cmos.layout b/src/mainboard/amd/union_station/cmos.layout deleted file mode 100644 index f9f52f7..0000000 --- a/src/mainboard/amd/union_station/cmos.layout +++ /dev/null @@ -1,68 +0,0 @@ -#***************************************************************************** -# -# This file is part of the coreboot project. -# -# Copyright (C) 2011 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -#***************************************************************************** - -entries - -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#392 3 r 0 unused -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum -# Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - - - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% - -checksums - -checksum 392 983 984 diff --git a/src/mainboard/amd/union_station/devicetree.cb b/src/mainboard/amd/union_station/devicetree.cb deleted file mode 100644 index 7bdc5f9..0000000 --- a/src/mainboard/amd/union_station/devicetree.cb +++ /dev/null @@ -1,77 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2011 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -chip northbridge/amd/agesa/family14/root_complex - device cpu_cluster 0 on - chip cpu/amd/agesa/family14 - device lapic 0 on end - end - end - device domain 0 on - subsystemid 0x1022 0x1510 inherit - chip northbridge/amd/agesa/family14 - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 - device pci 1.1 on end # Internal HDMI Audio - device pci 4.0 on end # PCIE P2P bridge 0x9604 - device pci 5.0 on end # PCIE P2P bridge 0x9605 - device pci 6.0 on end # PCIE P2P bridge 0x9606 - device pci 7.0 on end # PCIE P2P bridge 0x9607 - device pci 8.0 on end # NB/SB Link P2P bridge - end # agesa northbridge - - chip southbridge/amd/cimx/sb800 - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.1 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.1 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on end # LPC 0x439d - device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} - device pci 14.5 on end # USB 2 - device pci 15.0 off end # PCIe PortA - device pci 15.1 off end # PCIe PortB - device pci 15.2 off end # PCIe PortC - device pci 15.3 off end # PCIe PortD - device pci 16.0 off end # OHCI USB3 - device pci 16.2 off end # EHCI USB3 - register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow) - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/cimx/sb800 - - chip northbridge/amd/agesa/family14 - - # These seem unnecessary - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - - register "spdAddrLookup" = " - { - { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses - { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses - }" - - end # agesa northbridge - - end #domain -end #northbridge/amd/agesa/family14/root_complex diff --git a/src/mainboard/amd/union_station/dsdt.asl b/src/mainboard/amd/union_station/dsdt.asl deleted file mode 100644 index 5496288..0000000 --- a/src/mainboard/amd/union_station/dsdt.asl +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* DefinitionBlock Statement */ -#include <arch/acpi.h> -DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - OEM_ID, - ACPI_TABLE_CREATOR, - 0x00010001 /* OEM Revision */ - ) -{ /* Start of ASL file */ - /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ - - #include "acpi/mainboard.asl" - - #include <cpu/amd/agesa/family14/acpi/cpu.asl> - - #include "acpi/routing.asl" - - Scope(\_SB) { - /* global utility methods expected within the \_SB scope */ - #include <arch/x86/acpi/globutil.asl> - - Device(PCI0) { - - /* Describe the AMD Northbridge */ - #include <northbridge/amd/agesa/family14/acpi/northbridge.asl> - - /* Describe the AMD Fusion Controller Hub Southbridge */ - #include <southbridge/amd/cimx/sb800/acpi/fch.asl> - - /* Primary (and only) IDE channel */ - Device(IDEC) { - Name(_ADR, 0x00140001) - #include "acpi/ide.asl" - } /* end IDEC */ - - } - } /* End Scope(_SB) */ - - /* Contains the supported sleep states for this chipset */ - #include <southbridge/amd/common/acpi/sleepstates.asl> - - /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */ - #include "acpi/sleep.asl" - - #include "acpi/gpe.asl" -} -/* End of ASL file */ diff --git a/src/mainboard/amd/union_station/irq_tables.c b/src/mainboard/amd/union_station/irq_tables.c deleted file mode 100644 index a066864..0000000 --- a/src/mainboard/amd/union_station/irq_tables.c +++ /dev/null @@ -1,102 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <string.h> -#include <stdint.h> -#include <arch/pirq_routing.h> - -static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, - u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, - u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, - u8 slot, u8 rfu) -{ - pirq_info->bus = bus; - pirq_info->devfn = devfn; - pirq_info->irq[0].link = link0; - pirq_info->irq[0].bitmap = bitmap0; - pirq_info->irq[1].link = link1; - pirq_info->irq[1].bitmap = bitmap1; - pirq_info->irq[2].link = link2; - pirq_info->irq[2].bitmap = bitmap2; - pirq_info->irq[3].link = link3; - pirq_info->irq[3].bitmap = bitmap3; - pirq_info->slot = slot; - pirq_info->rfu = rfu; -} - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - - struct irq_routing_table *pirq; - struct irq_info *pirq_info; - u32 slot_num; - u8 *v; - - u8 sum = 0; - int i; - - /* Align the table to be 16 byte aligned. */ - addr += 15; - addr &= ~15; - - /* This table must be between 0xf0000 & 0x100000 */ - printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); - - pirq = (void *)(addr); - v = (u8 *) (addr); - - pirq->signature = PIRQ_SIGNATURE; - pirq->version = PIRQ_VERSION; - - pirq->rtr_bus = 0; - pirq->rtr_devfn = PCI_DEVFN(0x14, 4); - - pirq->exclusive_irqs = 0; - - pirq->rtr_vendor = 0x1002; - pirq->rtr_device = 0x4384; - - pirq->miniport_data = 0; - - memset(pirq->rfu, 0, sizeof(pirq->rfu)); - - pirq_info = (void *)(&pirq->checksum + 1); - slot_num = 0; - - /* pci bridge */ - write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), - 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, - 0); - pirq_info++; - - slot_num++; - - pirq->size = 32 + 16 * slot_num; - - for (i = 0; i < pirq->size; i++) - sum += v[i]; - - sum = pirq->checksum - sum; - - if (sum != pirq->checksum) { - pirq->checksum = sum; - } - - printk(BIOS_INFO, "write_pirq_routing_table done.\n"); - - return (unsigned long)pirq_info; - -} diff --git a/src/mainboard/amd/union_station/mainboard.c b/src/mainboard/amd/union_station/mainboard.c deleted file mode 100644 index d680520..0000000 --- a/src/mainboard/amd/union_station/mainboard.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <amdblocks/acpimmio.h> -#include <console/console.h> -#include <device/device.h> -#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> /* Platform Specific Definitions */ - -/********************************************** - * Enable the dedicated functions of the board. - **********************************************/ -static void mainboard_enable(struct device *dev) -{ - printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - - /* - * Initialize ASF registers to an arbitrary address because someone - * long ago set things up this way inside the SPD read code. The - * SPD read code has been made generic and moved out of the board - * directory, so the ASF init is being done here. - */ - pm_write8(0x29, 0x80); - pm_write8(0x28, 0x61); -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/amd/union_station/mptable.c b/src/mainboard/amd/union_station/mptable.c deleted file mode 100644 index c38708e..0000000 --- a/src/mainboard/amd/union_station/mptable.c +++ /dev/null @@ -1,144 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/smp/mpspec.h> -#include <arch/io.h> -#include <arch/ioapic.h> -#include <string.h> -#include <stdint.h> -#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> - -u8 intr_data[] = { - [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */ - [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */ - [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x10,0x11,0x12,0x13 -}; - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - mptable_write_buses(mc, NULL, &bus_isa); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - u8 byte; - - for (byte = 0x0; byte < sizeof(intr_data); byte ++) { - outb(byte | 0x80, 0xC00); - outb(intr_data[byte], 0xC01); - } - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) - - /* APU Internal Graphic Device*/ - PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); - - //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - /* Southbridge HD Audio: */ - PCI_INT(0x0, 0x14, 0x2, 0x12); - - PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */ - PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/amd/union_station/platform_cfg.h b/src/mainboard/amd/union_station/platform_cfg.h deleted file mode 100644 index d39a3ab..0000000 --- a/src/mainboard/amd/union_station/platform_cfg.h +++ /dev/null @@ -1,211 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -#ifndef _PLATFORM_CFG_H_ -#define _PLATFORM_CFG_H_ - -/** - * @def BIOS_SIZE - * BIOS_SIZE_{1,2,4,8,16}M - * - * In SB800, default ROM size is 1M Bytes, if your platform ROM - * bigger than 1M you have to set the ROM size outside CIMx module and - * before AGESA module get call. - */ -#ifndef BIOS_SIZE -#define BIOS_SIZE ((CONFIG_COREBOOT_ROMSIZE_KB >> 10) - 1) -#endif /* BIOS_SIZE */ - -/** - * @def SPREAD_SPECTRUM - * @brief - * 0 - Disable Spread Spectrum function - * 1 - Enable Spread Spectrum function - */ -#define SPREAD_SPECTRUM 0 - -/** - * @def SB_HPET_TIMER - * @brief - * 0 - Disable hpet - * 1 - Enable hpet - */ -#define HPET_TIMER 1 - -/** - * @def USB_CONFIG - * @brief bit[0-6] used to control USB - * 0 - Disable - * 1 - Enable - * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is define at BIT0 - * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is define at BIT1 - * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is define at BIT2 - * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is define at BIT3 - * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is define at BIT4 - * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is define at BIT5 - * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is define at BIT6 - */ -#define USB_CONFIG 0x7F - -/** - * @def PCI_CLOCK_CTRL - * @brief bit[0-4] used for PCI Slots Clock Control, - * 0 - disable - * 1 - enable - * PCI SLOT 0 define at BIT0 - * PCI SLOT 1 define at BIT1 - * PCI SLOT 2 define at BIT2 - * PCI SLOT 3 define at BIT3 - * PCI SLOT 4 define at BIT4 - */ -#define PCI_CLOCK_CTRL 0x1F - -/** - * @def SATA_CONTROLLER - * @brief INCHIP Sata Controller - */ -#define SATA_CONTROLLER CIMX_OPTION_ENABLED - -/** - * @def SATA_MODE - * @brief INCHIP Sata Controller Mode - * NOTE: DO NOT ALLOW SATA & IDE use same mode - */ -#define SATA_MODE CONFIG_SB800_SATA_MODE - -/** - * @brief INCHIP Sata IDE Controller Mode - */ -#define IDE_LEGACY_MODE 0 -#define IDE_NATIVE_MODE 1 - -/** - * @def SATA_IDE_MODE - * @brief INCHIP Sata IDE Controller Mode - * NOTE: DO NOT ALLOW SATA & IDE use same mode - */ -#define SATA_IDE_MODE IDE_LEGACY_MODE - -/** - * @def EXTERNAL_CLOCK - * @brief 00/10: Reference clock from crystal oscillator via - * PAD_XTALI and PAD_XTALO - * - * @def INTERNAL_CLOCK - * @brief 01/11: Reference clock from internal clock through - * CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL - */ -#define EXTERNAL_CLOCK 0x00 -#define INTERNAL_CLOCK 0x01 - -/* NOTE: inagua have to using internal clock, - * otherwise can not detect sata drive - */ -#define SATA_CLOCK_SOURCE INTERNAL_CLOCK - -/** - * @def SATA_PORT_MULT_CAP_RESERVED - * @brief 1 ON, 0 0FF - */ -#define SATA_PORT_MULT_CAP_RESERVED 1 - - -/** - * @def AZALIA_AUTO - * @brief Detect Azalia controller automatically. - * - * @def AZALIA_DISABLE - * @brief Disable Azalia controller. - - * @def AZALIA_ENABLE - * @brief Enable Azalia controller. - */ -#define AZALIA_AUTO 0 -#define AZALIA_DISABLE 1 -#define AZALIA_ENABLE 2 - -/** - * @brief INCHIP HDA controller - */ -#define AZALIA_CONTROLLER AZALIA_AUTO - -/** - * @def AZALIA_PIN_CONFIG - * @brief - * 0 - disable - * 1 - enable - */ -#define AZALIA_PIN_CONFIG 1 - -/** - * @def AZALIA_SDIN_PIN - * @brief - * SDIN0 is define at BIT0 & BIT1 - * 00 - GPIO PIN - * 01 - Reserved - * 10 - As a Azalia SDIN pin - * SDIN1 is define at BIT2 & BIT3 - * SDIN2 is define at BIT4 & BIT5 - * SDIN3 is define at BIT6 & BIT7 - */ -//#define AZALIA_SDIN_PIN 0xAA -#define AZALIA_SDIN_PIN 0x2A - -/** - * @def GPP_CONTROLLER - */ -#define GPP_CONTROLLER CIMX_OPTION_ENABLED - -/** - * @def GPP_CFGMODE - * @brief GPP Link Configuration - * four possible configuration: - * GPP_CFGMODE_X4000 - * GPP_CFGMODE_X2200 - * GPP_CFGMODE_X2110 - * GPP_CFGMODE_X1111 - */ -#define GPP_CFGMODE GPP_CFGMODE_X1111 - -/** - * @def NB_SB_GEN2 - * 0 - Disable - * 1 - Enable - */ -#define NB_SB_GEN2 TRUE - -/** - * @def SB_GPP_GEN2 - * 0 - Disable - * 1 - Enable - */ -#define SB_GPP_GEN2 TRUE - -/** - * @def SB_GPP_UNHIDE_PORTS - * TRUE - ports visible always, even port empty - * FALSE - ports invisible if port empty - */ -#define SB_GPP_UNHIDE_PORTS FALSE - -/** - * @def GEC_CONFIG - * 0 - Enable - * 1 - Disable - */ -#define GEC_CONFIG 0 - -#endif diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/romstage.c deleted file mode 100644 index af64ad8..0000000 --- a/src/mainboard/amd/union_station/romstage.c +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <northbridge/amd/agesa/state_machine.h> -#include <sb_cimx.h> - -void board_BeforeAgesa(struct sysinfo *cb) -{ - sb_Poweron_Init(); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/38110 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I095814d4f7fad282ab8823007cfdb3dc8900263c Gerrit-Change-Number: 38110 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/amd/south_station: Drop boards with ROMCC_BOOTBLOCK
by HAOUAS Elyes (Code Review) Jan. 7, 2020

Jan. 7, 2020

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38111 ) Change subject: mb/amd/south_station: Drop boards with ROMCC_BOOTBLOCK ...................................................................... mb/amd/south_station: Drop boards with ROMCC_BOOTBLOCK ROMCC_BOOTBLOCK is no more. Drop unsupported, unmaintained boards. Change-Id: I52cbe4acb4ffac654a5897756a90112ac81d0f97 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- D src/mainboard/amd/south_station/BiosCallOuts.c D src/mainboard/amd/south_station/Kconfig D src/mainboard/amd/south_station/Kconfig.name D src/mainboard/amd/south_station/Makefile.inc D src/mainboard/amd/south_station/OemCustomize.c D src/mainboard/amd/south_station/OptionsIds.h D src/mainboard/amd/south_station/acpi/gpe.asl D src/mainboard/amd/south_station/acpi/ide.asl D src/mainboard/amd/south_station/acpi/mainboard.asl D src/mainboard/amd/south_station/acpi/routing.asl D src/mainboard/amd/south_station/acpi/sata.asl D src/mainboard/amd/south_station/acpi/sleep.asl D src/mainboard/amd/south_station/acpi/superio.asl D src/mainboard/amd/south_station/acpi/usb_oc.asl D src/mainboard/amd/south_station/acpi_tables.c D src/mainboard/amd/south_station/board_info.txt D src/mainboard/amd/south_station/buildOpts.c D src/mainboard/amd/south_station/cmos.layout D src/mainboard/amd/south_station/devicetree.cb D src/mainboard/amd/south_station/dsdt.asl D src/mainboard/amd/south_station/irq_tables.c D src/mainboard/amd/south_station/mainboard.c D src/mainboard/amd/south_station/mptable.c D src/mainboard/amd/south_station/platform_cfg.h D src/mainboard/amd/south_station/romstage.c 25 files changed, 0 insertions(+), 2,809 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/38111/1 diff --git a/src/mainboard/amd/south_station/BiosCallOuts.c b/src/mainboard/amd/south_station/BiosCallOuts.c deleted file mode 100644 index ecb7e1c..0000000 --- a/src/mainboard/amd/south_station/BiosCallOuts.c +++ /dev/null @@ -1,202 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <AGESA.h> -#include <amdlib.h> -#include <northbridge/amd/agesa/BiosCallOuts.h> -#include <SB800.h> -#include <southbridge/amd/cimx/sb800/gpio_oem.h> -#include <stdlib.h> - -static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr); -static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr); - -const BIOS_CALLOUT_STRUCT BiosCallouts[] = -{ - {AGESA_DO_RESET, agesa_Reset }, - {AGESA_READ_SPD, agesa_ReadSpd }, - {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, - {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, - {AGESA_GNB_PCIE_SLOT_RESET, board_GnbPcieSlotReset }, - {AGESA_HOOKBEFORE_DRAM_INIT, board_BeforeDramInit }, - {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, agesa_NoopSuccess }, - {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, - {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, -}; -const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); - -/* Call the host environment interface to provide a user hook opportunity. */ -static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr) -{ - AGESA_STATUS Status; - UINTN FcnData; - MEM_DATA_STRUCT *MemData; - UINT32 AcpiMmioAddr; - UINT32 GpioMmioAddr; - UINT8 Data8; - UINT16 Data16; - UINT8 TempData8; - - FcnData = Data; - MemData = ConfigPtr; - - Status = AGESA_SUCCESS; - /* Get SB MMIO Base (AcpiMmioAddr) */ - WriteIo8 (0xCD6, 0x27); - Data8 = ReadIo8(0xCD7); - Data16 = Data8 << 8; - WriteIo8 (0xCD6, 0x26); - Data8 = ReadIo8(0xCD7); - Data16 |= Data8; - AcpiMmioAddr = (UINT32)Data16 << 16; - GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; - - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178); - Data8 &= ~BIT5; - TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); - TempData8 &= 0x03; - TempData8 |= Data8; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8); - - Data8 |= BIT2+BIT3; - Data8 &= ~BIT4; - TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); - TempData8 &= 0x23; - TempData8 |= Data8; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8); - - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179); - Data8 &= ~BIT5; - TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); - TempData8 &= 0x03; - TempData8 |= Data8; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8); - - Data8 |= BIT2+BIT3; - Data8 &= ~BIT4; - TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); - TempData8 &= 0x23; - TempData8 |= Data8; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8); - - switch(MemData->ParameterListPtr->DDR3Voltage){ - case VOLT1_35: - Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); - Data8 &= ~(UINT8)BIT6; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8); - Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); - Data8 |= (UINT8)BIT6; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8); - break; - case VOLT1_25: - Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); - Data8 &= ~(UINT8)BIT6; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8); - Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); - Data8 &= ~(UINT8)BIT6; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8); - break; - case VOLT1_5: - default: - Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); - Data8 |= (UINT8)BIT6; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8); - Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); - Data8 &= ~(UINT8)BIT6; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8); - } - return Status; -} - -/* PCIE slot reset control */ -static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr) -{ - AGESA_STATUS Status; - UINTN FcnData; - PCIe_SLOT_RESET_INFO *ResetInfo; - - UINT32 GpioMmioAddr; - UINT32 AcpiMmioAddr; - UINT8 Data8; - UINT16 Data16; - - FcnData = Data; - ResetInfo = ConfigPtr; - // Get SB800 MMIO Base (AcpiMmioAddr) - WriteIo8(0xCD6, 0x27); - Data8 = ReadIo8(0xCD7); - Data16 = Data8 << 8; - WriteIo8(0xCD6, 0x26); - Data8 = ReadIo8(0xCD7); - Data16 |= Data8; - AcpiMmioAddr = (UINT32)Data16 << 16; - Status = AGESA_UNSUPPORTED; - GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; - switch (ResetInfo->ResetId) - { - case 4: - switch (ResetInfo->ResetControl) - { - case AssertSlotReset: - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); - Data8 &= ~(UINT8)BIT6; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 - Status = AGESA_SUCCESS; - break; - case DeassertSlotReset: - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); - Data8 |= BIT6; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 - Status = AGESA_SUCCESS; - break; - } - break; - case 6: - switch (ResetInfo->ResetControl) - { - case AssertSlotReset: - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); - Data8 &= ~(UINT8)BIT6; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 - Status = AGESA_SUCCESS; - break; - case DeassertSlotReset: - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); - Data8 |= BIT6; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 - Status = AGESA_SUCCESS; - break; - } - break; - case 7: - switch (ResetInfo->ResetControl) - { - case AssertSlotReset: - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); - Data8 &= ~(UINT8)BIT6; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 - Status = AGESA_SUCCESS; - break; - case DeassertSlotReset: - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); - Data8 |= BIT6; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 - Status = AGESA_SUCCESS; - break; - } - break; - } - return Status; -} diff --git a/src/mainboard/amd/south_station/Kconfig b/src/mainboard/amd/south_station/Kconfig deleted file mode 100644 index 42841cb..0000000 --- a/src/mainboard/amd/south_station/Kconfig +++ /dev/null @@ -1,70 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2011 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -config BOARD_AMD_SOUTHSTATION - def_bool n - -if BOARD_AMD_SOUTHSTATION - -config BOARD_SPECIFIC_OPTIONS - def_bool y - #select ROMCC_BOOTBLOCK - select CPU_AMD_AGESA_FAMILY14 - select NORTHBRIDGE_AMD_AGESA_FAMILY14 - select SOUTHBRIDGE_AMD_CIMX_SB800 - select SUPERIO_FINTEK_F81865F - select HAVE_OPTION_TABLE - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select HAVE_ACPI_TABLES - select BOARD_ROMSIZE_KB_4096 - select GFXUMA - -config MAINBOARD_DIR - string - default "amd/south_station" - -config MAINBOARD_PART_NUMBER - string - default "Southstation" - -config HW_MEM_HOLE_SIZEK - hex - default 0x200000 - -config MAX_CPUS - int - default 4 - -config IRQ_SLOT_COUNT - int - default 11 - -config ONBOARD_VGA_IS_PRIMARY - bool - default y - -config VGA_BIOS - bool - default n -config VGA_BIOS_FILE - string - default "site-local/vgabios.bin" - -config VGA_BIOS_ID - string - default "1002,9806" - -endif # BOARD_AMD_SOUTHSTATION diff --git a/src/mainboard/amd/south_station/Kconfig.name b/src/mainboard/amd/south_station/Kconfig.name deleted file mode 100644 index f8f1404..0000000 --- a/src/mainboard/amd/south_station/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -#config BOARD_AMD_SOUTHSTATION -# bool"Southstation" diff --git a/src/mainboard/amd/south_station/Makefile.inc b/src/mainboard/amd/south_station/Makefile.inc deleted file mode 100644 index 440744c..0000000 --- a/src/mainboard/amd/south_station/Makefile.inc +++ /dev/null @@ -1,22 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2011 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -romstage-y += buildOpts.c -romstage-y += BiosCallOuts.c -romstage-y += OemCustomize.c - -ramstage-y += buildOpts.c -ramstage-y += BiosCallOuts.c -ramstage-y += OemCustomize.c diff --git a/src/mainboard/amd/south_station/OemCustomize.c b/src/mainboard/amd/south_station/OemCustomize.c deleted file mode 100644 index 45c9f11..0000000 --- a/src/mainboard/amd/south_station/OemCustomize.c +++ /dev/null @@ -1,122 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -#include <AGESA.h> -#include <northbridge/amd/agesa/state_machine.h> -#include <PlatformMemoryConfiguration.h> - -static const PCIe_PORT_DESCRIPTOR PortList[] = { - // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, - HotplugDisabled, - PcieGen2, - PcieGen2, - AspmL0sL1, 4) - }, - // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5, - HotplugDisabled, - PcieGen2, - PcieGen2, - AspmL0sL1, 5) - }, - // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, - HotplugDisabled, - PcieGen2, - PcieGen2, - AspmL0sL1, 6) - }, - // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7, - HotplugDisabled, - PcieGen2, - PcieGen2, - AspmL0sL1, 7) - }, - // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) - { - DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, - HotplugDisabled, - PcieGen2, - PcieGen2, - AspmL0sL1, 0) - } -}; - -static const PCIe_DDI_DESCRIPTOR DdiList[] = { - /* Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) DP1 HDMI */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux2, Hdp2) - }, - /* Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) DP0 VGA */ - { - DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeCrt, Aux1, Hdp1) - } -}; - -static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { - .Flags = DESCRIPTOR_TERMINATE_LIST, - .SocketId = 0, - .PciePortList = PortList, - .DdiLinkList = DdiList, -}; - -void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) -{ - InitEarly->GnbConfig.PcieComplexList = &PcieComplex; - InitEarly->GnbConfig.PsppPolicy = 0; -} - -/*---------------------------------------------------------------------------------------- - * CUSTOMER OVERIDES MEMORY TABLE - *---------------------------------------------------------------------------------------- - */ - -/* - * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA - * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable - * is populated, AGESA will base its settings on the data from the table. Otherwise, it will - * use its default conservative settings. - */ -static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { - NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2), - NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1), - PSO_END -}; - -void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) -{ - InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; -} diff --git a/src/mainboard/amd/south_station/OptionsIds.h b/src/mainboard/amd/south_station/OptionsIds.h deleted file mode 100644 index 2d8381b..0000000 --- a/src/mainboard/amd/south_station/OptionsIds.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDS_DEBUG_PORT - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE -#define IDSOPT_ASSERT_ENABLED TRUE - -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - -#endif diff --git a/src/mainboard/amd/south_station/acpi/gpe.asl b/src/mainboard/amd/south_station/acpi/gpe.asl deleted file mode 100644 index e7a320e..0000000 --- a/src/mainboard/amd/south_station/acpi/gpe.asl +++ /dev/null @@ -1,69 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Scope(\_GPE) { /* Start Scope GPE */ - - /* Legacy PM event */ - Method(_L08) { - /* DBGO("\\_GPE\\_L08\n") */ - } - - /* Temp warning (TWarn) event */ - Method(_L09) { - /* DBGO("\\_GPE\\_L09\n") */ - /* Notify (\_TZ.TZ00, 0x80) */ - } - - /* USB controller PME# */ - Method(_L0B) { - /* DBGO("\\_GPE\\_L0B\n") */ - Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* ExtEvent0 SCI event */ - Method(_L10) { - /* DBGO("\\_GPE\\_L10\n") */ - } - - - /* ExtEvent1 SCI event */ - Method(_L11) { - /* DBGO("\\_GPE\\_L11\n") */ - } - - /* GPIO0 or GEvent8 event */ - Method(_L18) { - /* DBGO("\\_GPE\\_L18\n") */ - Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* Azalia SCI event */ - Method(_L1B) { - /* DBGO("\\_GPE\\_L1B\n") */ - Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - } -} /* End Scope GPE */ - -/* Contains the GPEs for USB overcurrent */ -#include "usb_oc.asl" diff --git a/src/mainboard/amd/south_station/acpi/ide.asl b/src/mainboard/amd/south_station/acpi/ide.asl deleted file mode 100644 index 59ea078..0000000 --- a/src/mainboard/amd/south_station/acpi/ide.asl +++ /dev/null @@ -1,240 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* -Scope (_SB) { - Device(PCI0) { - Device(IDEC) { - Name(_ADR, 0x00140001) - #include "ide.asl" - } - } -} -*/ - -/* Some timing tables */ -Name(UDTT, Package(){ /* Udma timing table */ - 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */ -}) - -Name(MDTT, Package(){ /* MWDma timing table */ - 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */ -}) - -Name(POTT, Package(){ /* Pio timing table */ - 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */ -}) - -/* Some timing register value tables */ -Name(MDRT, Package(){ /* MWDma timing register table */ - 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */ -}) - -Name(PORT, Package(){ - 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */ -}) - -OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */ - Field(ICRG, AnyAcc, NoLock, Preserve) -{ - PPTS, 8, /* Primary PIO Slave Timing */ - PPTM, 8, /* Primary PIO Master Timing */ - OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */ - PMTM, 8, /* Primary MWDMA Master Timing */ - OFFSET(0x08), PPCR, 8, /* Primary PIO Control */ - OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */ - PPSM, 4, /* Primary PIO slave Mode */ - OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */ - OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */ - PDSM, 4, /* Primary UltraDMA Mode */ -} - -Method(GTTM, 1) /* get total time*/ -{ - Store(And(Arg0, 0x0F), Local0) /* Recovery Width */ - Increment(Local0) - Store(ShiftRight(Arg0, 4), Local1) /* Command Width */ - Increment(Local1) - Return(Multiply(30, Add(Local0, Local1))) -} - -Device(PRID) -{ - Name (_ADR, Zero) - Method(_GTM, 0, Serialized) - { - NAME(OTBF, Buffer(20) { /* out buffer */ - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 - }) - - CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */ - CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */ - CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */ - CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */ - CreateDwordField(OTBF, 16, BFFG) /* buffer flags */ - - /* Just return if the channel is disabled */ - If(And(PPCR, 0x01)) { /* primary PIO control */ - Return(OTBF) - } - - /* Always tell them independent timing available and IOChannelReady used on both drives */ - Or(BFFG, 0x1A, BFFG) - - Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */ - Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */ - - If(And(PDCR, 0x01)) { /* It's under UDMA mode */ - Or(BFFG, 0x01, BFFG) - Store(DerefOf(Index(UDTT, PDMM)), DSD0) - } - Else { - Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */ - } - - If(And(PDCR, 0x02)) { /* It's under UDMA mode */ - Or(BFFG, 0x04, BFFG) - Store(DerefOf(Index(UDTT, PDSM)), DSD1) - } - Else { - Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */ - } - - Return(OTBF) /* out buffer */ - } /* End Method(_GTM) */ - - Method(_STM, 3, Serialized) - { - NAME(INBF, Buffer(20) { /* in buffer */ - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 - }) - - CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */ - CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */ - CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */ - CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */ - CreateDwordField(INBF, 16, BFFG) /*buffer flag */ - - Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0) - Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */ - Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1) - Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */ - - Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */ - Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */ - - If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0) - Divide(Local0, 7, PDMM,) - Or(PDCR, 0x01, PDCR) - } - Else { - If(LNotEqual(DSD0, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTM) - } - } - - If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0) - Divide(Local0, 7, PDSM,) - Or(PDCR, 0x02, PDCR) - } - Else { - If(LNotEqual(DSD1, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTS) - } - } - /* Return(INBF) */ - } /*End Method(_STM) */ - Device(MST) - { - Name(_ADR, 0) - Method(_GTF, 0, Serialized) { - Name(CMBF, Buffer(21) { - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 - }) - CreateByteField(CMBF, 1, POMD) - CreateByteField(CMBF, 8, DMMD) - CreateByteField(CMBF, 5, CMDA) - CreateByteField(CMBF, 12, CMDB) - CreateByteField(CMBF, 19, CMDC) - - Store(0xA0, CMDA) - Store(0xA0, CMDB) - Store(0xA0, CMDC) - - Or(PPMM, 0x08, POMD) - - If(And(PDCR, 0x01)) { - Or(PDMM, 0x40, DMMD) - } - Else { - Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) - } - } - Return(CMBF) - } - } /* End Device(MST) */ - - Device(SLAV) - { - Name(_ADR, 1) - Method(_GTF, 0, Serialized) { - Name(CMBF, Buffer(21) { - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 - }) - CreateByteField(CMBF, 1, POMD) - CreateByteField(CMBF, 8, DMMD) - CreateByteField(CMBF, 5, CMDA) - CreateByteField(CMBF, 12, CMDB) - CreateByteField(CMBF, 19, CMDC) - - Store(0xB0, CMDA) - Store(0xB0, CMDB) - Store(0xB0, CMDC) - - Or(PPSM, 0x08, POMD) - - If(And(PDCR, 0x02)) { - Or(PDSM, 0x40, DMMD) - } - Else { - Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) - } - } - Return(CMBF) - } - } /* End Device(SLAV) */ -} diff --git a/src/mainboard/amd/south_station/acpi/mainboard.asl b/src/mainboard/amd/south_station/acpi/mainboard.asl deleted file mode 100644 index 702cb92..0000000 --- a/src/mainboard/amd/south_station/acpi/mainboard.asl +++ /dev/null @@ -1,61 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Data to be patched by the BIOS during POST */ -/* FIXME the patching is not done yet! */ -/* Memory related values */ -Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ -Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ -Name(PBLN, 0x0) /* Length of BIOS area */ - -Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ -Name(HPBA, 0xFED00000) /* Base address of HPET table */ - -/* Some global data */ -Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ -Name(OSV, Ones) /* Assume nothing */ -Name(PMOD, One) /* Assume APIC */ - -Scope(\_SB) { - Method(OSFL, 0){ - - if(LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */ - - if(CondRefOf(\_OSI)) - { - Store(1, OSVR) /* Assume some form of XP */ - if (\_OSI("Windows 2006")) /* Vista */ - { - Store(2, OSVR) - } - } else { - If(WCMP(\_OS,"Linux")) { - Store(3, OSVR) /* Linux */ - } Else { - Store(4, OSVR) /* Gotta be WinCE */ - } - } - Return(OSVR) - } -} - -Scope(\_SI) { - Method(_SST, 1) { - /* DBGO("\\_SI\\_SST\n") */ - /* DBGO(" New Indicator state: ") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - } -} /* End Scope SI */ diff --git a/src/mainboard/amd/south_station/acpi/routing.asl b/src/mainboard/amd/south_station/acpi/routing.asl deleted file mode 100644 index 537bcac..0000000 --- a/src/mainboard/amd/south_station/acpi/routing.asl +++ /dev/null @@ -1,404 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* -#include <arch/acpi.h> -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 - ) - { - #include "routing.asl" - } -*/ - -/* Routing is in System Bus scope */ -Scope(\_SB) { - Name(PR0, Package(){ - /* NB devices */ - /* Bus 0, Dev 0 - RS780 Host Controller */ - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ - Package(){0x0001FFFF, 0, INTC, 0 }, - Package(){0x0001FFFF, 1, INTD, 0 }, - /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){0x0002FFFF, 0, INTC, 0 }, - Package(){0x0002FFFF, 1, INTD, 0 }, - Package(){0x0002FFFF, 2, INTA, 0 }, - Package(){0x0002FFFF, 3, INTB, 0 }, - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - Package(){0x0003FFFF, 0, INTD, 0 }, - Package(){0x0003FFFF, 1, INTA, 0 }, - Package(){0x0003FFFF, 2, INTB, 0 }, - Package(){0x0003FFFF, 3, INTC, 0 }, - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, INTA, 0 }, - Package(){0x0004FFFF, 1, INTB, 0 }, - Package(){0x0004FFFF, 2, INTC, 0 }, - Package(){0x0004FFFF, 3, INTD, 0 }, - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - Package(){0x0005FFFF, 0, INTB, 0 }, - Package(){0x0005FFFF, 1, INTC, 0 }, - Package(){0x0005FFFF, 2, INTD, 0 }, - Package(){0x0005FFFF, 3, INTA, 0 }, - /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ - Package(){0x0006FFFF, 0, INTC, 0 }, - Package(){0x0006FFFF, 1, INTD, 0 }, - Package(){0x0006FFFF, 2, INTA, 0 }, - Package(){0x0006FFFF, 3, INTB, 0 }, - /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ - Package(){0x0007FFFF, 0, INTD, 0 }, - Package(){0x0007FFFF, 1, INTA, 0 }, - Package(){0x0007FFFF, 2, INTB, 0 }, - Package(){0x0007FFFF, 3, INTC, 0 }, - - Package(){0x0009FFFF, 0, INTB, 0 }, - Package(){0x0009FFFF, 1, INTC, 0 }, - Package(){0x0009FFFF, 2, INTD, 0 }, - Package(){0x0009FFFF, 3, INTA, 0 }, - - Package(){0x000AFFFF, 0, INTC, 0 }, - Package(){0x000AFFFF, 1, INTD, 0 }, - Package(){0x000AFFFF, 2, INTA, 0 }, - Package(){0x000AFFFF, 3, INTB, 0 }, - - Package(){0x000BFFFF, 0, INTD, 0 }, - Package(){0x000BFFFF, 1, INTA, 0 }, - Package(){0x000BFFFF, 2, INTB, 0 }, - Package(){0x000BFFFF, 3, INTC, 0 }, - - Package(){0x000CFFFF, 0, INTA, 0 }, - Package(){0x000CFFFF, 1, INTB, 0 }, - Package(){0x000CFFFF, 2, INTC, 0 }, - Package(){0x000CFFFF, 3, INTD, 0 }, - - /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ - - /* SB devices */ - /* Bus 0, Dev 17 - SATA controller #2 */ - /* Bus 0, Dev 18 - SATA controller #1 */ - Package(){0x0011FFFF, 0, INTD, 0 }, - - /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5; - * EHCI, dev 18, 19 func 2 */ - Package(){0x0012FFFF, 0, INTC, 0 }, - Package(){0x0012FFFF, 1, INTB, 0 }, - - Package(){0x0013FFFF, 0, INTC, 0 }, - Package(){0x0013FFFF, 1, INTB, 0 }, - - Package(){0x0016FFFF, 0, INTC, 0 }, - Package(){0x0016FFFF, 1, INTB, 0 }, - - /* Package(){0x0014FFFF, 1, INTA, 0 }, */ - - /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */ - Package(){0x0014FFFF, 0, INTA, 0 }, - Package(){0x0014FFFF, 1, INTB, 0 }, - Package(){0x0014FFFF, 2, INTC, 0 }, - Package(){0x0014FFFF, 3, INTD, 0 }, - - Package(){0x0015FFFF, 0, INTA, 0 }, - Package(){0x0015FFFF, 1, INTB, 0 }, - Package(){0x0015FFFF, 2, INTC, 0 }, - Package(){0x0015FFFF, 3, INTD, 0 }, - }) - - Name(APR0, Package(){ - /* NB devices in APIC mode */ - /* Bus 0, Dev 0 - RS780 Host Controller */ - - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ - Package(){0x0001FFFF, 0, 0, 18 }, - Package(){0x0001FFFF, 1, 0, 19 }, - - /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){0x0002FFFF, 0, 0, 18 }, - /* Package(){0x0002FFFF, 1, 0, 19 }, */ - /* Package(){0x0002FFFF, 2, 0, 16 }, */ - /* Package(){0x0002FFFF, 3, 0, 17 }, */ - - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - Package(){0x0003FFFF, 0, 0, 19 }, - Package(){0x0003FFFF, 1, 0, 16 }, - Package(){0x0003FFFF, 2, 0, 17 }, - Package(){0x0003FFFF, 3, 0, 18 }, - - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, 0, 16 }, - Package(){0x0004FFFF, 1, 0, 17 }, - Package(){0x0004FFFF, 2, 0, 18 }, - Package(){0x0004FFFF, 3, 0, 19 }, - - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - Package(){0x0005FFFF, 0, 0, 17 }, - Package(){0x0005FFFF, 1, 0, 18 }, - Package(){0x0005FFFF, 2, 0, 19 }, - Package(){0x0005FFFF, 3, 0, 16 }, - - /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ - Package(){0x0006FFFF, 0, 0, 18 }, - Package(){0x0006FFFF, 1, 0, 19 }, - Package(){0x0006FFFF, 2, 0, 16 }, - Package(){0x0006FFFF, 3, 0, 17 }, - - /* Bus 0, Dev 7 - PCIe Bridge for network card */ - Package(){0x0007FFFF, 0, 0, 19 }, - Package(){0x0007FFFF, 1, 0, 16 }, - Package(){0x0007FFFF, 2, 0, 17 }, - Package(){0x0007FFFF, 3, 0, 18 }, - - /* Bus 0, Dev 9 - PCIe Bridge for network card */ - Package(){0x0009FFFF, 0, 0, 17 }, - Package(){0x0009FFFF, 1, 0, 16 }, - Package(){0x0009FFFF, 2, 0, 17 }, - Package(){0x0009FFFF, 3, 0, 18 }, - /* Bus 0, Dev A - PCIe Bridge for network card */ - Package(){0x000AFFFF, 0, 0, 18 }, - Package(){0x000AFFFF, 1, 0, 16 }, - Package(){0x000AFFFF, 2, 0, 17 }, - Package(){0x000AFFFF, 3, 0, 18 }, - /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ - - /* SB devices in APIC mode */ - /* Bus 0, Dev 17 - SATA controller #2 */ - /* Bus 0, Dev 18 - SATA controller #1 */ - Package(){0x0011FFFF, 0, 0, 19 }, - - /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5; - * EHCI, dev 18, 19 func 2 */ - Package(){0x0012FFFF, 0, 0, 18 }, - Package(){0x0012FFFF, 1, 0, 17 }, - /* Package(){0x0012FFFF, 2, 0, 18 }, */ - - Package(){0x0013FFFF, 0, 0, 18 }, - Package(){0x0013FFFF, 1, 0, 17 }, - /* Package(){0x0013FFFF, 2, 0, 16 }, */ - - /* Package(){0x00140000, 0, 0, 16 }, */ - - Package(){0x0016FFFF, 0, 0, 18 }, - Package(){0x0016FFFF, 1, 0, 17 }, - - /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ - Package(){0x0014FFFF, 0, 0, 16 }, - Package(){0x0014FFFF, 1, 0, 17 }, - Package(){0x0014FFFF, 2, 0, 18 }, - Package(){0x0014FFFF, 3, 0, 19 }, - /* Package(){0x00140004, 2, 0, 18 }, */ - /* Package(){0x00140004, 3, 0, 19 }, */ - /* Package(){0x00140005, 1, 0, 17 }, */ - /* Package(){0x00140006, 1, 0, 17 }, */ - - /* TODO: pcie */ - Package(){0x0015FFFF, 0, 0, 16 }, - Package(){0x0015FFFF, 1, 0, 17 }, - Package(){0x0015FFFF, 2, 0, 18 }, - Package(){0x0015FFFF, 3, 0, 19 }, - }) - - Name(PR1, Package(){ - /* Internal graphics - RS780 VGA, Bus1, Dev5 */ - Package(){0x0005FFFF, 0, INTA, 0 }, - Package(){0x0005FFFF, 1, INTB, 0 }, - Package(){0x0005FFFF, 2, INTC, 0 }, - Package(){0x0005FFFF, 3, INTD, 0 }, - }) - Name(APR1, Package(){ - /* Internal graphics - RS780 VGA, Bus1, Dev5 */ - Package(){0x0005FFFF, 0, 0, 18 }, - Package(){0x0005FFFF, 1, 0, 19 }, - /* Package(){0x0005FFFF, 2, 0, 20 }, */ - /* Package(){0x0005FFFF, 3, 0, 17 }, */ - }) - - Name(PS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - Name(APS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, - }) - Name(APS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, - }) - - Name(PS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, - }) - Name(APS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - - Name(PS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - Name(APS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PS7, Package(){ - /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - Name(APS7, Package(){ - /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, - }) - - Name(PS9, Package(){ - /* PCIe slot - Hooked to PCIe slot 9 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - Name(APS9, Package(){ - /* PCIe slot - Hooked to PCIe slot 9 */ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - - Name(PSa, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - Name(APSa, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PE0, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, - }) - Name(APE0, Package(){ - /* PCIe slot - Hooked to PCIe */ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, - }) - - Name(PE1, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, - }) - Name(APE1, Package(){ - /* PCIe slot - Hooked to PCIe */ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - - Name(PE2, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - Name(APE2, Package(){ - /* PCIe slot - Hooked to PCIe */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PE3, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - Name(APE3, Package(){ - /* PCIe slot - Hooked to PCIe */ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, - }) - - Name(PCIB, Package(){ - /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */ - Package(){0x0005FFFF, 0, 0, 0x14 }, - Package(){0x0005FFFF, 1, 0, 0x15 }, - Package(){0x0005FFFF, 2, 0, 0x16 }, - Package(){0x0005FFFF, 3, 0, 0x17 }, - Package(){0x0006FFFF, 0, 0, 0x15 }, - Package(){0x0006FFFF, 1, 0, 0x16 }, - Package(){0x0006FFFF, 2, 0, 0x17 }, - Package(){0x0006FFFF, 3, 0, 0x14 }, - Package(){0x0007FFFF, 0, 0, 0x16 }, - Package(){0x0007FFFF, 1, 0, 0x17 }, - Package(){0x0007FFFF, 2, 0, 0x14 }, - Package(){0x0007FFFF, 3, 0, 0x15 }, - }) -} diff --git a/src/mainboard/amd/south_station/acpi/sata.asl b/src/mainboard/amd/south_station/acpi/sata.asl deleted file mode 100644 index 9e0e535..0000000 --- a/src/mainboard/amd/south_station/acpi/sata.asl +++ /dev/null @@ -1,145 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* simple name description */ - -/* -Scope (_SB) { - Device(PCI0) { - Device(SATA) { - Name(_ADR, 0x00110000) - #include "sata.asl" - } - } -} -*/ - -Name(STTM, Buffer(20) { - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x1f, 0x00, 0x00, 0x00 -}) - -/* Start by clearing the PhyRdyChg bits */ -Method(_INI) { - \_GPE._L1F() -} - -Device(PMRY) -{ - Name(_ADR, 0) - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(PMST) { - Name(_ADR, 0) - Method(_STA,0) { - if (LGreater(P0IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - }/* end of PMST */ - - Device(PSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (LGreater(P1IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of PSLA */ -} /* end of PMRY */ - - -Device(SEDY) -{ - Name(_ADR, 1) /* IDE Scondary Channel */ - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(SMST) - { - Name(_ADR, 0) - Method(_STA,0) { - if (LGreater(P2IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SMST */ - - Device(SSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (LGreater(P3IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SSLA */ -} /* end of SEDY */ - -/* SATA Hot Plug Support */ -Scope(\_GPE) { - Method(_L1F,0x0,NotSerialized) { - if (\_SB.P0PR) { - if (LGreater(\_SB.P0IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P0PR) - } - - if (\_SB.P1PR) { - if (LGreater(\_SB.P1IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P1PR) - } - - if (\_SB.P2PR) { - if (LGreater(\_SB.P2IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P2PR) - } - - if (\_SB.P3PR) { - if (LGreater(\_SB.P3IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P3PR) - } - } -} diff --git a/src/mainboard/amd/south_station/acpi/sleep.asl b/src/mainboard/amd/south_station/acpi/sleep.asl deleted file mode 100644 index 0069aa9..0000000 --- a/src/mainboard/amd/south_station/acpi/sleep.asl +++ /dev/null @@ -1,117 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Wake status package */ -Name(WKST,Package(){Zero, Zero}) - -/* -* \_PTS - Prepare to Sleep method -* -* Entry: -* Arg0=The value of the sleeping state S1=1, S2=2, etc -* -* Exit: -* -none- -* -* The _PTS control method is executed at the beginning of the sleep process -* for S1-S5. The sleeping value is passed to the _PTS control method. This -* control method may be executed a relatively long time before entering the -* sleep state and the OS may abort the operation without notification to -* the ACPI driver. This method cannot modify the configuration or power -* state of any device in the system. -*/ -Method(\_PTS, 1) { - /* DBGO("\\_PTS\n") */ - /* DBGO("From S0 to S") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - - /* Don't allow PCIRST# to reset USB */ - if (LEqual(Arg0,3)){ - Store(0,URRE) - } - - /* Clear sleep SMI status flag and enable sleep SMI trap. */ - /*Store(One, CSSM) - Store(One, SSEN)*/ - - /* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(\_SB.SBRI, 0x13)) { - * Store(0,\_SB.PWDE) - *} - */ - - /* Clear wake status structure. */ - Store(0, Index(WKST,0)) - Store(0, Index(WKST,1)) -} /* End Method(\_PTS) */ - -/* -* \_BFS OEM Back From Sleep method -* -* Entry: -* Arg0=The value of the sleeping state S1=1, S2=2 -* -* Exit: -* -none- -*/ -Method(\_BFS, 1) { - /* DBGO("\\_BFS\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ -} - -/* -* \_WAK System Wake method -* -* Entry: -* Arg0=The value of the sleeping state S1=1, S2=2 -* -* Exit: -* Return package of 2 DWords -* Dword 1 - Status -* 0x00000000 wake succeeded -* 0x00000001 Wake was signaled but failed due to lack of power -* 0x00000002 Wake was signaled but failed due to thermal condition -* Dword 2 - Power Supply state -* if non-zero the effective S-state the power supply entered -*/ -Method(\_WAK, 1) { - /* DBGO("\\_WAK\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - - /* Re-enable HPET */ - Store(1,HPDE) - - /* Restore PCIRST# so it resets USB */ - if (LEqual(Arg0,3)){ - Store(1,URRE) - } - - /* Arbitrarily clear PciExpWakeStatus */ - Store(PWST, Local1) - Store(Local1, PWST) - - /* if (DeRefOf(Index(WKST,0))) { - * Store(0, Index(WKST,1)) - * } else { - * Store(Arg0, Index(WKST,1)) - * } - */ - Return(WKST) -} /* End Method(\_WAK) */ diff --git a/src/mainboard/amd/south_station/acpi/superio.asl b/src/mainboard/amd/south_station/acpi/superio.asl deleted file mode 100644 index e69de29..0000000 --- a/src/mainboard/amd/south_station/acpi/superio.asl +++ /dev/null diff --git a/src/mainboard/amd/south_station/acpi/usb_oc.asl b/src/mainboard/amd/south_station/acpi/usb_oc.asl deleted file mode 100644 index 13111b7..0000000 --- a/src/mainboard/amd/south_station/acpi/usb_oc.asl +++ /dev/null @@ -1,171 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* simple name description */ -/* -#include <arch/acpi.h> -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 - ) - { - #include "usb.asl" - } -*/ - -/* USB overcurrent mapping pins. */ -Name(UOM0, 0) -Name(UOM1, 2) -Name(UOM2, 0) -Name(UOM3, 7) -Name(UOM4, 2) -Name(UOM5, 2) -Name(UOM6, 6) -Name(UOM7, 2) -Name(UOM8, 6) -Name(UOM9, 6) - -Method(UCOC, 0) { - Sleep(20) - Store(0x13,CMTI) - Store(0,GPSL) -} - -/* USB Port 0 overcurrent uses Gpm 0 */ -If(LLessEqual(UOM0,9)) { - Scope (\_GPE) { - Method (_L13) { - UCOC() - if(LEqual(GPB0,PLC0)) { - Not(PLC0,PLC0) - Store(PLC0, \_SB.PT0D) - } - } - } -} - -/* USB Port 1 overcurrent uses Gpm 1 */ -If (LLessEqual(UOM1,9)) { - Scope (\_GPE) { - Method (_L14) { - UCOC() - if (LEqual(GPB1,PLC1)) { - Not(PLC1,PLC1) - Store(PLC1, \_SB.PT1D) - } - } - } -} - -/* USB Port 2 overcurrent uses Gpm 2 */ -If (LLessEqual(UOM2,9)) { - Scope (\_GPE) { - Method (_L15) { - UCOC() - if (LEqual(GPB2,PLC2)) { - Not(PLC2,PLC2) - Store(PLC2, \_SB.PT2D) - } - } - } -} - -/* USB Port 3 overcurrent uses Gpm 3 */ -If (LLessEqual(UOM3,9)) { - Scope (\_GPE) { - Method (_L16) { - UCOC() - if (LEqual(GPB3,PLC3)) { - Not(PLC3,PLC3) - Store(PLC3, \_SB.PT3D) - } - } - } -} - -/* USB Port 4 overcurrent uses Gpm 4 */ -If (LLessEqual(UOM4,9)) { - Scope (\_GPE) { - Method (_L19) { - UCOC() - if (LEqual(GPB4,PLC4)) { - Not(PLC4,PLC4) - Store(PLC4, \_SB.PT4D) - } - } - } -} - -/* USB Port 5 overcurrent uses Gpm 5 */ -If (LLessEqual(UOM5,9)) { - Scope (\_GPE) { - Method (_L1A) { - UCOC() - if (LEqual(GPB5,PLC5)) { - Not(PLC5,PLC5) - Store(PLC5, \_SB.PT5D) - } - } - } -} - -/* USB Port 6 overcurrent uses Gpm 6 */ -If (LLessEqual(UOM6,9)) { - Scope (\_GPE) { - /* Method (_L1C) { */ - Method (_L06) { - UCOC() - if (LEqual(GPB6,PLC6)) { - Not(PLC6,PLC6) - Store(PLC6, \_SB.PT6D) - } - } - } -} - -/* USB Port 7 overcurrent uses Gpm 7 */ -If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { - /* Method (_L1D) { */ - Method (_L07) { - UCOC() - if (LEqual(GPB7,PLC7)) { - Not(PLC7,PLC7) - Store(PLC7, \_SB.PT7D) - } - } - } -} - -/* USB Port 8 overcurrent uses Gpm 8 */ -If (LLessEqual(UOM8,9)) { - Scope (\_GPE) { - Method (_L17) { - if (LEqual(G8IS,PLC8)) { - Not(PLC8,PLC8) - Store(PLC8, \_SB.PT8D) - } - } - } -} - -/* USB Port 9 overcurrent uses Gpm 9 */ -If (LLessEqual(UOM9,9)) { - Scope (\_GPE) { - Method (_L0E) { - if (LEqual(G9IS,0)) { - Store(1,\_SB.PT9D) - } - } - } -} diff --git a/src/mainboard/amd/south_station/acpi_tables.c b/src/mainboard/amd/south_station/acpi_tables.c deleted file mode 100644 index 97ea649..0000000 --- a/src/mainboard/amd/south_station/acpi_tables.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/acpi.h> -#include <arch/ioapic.h> - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); - - /* Write SB800 IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - CONFIG_MAX_CPUS, IO_APIC_ADDR, 0); - - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xF); - - /* 0: mean bus 0--->ISA */ - /* 0: PIC 0 */ - /* 2: APIC 2 */ - /* 5 mean: 0101 --> Edge-triggered, Active high */ - - /* create all subtables for processors */ - /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */ - /* 1: LINT1 connect to NMI */ - - return current; -} diff --git a/src/mainboard/amd/south_station/board_info.txt b/src/mainboard/amd/south_station/board_info.txt deleted file mode 100644 index 6391228..0000000 --- a/src/mainboard/amd/south_station/board_info.txt +++ /dev/null @@ -1,6 +0,0 @@ -Board name: South Station -Category: eval -ROM package: SOIC8 -ROM protocol: SPI -ROM socketed: n -Flashrom support: y diff --git a/src/mainboard/amd/south_station/buildOpts.c b/src/mainboard/amd/south_station/buildOpts.c deleted file mode 100644 index 244229d..0000000 --- a/src/mainboard/amd/south_station/buildOpts.c +++ /dev/null @@ -1,294 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/** - * @file - * - * AMD User options selection for a Brazos platform solution system - * - * This file is placed in the user's platform directory and contains the - * build option selections desired for that platform. - * - * For Information about this file, see @ref platforminstall. - * - */ - -#include <stdlib.h> - - -/* Select the CPU family. */ -#define INSTALL_FAMILY_10_SUPPORT FALSE -#define INSTALL_FAMILY_12_SUPPORT FALSE -#define INSTALL_FAMILY_14_SUPPORT TRUE -#define INSTALL_FAMILY_15_SUPPORT FALSE - -/* Select the CPU socket type. */ -#define INSTALL_G34_SOCKET_SUPPORT FALSE -#define INSTALL_C32_SOCKET_SUPPORT FALSE -#define INSTALL_S1G3_SOCKET_SUPPORT FALSE -#define INSTALL_S1G4_SOCKET_SUPPORT FALSE -#define INSTALL_ASB2_SOCKET_SUPPORT FALSE -#define INSTALL_FS1_SOCKET_SUPPORT FALSE -#define INSTALL_FM1_SOCKET_SUPPORT FALSE -#define INSTALL_FP1_SOCKET_SUPPORT FALSE -#define INSTALL_FT1_SOCKET_SUPPORT TRUE -#define INSTALL_AM3_SOCKET_SUPPORT FALSE - -/* - * Agesa optional capabilities selection. - * Uncomment and mark FALSE those features you wish to include in the build. - * Comment out or mark TRUE those features you want to REMOVE from the build. - */ - -#define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE -#define BLDOPT_REMOVE_FAMILY_12_SUPPORT TRUE -#define BLDOPT_REMOVE_FAMILY_14_SUPPORT FALSE -#define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE - -#define BLDOPT_REMOVE_AM3_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_C32_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FM1_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FP1_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FS1_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FT1_SOCKET_SUPPORT FALSE -#define BLDOPT_REMOVE_G34_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT TRUE - -#define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE -#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE -#define BLDOPT_REMOVE_ECC_SUPPORT FALSE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE -#define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE -#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE -#define BLDOPT_REMOVE_PARALLEL_TRAINING FALSE -#define BLDOPT_REMOVE_DQS_TRAINING FALSE -#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE -#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_ACPI_PSTATES FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PSD FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE - #define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT FALSE -#define BLDOPT_REMOVE_SRAT TRUE -#define BLDOPT_REMOVE_SLIT TRUE -#define BLDOPT_REMOVE_WHEA TRUE -#define BLDOPT_REMOVE_DMI TRUE -#define BLDOPT_REMOVE_HT_ASSIST TRUE -#define BLDOPT_REMOVE_ATM_MODE TRUE -//#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE -//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE -#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE -//#define BLDOPT_REMOVE_C6_STATE TRUE -#define BLDOPT_REMOVE_GFX_RECOVERY TRUE -#define BLDOPT_REMOVE_EARLY_SAMPLES TRUE - - -#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER - -#define BLDCFG_VRM_CURRENT_LIMIT 24000 -//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 -#define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000 -#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 -#define BLDCFG_VRM_SLEW_RATE 5000 -//#define BLDCFG_VRM_NB_SLEW_RATE 5000 -//#define BLDCFG_VRM_ADDITIONAL_DELAY 0 -//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 -#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE -//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE FALSE -#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 6000 -//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 - -//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C' -//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' -//#define BLDCFG_PROCESSOR_SCOPE_IN_SB FALSE -#define BLDCFG_PLAT_NUM_IO_APICS 3 -//#define BLDCFG_PLATFORM_C1E_MODE C1eModeDisabled -//#define BLDCFG_PLATFORM_C1E_OPDATA 0 -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0 -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0 -#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 -#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 -#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 -//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto -#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST -#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE -//#define BLDCFG_STARTING_BUSNUM 0 -//#define BLDCFG_MAXIMUM_BUSNUM 0xf8 -//#define BLDCFG_ALLOCATED_BUSNUMS 0x20 -//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST 0 -//#define BLDCFG_BUID_SWAP_LIST 0 -//#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST 0 -//#define BLDCFG_HTFABRIC_LIMITS_LIST 0 -//#define BLDCFG_HTCHAIN_LIMITS_LIST 0 -//#define BLDCFG_BUS_NUMBERS_LIST 0 -//#define BLDCFG_IGNORE_LINK_LIST 0 -//#define BLDCFG_LINK_SKIP_REGANG_LIST 0 -//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST 0 -//#define BLDCFG_USE_HT_ASSIST TRUE -//#define BLDCFG_USE_ATM_MODE TRUE -//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm -#define BLDCFG_S3_LATE_RESTORE FALSE -//#define BLDCFG_USE_32_BYTE_REFRESH FALSE -//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE -//#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance -//#define BLDCFG_SET_HTCRC_SYNC_FLOOD FALSE -//#define BLDCFG_USE_UNIT_ID_CLUMPING FALSE -//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP 0 -#define BLDCFG_CFG_GNB_HD_AUDIO TRUE -//#define BLDCFG_CFG_ABM_SUPPORT FALSE -//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE 0 -//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 0 -//#define BLDCFG_MEM_INIT_PSTATE 0 -//#define BLDCFG_AMD_PSTATE_CAP_VALUE 0 -#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY -#define BLDCFG_MEMORY_MODE_UNGANGED TRUE -//#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE -//#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE -#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE -#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE -#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE -#define BLDCFG_MEMORY_POWER_DOWN TRUE -#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT -//#define BLDCFG_ONLINE_SPARE FALSE -//#define BLDCFG_MEMORY_PARITY_ENABLE FALSE -#define BLDCFG_BANK_SWIZZLE TRUE -#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY -#define BLDCFG_DQS_TRAINING_CONTROL TRUE -#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE -#define BLDCFG_USE_BURST_MODE FALSE -#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE -//#define BLDCFG_ENABLE_ECC_FEATURE TRUE -//#define BLDCFG_ECC_REDIRECTION FALSE -//#define BLDCFG_SCRUB_DRAM_RATE 0 -//#define BLDCFG_SCRUB_L2_RATE 0 -//#define BLDCFG_SCRUB_L3_RATE 0 -//#define BLDCFG_SCRUB_IC_RATE 0 -//#define BLDCFG_SCRUB_DC_RATE 0 -//#define BLDCFG_ECC_SYNC_FLOOD 0 -//#define BLDCFG_ECC_SYMBOL_SIZE 0 -//#define BLDCFG_1GB_ALIGN FALSE -#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO -#define BLDCFG_UMA_ALLOCATION_SIZE 0 -#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE -#define BLDCFG_UMA_ALIGNMENT NO_UMA_ALIGNED -#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 -#define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000 - -/* - * Agesa configuration values selection. - * Uncomment and specify the value for the configuration options - * needed by the system. - */ -#include <AGESA.h> - -/* The fixed MTRR values to be set after memory initialization. */ -CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = -{ - { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull }, - { AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull }, - { CPU_LIST_TERMINAL } -}; - -/* Include the files that instantiate the configuration definitions. */ - -#include "cpuRegisters.h" -#include "cpuFamRegisters.h" -#include "cpuFamilyTranslation.h" -#include "AdvancedApi.h" -#include "heapManager.h" -#include "CreateStruct.h" -#include "cpuFeatures.h" -#include "Table.h" -#include "cpuEarlyInit.h" -#include "cpuLateInit.h" -#include "GnbInterface.h" - -/***************************************************************************** - * Define the RELEASE VERSION string - * - * The Release Version string should identify the next planned release. - * When a branch is made in preparation for a release, the release manager - * should change/confirm that the branch version of this file contains the - * string matching the desired version for the release. The trunk version of - * the file should always contain a trailing 'X'. This will make sure that a - * development build from trunk will not be confused for a released version. - * The release manager will need to remove the trailing 'X' and update the - * version string as appropriate for the release. The trunk copy of this file - * should also be updated/incremented for the next expected version, + trailing 'X' - ****************************************************************************/ - // This is the delivery package title, "BrazosPI" - // This string MUST be exactly 8 characters long -#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} - - // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long -#define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '} - -/* MEMORY_BUS_SPEED */ -#define DDR400_FREQUENCY 200 ///< DDR 400 -#define DDR533_FREQUENCY 266 ///< DDR 533 -#define DDR667_FREQUENCY 333 ///< DDR 667 -#define DDR800_FREQUENCY 400 ///< DDR 800 -#define DDR1066_FREQUENCY 533 ///< DDR 1066 -#define DDR1333_FREQUENCY 667 ///< DDR 1333 -#define DDR1600_FREQUENCY 800 ///< DDR 1600 -#define DDR1866_FREQUENCY 933 ///< DDR 1866 -#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency - -/* QUANDRANK_TYPE*/ -#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM - -/* USER_MEMORY_TIMING_MODE */ -#define TIMING_MODE_AUTO 0 ///< Use best rate possible -#define TIMING_MODE_LIMITED 1 ///< Set user top limit -#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed - -/* POWER_DOWN_MODE */ -#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode - -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. -#define DFLT_SCRUB_DRAM_RATE (0) -#define DFLT_SCRUB_L2_RATE (0) -#define DFLT_SCRUB_L3_RATE (0) -#define DFLT_SCRUB_IC_RATE (0) -#define DFLT_SCRUB_DC_RATE (0) -#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define DFLT_VRM_SLEW_RATE (5000) - -// Instantiate all solution relevant data. -#include <PlatformInstall.h> diff --git a/src/mainboard/amd/south_station/cmos.layout b/src/mainboard/amd/south_station/cmos.layout deleted file mode 100644 index f9f52f7..0000000 --- a/src/mainboard/amd/south_station/cmos.layout +++ /dev/null @@ -1,68 +0,0 @@ -#***************************************************************************** -# -# This file is part of the coreboot project. -# -# Copyright (C) 2011 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -#***************************************************************************** - -entries - -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#392 3 r 0 unused -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum -# Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - - - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% - -checksums - -checksum 392 983 984 diff --git a/src/mainboard/amd/south_station/devicetree.cb b/src/mainboard/amd/south_station/devicetree.cb deleted file mode 100644 index ccb60ff..0000000 --- a/src/mainboard/amd/south_station/devicetree.cb +++ /dev/null @@ -1,101 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2011 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -chip northbridge/amd/agesa/family14/root_complex - device cpu_cluster 0 on - chip cpu/amd/agesa/family14 - device lapic 0 on end - end - end - device domain 0 on - subsystemid 0x1022 0x1510 inherit - chip northbridge/amd/agesa/family14 - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 - device pci 1.1 on end # Internal HDMI Audio - device pci 4.0 on end # PCIE P2P bridge 0x9604 - device pci 5.0 on end # PCIE P2P bridge 0x9605 - device pci 6.0 on end # PCIE P2P bridge 0x9606 - device pci 7.0 on end # PCIE P2P bridge 0x9607 - device pci 8.0 on end # NB/SB Link P2P bridge - end # agesa northbridge - - chip southbridge/amd/cimx/sb800 - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.1 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.1 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/fintek/f81865f - device pnp 4e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 4e.3 off end # Parallel Port - device pnp 4e.4 off end # Hardware Monitor - device pnp 4e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 4e.6 off end # GPIO - device pnp 4e.a off end # PME - device pnp 4e.10 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 4e.11 off # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - end # f81865f - end #LPC - device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} - device pci 14.5 on end # USB 2 - device pci 15.0 off end # PCIe PortA - device pci 15.1 off end # PCIe PortB - device pci 15.2 off end # PCIe PortC - device pci 15.3 off end # PCIe PortD - device pci 16.0 off end # OHCI USB3 - device pci 16.2 off end # EHCI USB3 - register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow) - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/cimx/sb800 - - chip northbridge/amd/agesa/family14 - - # These seem unnecessary - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - - register "spdAddrLookup" = " - { - { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses - { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses - }" - - end # agesa northbridge - - end #domain -end #northbridge/amd/agesa/family14/root_complex diff --git a/src/mainboard/amd/south_station/dsdt.asl b/src/mainboard/amd/south_station/dsdt.asl deleted file mode 100644 index 5496288..0000000 --- a/src/mainboard/amd/south_station/dsdt.asl +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* DefinitionBlock Statement */ -#include <arch/acpi.h> -DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - OEM_ID, - ACPI_TABLE_CREATOR, - 0x00010001 /* OEM Revision */ - ) -{ /* Start of ASL file */ - /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ - - #include "acpi/mainboard.asl" - - #include <cpu/amd/agesa/family14/acpi/cpu.asl> - - #include "acpi/routing.asl" - - Scope(\_SB) { - /* global utility methods expected within the \_SB scope */ - #include <arch/x86/acpi/globutil.asl> - - Device(PCI0) { - - /* Describe the AMD Northbridge */ - #include <northbridge/amd/agesa/family14/acpi/northbridge.asl> - - /* Describe the AMD Fusion Controller Hub Southbridge */ - #include <southbridge/amd/cimx/sb800/acpi/fch.asl> - - /* Primary (and only) IDE channel */ - Device(IDEC) { - Name(_ADR, 0x00140001) - #include "acpi/ide.asl" - } /* end IDEC */ - - } - } /* End Scope(_SB) */ - - /* Contains the supported sleep states for this chipset */ - #include <southbridge/amd/common/acpi/sleepstates.asl> - - /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */ - #include "acpi/sleep.asl" - - #include "acpi/gpe.asl" -} -/* End of ASL file */ diff --git a/src/mainboard/amd/south_station/irq_tables.c b/src/mainboard/amd/south_station/irq_tables.c deleted file mode 100644 index a066864..0000000 --- a/src/mainboard/amd/south_station/irq_tables.c +++ /dev/null @@ -1,102 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <string.h> -#include <stdint.h> -#include <arch/pirq_routing.h> - -static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, - u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, - u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, - u8 slot, u8 rfu) -{ - pirq_info->bus = bus; - pirq_info->devfn = devfn; - pirq_info->irq[0].link = link0; - pirq_info->irq[0].bitmap = bitmap0; - pirq_info->irq[1].link = link1; - pirq_info->irq[1].bitmap = bitmap1; - pirq_info->irq[2].link = link2; - pirq_info->irq[2].bitmap = bitmap2; - pirq_info->irq[3].link = link3; - pirq_info->irq[3].bitmap = bitmap3; - pirq_info->slot = slot; - pirq_info->rfu = rfu; -} - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - - struct irq_routing_table *pirq; - struct irq_info *pirq_info; - u32 slot_num; - u8 *v; - - u8 sum = 0; - int i; - - /* Align the table to be 16 byte aligned. */ - addr += 15; - addr &= ~15; - - /* This table must be between 0xf0000 & 0x100000 */ - printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); - - pirq = (void *)(addr); - v = (u8 *) (addr); - - pirq->signature = PIRQ_SIGNATURE; - pirq->version = PIRQ_VERSION; - - pirq->rtr_bus = 0; - pirq->rtr_devfn = PCI_DEVFN(0x14, 4); - - pirq->exclusive_irqs = 0; - - pirq->rtr_vendor = 0x1002; - pirq->rtr_device = 0x4384; - - pirq->miniport_data = 0; - - memset(pirq->rfu, 0, sizeof(pirq->rfu)); - - pirq_info = (void *)(&pirq->checksum + 1); - slot_num = 0; - - /* pci bridge */ - write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), - 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, - 0); - pirq_info++; - - slot_num++; - - pirq->size = 32 + 16 * slot_num; - - for (i = 0; i < pirq->size; i++) - sum += v[i]; - - sum = pirq->checksum - sum; - - if (sum != pirq->checksum) { - pirq->checksum = sum; - } - - printk(BIOS_INFO, "write_pirq_routing_table done.\n"); - - return (unsigned long)pirq_info; - -} diff --git a/src/mainboard/amd/south_station/mainboard.c b/src/mainboard/amd/south_station/mainboard.c deleted file mode 100644 index 9b041e0..0000000 --- a/src/mainboard/amd/south_station/mainboard.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <amdblocks/acpimmio.h> -#include <console/console.h> -#include <delay.h> -#include <device/device.h> -#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> /* Platform Specific Definitions */ - -/** - * Southstation using SB GPIO 17/18 to control the Red/Green LED - * These two LEDs can be used to show the OS booting status. - */ -static void southstation_led_init(void) -{ -#define GPIO_FUNCTION 2 //GPIO function -#define SB_GPIO_REG17 17 //Red Light -#define SB_GPIO_REG18 18 //Green Light - - /* multi-function pins switch to GPIO0-35 */ - RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, 1); - - /* select IOMux to function2, corresponds to GPIO */ - RWMEM(ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG17, AccWidthUint8, ~(BIT0 | BIT1), GPIO_FUNCTION); - RWMEM(ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG18, AccWidthUint8, ~(BIT0 | BIT1), GPIO_FUNCTION); - - /* Lighting test */ - RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG17, AccWidthUint8, ~(0xFF), 0x08); //output high - RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG18, AccWidthUint8, ~(0xFF), 0x08); - mdelay(100); - RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG17, AccWidthUint8, ~(0xFF), 0x48); //output low - RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG18, AccWidthUint8, ~(0xFF), 0x48); -} - - -/********************************************** - * Enable the dedicated functions of the board. - **********************************************/ -static void mainboard_enable(struct device *dev) -{ - printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - southstation_led_init(); - - /* - * Initialize ASF registers to an arbitrary address because someone - * long ago set things up this way inside the SPD read code. The - * SPD read code has been made generic and moved out of the board - * directory, so the ASF init is being done here. - */ - pm_write8(0x29, 0x80); - pm_write8(0x28, 0x61); -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/amd/south_station/mptable.c b/src/mainboard/amd/south_station/mptable.c deleted file mode 100644 index c38708e..0000000 --- a/src/mainboard/amd/south_station/mptable.c +++ /dev/null @@ -1,144 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/smp/mpspec.h> -#include <arch/io.h> -#include <arch/ioapic.h> -#include <string.h> -#include <stdint.h> -#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> - -u8 intr_data[] = { - [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */ - [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */ - [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x10,0x11,0x12,0x13 -}; - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - mptable_write_buses(mc, NULL, &bus_isa); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - u8 byte; - - for (byte = 0x0; byte < sizeof(intr_data); byte ++) { - outb(byte | 0x80, 0xC00); - outb(intr_data[byte], 0xC01); - } - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) - - /* APU Internal Graphic Device*/ - PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); - - //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - /* Southbridge HD Audio: */ - PCI_INT(0x0, 0x14, 0x2, 0x12); - - PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */ - PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/amd/south_station/platform_cfg.h b/src/mainboard/amd/south_station/platform_cfg.h deleted file mode 100644 index d39a3ab..0000000 --- a/src/mainboard/amd/south_station/platform_cfg.h +++ /dev/null @@ -1,211 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -#ifndef _PLATFORM_CFG_H_ -#define _PLATFORM_CFG_H_ - -/** - * @def BIOS_SIZE - * BIOS_SIZE_{1,2,4,8,16}M - * - * In SB800, default ROM size is 1M Bytes, if your platform ROM - * bigger than 1M you have to set the ROM size outside CIMx module and - * before AGESA module get call. - */ -#ifndef BIOS_SIZE -#define BIOS_SIZE ((CONFIG_COREBOOT_ROMSIZE_KB >> 10) - 1) -#endif /* BIOS_SIZE */ - -/** - * @def SPREAD_SPECTRUM - * @brief - * 0 - Disable Spread Spectrum function - * 1 - Enable Spread Spectrum function - */ -#define SPREAD_SPECTRUM 0 - -/** - * @def SB_HPET_TIMER - * @brief - * 0 - Disable hpet - * 1 - Enable hpet - */ -#define HPET_TIMER 1 - -/** - * @def USB_CONFIG - * @brief bit[0-6] used to control USB - * 0 - Disable - * 1 - Enable - * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is define at BIT0 - * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is define at BIT1 - * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is define at BIT2 - * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is define at BIT3 - * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is define at BIT4 - * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is define at BIT5 - * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is define at BIT6 - */ -#define USB_CONFIG 0x7F - -/** - * @def PCI_CLOCK_CTRL - * @brief bit[0-4] used for PCI Slots Clock Control, - * 0 - disable - * 1 - enable - * PCI SLOT 0 define at BIT0 - * PCI SLOT 1 define at BIT1 - * PCI SLOT 2 define at BIT2 - * PCI SLOT 3 define at BIT3 - * PCI SLOT 4 define at BIT4 - */ -#define PCI_CLOCK_CTRL 0x1F - -/** - * @def SATA_CONTROLLER - * @brief INCHIP Sata Controller - */ -#define SATA_CONTROLLER CIMX_OPTION_ENABLED - -/** - * @def SATA_MODE - * @brief INCHIP Sata Controller Mode - * NOTE: DO NOT ALLOW SATA & IDE use same mode - */ -#define SATA_MODE CONFIG_SB800_SATA_MODE - -/** - * @brief INCHIP Sata IDE Controller Mode - */ -#define IDE_LEGACY_MODE 0 -#define IDE_NATIVE_MODE 1 - -/** - * @def SATA_IDE_MODE - * @brief INCHIP Sata IDE Controller Mode - * NOTE: DO NOT ALLOW SATA & IDE use same mode - */ -#define SATA_IDE_MODE IDE_LEGACY_MODE - -/** - * @def EXTERNAL_CLOCK - * @brief 00/10: Reference clock from crystal oscillator via - * PAD_XTALI and PAD_XTALO - * - * @def INTERNAL_CLOCK - * @brief 01/11: Reference clock from internal clock through - * CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL - */ -#define EXTERNAL_CLOCK 0x00 -#define INTERNAL_CLOCK 0x01 - -/* NOTE: inagua have to using internal clock, - * otherwise can not detect sata drive - */ -#define SATA_CLOCK_SOURCE INTERNAL_CLOCK - -/** - * @def SATA_PORT_MULT_CAP_RESERVED - * @brief 1 ON, 0 0FF - */ -#define SATA_PORT_MULT_CAP_RESERVED 1 - - -/** - * @def AZALIA_AUTO - * @brief Detect Azalia controller automatically. - * - * @def AZALIA_DISABLE - * @brief Disable Azalia controller. - - * @def AZALIA_ENABLE - * @brief Enable Azalia controller. - */ -#define AZALIA_AUTO 0 -#define AZALIA_DISABLE 1 -#define AZALIA_ENABLE 2 - -/** - * @brief INCHIP HDA controller - */ -#define AZALIA_CONTROLLER AZALIA_AUTO - -/** - * @def AZALIA_PIN_CONFIG - * @brief - * 0 - disable - * 1 - enable - */ -#define AZALIA_PIN_CONFIG 1 - -/** - * @def AZALIA_SDIN_PIN - * @brief - * SDIN0 is define at BIT0 & BIT1 - * 00 - GPIO PIN - * 01 - Reserved - * 10 - As a Azalia SDIN pin - * SDIN1 is define at BIT2 & BIT3 - * SDIN2 is define at BIT4 & BIT5 - * SDIN3 is define at BIT6 & BIT7 - */ -//#define AZALIA_SDIN_PIN 0xAA -#define AZALIA_SDIN_PIN 0x2A - -/** - * @def GPP_CONTROLLER - */ -#define GPP_CONTROLLER CIMX_OPTION_ENABLED - -/** - * @def GPP_CFGMODE - * @brief GPP Link Configuration - * four possible configuration: - * GPP_CFGMODE_X4000 - * GPP_CFGMODE_X2200 - * GPP_CFGMODE_X2110 - * GPP_CFGMODE_X1111 - */ -#define GPP_CFGMODE GPP_CFGMODE_X1111 - -/** - * @def NB_SB_GEN2 - * 0 - Disable - * 1 - Enable - */ -#define NB_SB_GEN2 TRUE - -/** - * @def SB_GPP_GEN2 - * 0 - Disable - * 1 - Enable - */ -#define SB_GPP_GEN2 TRUE - -/** - * @def SB_GPP_UNHIDE_PORTS - * TRUE - ports visible always, even port empty - * FALSE - ports invisible if port empty - */ -#define SB_GPP_UNHIDE_PORTS FALSE - -/** - * @def GEC_CONFIG - * 0 - Enable - * 1 - Disable - */ -#define GEC_CONFIG 0 - -#endif diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c deleted file mode 100644 index 7ccf167..0000000 --- a/src/mainboard/amd/south_station/romstage.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <northbridge/amd/agesa/state_machine.h> -#include <superio/fintek/common/fintek.h> -#include <superio/fintek/f81865f/f81865f.h> -#include <sb_cimx.h> - -#define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) - -void board_BeforeAgesa(struct sysinfo *cb) -{ - sb_Poweron_Init(); - fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/38111 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52cbe4acb4ffac654a5897756a90112ac81d0f97 Gerrit-Change-Number: 38111 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/amd/persimmon: Drop boards with ROMCC_BOOTBLOCK
by HAOUAS Elyes (Code Review) Jan. 7, 2020

Jan. 7, 2020

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38112 ) Change subject: mb/amd/persimmon: Drop boards with ROMCC_BOOTBLOCK ...................................................................... mb/amd/persimmon: Drop boards with ROMCC_BOOTBLOCK ROMCC_BOOTBLOCK is no more. Drop unsupported, unmaintained boards. Change-Id: I07a117abcce379dcae970accc6f75d0ad5ab32f6 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- D src/mainboard/amd/persimmon/BiosCallOuts.c D src/mainboard/amd/persimmon/Kconfig D src/mainboard/amd/persimmon/Kconfig.name D src/mainboard/amd/persimmon/Makefile.inc D src/mainboard/amd/persimmon/OemCustomize.c D src/mainboard/amd/persimmon/OptionsIds.h D src/mainboard/amd/persimmon/acpi/gpe.asl D src/mainboard/amd/persimmon/acpi/ide.asl D src/mainboard/amd/persimmon/acpi/mainboard.asl D src/mainboard/amd/persimmon/acpi/routing.asl D src/mainboard/amd/persimmon/acpi/sata.asl D src/mainboard/amd/persimmon/acpi/sleep.asl D src/mainboard/amd/persimmon/acpi/superio.asl D src/mainboard/amd/persimmon/acpi/usb_oc.asl D src/mainboard/amd/persimmon/acpi_tables.c D src/mainboard/amd/persimmon/board_info.txt D src/mainboard/amd/persimmon/buildOpts.c D src/mainboard/amd/persimmon/cmos.layout D src/mainboard/amd/persimmon/devicetree.cb D src/mainboard/amd/persimmon/dsdt.asl D src/mainboard/amd/persimmon/irq_tables.c D src/mainboard/amd/persimmon/mainboard.c D src/mainboard/amd/persimmon/mptable.c D src/mainboard/amd/persimmon/platform_cfg.h D src/mainboard/amd/persimmon/romstage.c M src/mainboard/pcengines/apu1/BiosCallOuts.c 26 files changed, 0 insertions(+), 2,835 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/38112/1 diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.c b/src/mainboard/amd/persimmon/BiosCallOuts.c deleted file mode 100644 index 60ce3ee..0000000 --- a/src/mainboard/amd/persimmon/BiosCallOuts.c +++ /dev/null @@ -1,92 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <AGESA.h> -#include <amdlib.h> -#include <northbridge/amd/agesa/BiosCallOuts.h> -#include <SB800.h> -#include <stdlib.h> - -static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr); -static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr); - -const BIOS_CALLOUT_STRUCT BiosCallouts[] = -{ - {AGESA_DO_RESET, agesa_Reset }, - {AGESA_READ_SPD, agesa_ReadSpd }, - {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, - {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, - {AGESA_GNB_PCIE_SLOT_RESET, board_GnbPcieSlotReset }, - {AGESA_HOOKBEFORE_DRAM_INIT, board_BeforeDramInit }, - {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, agesa_NoopSuccess }, - {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, - {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, -}; -const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); - -/* Call the host environment interface to provide a user hook opportunity. */ -static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr) -{ - // Unlike e.g. AMD Inagua, Persimmon is unable to vary the RAM voltage. - // Make sure the right speed settings are selected. - ((MEM_DATA_STRUCT*)ConfigPtr)->ParameterListPtr->DDR3Voltage = VOLT1_5; - return AGESA_SUCCESS; -} - -/* PCIE slot reset control */ -static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr) -{ - AGESA_STATUS Status; - UINTN FcnData; - PCIe_SLOT_RESET_INFO *ResetInfo; - - UINT32 GpioMmioAddr; - UINT32 AcpiMmioAddr; - UINT8 Data8; - UINT16 Data16; - - FcnData = Data; - ResetInfo = ConfigPtr; - // Get SB800 MMIO Base (AcpiMmioAddr) - WriteIo8(0xCD6, 0x27); - Data8 = ReadIo8(0xCD7); - Data16 = Data8 << 8; - WriteIo8(0xCD6, 0x26); - Data8 = ReadIo8(0xCD7); - Data16 |= Data8; - AcpiMmioAddr = (UINT32)Data16 << 16; - Status = AGESA_UNSUPPORTED; - GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; - switch (ResetInfo->ResetId) - { - case 46: // GPIO50 = SBGPIO_PCIE_RST# affects LAN0, LAN1, PCIe slot - switch (ResetInfo->ResetControl) { - case AssertSlotReset: - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50); - Data8 &= ~(UINT8)BIT6; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG50, Data8); - Status = AGESA_SUCCESS; - break; - case DeassertSlotReset: - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50); - Data8 |= BIT6; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG50, Data8); - Status = AGESA_SUCCESS; - break; - } - break; - } - return Status; -} diff --git a/src/mainboard/amd/persimmon/Kconfig b/src/mainboard/amd/persimmon/Kconfig deleted file mode 100644 index f243f0f..0000000 --- a/src/mainboard/amd/persimmon/Kconfig +++ /dev/null @@ -1,77 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2011 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -config BOARD_AMD_PERSIMMON - def_bool n - -if BOARD_AMD_PERSIMMON - -config BOARD_SPECIFIC_OPTIONS - def_bool y - #select ROMCC_BOOTBLOCK - select CPU_AMD_AGESA_FAMILY14 - select NORTHBRIDGE_AMD_AGESA_FAMILY14 - select SOUTHBRIDGE_AMD_CIMX_SB800 - select SUPERIO_FINTEK_F81865F - select HAVE_OPTION_TABLE - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select HAVE_ACPI_RESUME - select HAVE_ACPI_TABLES - select BOARD_ROMSIZE_KB_4096 - select GFXUMA - -config MAINBOARD_DIR - string - default "amd/persimmon" - -config MAINBOARD_PART_NUMBER - string - default "Persimmon" - -config HW_MEM_HOLE_SIZEK - hex - default 0x200000 - -config MAX_CPUS - int - default 2 - -config IRQ_SLOT_COUNT - int - default 11 - -config ONBOARD_VGA_IS_PRIMARY - bool - default y - -config VGA_BIOS - bool - default n - -#config VGA_BIOS_FILE -# string "VGA BIOS path and filename" -# depends on VGA_BIOS -# default "rom/video/OntarioGenericVbios.bin" - -config VGA_BIOS_ID - string - default "1002,9802" - -config SB800_AHCI_ROM - bool - default n - -endif # BOARD_AMD_PERSIMMON diff --git a/src/mainboard/amd/persimmon/Kconfig.name b/src/mainboard/amd/persimmon/Kconfig.name deleted file mode 100644 index d50ebbe..0000000 --- a/src/mainboard/amd/persimmon/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -#config BOARD_AMD_PERSIMMON -# bool"Persimmon" diff --git a/src/mainboard/amd/persimmon/Makefile.inc b/src/mainboard/amd/persimmon/Makefile.inc deleted file mode 100644 index ba56286..0000000 --- a/src/mainboard/amd/persimmon/Makefile.inc +++ /dev/null @@ -1,29 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2011 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -ifeq ($(CONFIG_AHCI_BIOS),y) -stripped_ahcibios_id = $(call strip_quotes,$(CONFIG_AHCI_BIOS_ID)) -cbfs-files-$(CONFIG_AHCI_BIOS) += pci$(stripped_ahcibios_id).rom -pci$(stripped_ahcibios_id).rom-file := $(call strip_quotes,$(CONFIG_AHCI_BIOS_FILE)) -pci$(stripped_ahcibios_id).rom-type := optionrom -endif - -romstage-y += buildOpts.c -romstage-y += BiosCallOuts.c -romstage-y += OemCustomize.c - -ramstage-y += buildOpts.c -ramstage-y += BiosCallOuts.c -ramstage-y += OemCustomize.c diff --git a/src/mainboard/amd/persimmon/OemCustomize.c b/src/mainboard/amd/persimmon/OemCustomize.c deleted file mode 100644 index 68de652..0000000 --- a/src/mainboard/amd/persimmon/OemCustomize.c +++ /dev/null @@ -1,123 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -#include <AGESA.h> -#include <northbridge/amd/agesa/state_machine.h> -#include <PlatformMemoryConfiguration.h> - - -static const PCIe_PORT_DESCRIPTOR PortList[] = { - // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, - HotplugDisabled, - PcieGen2, - PcieGen2, - AspmL0sL1, 46) - }, - // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5, - HotplugDisabled, - PcieGen2, - PcieGen2, - AspmL0sL1, 46) - }, - // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, - HotplugDisabled, - PcieGen2, - PcieGen2, - AspmL0sL1, 46) - }, - // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7), - PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 7, - HotplugDisabled, - PcieGen2, - PcieGen2, - AspmL0sL1, 0) - }, - // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) - { - DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, - HotplugDisabled, - PcieGen2, - PcieGen2, - AspmL0sL1, 0) - } -}; - -static const PCIe_DDI_DESCRIPTOR DdiList[] = { - // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeLvds, Aux1, Hdp1) - }, - // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) - { - DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2) - } -}; - -static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { - .Flags = DESCRIPTOR_TERMINATE_LIST, - .SocketId = 0, - .PciePortList = PortList, - .DdiLinkList = DdiList, -}; - -void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) -{ - InitEarly->GnbConfig.PcieComplexList = &PcieComplex; - InitEarly->GnbConfig.PsppPolicy = 0; -} - -/*---------------------------------------------------------------------------------------- - * CUSTOMER OVERIDES MEMORY TABLE - *---------------------------------------------------------------------------------------- - */ - -/* - * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA - * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable - * is populated, AGESA will base its settings on the data from the table. Otherwise, it will - * use its default conservative settings. - */ -static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { - NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2), - NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1), - PSO_END -}; - -void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) -{ - InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; -} diff --git a/src/mainboard/amd/persimmon/OptionsIds.h b/src/mainboard/amd/persimmon/OptionsIds.h deleted file mode 100644 index 2d8381b..0000000 --- a/src/mainboard/amd/persimmon/OptionsIds.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDS_DEBUG_PORT - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE -#define IDSOPT_ASSERT_ENABLED TRUE - -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - -#endif diff --git a/src/mainboard/amd/persimmon/acpi/gpe.asl b/src/mainboard/amd/persimmon/acpi/gpe.asl deleted file mode 100644 index 3cf38c0..0000000 --- a/src/mainboard/amd/persimmon/acpi/gpe.asl +++ /dev/null @@ -1,69 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Scope(\_GPE) { /* Start Scope GPE */ - - /* Legacy PM event */ - Method(_L08) { - /* DBGO("\\_GPE\\_L08\n") */ - } - - /* Temp warning (TWarn) event */ - Method(_L09) { - /* DBGO("\\_GPE\\_L09\n") */ - /* Notify (\_TZ.TZ00, 0x80) */ - } - - /* USB controller PME# */ - Method(_L0B) { - /* DBGO("\\_GPE\\_L0B\n") */ - Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* ExtEvent0 SCI event */ - Method(_L10) { - /* DBGO("\\_GPE\\_L10\n") */ - } - - - /* ExtEvent1 SCI event */ - Method(_L11) { - /* DBGO("\\_GPE\\_L11\n") */ - } - - /* GPIO0 or GEvent8 event */ - Method(_L18) { - /* DBGO("\\_GPE\\_L18\n") */ - Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* Azalia SCI event */ - Method(_L1B) { - /* DBGO("\\_GPE\\_L1B\n") */ - Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - } -} /* End Scope GPE */ - -/* Contains the GPEs for USB overcurrent */ -#include "usb_oc.asl" diff --git a/src/mainboard/amd/persimmon/acpi/ide.asl b/src/mainboard/amd/persimmon/acpi/ide.asl deleted file mode 100644 index 59ea078..0000000 --- a/src/mainboard/amd/persimmon/acpi/ide.asl +++ /dev/null @@ -1,240 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* -Scope (_SB) { - Device(PCI0) { - Device(IDEC) { - Name(_ADR, 0x00140001) - #include "ide.asl" - } - } -} -*/ - -/* Some timing tables */ -Name(UDTT, Package(){ /* Udma timing table */ - 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */ -}) - -Name(MDTT, Package(){ /* MWDma timing table */ - 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */ -}) - -Name(POTT, Package(){ /* Pio timing table */ - 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */ -}) - -/* Some timing register value tables */ -Name(MDRT, Package(){ /* MWDma timing register table */ - 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */ -}) - -Name(PORT, Package(){ - 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */ -}) - -OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */ - Field(ICRG, AnyAcc, NoLock, Preserve) -{ - PPTS, 8, /* Primary PIO Slave Timing */ - PPTM, 8, /* Primary PIO Master Timing */ - OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */ - PMTM, 8, /* Primary MWDMA Master Timing */ - OFFSET(0x08), PPCR, 8, /* Primary PIO Control */ - OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */ - PPSM, 4, /* Primary PIO slave Mode */ - OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */ - OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */ - PDSM, 4, /* Primary UltraDMA Mode */ -} - -Method(GTTM, 1) /* get total time*/ -{ - Store(And(Arg0, 0x0F), Local0) /* Recovery Width */ - Increment(Local0) - Store(ShiftRight(Arg0, 4), Local1) /* Command Width */ - Increment(Local1) - Return(Multiply(30, Add(Local0, Local1))) -} - -Device(PRID) -{ - Name (_ADR, Zero) - Method(_GTM, 0, Serialized) - { - NAME(OTBF, Buffer(20) { /* out buffer */ - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 - }) - - CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */ - CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */ - CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */ - CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */ - CreateDwordField(OTBF, 16, BFFG) /* buffer flags */ - - /* Just return if the channel is disabled */ - If(And(PPCR, 0x01)) { /* primary PIO control */ - Return(OTBF) - } - - /* Always tell them independent timing available and IOChannelReady used on both drives */ - Or(BFFG, 0x1A, BFFG) - - Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */ - Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */ - - If(And(PDCR, 0x01)) { /* It's under UDMA mode */ - Or(BFFG, 0x01, BFFG) - Store(DerefOf(Index(UDTT, PDMM)), DSD0) - } - Else { - Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */ - } - - If(And(PDCR, 0x02)) { /* It's under UDMA mode */ - Or(BFFG, 0x04, BFFG) - Store(DerefOf(Index(UDTT, PDSM)), DSD1) - } - Else { - Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */ - } - - Return(OTBF) /* out buffer */ - } /* End Method(_GTM) */ - - Method(_STM, 3, Serialized) - { - NAME(INBF, Buffer(20) { /* in buffer */ - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 - }) - - CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */ - CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */ - CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */ - CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */ - CreateDwordField(INBF, 16, BFFG) /*buffer flag */ - - Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0) - Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */ - Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1) - Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */ - - Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */ - Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */ - - If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0) - Divide(Local0, 7, PDMM,) - Or(PDCR, 0x01, PDCR) - } - Else { - If(LNotEqual(DSD0, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTM) - } - } - - If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0) - Divide(Local0, 7, PDSM,) - Or(PDCR, 0x02, PDCR) - } - Else { - If(LNotEqual(DSD1, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTS) - } - } - /* Return(INBF) */ - } /*End Method(_STM) */ - Device(MST) - { - Name(_ADR, 0) - Method(_GTF, 0, Serialized) { - Name(CMBF, Buffer(21) { - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 - }) - CreateByteField(CMBF, 1, POMD) - CreateByteField(CMBF, 8, DMMD) - CreateByteField(CMBF, 5, CMDA) - CreateByteField(CMBF, 12, CMDB) - CreateByteField(CMBF, 19, CMDC) - - Store(0xA0, CMDA) - Store(0xA0, CMDB) - Store(0xA0, CMDC) - - Or(PPMM, 0x08, POMD) - - If(And(PDCR, 0x01)) { - Or(PDMM, 0x40, DMMD) - } - Else { - Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) - } - } - Return(CMBF) - } - } /* End Device(MST) */ - - Device(SLAV) - { - Name(_ADR, 1) - Method(_GTF, 0, Serialized) { - Name(CMBF, Buffer(21) { - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 - }) - CreateByteField(CMBF, 1, POMD) - CreateByteField(CMBF, 8, DMMD) - CreateByteField(CMBF, 5, CMDA) - CreateByteField(CMBF, 12, CMDB) - CreateByteField(CMBF, 19, CMDC) - - Store(0xB0, CMDA) - Store(0xB0, CMDB) - Store(0xB0, CMDC) - - Or(PPSM, 0x08, POMD) - - If(And(PDCR, 0x02)) { - Or(PDSM, 0x40, DMMD) - } - Else { - Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) - } - } - Return(CMBF) - } - } /* End Device(SLAV) */ -} diff --git a/src/mainboard/amd/persimmon/acpi/mainboard.asl b/src/mainboard/amd/persimmon/acpi/mainboard.asl deleted file mode 100644 index 702cb92..0000000 --- a/src/mainboard/amd/persimmon/acpi/mainboard.asl +++ /dev/null @@ -1,61 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Data to be patched by the BIOS during POST */ -/* FIXME the patching is not done yet! */ -/* Memory related values */ -Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ -Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ -Name(PBLN, 0x0) /* Length of BIOS area */ - -Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ -Name(HPBA, 0xFED00000) /* Base address of HPET table */ - -/* Some global data */ -Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ -Name(OSV, Ones) /* Assume nothing */ -Name(PMOD, One) /* Assume APIC */ - -Scope(\_SB) { - Method(OSFL, 0){ - - if(LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */ - - if(CondRefOf(\_OSI)) - { - Store(1, OSVR) /* Assume some form of XP */ - if (\_OSI("Windows 2006")) /* Vista */ - { - Store(2, OSVR) - } - } else { - If(WCMP(\_OS,"Linux")) { - Store(3, OSVR) /* Linux */ - } Else { - Store(4, OSVR) /* Gotta be WinCE */ - } - } - Return(OSVR) - } -} - -Scope(\_SI) { - Method(_SST, 1) { - /* DBGO("\\_SI\\_SST\n") */ - /* DBGO(" New Indicator state: ") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - } -} /* End Scope SI */ diff --git a/src/mainboard/amd/persimmon/acpi/routing.asl b/src/mainboard/amd/persimmon/acpi/routing.asl deleted file mode 100644 index 2cf17a7..0000000 --- a/src/mainboard/amd/persimmon/acpi/routing.asl +++ /dev/null @@ -1,337 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* -#include <arch/acpi.h> -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 - ) - { - #include "routing.asl" - } -*/ - -/* Routing is in System Bus scope */ -Scope(\_SB) { - Name(PR0, Package(){ - /* NB devices */ - /* Bus 0, Dev 0 - RS780 Host Controller */ - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ - Package(){0x0001FFFF, 0, INTC, 0 }, - Package(){0x0001FFFF, 1, INTD, 0 }, - /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){0x0002FFFF, 0, INTC, 0 }, - Package(){0x0002FFFF, 1, INTD, 0 }, - Package(){0x0002FFFF, 2, INTA, 0 }, - Package(){0x0002FFFF, 3, INTB, 0 }, - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - Package(){0x0003FFFF, 0, INTD, 0 }, - Package(){0x0003FFFF, 1, INTA, 0 }, - Package(){0x0003FFFF, 2, INTB, 0 }, - Package(){0x0003FFFF, 3, INTC, 0 }, - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, INTA, 0 }, - Package(){0x0004FFFF, 1, INTB, 0 }, - Package(){0x0004FFFF, 2, INTC, 0 }, - Package(){0x0004FFFF, 3, INTD, 0 }, - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - Package(){0x0005FFFF, 0, INTB, 0 }, - Package(){0x0005FFFF, 1, INTC, 0 }, - Package(){0x0005FFFF, 2, INTD, 0 }, - Package(){0x0005FFFF, 3, INTA, 0 }, - /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ - Package(){0x0006FFFF, 0, INTC, 0 }, - Package(){0x0006FFFF, 1, INTD, 0 }, - Package(){0x0006FFFF, 2, INTA, 0 }, - Package(){0x0006FFFF, 3, INTB, 0 }, - /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ - Package(){0x0007FFFF, 0, INTD, 0 }, - Package(){0x0007FFFF, 1, INTA, 0 }, - Package(){0x0007FFFF, 2, INTB, 0 }, - Package(){0x0007FFFF, 3, INTC, 0 }, - - /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ - - - /* SB devices */ - /* Bus 0, Dev 17 - SATA controller */ - Package(){0x0011FFFF, 0, INTD, 0 }, - - /* OHCI, dev 18, 19, 22 func 0 - * EHCI, dev 18, 19, 22 func 2 */ - Package(){0x0012FFFF, 0, INTC, 0 }, /* Dev 12, INTA, handled by INTC device, Global */ - Package(){0x0012FFFF, 1, INTB, 0 }, /* Dev 12, INTB, handled by INTB device, Global */ - - Package(){0x0013FFFF, 0, INTC, 0 }, - Package(){0x0013FFFF, 1, INTB, 0 }, - - Package(){0x0016FFFF, 0, INTC, 0 }, - Package(){0x0016FFFF, 1, INTB, 0 }, - - /* Bus 0, Dev 20 - F0:SMBus/ACPI; F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ - Package(){0x0014FFFF, 0, INTA, 0 }, - Package(){0x0014FFFF, 1, INTB, 0 }, - Package(){0x0014FFFF, 2, INTC, 0 }, - Package(){0x0014FFFF, 3, INTD, 0 }, - - Package(){0x0015FFFF, 0, INTA, 0 }, - Package(){0x0015FFFF, 1, INTB, 0 }, - Package(){0x0015FFFF, 2, INTC, 0 }, - Package(){0x0015FFFF, 3, INTD, 0 }, - }) - - Name(APR0, Package(){ - /* NB devices in APIC mode */ - /* Bus 0, Dev 0 - RS780 Host Controller */ - - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ - Package(){0x0001FFFF, 0, 0, 18 }, - Package(){0x0001FFFF, 1, 0, 19 }, - - /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){0x0002FFFF, 0, 0, 18 }, - /* Package(){0x0002FFFF, 1, 0, 19 }, */ - /* Package(){0x0002FFFF, 2, 0, 16 }, */ - /* Package(){0x0002FFFF, 3, 0, 17 }, */ - - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - Package(){0x0003FFFF, 0, 0, 19 }, - Package(){0x0003FFFF, 1, 0, 16 }, - Package(){0x0003FFFF, 2, 0, 17 }, - Package(){0x0003FFFF, 3, 0, 18 }, - - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, 0, 16 }, - Package(){0x0004FFFF, 1, 0, 17 }, - Package(){0x0004FFFF, 2, 0, 18 }, - Package(){0x0004FFFF, 3, 0, 19 }, - - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - Package(){0x0005FFFF, 0, 0, 17 }, - Package(){0x0005FFFF, 1, 0, 18 }, - Package(){0x0005FFFF, 2, 0, 19 }, - Package(){0x0005FFFF, 3, 0, 16 }, - - /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ - Package(){0x0006FFFF, 0, 0, 18 }, - Package(){0x0006FFFF, 1, 0, 19 }, - Package(){0x0006FFFF, 2, 0, 16 }, - Package(){0x0006FFFF, 3, 0, 17 }, - - /* Bus 0, Dev 7 - PCIe Bridge for network card */ - Package(){0x0007FFFF, 0, 0, 19 }, - Package(){0x0007FFFF, 1, 0, 16 }, - Package(){0x0007FFFF, 2, 0, 17 }, - Package(){0x0007FFFF, 3, 0, 18 }, - - /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ - - /* SB devices in APIC mode */ - /* Bus 0, Dev 17 - SATA controller */ - Package(){0x0011FFFF, 0, 0, 19 }, - - /* OHCI, dev 18, 19, 22 func 0 - * EHCI, dev 18, 19, 22 func 2 */ - Package(){0x0012FFFF, 0, 0, 18 }, - Package(){0x0012FFFF, 1, 0, 17 }, - - Package(){0x0013FFFF, 0, 0, 18 }, - Package(){0x0013FFFF, 1, 0, 17 }, - - Package(){0x0016FFFF, 0, 0, 18 }, - Package(){0x0016FFFF, 1, 0, 17 }, - - /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ - Package(){0x0014FFFF, 0, 0, 16 }, - Package(){0x0014FFFF, 1, 0, 17 }, - Package(){0x0014FFFF, 2, 0, 18 }, - Package(){0x0014FFFF, 3, 0, 19 }, - /* Package(){0x00140004, 2, 0, 18 }, */ - /* Package(){0x00140004, 3, 0, 19 }, */ - /* Package(){0x00140005, 1, 0, 17 }, */ - /* Package(){0x00140006, 1, 0, 17 }, */ - - /* TODO: pcie */ - Package(){0x0015FFFF, 0, 0, 16 }, - Package(){0x0015FFFF, 1, 0, 17 }, - Package(){0x0015FFFF, 2, 0, 18 }, - Package(){0x0015FFFF, 3, 0, 19 }, - }) - - Name(PR1, Package(){ - /* Internal graphics - RS780 VGA, Bus1, Dev5 */ - Package(){0x0005FFFF, 0, INTA, 0 }, - Package(){0x0005FFFF, 1, INTB, 0 }, - Package(){0x0005FFFF, 2, INTC, 0 }, - Package(){0x0005FFFF, 3, INTD, 0 }, - }) - Name(APR1, Package(){ - /* Internal graphics - RS780 VGA, Bus1, Dev5 */ - Package(){0x0005FFFF, 0, 0, 18 }, - Package(){0x0005FFFF, 1, 0, 19 }, - /* Package(){0x0005FFFF, 2, 0, 20 }, */ - /* Package(){0x0005FFFF, 3, 0, 17 }, */ - }) - - Name(PS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - Name(APS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, - }) - Name(APS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, - }) - - Name(PS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, - }) - Name(APS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - - Name(PS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - Name(APS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PS7, Package(){ - /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - Name(APS7, Package(){ - /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, - }) - - Name(PE0, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, - }) - Name(APE0, Package(){ - /* PCIe slot - Hooked to PCIe */ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, - }) - - Name(PE1, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, - }) - Name(APE1, Package(){ - /* PCIe slot - Hooked to PCIe */ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - - Name(PE2, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - Name(APE2, Package(){ - /* PCIe slot - Hooked to PCIe */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PE3, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - Name(APE3, Package(){ - /* PCIe slot - Hooked to PCIe */ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, - }) - - Name(PCIB, Package(){ - /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Func 4. */ - Package(){0x0003FFFF, 0, 0, 0x14 }, - Package(){0x0003FFFF, 1, 0, 0x15 }, - Package(){0x0003FFFF, 2, 0, 0x16 }, - Package(){0x0003FFFF, 3, 0, 0x17 }, - Package(){0x0004FFFF, 0, 0, 0x15 }, - Package(){0x0004FFFF, 1, 0, 0x16 }, - Package(){0x0004FFFF, 2, 0, 0x17 }, - Package(){0x0004FFFF, 3, 0, 0x14 }, - Package(){0x0005FFFF, 0, 0, 0x16 }, - Package(){0x0005FFFF, 1, 0, 0x17 }, - Package(){0x0005FFFF, 2, 0, 0x14 }, - Package(){0x0005FFFF, 3, 0, 0x15 }, - }) -} diff --git a/src/mainboard/amd/persimmon/acpi/sata.asl b/src/mainboard/amd/persimmon/acpi/sata.asl deleted file mode 100644 index 9e0e535..0000000 --- a/src/mainboard/amd/persimmon/acpi/sata.asl +++ /dev/null @@ -1,145 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* simple name description */ - -/* -Scope (_SB) { - Device(PCI0) { - Device(SATA) { - Name(_ADR, 0x00110000) - #include "sata.asl" - } - } -} -*/ - -Name(STTM, Buffer(20) { - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x1f, 0x00, 0x00, 0x00 -}) - -/* Start by clearing the PhyRdyChg bits */ -Method(_INI) { - \_GPE._L1F() -} - -Device(PMRY) -{ - Name(_ADR, 0) - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(PMST) { - Name(_ADR, 0) - Method(_STA,0) { - if (LGreater(P0IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - }/* end of PMST */ - - Device(PSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (LGreater(P1IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of PSLA */ -} /* end of PMRY */ - - -Device(SEDY) -{ - Name(_ADR, 1) /* IDE Scondary Channel */ - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(SMST) - { - Name(_ADR, 0) - Method(_STA,0) { - if (LGreater(P2IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SMST */ - - Device(SSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (LGreater(P3IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SSLA */ -} /* end of SEDY */ - -/* SATA Hot Plug Support */ -Scope(\_GPE) { - Method(_L1F,0x0,NotSerialized) { - if (\_SB.P0PR) { - if (LGreater(\_SB.P0IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P0PR) - } - - if (\_SB.P1PR) { - if (LGreater(\_SB.P1IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P1PR) - } - - if (\_SB.P2PR) { - if (LGreater(\_SB.P2IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P2PR) - } - - if (\_SB.P3PR) { - if (LGreater(\_SB.P3IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P3PR) - } - } -} diff --git a/src/mainboard/amd/persimmon/acpi/sleep.asl b/src/mainboard/amd/persimmon/acpi/sleep.asl deleted file mode 100644 index 47de049..0000000 --- a/src/mainboard/amd/persimmon/acpi/sleep.asl +++ /dev/null @@ -1,117 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Wake status package */ -Name(WKST,Package(){Zero, Zero}) - -/* -* \_PTS - Prepare to Sleep method -* -* Entry: -* Arg0=The value of the sleeping state S1=1, S2=2, etc -* -* Exit: -* -none- -* -* The _PTS control method is executed at the beginning of the sleep process -* for S1-S5. The sleeping value is passed to the _PTS control method. This -* control method may be executed a relatively long time before entering the -* sleep state and the OS may abort the operation without notification to -* the ACPI driver. This method cannot modify the configuration or power -* state of any device in the system. -*/ -Method(\_PTS, 1) { - /* DBGO("\\_PTS\n") */ - /* DBGO("From S0 to S") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - - /* Don't allow PCIRST# to reset USB */ - if (LEqual(Arg0,3)){ - Store(0,URRE) - } - - /* Clear sleep SMI status flag and enable sleep SMI trap. */ - /*Store(One, CSSM) - Store(One, SSEN)*/ - - /* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(\_SB.SBRI, 0x13)) { - * Store(0,\_SB.PWDE) - *} - */ - - /* Clear wake status structure. */ - Store(0, Index(WKST,0)) - Store(0, Index(WKST,1)) -} /* End Method(\_PTS) */ - -/* -* \_BFS OEM Back From Sleep method -* -* Entry: -* Arg0=The value of the sleeping state S1=1, S2=2 -* -* Exit: -* -none- -*/ -Method(\_BFS, 1) { - /* DBGO("\\_BFS\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ -} - -/* -* \_WAK System Wake method -* -* Entry: -* Arg0=The value of the sleeping state S1=1, S2=2 -* -* Exit: -* Return package of 2 DWords -* Dword 1 - Status -* 0x00000000 wake succeeded -* 0x00000001 Wake was signaled but failed due to lack of power -* 0x00000002 Wake was signaled but failed due to thermal condition -* Dword 2 - Power Supply state -* if non-zero the effective S-state the power supply entered -*/ -Method(\_WAK, 1) { - /* DBGO("\\_WAK\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - - /* Re-enable HPET */ - Store(1,HPDE) - - /* Restore PCIRST# so it resets USB */ - if (LEqual(Arg0,3)){ - Store(1,URRE) - } - - /* Arbitrarily clear PciExpWakeStatus */ - Store(PWST, Local1) - Store(Local1, PWST) - - /* if (DeRefOf(Index(WKST,0))) { - * Store(0, Index(WKST,1)) - * } else { - * Store(Arg0, Index(WKST,1)) - * } - */ - Return(WKST) -} /* End Method(\_WAK) */ diff --git a/src/mainboard/amd/persimmon/acpi/superio.asl b/src/mainboard/amd/persimmon/acpi/superio.asl deleted file mode 100644 index daf6e91..0000000 --- a/src/mainboard/amd/persimmon/acpi/superio.asl +++ /dev/null @@ -1,14 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* No Super I/O device or functionality yet */ diff --git a/src/mainboard/amd/persimmon/acpi/usb_oc.asl b/src/mainboard/amd/persimmon/acpi/usb_oc.asl deleted file mode 100644 index a209909..0000000 --- a/src/mainboard/amd/persimmon/acpi/usb_oc.asl +++ /dev/null @@ -1,171 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* simple name description */ -/* -#include <arch/acpi.h> -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 - ) - { - #include "usb.asl" - } -*/ - -/* USB overcurrent mapping pins. */ -Name(UOM0, 0) -Name(UOM1, 2) -Name(UOM2, 0) -Name(UOM3, 7) -Name(UOM4, 2) -Name(UOM5, 2) -Name(UOM6, 6) -Name(UOM7, 2) -Name(UOM8, 6) -Name(UOM9, 6) - -Method(UCOC, 0) { - Sleep(20) - Store(0x13,CMTI) - Store(0,GPSL) -} - -/* USB Port 0 overcurrent uses Gpm 0 */ -If(LLessEqual(UOM0,9)) { - Scope (\_GPE) { - Method (_L13) { - UCOC() - if(LEqual(GPB0,PLC0)) { - Not(PLC0,PLC0) - Store(PLC0, \_SB.PT0D) - } - } - } -} - -/* USB Port 1 overcurrent uses Gpm 1 */ -If (LLessEqual(UOM1,9)) { - Scope (\_GPE) { - Method (_L14) { - UCOC() - if (LEqual(GPB1,PLC1)) { - Not(PLC1,PLC1) - Store(PLC1, \_SB.PT1D) - } - } - } -} - -/* USB Port 2 overcurrent uses Gpm 2 */ -If (LLessEqual(UOM2,9)) { - Scope (\_GPE) { - Method (_L15) { - UCOC() - if (LEqual(GPB2,PLC2)) { - Not(PLC2,PLC2) - Store(PLC2, \_SB.PT2D) - } - } - } -} - -/* USB Port 3 overcurrent uses Gpm 3 */ -If (LLessEqual(UOM3,9)) { - Scope (\_GPE) { - Method (_L16) { - UCOC() - if (LEqual(GPB3,PLC3)) { - Not(PLC3,PLC3) - Store(PLC3, \_SB.PT3D) - } - } - } -} - -/* USB Port 4 overcurrent uses Gpm 4 */ -If (LLessEqual(UOM4,9)) { - Scope (\_GPE) { - Method (_L19) { - UCOC() - if (LEqual(GPB4,PLC4)) { - Not(PLC4,PLC4) - Store(PLC4, \_SB.PT4D) - } - } - } -} - -/* USB Port 5 overcurrent uses Gpm 5 */ -If (LLessEqual(UOM5,9)) { - Scope (\_GPE) { - Method (_L1A) { - UCOC() - if (LEqual(GPB5,PLC5)) { - Not(PLC5,PLC5) - Store(PLC5, \_SB.PT5D) - } - } - } -} - -/* USB Port 6 overcurrent uses Gpm 6 */ -If (LLessEqual(UOM6,9)) { - Scope (\_GPE) { - /* Method (_L1C) { */ - Method (_L06) { - UCOC() - if (LEqual(GPB6,PLC6)) { - Not(PLC6,PLC6) - Store(PLC6, \_SB.PT6D) - } - } - } -} - -/* USB Port 7 overcurrent uses Gpm 7 */ -If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { - /* Method (_L1D) { */ - Method (_L07) { - UCOC() - if (LEqual(GPB7,PLC7)) { - Not(PLC7,PLC7) - Store(PLC7, \_SB.PT7D) - } - } - } -} - -/* USB Port 8 overcurrent uses Gpm 8 */ -If (LLessEqual(UOM8,9)) { - Scope (\_GPE) { - Method (_L17) { - if (LEqual(G8IS,PLC8)) { - Not(PLC8,PLC8) - Store(PLC8, \_SB.PT8D) - } - } - } -} - -/* USB Port 9 overcurrent uses Gpm 9 */ -If (LLessEqual(UOM9,9)) { - Scope (\_GPE) { - Method (_L0E) { - if (LEqual(G9IS,0)) { - Store(1,\_SB.PT9D) - } - } - } -} diff --git a/src/mainboard/amd/persimmon/acpi_tables.c b/src/mainboard/amd/persimmon/acpi_tables.c deleted file mode 100644 index 97ea649..0000000 --- a/src/mainboard/amd/persimmon/acpi_tables.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/acpi.h> -#include <arch/ioapic.h> - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); - - /* Write SB800 IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - CONFIG_MAX_CPUS, IO_APIC_ADDR, 0); - - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xF); - - /* 0: mean bus 0--->ISA */ - /* 0: PIC 0 */ - /* 2: APIC 2 */ - /* 5 mean: 0101 --> Edge-triggered, Active high */ - - /* create all subtables for processors */ - /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */ - /* 1: LINT1 connect to NMI */ - - return current; -} diff --git a/src/mainboard/amd/persimmon/board_info.txt b/src/mainboard/amd/persimmon/board_info.txt deleted file mode 100644 index 85cb19a..0000000 --- a/src/mainboard/amd/persimmon/board_info.txt +++ /dev/null @@ -1,5 +0,0 @@ -Board name: DBFT1-00-EVAL-KT (Persimmon) -Category: eval -ROM protocol: SPI -ROM socketed: n -Flashrom support: y diff --git a/src/mainboard/amd/persimmon/buildOpts.c b/src/mainboard/amd/persimmon/buildOpts.c deleted file mode 100644 index d99cc81..0000000 --- a/src/mainboard/amd/persimmon/buildOpts.c +++ /dev/null @@ -1,294 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/** - * @file - * - * AMD User options selection for a Brazos platform solution system - * - * This file is placed in the user's platform directory and contains the - * build option selections desired for that platform. - * - * For Information about this file, see @ref platforminstall. - * - */ - -#include <stdlib.h> - - -/* Select the CPU family. */ -#define INSTALL_FAMILY_10_SUPPORT FALSE -#define INSTALL_FAMILY_12_SUPPORT FALSE -#define INSTALL_FAMILY_14_SUPPORT TRUE -#define INSTALL_FAMILY_15_SUPPORT FALSE - -/* Select the CPU socket type. */ -#define INSTALL_G34_SOCKET_SUPPORT FALSE -#define INSTALL_C32_SOCKET_SUPPORT FALSE -#define INSTALL_S1G3_SOCKET_SUPPORT FALSE -#define INSTALL_S1G4_SOCKET_SUPPORT FALSE -#define INSTALL_ASB2_SOCKET_SUPPORT FALSE -#define INSTALL_FS1_SOCKET_SUPPORT FALSE -#define INSTALL_FM1_SOCKET_SUPPORT FALSE -#define INSTALL_FP1_SOCKET_SUPPORT FALSE -#define INSTALL_FT1_SOCKET_SUPPORT TRUE -#define INSTALL_AM3_SOCKET_SUPPORT FALSE - -/* - * Agesa optional capabilities selection. - * Uncomment and mark FALSE those features you wish to include in the build. - * Comment out or mark TRUE those features you want to REMOVE from the build. - */ - -#define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE -#define BLDOPT_REMOVE_FAMILY_12_SUPPORT TRUE -#define BLDOPT_REMOVE_FAMILY_14_SUPPORT FALSE -#define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE - -#define BLDOPT_REMOVE_AM3_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_C32_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FM1_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FP1_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FS1_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FT1_SOCKET_SUPPORT FALSE -#define BLDOPT_REMOVE_G34_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT TRUE - -#define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE -#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE -#define BLDOPT_REMOVE_ECC_SUPPORT FALSE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE -#define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE -#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE -#define BLDOPT_REMOVE_PARALLEL_TRAINING FALSE -#define BLDOPT_REMOVE_DQS_TRAINING FALSE -#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE -#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_ACPI_PSTATES FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PSD FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE - #define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT FALSE -#define BLDOPT_REMOVE_SRAT FALSE -#define BLDOPT_REMOVE_SLIT FALSE -#define BLDOPT_REMOVE_WHEA FALSE -#define BLDOPT_REMOVE_DMI TRUE -#define BLDOPT_REMOVE_HT_ASSIST TRUE -#define BLDOPT_REMOVE_ATM_MODE TRUE -//#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE -//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE -#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE -//#define BLDOPT_REMOVE_C6_STATE TRUE -#define BLDOPT_REMOVE_GFX_RECOVERY TRUE -#define BLDOPT_REMOVE_EARLY_SAMPLES TRUE - - -#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER - -#define BLDCFG_VRM_CURRENT_LIMIT 24000 -//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 -#define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000 -#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 -#define BLDCFG_VRM_SLEW_RATE 5000 -//#define BLDCFG_VRM_NB_SLEW_RATE 5000 -//#define BLDCFG_VRM_ADDITIONAL_DELAY 0 -//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 -#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE -//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE FALSE -#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 6000 -//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 - -//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C' -//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' -//#define BLDCFG_PROCESSOR_SCOPE_IN_SB FALSE -#define BLDCFG_PLAT_NUM_IO_APICS 3 -//#define BLDCFG_PLATFORM_C1E_MODE C1eModeDisabled -//#define BLDCFG_PLATFORM_C1E_OPDATA 0 -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0 -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0 -#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 -#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 -#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 -//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto -#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST -#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE -//#define BLDCFG_STARTING_BUSNUM 0 -//#define BLDCFG_MAXIMUM_BUSNUM 0xf8 -//#define BLDCFG_ALLOCATED_BUSNUMS 0x20 -//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST 0 -//#define BLDCFG_BUID_SWAP_LIST 0 -//#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST 0 -//#define BLDCFG_HTFABRIC_LIMITS_LIST 0 -//#define BLDCFG_HTCHAIN_LIMITS_LIST 0 -//#define BLDCFG_BUS_NUMBERS_LIST 0 -//#define BLDCFG_IGNORE_LINK_LIST 0 -//#define BLDCFG_LINK_SKIP_REGANG_LIST 0 -//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST 0 -//#define BLDCFG_USE_HT_ASSIST TRUE -//#define BLDCFG_USE_ATM_MODE TRUE -//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm -#define BLDCFG_S3_LATE_RESTORE TRUE -//#define BLDCFG_USE_32_BYTE_REFRESH FALSE -//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE -//#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance -//#define BLDCFG_SET_HTCRC_SYNC_FLOOD FALSE -//#define BLDCFG_USE_UNIT_ID_CLUMPING FALSE -//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP 0 -#define BLDCFG_CFG_GNB_HD_AUDIO FALSE -//#define BLDCFG_CFG_ABM_SUPPORT FALSE -//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE 0 -//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 0 -//#define BLDCFG_MEM_INIT_PSTATE 0 -//#define BLDCFG_AMD_PSTATE_CAP_VALUE 0 -#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY -#define BLDCFG_MEMORY_MODE_UNGANGED TRUE -//#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE -//#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE -#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE -#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE -#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE -#define BLDCFG_MEMORY_POWER_DOWN TRUE -#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT -//#define BLDCFG_ONLINE_SPARE FALSE -//#define BLDCFG_MEMORY_PARITY_ENABLE FALSE -#define BLDCFG_BANK_SWIZZLE TRUE -#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY -#define BLDCFG_DQS_TRAINING_CONTROL TRUE -#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE -#define BLDCFG_USE_BURST_MODE FALSE -#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE -//#define BLDCFG_ENABLE_ECC_FEATURE TRUE -//#define BLDCFG_ECC_REDIRECTION FALSE -//#define BLDCFG_SCRUB_DRAM_RATE 0 -//#define BLDCFG_SCRUB_L2_RATE 0 -//#define BLDCFG_SCRUB_L3_RATE 0 -//#define BLDCFG_SCRUB_IC_RATE 0 -//#define BLDCFG_SCRUB_DC_RATE 0 -//#define BLDCFG_ECC_SYNC_FLOOD 0 -//#define BLDCFG_ECC_SYMBOL_SIZE 0 -//#define BLDCFG_1GB_ALIGN FALSE -#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO -#define BLDCFG_UMA_ALLOCATION_SIZE 0 -#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE -#define BLDCFG_UMA_ALIGNMENT NO_UMA_ALIGNED -#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 -#define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000 - -/* - * Agesa configuration values selection. - * Uncomment and specify the value for the configuration options - * needed by the system. - */ -#include <AGESA.h> - -/* The fixed MTRR values to be set after memory initialization. */ -CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = -{ - { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull }, - { AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull }, - { CPU_LIST_TERMINAL } -}; - -/* Include the files that instantiate the configuration definitions. */ - -#include "cpuRegisters.h" -#include "cpuFamRegisters.h" -#include "cpuFamilyTranslation.h" -#include "AdvancedApi.h" -#include "heapManager.h" -#include "CreateStruct.h" -#include "cpuFeatures.h" -#include "Table.h" -#include "cpuEarlyInit.h" -#include "cpuLateInit.h" -#include "GnbInterface.h" - -/***************************************************************************** - * Define the RELEASE VERSION string - * - * The Release Version string should identify the next planned release. - * When a branch is made in preparation for a release, the release manager - * should change/confirm that the branch version of this file contains the - * string matching the desired version for the release. The trunk version of - * the file should always contain a trailing 'X'. This will make sure that a - * development build from trunk will not be confused for a released version. - * The release manager will need to remove the trailing 'X' and update the - * version string as appropriate for the release. The trunk copy of this file - * should also be updated/incremented for the next expected version, + trailing 'X' - ****************************************************************************/ -// This is the delivery package title, "BrazosPI" -// This string MUST be exactly 8 characters long -#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} - -// This is the release version number of the AGESA component -// This string MUST be exactly 12 characters long -#define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '} - -/* MEMORY_BUS_SPEED */ -#define DDR400_FREQUENCY 200 ///< DDR 400 -#define DDR533_FREQUENCY 266 ///< DDR 533 -#define DDR667_FREQUENCY 333 ///< DDR 667 -#define DDR800_FREQUENCY 400 ///< DDR 800 -#define DDR1066_FREQUENCY 533 ///< DDR 1066 -#define DDR1333_FREQUENCY 667 ///< DDR 1333 -#define DDR1600_FREQUENCY 800 ///< DDR 1600 -#define DDR1866_FREQUENCY 933 ///< DDR 1866 -#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency - -/* QUANDRANK_TYPE*/ -#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM - -/* USER_MEMORY_TIMING_MODE */ -#define TIMING_MODE_AUTO 0 ///< Use best rate possible -#define TIMING_MODE_LIMITED 1 ///< Set user top limit -#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed - -/* POWER_DOWN_MODE */ -#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode - -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. -#define DFLT_SCRUB_DRAM_RATE (0) -#define DFLT_SCRUB_L2_RATE (0) -#define DFLT_SCRUB_L3_RATE (0) -#define DFLT_SCRUB_IC_RATE (0) -#define DFLT_SCRUB_DC_RATE (0) -#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define DFLT_VRM_SLEW_RATE (5000) - -// Instantiate all solution relevant data. -#include <PlatformInstall.h> diff --git a/src/mainboard/amd/persimmon/cmos.layout b/src/mainboard/amd/persimmon/cmos.layout deleted file mode 100644 index f9f52f7..0000000 --- a/src/mainboard/amd/persimmon/cmos.layout +++ /dev/null @@ -1,68 +0,0 @@ -#***************************************************************************** -# -# This file is part of the coreboot project. -# -# Copyright (C) 2011 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -#***************************************************************************** - -entries - -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#392 3 r 0 unused -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum -# Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - - - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% - -checksums - -checksum 392 983 984 diff --git a/src/mainboard/amd/persimmon/devicetree.cb b/src/mainboard/amd/persimmon/devicetree.cb deleted file mode 100644 index 73cf19d..0000000 --- a/src/mainboard/amd/persimmon/devicetree.cb +++ /dev/null @@ -1,151 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2011 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -chip northbridge/amd/agesa/family14/root_complex - device cpu_cluster 0 on - chip cpu/amd/agesa/family14 - device lapic 0 on end - end - end - device domain 0 on - subsystemid 0x1022 0x1510 inherit - chip northbridge/amd/agesa/family14 - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456] - device pci 4.0 on end # PCIE P2P bridge on-board NIC - device pci 5.0 off end # PCIE P2P bridge - device pci 6.0 on end # PCIE P2P bridge PCIe slot - device pci 7.0 off end # PCIE P2P bridge - device pci 8.0 off end # NB/SB Link P2P bridge - end # agesa northbridge - - chip southbridge/amd/cimx/sb800 - device pci 11.0 on end # SATA - device pci 12.0 on end # OHCI USB 0-4 - device pci 12.2 on end # EHCI USB 0-4 - device pci 13.0 on end # OHCI USB 5-9 - device pci 13.2 on end # EHCI USB 5-9 - device pci 14.0 on end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/fintek/f81865f - device pnp 4e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 4e.3 off end # Parallel Port - device pnp 4e.4 off end # Hardware Monitor - device pnp 4e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 4e.6 off end # GPIO - device pnp 4e.a off end # PME - device pnp 4e.10 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 4e.11 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - end # f81865f - end #LPC - device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} - device pci 14.5 off end # OHCI FS/LS USB - device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699) - device pci 15.0 off end # PCIe PortA - device pci 15.1 off end # PCIe PortB - device pci 15.2 off end # PCIe PortC - device pci 15.3 off end # PCIe PortD - device pci 16.0 off end # OHCI USB 10-13 - device pci 16.2 off end # EHCI USB 10-13 - register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow) - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - - #set up SB800 Fan control registers and IMC fan controls - register "imc_port_address" = "0x6E" # 0x2E and 0x6E are common - register "fan0_enabled" = "1" - register "fan1_enabled" = "1" - register "imc_fan_zone0_enabled" = "1" - register "imc_fan_zone1_enabled" = "1" - - register "fan0_config_vals" = "{ \ - FAN_INPUT_INTERNAL_DIODE, FAN_POLARITY_HIGH, \ - FREQ_25KHZ, 0x08, 0x00, 0x00, 0x00, 0x00,\ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }" - register "fan1_config_vals" = "{ \ - FAN_INPUT_INTERNAL_DIODE, FAN_POLARITY_HIGH, \ - FREQ_25KHZ, 0x10, 0x00, 0x00, 0x00, 0x00, \ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }" - - register "imc_zone0_mode1" = " \ - IMC_MODE1_FAN_ENABLED | IMC_MODE1_FAN_IMC_CONTROLLED | \ - IMC_MODE1_FAN_STEP_MODE | IMC_MODE1_FANOUT0" - register "imc_zone0_mode2" = " IMC_MODE2_TEMPIN_SB_TSI | \ - IMC_MODE2_FANIN0 | IMC_MODE2_TEMP_AVERAGING_DISABLED" - register "imc_zone0_temp_offset" = "0x00" # No temp offset - register "imc_zone0_hysteresis" = "0x05" # Degrees C Hysteresis - register "imc_zone0_smbus_addr" = "0x98" # Temp Sensor SMBus address - register "imc_zone0_smbus_num" = "IMC_TEMP_SENSOR_ON_SMBUS_3" # SMBUS number - register "imc_zone0_pwm_step" = "0x01" # Fan PWM stepping rate - register "imc_zone0_ramping" = "0x00" # Disable Fan PWM ramping and stepping - - register "imc_zone1_mode1" = " \ - IMC_MODE1_FAN_ENABLED | IMC_MODE1_FAN_IMC_CONTROLLED | \ - IMC_MODE1_FAN_STEP_MODE | IMC_MODE1_FANOUT1" - register "imc_zone1_mode2" = " IMC_MODE2_TEMPIN_SB_TSI | \ - IMC_MODE2_FANIN1 | IMC_MODE2_TEMP_AVERAGING_DISABLED" - register "imc_zone1_temp_offset" = "0x00" # No temp offset - register "imc_zone1_hysteresis" = "0x05" # Degrees C Hysteresis - register "imc_zone1_smbus_addr" = "0x98" # Temp Sensor SMBus address - register "imc_zone1_smbus_num" = "IMC_TEMP_SENSOR_ON_SMBUS_3" # SMBUS number - register "imc_zone1_pwm_step" = "0x01" # Fan PWM stepping rate - register "imc_zone1_ramping" = "0x00" # Disable Fan PWM ramping and stepping - - # T56N has a Maximum operating temperature of 90C - # ZONEX_THRESHOLDS - _AC0 - _AC7, _CRT - Temp Threshold in degrees C - # ZONEX_FANSPEEDS - Fan speeds as a "percentage" - register "imc_zone0_thresholds" = "{ 87, 82, 77, 72, 65, 1, 0, 0, 90 }" - register "imc_zone0_fanspeeds" = "{100, 7, 5, 4, 3, 2, 0, 0 }" - register "imc_zone1_thresholds" = "{ 85, 80, 75, 65, 1, 0, 0, 0, 90 }" - register "imc_zone1_fanspeeds" = "{100, 10, 6, 4, 3, 0, 0, 0 }" - - end #southbridge/amd/cimx/sb800 - - chip northbridge/amd/agesa/family14 - - # These seem unnecessary - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - device pci 18.6 on end - device pci 18.7 on end - - register "spdAddrLookup" = " - { - { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses - { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses - }" - - end # agesa northbridge - - end #domain -end #northbridge/amd/agesa/family14/root_complex diff --git a/src/mainboard/amd/persimmon/dsdt.asl b/src/mainboard/amd/persimmon/dsdt.asl deleted file mode 100644 index 5496288..0000000 --- a/src/mainboard/amd/persimmon/dsdt.asl +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* DefinitionBlock Statement */ -#include <arch/acpi.h> -DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - OEM_ID, - ACPI_TABLE_CREATOR, - 0x00010001 /* OEM Revision */ - ) -{ /* Start of ASL file */ - /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ - - #include "acpi/mainboard.asl" - - #include <cpu/amd/agesa/family14/acpi/cpu.asl> - - #include "acpi/routing.asl" - - Scope(\_SB) { - /* global utility methods expected within the \_SB scope */ - #include <arch/x86/acpi/globutil.asl> - - Device(PCI0) { - - /* Describe the AMD Northbridge */ - #include <northbridge/amd/agesa/family14/acpi/northbridge.asl> - - /* Describe the AMD Fusion Controller Hub Southbridge */ - #include <southbridge/amd/cimx/sb800/acpi/fch.asl> - - /* Primary (and only) IDE channel */ - Device(IDEC) { - Name(_ADR, 0x00140001) - #include "acpi/ide.asl" - } /* end IDEC */ - - } - } /* End Scope(_SB) */ - - /* Contains the supported sleep states for this chipset */ - #include <southbridge/amd/common/acpi/sleepstates.asl> - - /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */ - #include "acpi/sleep.asl" - - #include "acpi/gpe.asl" -} -/* End of ASL file */ diff --git a/src/mainboard/amd/persimmon/irq_tables.c b/src/mainboard/amd/persimmon/irq_tables.c deleted file mode 100644 index a066864..0000000 --- a/src/mainboard/amd/persimmon/irq_tables.c +++ /dev/null @@ -1,102 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <string.h> -#include <stdint.h> -#include <arch/pirq_routing.h> - -static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, - u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, - u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, - u8 slot, u8 rfu) -{ - pirq_info->bus = bus; - pirq_info->devfn = devfn; - pirq_info->irq[0].link = link0; - pirq_info->irq[0].bitmap = bitmap0; - pirq_info->irq[1].link = link1; - pirq_info->irq[1].bitmap = bitmap1; - pirq_info->irq[2].link = link2; - pirq_info->irq[2].bitmap = bitmap2; - pirq_info->irq[3].link = link3; - pirq_info->irq[3].bitmap = bitmap3; - pirq_info->slot = slot; - pirq_info->rfu = rfu; -} - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - - struct irq_routing_table *pirq; - struct irq_info *pirq_info; - u32 slot_num; - u8 *v; - - u8 sum = 0; - int i; - - /* Align the table to be 16 byte aligned. */ - addr += 15; - addr &= ~15; - - /* This table must be between 0xf0000 & 0x100000 */ - printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); - - pirq = (void *)(addr); - v = (u8 *) (addr); - - pirq->signature = PIRQ_SIGNATURE; - pirq->version = PIRQ_VERSION; - - pirq->rtr_bus = 0; - pirq->rtr_devfn = PCI_DEVFN(0x14, 4); - - pirq->exclusive_irqs = 0; - - pirq->rtr_vendor = 0x1002; - pirq->rtr_device = 0x4384; - - pirq->miniport_data = 0; - - memset(pirq->rfu, 0, sizeof(pirq->rfu)); - - pirq_info = (void *)(&pirq->checksum + 1); - slot_num = 0; - - /* pci bridge */ - write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), - 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, - 0); - pirq_info++; - - slot_num++; - - pirq->size = 32 + 16 * slot_num; - - for (i = 0; i < pirq->size; i++) - sum += v[i]; - - sum = pirq->checksum - sum; - - if (sum != pirq->checksum) { - pirq->checksum = sum; - } - - printk(BIOS_INFO, "write_pirq_routing_table done.\n"); - - return (unsigned long)pirq_info; - -} diff --git a/src/mainboard/amd/persimmon/mainboard.c b/src/mainboard/amd/persimmon/mainboard.c deleted file mode 100644 index 0e89ffd..0000000 --- a/src/mainboard/amd/persimmon/mainboard.c +++ /dev/null @@ -1,151 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <amdblocks/acpimmio.h> -#include <console/console.h> -#include <device/device.h> -#include <device/mmio.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> -#include <southbridge/amd/cimx/sb800/pci_devs.h> -#include <northbridge/amd/agesa/family14/pci_devs.h> - -/*********************************************************** - * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. - * This table is responsible for physically routing the PIC and - * IOAPIC IRQs to the different PCI devices on the system. It - * is read and written via registers 0xC00/0xC01 as an - * Index/Data pair. These values are chipset and mainboard - * dependent and should be updated accordingly. - * - * These values are used by the PCI configuration space, - * MP Tables. TODO: Make ACPI use these values too. - * - * The Persimmon PCI INTA/B/C/D pins are connected to - * FCH pins INTE/F/G/H on the schematic so these need - * to be routed as well. - */ -static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = { - /* INTA# - INTH# */ - [0x00] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B, - /* Misc-nil,0,1,2, INT from Serial irq */ - [0x08] = 0x00,0xF0,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerfMon */ - [0x10] = 0x1F,0x1F,0x1F,0x0A,0x1F,0x1F,0x1F, - /* IMC INT0 - 5 */ - [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, - /* USB Devs 18/19/20/22 INTA-C */ - [0x30] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A, - /* IDE, SATA */ - [0x40] = 0x0B,0x0B, - /* GPPInt0 - 3 */ - [0x50] = 0x0A,0x0B,0x0A,0x0B -}; - -static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = { - /* INTA# - INTH# */ - [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, - /* Misc-nil,0,1,2, INT from Serial irq */ - [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon */ - [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F, - /* IMC INT0 - 5 */ - [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, - /* USB Devs 18/19/22/20 INTA-C */ - [0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12, - /* IDE, SATA */ - [0x40] = 0x11,0x13, - /* GPPInt0 - 3 */ - [0x50] = 0x10,0x11,0x12,0x13 -}; - -/* - * This table defines the index into the picr/intr_data - * tables for each device. Any enabled device and slot - * that uses hardware interrupts should have an entry - * in this table to define its index into the FCH - * PCI_INTR register 0xC00/0xC01. This index will define - * the interrupt that it should use. Putting PIRQ_A into - * the PIN A index for a device will tell that device to - * use PIC IRQ 10 if it uses PIN A for its hardware INT. - */ -/* - * Persimmon has PCI slot INTA/B/C/D connected to PIRQE/F/G/H - * but because PCI INT_PIN swizzling isn't implemented to match - * the IDSEL (dev 3) of the slot, the table is adjusted for the - * swizzle and INTA is connected to PIRQH so PINA/B/C/D on - * off-chip devices should get mapped to PIRQH/E/F/G. - */ -static const struct pirq_struct mainboard_pirq_data[] = { - /* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D}}, */ - {GFX_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_NC, PIRQ_NC}}, /* VGA: 01.0 */ - {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* NIC: 04.0 */ - {NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* PCIe bdg: 06.0 */ - {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SATA: 11.0 */ - {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1: 12.0 */ - {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1: 12.2 */ - {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2: 13.0 */ - {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2: 13.2 */ - {SMBUS_DEVFN, {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SMBUS: 14.0 */ - {IDE_DEVFN, {PIRQ_NC, PIRQ_IDE, PIRQ_NC, PIRQ_NC}}, /* IDE: 14.1 */ - {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* HDA: 14.2 */ - {SB_PCI_PORT_DEVFN, {PIRQ_H, PIRQ_E, PIRQ_F, PIRQ_G}}, /* PCI bdg: 14.4 */ - {OHCI4_DEVFN, {PIRQ_NC, PIRQ_NC, PIRQ_OHCI4, PIRQ_NC}}, /* OHCI4: 14.5 */ - {OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI3: 16.0 */ - {EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}}, /* EHCI3: 16.2 */ -}; - -/* PIRQ Setup */ -static void pirq_setup(void) -{ - pirq_data_ptr = mainboard_pirq_data; - pirq_data_size = sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct); - intr_data_ptr = mainboard_intr_data; - picr_data_ptr = mainboard_picr_data; -} - -/********************************************** - * Enable the dedicated functions of the board. - **********************************************/ -static void mainboard_enable(struct device *dev) -{ - printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - - /* enable GPP CLK0 thru CLK1 */ - /* disable GPP CLK2 thru SLT_GFX_CLK */ - u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE); - write8(misc_mem_clk_cntrl + 0, 0xFF); - write8(misc_mem_clk_cntrl + 1, 0x00); - write8(misc_mem_clk_cntrl + 2, 0x00); - write8(misc_mem_clk_cntrl + 3, 0x00); - write8(misc_mem_clk_cntrl + 4, 0x00); - - /* - * Initialize ASF registers to an arbitrary address because someone - * long ago set things up this way inside the SPD read code. The - * SPD read code has been made generic and moved out of the board - * directory, so the ASF init is being done here. - */ - pm_write8(0x29, 0x80); - pm_write8(0x28, 0x61); - - /* Initialize the PIRQ data structures for consumption */ - pirq_setup(); -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/amd/persimmon/mptable.c b/src/mainboard/amd/persimmon/mptable.c deleted file mode 100644 index bc7a3ac..0000000 --- a/src/mainboard/amd/persimmon/mptable.c +++ /dev/null @@ -1,142 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/smp/mpspec.h> -#include <stdint.h> -#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <drivers/generic/ioapic/chip.h> -#include <arch/ioapic.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - /* Initialize the MP_Table */ - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - /* - * Type 0: Processor Entries: - * LAPIC ID, LAPIC Version, CPU Flags:EN/BP, - * CPU Signature (Stepping, Model, Family), - * Feature Flags - */ - smp_write_processors(mc); - - /* - * Type 1: Bus Entries: - * Bus ID, Bus Type - */ - mptable_write_buses(mc, NULL, &bus_isa); - - /* - * Type 2: I/O APICs: - * APIC ID, Version, APIC Flags:EN, Address - */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* - * Type 3: I/O Interrupt Table Entries: - * Int Type, Int Polarity, Int Level, Source Bus ID, - * Source Bus IRQ, Dest APIC ID, Dest PIN# - */ - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) - - /* APU Internal Graphic Device */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]); - - /* SMBUS / ACPI */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]); - - /* Southbridge HD Audio */ - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]); - - /* LPC */ - PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]); - PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]); - PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]); - PCI_INT(0x0, 0x14, 0x5, intr_data_ptr[PIRQ_OHCI4]); - - /* IDE */ - PCI_INT(0x0, 0x14, 0x1, intr_data_ptr[PIRQ_IDE]); - - /* SATA */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]); - - /* on board NIC & Slot PCIE */ - PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ - PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0 */ - PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */ - PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */ - PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */ - PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */ - } - - /* PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */ - /* PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */ - /* PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */ - /* PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */ - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */ - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/amd/persimmon/platform_cfg.h b/src/mainboard/amd/persimmon/platform_cfg.h deleted file mode 100644 index 660be41..0000000 --- a/src/mainboard/amd/persimmon/platform_cfg.h +++ /dev/null @@ -1,254 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -#ifndef _PLATFORM_CFG_H_ -#define _PLATFORM_CFG_H_ - -/** - * @def BIOS_SIZE - * BIOS_SIZE_{1,2,4,8,16}M - * - * In SB800, default ROM size is 1M Bytes, if your platform ROM - * bigger than 1M you have to set the ROM size outside CIMx module and - * before AGESA module get call. - */ -#ifndef BIOS_SIZE -#define BIOS_SIZE ((CONFIG_COREBOOT_ROMSIZE_KB >> 10) - 1) -#endif /* BIOS_SIZE */ - -/** - * @def SPREAD_SPECTRUM - * @brief - * 0 - Disable Spread Spectrum function - * 1 - Enable Spread Spectrum function - */ -#define SPREAD_SPECTRUM 0 - -/** - * @def SB_HPET_TIMER - * @brief - * 0 - Disable hpet - * 1 - Enable hpet - */ -#define HPET_TIMER 1 - -/** - * @def USB_CONFIG - * @brief bit[0-6] used to control USB - * 0 - Disable - * 1 - Enable - * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is define at BIT0 - * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is define at BIT1 - * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is define at BIT2 - * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is define at BIT3 - * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is define at BIT4 - * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is define at BIT5 - * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is define at BIT6 - */ -#define USB_CONFIG 0x7F - -/** - * @def PCI_CLOCK_CTRL - * @brief bit[0-4] used for PCI Slots Clock Control, - * 0 - disable - * 1 - enable - * PCI SLOT 0 define at BIT0 - * PCI SLOT 1 define at BIT1 - * PCI SLOT 2 define at BIT2 - * PCI SLOT 3 define at BIT3 - * PCI SLOT 4 define at BIT4 - */ -#define PCI_CLOCK_CTRL 0x07 - -/** - * @def SATA_CONTROLLER - * @brief INCHIP Sata Controller - */ -#define SATA_CONTROLLER CIMX_OPTION_ENABLED - -/** - * @def SATA_MODE - * @brief INCHIP Sata Controller Mode - * NOTE: DO NOT ALLOW SATA & IDE use same mode - */ -#define SATA_MODE CONFIG_SB800_SATA_MODE - -/** - * @brief INCHIP Sata IDE Controller Mode - */ -#define IDE_LEGACY_MODE 0 -#define IDE_NATIVE_MODE 1 - -/** - * @def SATA_IDE_MODE - * @brief INCHIP Sata IDE Controller Mode - * NOTE: DO NOT ALLOW SATA & IDE use same mode - */ -#define SATA_IDE_MODE IDE_LEGACY_MODE - -/** - * @def EXTERNAL_CLOCK - * @brief 00/10: Reference clock from crystal oscillator via - * PAD_XTALI and PAD_XTALO - * - * @def INTERNAL_CLOCK - * @brief 01/11: Reference clock from internal clock through - * CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL - */ -#define EXTERNAL_CLOCK 0x00 -#define INTERNAL_CLOCK 0x01 - -/* NOTE: inagua have to using internal clock, - * otherwise can not detect sata drive - */ -#define SATA_CLOCK_SOURCE INTERNAL_CLOCK - -/** - * @def SATA_PORT_MULT_CAP_RESERVED - * @brief 1 ON, 0 0FF - */ -#define SATA_PORT_MULT_CAP_RESERVED 1 - - -/** - * @def AZALIA_AUTO - * @brief Detect Azalia controller automatically. - * - * @def AZALIA_DISABLE - * @brief Disable Azalia controller. - - * @def AZALIA_ENABLE - * @brief Enable Azalia controller. - */ -#define AZALIA_AUTO 0 -#define AZALIA_DISABLE 1 -#define AZALIA_ENABLE 2 - -/** - * @brief INCHIP HDA controller - */ -#define AZALIA_CONTROLLER AZALIA_AUTO - -/** - * @def AZALIA_PIN_CONFIG - * @brief - * 0 - disable - * 1 - enable - */ -#define AZALIA_PIN_CONFIG 1 - -/** - * @def AZALIA_SDIN_PIN - * @brief - * SDIN0 is define at BIT0 & BIT1 - * 00 - GPIO PIN - * 01 - Reserved - * 10 - As a Azalia SDIN pin - * SDIN1 is define at BIT2 & BIT3 - * SDIN2 is define at BIT4 & BIT5 - * SDIN3 is define at BIT6 & BIT7 - */ -//#define AZALIA_SDIN_PIN 0xAA -#define AZALIA_SDIN_PIN 0x2A - -/** - * @def GPP_CONTROLLER - */ -#define GPP_CONTROLLER CIMX_OPTION_ENABLED - -/** - * @def GPP_CFGMODE - * @brief GPP Link Configuration - * four possible configuration: - * GPP_CFGMODE_X4000 - * GPP_CFGMODE_X2200 - * GPP_CFGMODE_X2110 - * GPP_CFGMODE_X1111 - */ -#define GPP_CFGMODE GPP_CFGMODE_X1111 - -/** - * @def NB_SB_GEN2 - * 0 - Disable - * 1 - Enable - */ -#define NB_SB_GEN2 TRUE - -/** - * @def SB_GPP_GEN2 - * 0 - Disable - * 1 - Enable - */ -#define SB_GPP_GEN2 TRUE - -/** - * @def SB_GPP_UNHIDE_PORTS - * TRUE - ports visible always, even port empty - * FALSE - ports invisible if port empty - */ -#define SB_GPP_UNHIDE_PORTS FALSE - -/** - * @def GEC_CONFIG - * 0 - Enable - * 1 - Disable - */ -#define GEC_CONFIG 0 - -static const CODECENTRY persimmon_codec_alc269[] = -{ - /* NID, PinConfig */ - {0x12, 0x411111F0}, - {0x14, 0x99130110}, - {0x21, 0x0121401F}, - {0x17, 0x411111F0}, - {0x18, 0x01A19820}, - {0x19, 0x411111F0}, - {0x1A, 0x0181302F}, - {0x1B, 0x411111F0}, - {0x1D, 0x40069E05}, - {0x1E, 0x411111F0}, - {0x20, 0x0001FFFF}, - {0xff, 0xffffffff} /* end of table */ -}; - -static const CODECTBLLIST codec_tablelist[] = -{ - {0x010ec0269, (CODECENTRY*)&persimmon_codec_alc269[0]}, - {0x0FFFFFFFFUL, (CODECENTRY*)0x0FFFFFFFFUL} -}; - -/** - * @def AZALIA_OEM_VERB_TABLE - * Mainboard specific codec verb table list - */ -#define AZALIA_OEM_VERB_TABLE (&codec_tablelist[0]) - -/* set up an ACPI preferred power management profile */ -/* from acpi.h - * PM_UNSPECIFIED = 0, - * PM_DESKTOP = 1, - * PM_MOBILE = 2, - * PM_WORKSTATION = 3, - * PM_ENTERPRISE_SERVER = 4, - * PM_SOHO_SERVER = 5, - * PM_APPLIANCE_PC = 6, - * PM_PERFORMANCE_SERVER = 7, - * PM_TABLET = 8 - */ -#define FADT_PM_PROFILE 1 - -#endif /* _PLATFORM_CFG_H_ */ diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c deleted file mode 100644 index 7ccf167..0000000 --- a/src/mainboard/amd/persimmon/romstage.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <northbridge/amd/agesa/state_machine.h> -#include <superio/fintek/common/fintek.h> -#include <superio/fintek/f81865f/f81865f.h> -#include <sb_cimx.h> - -#define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) - -void board_BeforeAgesa(struct sysinfo *cb) -{ - sb_Poweron_Init(); - fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); -} diff --git a/src/mainboard/pcengines/apu1/BiosCallOuts.c b/src/mainboard/pcengines/apu1/BiosCallOuts.c index f738aa3..031f89c 100644 --- a/src/mainboard/pcengines/apu1/BiosCallOuts.c +++ b/src/mainboard/pcengines/apu1/BiosCallOuts.c @@ -41,7 +41,6 @@ /* Call the host environment interface to provide a user hook opportunity. */ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr) { - // Unlike e.g. AMD Inagua, Persimmon is unable to vary the RAM voltage. // Make sure the right speed settings are selected. ((MEM_DATA_STRUCT*)ConfigPtr)->ParameterListPtr->DDR3Voltage = VOLT1_5; return AGESA_SUCCESS; -- To view, visit https://review.coreboot.org/c/coreboot/+/38112 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I07a117abcce379dcae970accc6f75d0ad5ab32f6 Gerrit-Change-Number: 38112 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/amd/olivehillplus: Drop boards with ROMCC_BOOTBLOCK
by HAOUAS Elyes (Code Review) Jan. 7, 2020

Jan. 7, 2020

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38113 ) Change subject: mb/amd/olivehillplus: Drop boards with ROMCC_BOOTBLOCK ...................................................................... mb/amd/olivehillplus: Drop boards with ROMCC_BOOTBLOCK ROMCC_BOOTBLOCK is no more. Drop unsupported, unmaintained boards. Change-Id: I80269df041a0f8f50afb53682994544815f8fc75 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- D src/mainboard/amd/olivehillplus/BiosCallOuts.c D src/mainboard/amd/olivehillplus/Kconfig D src/mainboard/amd/olivehillplus/Kconfig.name D src/mainboard/amd/olivehillplus/Makefile.inc D src/mainboard/amd/olivehillplus/OemCustomize.c D src/mainboard/amd/olivehillplus/acpi/gpe.asl D src/mainboard/amd/olivehillplus/acpi/ide.asl D src/mainboard/amd/olivehillplus/acpi/mainboard.asl D src/mainboard/amd/olivehillplus/acpi/routing.asl D src/mainboard/amd/olivehillplus/acpi/si.asl D src/mainboard/amd/olivehillplus/acpi/sleep.asl D src/mainboard/amd/olivehillplus/acpi/thermal.asl D src/mainboard/amd/olivehillplus/acpi/usb_oc.asl D src/mainboard/amd/olivehillplus/acpi_tables.c D src/mainboard/amd/olivehillplus/board_info.txt D src/mainboard/amd/olivehillplus/cmos.layout D src/mainboard/amd/olivehillplus/devicetree.cb D src/mainboard/amd/olivehillplus/dsdt.asl D src/mainboard/amd/olivehillplus/irq_tables.c D src/mainboard/amd/olivehillplus/mainboard.c D src/mainboard/amd/olivehillplus/mptable.c D src/mainboard/amd/olivehillplus/romstage.c M src/mainboard/asus/am1i-a/BiosCallOuts.c M src/mainboard/biostar/am1ml/BiosCallOuts.c 24 files changed, 1 insertion(+), 1,623 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/38113/1 diff --git a/src/mainboard/amd/olivehillplus/BiosCallOuts.c b/src/mainboard/amd/olivehillplus/BiosCallOuts.c deleted file mode 100644 index 8975dc8..0000000 --- a/src/mainboard/amd/olivehillplus/BiosCallOuts.c +++ /dev/null @@ -1,296 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <AGESA.h> -#include <console/console.h> -#include <northbridge/amd/agesa/BiosCallOuts.h> -#include <FchPlatform.h> -#include <stdlib.h> - -#include "imc.h" -#include "hudson.h" - -static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr); - -const BIOS_CALLOUT_STRUCT BiosCallouts[] = -{ - {AGESA_READ_SPD, agesa_ReadSpd }, - {AGESA_DO_RESET, agesa_Reset }, - {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, - {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, - {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData }, - {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, - {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, - {AGESA_FCH_OEM_CALLOUT, Fch_Oem_config }, - {AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage } -}; -const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); - -/** - * Realtek ALC272 CODEC Verb Table - */ -static const CODEC_ENTRY Alc272_VerbTbl[] = { - {0x11, 0x411111F0}, // - SPDIF_OUT2 - {0x12, 0x411111F0}, // - DMIC_1/2 - {0x13, 0x411111F0}, // - DMIC_3/4 - {0x14, 0x411111F0}, // Port D - LOUT1 - {0x15, 0x411111F0}, // Port A - LOUT2 - {0x16, 0x411111F0}, // - {0x17, 0x411111F0}, // Port H - MONO - {0x18, 0x01a19840}, // Port B - MIC1 - {0x19, 0x411111F0}, // Port F - MIC2 - {0x1a, 0x01813030}, // Port C - LINE1 - {0x1b, 0x411111F0}, // Port E - LINE2 - {0x1d, 0x40251E05}, // - PCBEEP - {0x1e, 0x01441120}, // - SPDIF_OUT1 - {0x21, 0x01214010}, // Port I - HPOUT - {0xff, 0xffffffff} -}; - -static const CODEC_TBL_LIST CodecTableList[] = -{ - {0x10ec0272, (CODEC_ENTRY*)&Alc272_VerbTbl[0]}, - {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL} -}; - -#define FAN_INPUT_INTERNAL_DIODE 0 -#define FAN_INPUT_TEMP0 1 -#define FAN_INPUT_TEMP1 2 -#define FAN_INPUT_TEMP2 3 -#define FAN_INPUT_TEMP3 4 -#define FAN_INPUT_TEMP0_FILTER 5 -#define FAN_INPUT_ZERO 6 -#define FAN_INPUT_DISABLED 7 - -#define FAN_AUTOMODE (1 << 0) -#define FAN_LINEARMODE (1 << 1) -#define FAN_STEPMODE ~(1 << 1) -#define FAN_POLARITY_HIGH (1 << 2) -#define FAN_POLARITY_LOW ~(1 << 2) - -/* Normally, 4-wire fan runs at 25KHz and 3-wire fan runs at 100Hz */ -#define FREQ_28KHZ 0x0 -#define FREQ_25KHZ 0x1 -#define FREQ_23KHZ 0x2 -#define FREQ_21KHZ 0x3 -#define FREQ_29KHZ 0x4 -#define FREQ_18KHZ 0x5 -#define FREQ_100HZ 0xF7 -#define FREQ_87HZ 0xF8 -#define FREQ_58HZ 0xF9 -#define FREQ_44HZ 0xFA -#define FREQ_35HZ 0xFB -#define FREQ_29HZ 0xFC -#define FREQ_22HZ 0xFD -#define FREQ_14HZ 0xFE -#define FREQ_11HZ 0xFF - -/* - * Hardware Monitor Fan Control - * Hardware limitation: - * HWM will fail to read the input temperature via I2C if other - * software switches the I2C address. AMD recommends using IMC - * to control fans, instead of HWM. - */ -static void oem_fan_control(FCH_DATA_BLOCK *FchParams) -{ - FCH_HWM_FAN_CTR oem_factl[5] = { - /*temperature input, fan mode, frequency, low_duty, med_duty, multiplier, lowtemp, medtemp, hightemp, LinearRange, LinearHoldCount */ - /* DB-FT3 FanOUT0 Fan header J32 */ - {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, - /* DB-FT3 FanOUT1 Fan header J31*/ - {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, - {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, - {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, - {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, - }; - LibAmdMemCopy ((VOID *)(FchParams->Hwm.HwmFanControl), &oem_factl, (sizeof(FCH_HWM_FAN_CTR) * 5), FchParams->StdHeader); - - /* Enable IMC fan control. the recommended way */ - if (CONFIG(HUDSON_IMC_FWM)) { - /* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */ - FchParams->Hwm.HwMonitorEnable = TRUE; - FchParams->Hwm.HwmFchtsiAutoPoll = FALSE; /* 0 disable, 1 enable TSI Auto Polling */ - - FchParams->Imc.ImcEnable = TRUE; - FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */ - FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ - - LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader); - - /* Thermal Zone Parameter */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; //BIT0 | BIT2 | BIT5; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x4e; //6 | BIT3; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x04; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x9a; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg7 = 0x01; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg8 = 0x01; /* PWM steping rate in unit of PWM level percentage */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg9 = 0x00; - - /* IMC Fan Policy temperature thresholds */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x46; /*AC0 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0x3c; /*AC1 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0x32; /*AC2 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff; /*AC3 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0xff; /*AC4 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0xff; /*AC5 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0xff; /*AC6 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0xff; /*AC7 lowest threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegA = 0x4b; /*critical threshold* in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegB = 0x00; - - /* IMC Fan Policy PWM Settings */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg2 = 0x5a; /* AL0 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg3 = 0x46; /* AL1 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg4 = 0x28; /* AL2 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg5 = 0xff; /* AL3 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg6 = 0xff; /* AL4 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg7 = 0xff; /* AL5 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0xff; /* AL6 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0xff; /* AL7 percentage */ - - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg1 = 0x01; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg2 = 0x55; //BIT0 | BIT2 | BIT5; - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg3 = 0x17; - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg4 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg5 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg6 = 0x90; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg7 = 0; - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg8 = 0; /* PWM steping rate in unit of PWM level percentage */ - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg9 = 0; - - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg1 = 0x01; /* zone */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg2 = 60; /*AC0 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg3 = 40; /*AC1 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg4 = 0; /*AC2 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg5 = 0; /*AC3 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg6 = 0; /*AC4 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg7 = 0; /*AC5 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg8 = 0; /*AC6 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg9 = 0; /*AC7 lowest threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgRegA = 0; /*critical threshold* in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgRegB = 0x00; - - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg1 = 0x01; /*Zone */ - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg2 = 0; /* AL0 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg3 = 0; /* AL1 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg4 = 0; /* AL2 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg5 = 0x00; /* AL3 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg6 = 0x00; /* AL4 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg7 = 0x00; /* AL5 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg8 = 0x00; /* AL6 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg9 = 0x00; /* AL7 percentage */ - - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg1 = 0x2; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg2 = 0x0; //BIT0 | BIT2 | BIT5; - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg3 = 0x0; - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg4 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg5 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg7 = 2; - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg8 = 5; /* PWM steping rate in unit of PWM level percentage */ - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg9 = 0; - - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg1 = 0x3; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg2 = 0x0; //BIT0 | BIT2 | BIT5; - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg3 = 0x0; - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg4 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg5 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg6 = 0x0; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg7 = 0; - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg8 = 0; /* PWM steping rate in unit of PWM level percentage */ - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg9 = 0; - - /* IMC Function */ - FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x333; //BIT0 | BIT4 |BIT8; - - /* NOTE: - * FchInitLateHwm will overwrite the EcStruct with EcDefaultMessage, - * AGESA put EcDefaultMessage as global data in ROM, so we can't override it. - * so we remove it from AGESA code. Please See FchInitLateHwm. - */ - } else { - /* HWM fan control, using the alternative method */ - FchParams->Imc.ImcEnable = FALSE; - FchParams->Hwm.HwMonitorEnable = TRUE; - FchParams->Hwm.HwmFchtsiAutoPoll = TRUE; /* 1 enable, 0 disable TSI Auto Polling */ - } -} - -/** - * Fch Oem setting callback - * - * Configure platform specific Hudson device, - * such Azalia, SATA, IMC etc. - */ -static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr) -{ - AMD_CONFIG_PARAMS *StdHeader = (AMD_CONFIG_PARAMS *)ConfigPtr; - if (StdHeader->Func == AMD_INIT_RESET) { - FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *) FchData; - printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); - //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ - FchParams->LegacyFree = CONFIG(HUDSON_LEGACY_FREE); - FchParams->FchReset.SataEnable = hudson_sata_enable(); - FchParams->FchReset.IdeEnable = hudson_ide_enable(); - FchParams->FchReset.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); - FchParams->FchReset.Xhci1Enable = FALSE; - } else if (StdHeader->Func == AMD_INIT_ENV) { - FCH_DATA_BLOCK *FchParams = (FCH_DATA_BLOCK *)FchData; - printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); - - /* Azalia Controller OEM Codec Table Pointer */ - FchParams->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&CodecTableList[0]); - /* Azalia Controller Front Panel OEM Table Pointer */ - - /* Fan Control */ - oem_fan_control(FchParams); - - /* XHCI configuration */ - FchParams->Usb.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); - FchParams->Usb.Xhci1Enable = FALSE; - - /* sata configuration */ - FchParams->Sata.SataClass = CONFIG_HUDSON_SATA_MODE; - switch ((SATA_CLASS)CONFIG_HUDSON_SATA_MODE) { - case SataRaid: - case SataAhci: - case SataAhci7804: - case SataLegacyIde: - FchParams->Sata.SataIdeMode = FALSE; - break; - case SataIde2Ahci: - case SataIde2Ahci7804: - default: /* SataNativeIde */ - FchParams->Sata.SataIdeMode = TRUE; - break; - } - } - printk(BIOS_DEBUG, "Done\n"); - - return AGESA_SUCCESS; -} diff --git a/src/mainboard/amd/olivehillplus/Kconfig b/src/mainboard/amd/olivehillplus/Kconfig deleted file mode 100644 index 907de3b..0000000 --- a/src/mainboard/amd/olivehillplus/Kconfig +++ /dev/null @@ -1,60 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2012 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -config BOARD_AMD_OLIVEHILLPLUS - def_bool n - -if BOARD_AMD_OLIVEHILLPLUS - -config BOARD_SPECIFIC_OPTIONS - def_bool y - #select BINARYPI_LEGACY_WRAPPER - #select ROMCC_BOOTBLOCK - select CPU_AMD_PI_00730F01 - select NORTHBRIDGE_AMD_PI_00730F01 - select SOUTHBRIDGE_AMD_PI_AVALON - select DEFAULT_POST_ON_LPC - select HAVE_OPTION_TABLE - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select HAVE_ACPI_TABLES - select BOARD_ROMSIZE_KB_8192 - select GFXUMA - -config MAINBOARD_DIR - string - default "amd/olivehillplus" - -config MAINBOARD_PART_NUMBER - string - default "DB-FT3b" - -config MAX_CPUS - int - default 4 - -config IRQ_SLOT_COUNT - int - default 11 - -config ONBOARD_VGA_IS_PRIMARY - bool - default y - -config HUDSON_LEGACY_FREE - bool - default y - -endif # BOARD_AMD_OLIVEHILLPLUS diff --git a/src/mainboard/amd/olivehillplus/Kconfig.name b/src/mainboard/amd/olivehillplus/Kconfig.name deleted file mode 100644 index 1ce4a20..0000000 --- a/src/mainboard/amd/olivehillplus/Kconfig.name +++ /dev/null @@ -1,3 +0,0 @@ -# Disabled -#config BOARD_AMD_OLIVEHILLPLUS -# bool "Olive Hill Plus" diff --git a/src/mainboard/amd/olivehillplus/Makefile.inc b/src/mainboard/amd/olivehillplus/Makefile.inc deleted file mode 100644 index 37c1dce..0000000 --- a/src/mainboard/amd/olivehillplus/Makefile.inc +++ /dev/null @@ -1,20 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2012 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -romstage-y += BiosCallOuts.c -romstage-y += OemCustomize.c - -ramstage-y += BiosCallOuts.c -ramstage-y += OemCustomize.c diff --git a/src/mainboard/amd/olivehillplus/OemCustomize.c b/src/mainboard/amd/olivehillplus/OemCustomize.c deleted file mode 100644 index 76b7f25..0000000 --- a/src/mainboard/amd/olivehillplus/OemCustomize.c +++ /dev/null @@ -1,121 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <AGESA.h> - - -static const PCIe_PORT_DESCRIPTOR PortList[] = { - /* Initialize Port descriptor (PCIe port, Lane 3, PCI Device 2, Function 5) */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 3, 3), - PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 5, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 0x01, 0) - }, - /* Initialize Port descriptor (PCIe port, Lane 2, PCI Device 2, Function 4) */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 2), - PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 4, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 0x02, 0) - }, - /* Initialize Port descriptor (PCIe port, Lane 1, PCI Device 2, Function 3) */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 1, 1), - PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 3, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 0x03, 0) - }, - /* Initialize Port descriptor (PCIe port, Lane 0, PCI Device 2, Function 2) */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 0), - PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 2, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 0x04, 0) - }, - /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device 2, Function 1) */ - { - DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7), - PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 1, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 0x05, 0) - } -}; - -static const PCIe_DDI_DESCRIPTOR DdiList[] = { - /* DP0 to HDMI0/DP */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1) - }, - /* DP1 to FCH */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2) - }, - /* DP2 to HDMI1/DP */ - { - DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 16, 19), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeCrt, Aux3, Hdp3) - }, -}; - -static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { - .Flags = DESCRIPTOR_TERMINATE_LIST, - .SocketId = 0, - .PciePortList = PortList, - .DdiLinkList = DdiList -}; - -/*---------------------------------------------------------------------------------------*/ -/** - * OemCustomizeInitEarly - * - * Description: - * This stub function will call the host environment through the binary block - * interface (call-out port) to provide a user hook opportunity - * - * Parameters: - * @param[in] *InitEarly - * - * @retval VOID - * - **/ -/*---------------------------------------------------------------------------------------*/ -VOID -OemCustomizeInitEarly ( - IN OUT AMD_EARLY_PARAMS *InitEarly - ) -{ - InitEarly->GnbConfig.PcieComplexList = &PcieComplex; -} diff --git a/src/mainboard/amd/olivehillplus/acpi/gpe.asl b/src/mainboard/amd/olivehillplus/acpi/gpe.asl deleted file mode 100644 index 87b0d21..0000000 --- a/src/mainboard/amd/olivehillplus/acpi/gpe.asl +++ /dev/null @@ -1,74 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Scope(\_GPE) { /* Start Scope GPE */ - - /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* Legacy PM event */ - Method(_L08) { - /* DBGO("\\_GPE\\_L08\n") */ - } - - /* Temp warning (TWarn) event */ - Method(_L09) { - /* DBGO("\\_GPE\\_L09\n") */ - /* Notify (\_TZ.TZ00, 0x80) */ - } - - /* USB controller PME# */ - Method(_L0B) { - /* DBGO("\\_GPE\\_L0B\n") */ - Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* ExtEvent0 SCI event */ - Method(_L10) { - /* DBGO("\\_GPE\\_L10\n") */ - } - - /* ExtEvent1 SCI event */ - Method(_L11) { - /* DBGO("\\_GPE\\_L11\n") */ - } - - /* GPIO0 or GEvent8 event */ - Method(_L18) { - /* DBGO("\\_GPE\\_L18\n") */ - Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* Azalia SCI event */ - Method(_L1B) { - /* DBGO("\\_GPE\\_L1B\n") */ - Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } -} /* End Scope GPE */ diff --git a/src/mainboard/amd/olivehillplus/acpi/ide.asl b/src/mainboard/amd/olivehillplus/acpi/ide.asl deleted file mode 100644 index 4a3eac8..0000000 --- a/src/mainboard/amd/olivehillplus/acpi/ide.asl +++ /dev/null @@ -1,2 +0,0 @@ -/* No license required */ -/* No IDE functionality */ diff --git a/src/mainboard/amd/olivehillplus/acpi/mainboard.asl b/src/mainboard/amd/olivehillplus/acpi/mainboard.asl deleted file mode 100644 index 68609d8..0000000 --- a/src/mainboard/amd/olivehillplus/acpi/mainboard.asl +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Memory related values */ -Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ -Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ -Name(PBLN, 0x0) /* Length of BIOS area */ - -Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ -Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */ -Name(HPBA, 0xFED00000) /* Base address of HPET table */ - -/* Some global data */ -Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ -Name(OSV, Ones) /* Assume nothing */ -Name(PMOD, One) /* Assume APIC */ - -/* AcpiGpe0Blk */ -OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04) - Field(GP0B, ByteAcc, NoLock, Preserve) { - , 11, - USBS, 1, -} diff --git a/src/mainboard/amd/olivehillplus/acpi/routing.asl b/src/mainboard/amd/olivehillplus/acpi/routing.asl deleted file mode 100644 index 1fb4c1d..0000000 --- a/src/mainboard/amd/olivehillplus/acpi/routing.asl +++ /dev/null @@ -1,194 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* -#include <arch/acpi.h> -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 - ) - { - #include "routing.asl" - } -*/ - -/* Routing is in System Bus scope */ -Name(PR0, Package(){ - /* NB devices */ - /* Bus 0, Dev 0 - F16 Host Controller */ - - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ - /* Bus 0, Dev 1, Func 1 - HDMI Audio Controller */ - Package(){0x0001FFFF, 0, INTB, 0 }, - Package(){0x0001FFFF, 1, INTC, 0 }, - - - /* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */ - Package(){0x0002FFFF, 0, INTC, 0 }, - Package(){0x0002FFFF, 1, INTD, 0 }, - Package(){0x0002FFFF, 2, INTA, 0 }, - Package(){0x0002FFFF, 3, INTB, 0 }, - - /* FCH devices */ - /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */ - Package(){0x0014FFFF, 0, INTA, 0 }, - Package(){0x0014FFFF, 1, INTB, 0 }, - Package(){0x0014FFFF, 2, INTC, 0 }, - Package(){0x0014FFFF, 3, INTD, 0 }, - - /* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */ - /* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */ - Package(){0x0012FFFF, 0, INTC, 0 }, - Package(){0x0012FFFF, 1, INTB, 0 }, - - Package(){0x0013FFFF, 0, INTC, 0 }, - Package(){0x0013FFFF, 1, INTB, 0 }, - - Package(){0x0016FFFF, 0, INTC, 0 }, - Package(){0x0016FFFF, 1, INTB, 0 }, - - /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */ - Package(){0x0010FFFF, 0, INTC, 0 }, - Package(){0x0010FFFF, 1, INTB, 0 }, - - /* Bus 0, Dev 17 - SATA controller */ - Package(){0x0011FFFF, 0, INTD, 0 }, - -}) - -Name(APR0, Package(){ - /* NB devices in APIC mode */ - /* Bus 0, Dev 0 - F15 Host Controller */ - - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ - Package(){0x0001FFFF, 0, 0, 44 }, - Package(){0x0001FFFF, 1, 0, 45 }, - - /* Bus 0, Dev 2 - PCIe Bridges */ - Package(){0x0002FFFF, 0, 0, 24 }, - Package(){0x0002FFFF, 1, 0, 25 }, - Package(){0x0002FFFF, 2, 0, 26 }, - Package(){0x0002FFFF, 3, 0, 27 }, - - - /* SB devices in APIC mode */ - /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */ - Package(){0x0014FFFF, 0, 0, 16 }, - Package(){0x0014FFFF, 1, 0, 17 }, - Package(){0x0014FFFF, 2, 0, 18 }, - Package(){0x0014FFFF, 3, 0, 19 }, - - /* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */ - /* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */ - Package(){0x0012FFFF, 0, 0, 18 }, - Package(){0x0012FFFF, 1, 0, 17 }, - - Package(){0x0013FFFF, 0, 0, 18 }, - Package(){0x0013FFFF, 1, 0, 17 }, - - Package(){0x0016FFFF, 0, 0, 18 }, - Package(){0x0016FFFF, 1, 0, 17 }, - - /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */ - Package(){0x0010FFFF, 0, 0, 0x12}, - Package(){0x0010FFFF, 1, 0, 0x11}, - - /* Bus 0, Dev 17 - SATA controller */ - Package(){0x0011FFFF, 0, 0, 19 }, - -}) - -Name(PS2, Package(){ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, -}) -Name(APS2, Package(){ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, -}) - -/* GFX */ -Name(PS4, Package(){ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, -}) -Name(APS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, 0, 24 }, - Package(){0x0000FFFF, 1, 0, 25 }, - Package(){0x0000FFFF, 2, 0, 26 }, - Package(){0x0000FFFF, 3, 0, 27 }, -}) - -/* GPP 0 */ -Name(PS5, Package(){ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, -}) -Name(APS5, Package(){ - Package(){0x0000FFFF, 0, 0, 28 }, - Package(){0x0000FFFF, 1, 0, 29 }, - Package(){0x0000FFFF, 2, 0, 30 }, - Package(){0x0000FFFF, 3, 0, 31 }, -}) - -/* GPP 1 */ -Name(PS6, Package(){ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, -}) -Name(APS6, Package(){ - Package(){0x0000FFFF, 0, 0, 32 }, - Package(){0x0000FFFF, 1, 0, 33 }, - Package(){0x0000FFFF, 2, 0, 34 }, - Package(){0x0000FFFF, 3, 0, 35 }, -}) - -/* GPP 2 */ -Name(PS7, Package(){ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, -}) -Name(APS7, Package(){ - Package(){0x0000FFFF, 0, 0, 36 }, - Package(){0x0000FFFF, 1, 0, 37 }, - Package(){0x0000FFFF, 2, 0, 38 }, - Package(){0x0000FFFF, 3, 0, 39 }, -}) - -/* GPP 3 */ -Name(PS8, Package(){ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, -}) -Name(APS8, Package(){ - Package(){0x0000FFFF, 0, 0, 40 }, - Package(){0x0000FFFF, 1, 0, 41 }, - Package(){0x0000FFFF, 2, 0, 42 }, - Package(){0x0000FFFF, 3, 0, 43 }, -}) diff --git a/src/mainboard/amd/olivehillplus/acpi/si.asl b/src/mainboard/amd/olivehillplus/acpi/si.asl deleted file mode 100644 index 2923471..0000000 --- a/src/mainboard/amd/olivehillplus/acpi/si.asl +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Scope(\_SI) { - Method(_SST, 1) { - /* DBGO("\\_SI\\_SST\n") */ - /* DBGO(" New Indicator state: ") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - } -} /* End Scope SI */ diff --git a/src/mainboard/amd/olivehillplus/acpi/sleep.asl b/src/mainboard/amd/olivehillplus/acpi/sleep.asl deleted file mode 100644 index 0734c8e..0000000 --- a/src/mainboard/amd/olivehillplus/acpi/sleep.asl +++ /dev/null @@ -1,95 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Wake status package */ -Name(WKST,Package(){Zero, Zero}) - -/* -* \_PTS - Prepare to Sleep method -* -* Entry: -* Arg0=The value of the sleeping state S1=1, S2=2, etc -* -* Exit: -* -none- -* -* The _PTS control method is executed at the beginning of the sleep process -* for S1-S5. The sleeping value is passed to the _PTS control method. This -* control method may be executed a relatively long time before entering the -* sleep state and the OS may abort the operation without notification to -* the ACPI driver. This method cannot modify the configuration or power -* state of any device in the system. -*/ - -External(\_SB.APTS, MethodObj) -External(\_SB.AWAK, MethodObj) - -Method(_PTS, 1) { - /* DBGO("\\_PTS\n") */ - /* DBGO("From S0 to S") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - - /* Clear wake status structure. */ - Store(0, Index(WKST,0)) - Store(0, Index(WKST,1)) - Store(7, UPWS) - \_SB.APTS(Arg0) -} /* End Method(\_PTS) */ - -/* -* \_BFS OEM Back From Sleep method -* -* Entry: -* Arg0=The value of the sleeping state S1=1, S2=2 -* -* Exit: -* -none- -*/ -Method(\_BFS, 1) { - /* DBGO("\\_BFS\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ -} - -/* -* \_WAK System Wake method -* -* Entry: -* Arg0=The value of the sleeping state S1=1, S2=2 -* -* Exit: -* Return package of 2 DWords -* Dword 1 - Status -* 0x00000000 wake succeeded -* 0x00000001 Wake was signaled but failed due to lack of power -* 0x00000002 Wake was signaled but failed due to thermal condition -* Dword 2 - Power Supply state -* if non-zero the effective S-state the power supply entered -*/ -Method(\_WAK, 1) { - /* DBGO("\\_WAK\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - - /* clear USB wake up signal */ - Store(1, USBS) - - \_SB.AWAK(Arg0) - - Return(WKST) -} /* End Method(\_WAK) */ diff --git a/src/mainboard/amd/olivehillplus/acpi/thermal.asl b/src/mainboard/amd/olivehillplus/acpi/thermal.asl deleted file mode 100644 index 73077ac..0000000 --- a/src/mainboard/amd/olivehillplus/acpi/thermal.asl +++ /dev/null @@ -1,2 +0,0 @@ -/* No license required */ -/* No thermal zone functionality */ diff --git a/src/mainboard/amd/olivehillplus/acpi/usb_oc.asl b/src/mainboard/amd/olivehillplus/acpi/usb_oc.asl deleted file mode 100644 index 4ebb4b6..0000000 --- a/src/mainboard/amd/olivehillplus/acpi/usb_oc.asl +++ /dev/null @@ -1,37 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* simple name description */ -/* -#include <arch/acpi.h> -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 - ) - { - #include "usb.asl" - } -*/ - -/* USB overcurrent mapping pins. */ -Name(UOM0, 0) -Name(UOM1, 2) -Name(UOM2, 0) -Name(UOM3, 7) -Name(UOM4, 2) -Name(UOM5, 2) -Name(UOM6, 6) -Name(UOM7, 2) -Name(UOM8, 6) -Name(UOM9, 6) diff --git a/src/mainboard/amd/olivehillplus/acpi_tables.c b/src/mainboard/amd/olivehillplus/acpi_tables.c deleted file mode 100644 index 20509e9..0000000 --- a/src/mainboard/amd/olivehillplus/acpi_tables.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/acpi.h> -#include <arch/ioapic.h> - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); - - /* Write SB800 IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, - IO_APIC_ADDR, 0); - - /* TODO: Remove the hardcode */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS+1, - 0xFEC20000, 24); - - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xF); - /* 0: mean bus 0--->ISA */ - /* 0: PIC 0 */ - /* 2: APIC 2 */ - /* 5 mean: 0101 --> Edge-triggered, Active high */ - - /* create all subtables for processors */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1); - /* 1: LINT1 connect to NMI */ - - return current; -} diff --git a/src/mainboard/amd/olivehillplus/board_info.txt b/src/mainboard/amd/olivehillplus/board_info.txt deleted file mode 100644 index d2c6670..0000000 --- a/src/mainboard/amd/olivehillplus/board_info.txt +++ /dev/null @@ -1,6 +0,0 @@ -Board name: DB-FT3b (Olive Hill+) -Board URL: http://wwwd.amd.com/amd/devsite.nsf/platforms/DB-FT3.htm -Category: eval -ROM protocol: SPI -ROM socketed: n -Flashrom support: y diff --git a/src/mainboard/amd/olivehillplus/cmos.layout b/src/mainboard/amd/olivehillplus/cmos.layout deleted file mode 100644 index e1dbd9a..0000000 --- a/src/mainboard/amd/olivehillplus/cmos.layout +++ /dev/null @@ -1,66 +0,0 @@ -#***************************************************************************** -# -# This file is part of the coreboot project. -# -# Copyright (C) 2012 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -#***************************************************************************** - -entries - -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#392 3 r 0 unused -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum -# Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% - -checksums - -checksum 392 983 984 diff --git a/src/mainboard/amd/olivehillplus/devicetree.cb b/src/mainboard/amd/olivehillplus/devicetree.cb deleted file mode 100644 index 9b59d99..0000000 --- a/src/mainboard/amd/olivehillplus/devicetree.cb +++ /dev/null @@ -1,66 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2013 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -chip northbridge/amd/pi/00730F01/root_complex - device cpu_cluster 0 on - chip cpu/amd/pi/00730F01 - device lapic 0 on end - end - end - - device domain 0 on - subsystemid 0x1022 0x1410 inherit - - chip northbridge/amd/pi/00730F01 - device pci 0.0 on end # Root Complex - device pci 0.2 off end # IOMMU - device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 - device pci 1.1 on end # Internal Multimedia - device pci 2.0 on end # PCIe Host Bridge - device pci 2.1 on end # x4 PCIe slot - device pci 2.2 on end # mPCIe slot - device pci 2.3 on end # Realtek NIC - device pci 2.4 on end # Edge Connector - device pci 2.5 on end # Edge Connector - device pci 8.0 on end # Platform Security Processor - end #chip northbridge/amd/pi/00730F01 - - chip southbridge/amd/pi/hudson - device pci 10.0 on end # XHCI HC0 - device pci 11.0 on end # SATA - device pci 12.0 on end # EHCI #0 - device pci 13.0 on end # EHCI #1 - device pci 14.0 on end # SMBus - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on end # LPC 0x439d - device pci 14.7 on end # SD - device pci 16.0 on end # EHCI #2 - end #chip southbridge/amd/pi/hudson - - chip northbridge/amd/pi/00730F01 - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - - register "spdAddrLookup" = " - { - { {0xA0, 0xA2} }, // socket 0, channel 0, slots 0 & 1 - 8-bit SPD addresses - }" - end - - end #domain -end #northbridge/amd/pi/00730F01/root_complex diff --git a/src/mainboard/amd/olivehillplus/dsdt.asl b/src/mainboard/amd/olivehillplus/dsdt.asl deleted file mode 100644 index f1ff974..0000000 --- a/src/mainboard/amd/olivehillplus/dsdt.asl +++ /dev/null @@ -1,88 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* DefinitionBlock Statement */ -#include <arch/acpi.h> -DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - OEM_ID, - ACPI_TABLE_CREATOR, - 0x00010001 /* OEM Revision */ - ) -{ /* Start of ASL file */ - /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ - - /* Globals for the platform */ - #include "acpi/mainboard.asl" - - /* Describe the USB Overcurrent pins */ - #include "acpi/usb_oc.asl" - - /* PCI IRQ mapping for the Southbridge */ - #include <southbridge/amd/pi/hudson/acpi/pcie.asl> - - /* Describe the processor tree (\_PR) */ - #include <cpu/amd/pi/00730F01/acpi/cpu.asl> - - /* Contains the supported sleep states for this chipset */ - #include <southbridge/amd/common/acpi/sleepstates.asl> - - /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */ - #include "acpi/sleep.asl" - - /* System Bus */ - Scope(\_SB) { /* Start \_SB scope */ - /* global utility methods expected within the \_SB scope */ - #include <arch/x86/acpi/globutil.asl> - - /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ - #include "acpi/routing.asl" - - Device(PWRB) { - Name(_HID, EISAID("PNP0C0C")) - Name(_UID, 0xAA) - Name(_PRW, Package () {3, 0x04}) - Name(_STA, 0x0B) - } - - Device(PCI0) { - /* Describe the AMD Northbridge */ - #include <northbridge/amd/pi/00730F01/acpi/northbridge.asl> - - /* Describe the AMD Fusion Controller Hub Southbridge */ - #include <southbridge/amd/pi/hudson/acpi/fch.asl> - } - - /* Describe PCI INT[A-H] for the Southbridge */ - #include <southbridge/amd/pi/hudson/acpi/pci_int.asl> - - } /* End \_SB scope */ - - /* Describe SMBUS for the Southbridge */ - #include <southbridge/amd/pi/hudson/acpi/smbus.asl> - - /* Define the General Purpose Events for the platform */ - #include "acpi/gpe.asl" - - /* Define the Thermal zones and methods for the platform */ - #include "acpi/thermal.asl" - - /* Define the System Indicators for the platform */ - #include "acpi/si.asl" -} -/* End of ASL file */ diff --git a/src/mainboard/amd/olivehillplus/irq_tables.c b/src/mainboard/amd/olivehillplus/irq_tables.c deleted file mode 100644 index 530c132..0000000 --- a/src/mainboard/amd/olivehillplus/irq_tables.c +++ /dev/null @@ -1,100 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <string.h> -#include <stdint.h> -#include <arch/pirq_routing.h> - -static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, - u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, - u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, - u8 slot, u8 rfu) -{ - pirq_info->bus = bus; - pirq_info->devfn = devfn; - pirq_info->irq[0].link = link0; - pirq_info->irq[0].bitmap = bitmap0; - pirq_info->irq[1].link = link1; - pirq_info->irq[1].bitmap = bitmap1; - pirq_info->irq[2].link = link2; - pirq_info->irq[2].bitmap = bitmap2; - pirq_info->irq[3].link = link3; - pirq_info->irq[3].bitmap = bitmap3; - pirq_info->slot = slot; - pirq_info->rfu = rfu; -} - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - struct irq_routing_table *pirq; - struct irq_info *pirq_info; - u32 slot_num; - u8 *v; - - u8 sum = 0; - int i; - - /* Align the table to be 16 byte aligned. */ - addr += 15; - addr &= ~15; - - /* This table must be between 0xf0000 & 0x100000 */ - printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); - - pirq = (void *)(addr); - v = (u8 *) (addr); - - pirq->signature = PIRQ_SIGNATURE; - pirq->version = PIRQ_VERSION; - - pirq->rtr_bus = 0; - pirq->rtr_devfn = PCI_DEVFN(0x14, 4); - - pirq->exclusive_irqs = 0; - - pirq->rtr_vendor = 0x1002; - pirq->rtr_device = 0x4384; - - pirq->miniport_data = 0; - - memset(pirq->rfu, 0, sizeof(pirq->rfu)); - - pirq_info = (void *)(&pirq->checksum + 1); - slot_num = 0; - - /* pci bridge */ - write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), - 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, - 0); - pirq_info++; - - slot_num++; - - pirq->size = 32 + 16 * slot_num; - - for (i = 0; i < pirq->size; i++) - sum += v[i]; - - sum = pirq->checksum - sum; - - if (sum != pirq->checksum) { - pirq->checksum = sum; - } - - printk(BIOS_INFO, "write_pirq_routing_table done.\n"); - - return (unsigned long)pirq_info; -} diff --git a/src/mainboard/amd/olivehillplus/mainboard.c b/src/mainboard/amd/olivehillplus/mainboard.c deleted file mode 100644 index 1367b03..0000000 --- a/src/mainboard/amd/olivehillplus/mainboard.c +++ /dev/null @@ -1,32 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci_def.h> -#include <cpu/x86/msr.h> -#include <cpu/amd/mtrr.h> - -/********************************************** - * enable the dedicated function in mainboard. - **********************************************/ -static void mainboard_enable(struct device *dev) -{ - printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/amd/olivehillplus/mptable.c b/src/mainboard/amd/olivehillplus/mptable.c deleted file mode 100644 index 6c81d06..0000000 --- a/src/mainboard/amd/olivehillplus/mptable.c +++ /dev/null @@ -1,186 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/smp/mpspec.h> -#include <arch/io.h> -#include <arch/ioapic.h> -#include <string.h> -#include <stdint.h> -#include <cpu/x86/lapic.h> -#include <southbridge/amd/pi/hudson/hudson.h> - -u8 picr_data[0x54] = { - 0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - 0x1F,0x1F,0x1F,0x03,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x05,0x04,0x05,0x04,0x04,0x05,0x04,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x04,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x03,0x04,0x05,0x07 -}; -u8 intr_data[0x54] = { - 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x10,0x11,0x12,0x13 -}; - -static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) -{ - mc->mpc_length += length; - mc->mpc_entry_count++; -} - -static void my_smp_write_bus(struct mp_config_table *mc, - unsigned char id, const char *bustype) -{ - struct mpc_config_bus *mpc; - mpc = smp_next_mpc_entry(mc); - memset(mpc, '\0', sizeof(*mpc)); - mpc->mpc_type = MP_BUS; - mpc->mpc_busid = id; - memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); - smp_add_mpc_entry(mc, sizeof(*mpc)); -} - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - u8 byte; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - //mptable_write_buses(mc, NULL, &bus_isa); - my_smp_write_bus(mc, 0, "PCI "); - my_smp_write_bus(mc, 1, "PCI "); - bus_isa = 0x02; - my_smp_write_bus(mc, bus_isa, "ISA "); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000); - /* PIC IRQ routine */ - for (byte = 0x0; byte < sizeof(picr_data); byte ++) { - outb(byte, 0xC00); - outb(picr_data[byte], 0xC01); - } - - /* APIC IRQ routine */ - for (byte = 0x0; byte < sizeof(intr_data); byte ++) { - outb(byte | 0x80, 0xC00); - outb(intr_data[byte], 0xC01); - } - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) - - /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); - - /* SMBUS */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - - /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe Lan*/ - PCI_INT(0x0, 0x06, 0x0, 0x13); - - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/amd/olivehillplus/romstage.c b/src/mainboard/amd/olivehillplus/romstage.c deleted file mode 100644 index 3dd7d53..0000000 --- a/src/mainboard/amd/olivehillplus/romstage.c +++ /dev/null @@ -1,69 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <device/pci_def.h> -#include <arch/io.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> -#include <console/console.h> -#include <northbridge/amd/agesa/state_machine.h> -#include <southbridge/amd/pi/hudson/hudson.h> - -static void romstage_main_template(void) -{ - u32 val; - - /* - * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for - * LpcClk[1:0]". This following register setting has been - * replicated in every reference design since Parmer, so it is - * believed to be required even though it is not documented in - * the SoC BKDGs. Without this setting, there is no serial - * output. - */ - outb(0xD2, 0xcd6); - outb(0x00, 0xcd7); - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - - post_code(0x31); - console_init(); - } - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - /* - * This refers to LpcClkDrvSth settling time. Without this setting, processor - * initialization is slow or incorrect, so this wait has been replicated from - * earlier development boards. - */ - { - int i; - for (i = 0; i < 200000; i++) - inb(0xCD6); - } -} - -void agesa_postcar(struct sysinfo *cb) -{ - /* After AMD_INIT_ENV -> move to ramstage ? */ - outb(0xEA, 0xCD6); - outb(0x1, 0xcd7); -} diff --git a/src/mainboard/asus/am1i-a/BiosCallOuts.c b/src/mainboard/asus/am1i-a/BiosCallOuts.c index ce54741..8c47836 100644 --- a/src/mainboard/asus/am1i-a/BiosCallOuts.c +++ b/src/mainboard/asus/am1i-a/BiosCallOuts.c @@ -130,7 +130,6 @@ printk(BIOS_DEBUG, "ERROR: cannot read CMOS setting, falling back to default. Error code: %x\n", (int)ret); } - // code from olivehillplus (ft3b) - only place where sata is configured switch ((SATA_CLASS)FchParams_env->Sata.SataClass) { case SataLegacyIde: case SataRaid: diff --git a/src/mainboard/biostar/am1ml/BiosCallOuts.c b/src/mainboard/biostar/am1ml/BiosCallOuts.c index 6181226..9634fed 100644 --- a/src/mainboard/biostar/am1ml/BiosCallOuts.c +++ b/src/mainboard/biostar/am1ml/BiosCallOuts.c @@ -108,7 +108,7 @@ FchParams_env->Hwm.HwmFchtsiAutoPoll = FALSE;/* 1 enable, 0 disable TSI Auto Polling */ FchParams_env->Sata.SataClass = CONFIG_HUDSON_SATA_MODE; - switch ((SATA_CLASS)CONFIG_HUDSON_SATA_MODE) { // code from olivehillplus (ft3b) - only one place where sata is configured + switch ((SATA_CLASS)CONFIG_HUDSON_SATA_MODE) { case SataLegacyIde: case SataRaid: case SataAhci: -- To view, visit https://review.coreboot.org/c/coreboot/+/38113 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I80269df041a0f8f50afb53682994544815f8fc75 Gerrit-Change-Number: 38113 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: mb/amd/olivehill: Drop boards with ROMCC_BOOTBLOCK
by HAOUAS Elyes (Code Review) Jan. 7, 2020

Jan. 7, 2020

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38114 ) Change subject: mb/amd/olivehill: Drop boards with ROMCC_BOOTBLOCK ...................................................................... mb/amd/olivehill: Drop boards with ROMCC_BOOTBLOCK ROMCC_BOOTBLOCK is no more. Drop unsupported, unmaintained boards. Change-Id: I44280d8f078ea2fb662d4b1e23737ac0c86b8d9d Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- D src/mainboard/amd/olivehill/BiosCallOuts.c D src/mainboard/amd/olivehill/Kconfig D src/mainboard/amd/olivehill/Kconfig.name D src/mainboard/amd/olivehill/Makefile.inc D src/mainboard/amd/olivehill/OemCustomize.c D src/mainboard/amd/olivehill/OptionsIds.h D src/mainboard/amd/olivehill/acpi/gpe.asl D src/mainboard/amd/olivehill/acpi/ide.asl D src/mainboard/amd/olivehill/acpi/mainboard.asl D src/mainboard/amd/olivehill/acpi/routing.asl D src/mainboard/amd/olivehill/acpi/sata.asl D src/mainboard/amd/olivehill/acpi/si.asl D src/mainboard/amd/olivehill/acpi/sleep.asl D src/mainboard/amd/olivehill/acpi/superio.asl D src/mainboard/amd/olivehill/acpi/thermal.asl D src/mainboard/amd/olivehill/acpi/usb_oc.asl D src/mainboard/amd/olivehill/acpi_tables.c D src/mainboard/amd/olivehill/board_info.txt D src/mainboard/amd/olivehill/buildOpts.c D src/mainboard/amd/olivehill/cmos.layout D src/mainboard/amd/olivehill/devicetree.cb D src/mainboard/amd/olivehill/dsdt.asl D src/mainboard/amd/olivehill/irq_tables.c D src/mainboard/amd/olivehill/mainboard.c D src/mainboard/amd/olivehill/mptable.c D src/mainboard/amd/olivehill/romstage.c 26 files changed, 0 insertions(+), 2,391 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/38114/1 diff --git a/src/mainboard/amd/olivehill/BiosCallOuts.c b/src/mainboard/amd/olivehill/BiosCallOuts.c deleted file mode 100644 index b6a8a3a..0000000 --- a/src/mainboard/amd/olivehill/BiosCallOuts.c +++ /dev/null @@ -1,182 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <AGESA.h> -#include <northbridge/amd/agesa/BiosCallOuts.h> -#include <northbridge/amd/agesa/state_machine.h> -#include <FchPlatform.h> -#include <stdlib.h> - -#include "imc.h" - -const BIOS_CALLOUT_STRUCT BiosCallouts[] = -{ - {AGESA_DO_RESET, agesa_Reset }, - {AGESA_READ_SPD, agesa_ReadSpd }, - {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, - {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, - {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData }, - {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, - {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, - {AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage } -}; -const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); - -/** - * AMD Olivehill Platform ALC272 Verb Table - */ -static const CODEC_ENTRY Olivehill_Alc272_VerbTbl[] = { - {0x11, 0x411111F0}, // - SPDIF_OUT2 - {0x12, 0x411111F0}, // - DMIC_1/2 - {0x13, 0x411111F0}, // - DMIC_3/4 - {0x14, 0x411111F0}, // Port D - LOUT1 - {0x15, 0x411111F0}, // Port A - LOUT2 - {0x16, 0x411111F0}, // - {0x17, 0x411111F0}, // Port H - MONO - {0x18, 0x01a19840}, // Port B - MIC1 - {0x19, 0x411111F0}, // Port F - MIC2 - {0x1a, 0x01813030}, // Port C - LINE1 - {0x1b, 0x411111F0}, // Port E - LINE2 - {0x1d, 0x40130605}, // - PCBEEP - {0x1e, 0x01441120}, // - SPDIF_OUT1 - {0x21, 0x01214010}, // Port I - HPOUT - {0xff, 0xffffffff} -}; - -static const CODEC_TBL_LIST OlivehillCodecTableList[] = -{ - {0x10ec0272, (CODEC_ENTRY*)&Olivehill_Alc272_VerbTbl[0]}, - {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL} -}; - -#define FAN_INPUT_INTERNAL_DIODE 0 -#define FAN_INPUT_TEMP0 1 -#define FAN_INPUT_TEMP1 2 -#define FAN_INPUT_TEMP2 3 -#define FAN_INPUT_TEMP3 4 -#define FAN_INPUT_TEMP0_FILTER 5 -#define FAN_INPUT_ZERO 6 -#define FAN_INPUT_DISABLED 7 - -#define FAN_AUTOMODE (1 << 0) -#define FAN_LINEARMODE (1 << 1) -#define FAN_STEPMODE ~(1 << 1) -#define FAN_POLARITY_HIGH (1 << 2) -#define FAN_POLARITY_LOW ~(1 << 2) - -/* Normally, 4-wire fan runs at 25KHz and 3-wire fan runs at 100Hz */ -#define FREQ_28KHZ 0x0 -#define FREQ_25KHZ 0x1 -#define FREQ_23KHZ 0x2 -#define FREQ_21KHZ 0x3 -#define FREQ_29KHZ 0x4 -#define FREQ_18KHZ 0x5 -#define FREQ_100HZ 0xF7 -#define FREQ_87HZ 0xF8 -#define FREQ_58HZ 0xF9 -#define FREQ_44HZ 0xFA -#define FREQ_35HZ 0xFB -#define FREQ_29HZ 0xFC -#define FREQ_22HZ 0xFD -#define FREQ_14HZ 0xFE -#define FREQ_11HZ 0xFF - -/* Olivehill Hardware Monitor Fan Control - * Hardware limitation: - * HWM failed to read the input temperture vi I2C, - * if other software switch the I2C switch by mistake or intention. - * We recommend to using IMC to control Fans, instead of HWM. - */ -static void oem_fan_control(FCH_DATA_BLOCK *FchParams) -{ - /* Enable IMC fan control. the recommand way */ - if (CONFIG(HUDSON_IMC_FWM)) { - imc_reg_init(); - - /* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */ - FchParams->Hwm.HwMonitorEnable = TRUE; - FchParams->Hwm.HwmFchtsiAutoPoll = FALSE;/* 0 disable, 1 enable TSI Auto Polling */ - - FchParams->Imc.ImcEnable = TRUE; - FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */ - FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ - - LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader); - - /* Thermal Zone Parameter */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; //BIT0 | BIT2 | BIT5; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x4e;//6 | BIT3; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x04; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x9a; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg7 = 0x01; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg8 = 0x01; /* PWM steping rate in unit of PWM level percentage */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg9 = 0x00; - - /* IMC Fan Policy temperature thresholds */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x46;///80; /*AC0 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0x3c; /*AC1 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0x32; /*AC2 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff; /*AC3 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0xff; /*AC4 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0xff; /*AC5 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0xff; /*AC6 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0xff; /*AC7 lowest threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegA = 0x4b; /*critical threshold* in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegB = 0x00; - - /* IMC Fan Policy PWM Settings */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg2 = 0x5a; /* AL0 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg3 = 0x46; /* AL1 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg4 = 0x28; /* AL2 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg5 = 0xff; /* AL3 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg6 = 0xff; /* AL4 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg7 = 0xff; /* AL5 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0xff; /* AL6 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0xff; /* AL7 percentage */ - - FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x111;//BIT0 | BIT4 |BIT8; - - /* NOTE: - * FchInitLateHwm will overwrite the EcStruct with EcDefaultMassege, - * AGESA put EcDefaultMassege as global data in ROM, so we can't overwride it. - * so we remove it from AGESA code. Please Seee FchInitLateHwm. - */ - } else { - /* HWM fan control, the way not recommand */ - FchParams->Imc.ImcEnable = FALSE; - FchParams->Hwm.HwMonitorEnable = TRUE; - FchParams->Hwm.HwmFchtsiAutoPoll = TRUE;/* 1 enable, 0 disable TSI Auto Polling */ - } -} - -void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset) -{ -} - -void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env) -{ - /* Azalia Controller OEM Codec Table Pointer */ - FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&OlivehillCodecTableList[0]); - - /* Fan Control */ - oem_fan_control(FchParams_env); -} diff --git a/src/mainboard/amd/olivehill/Kconfig b/src/mainboard/amd/olivehill/Kconfig deleted file mode 100644 index 78f768f..0000000 --- a/src/mainboard/amd/olivehill/Kconfig +++ /dev/null @@ -1,64 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2012 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -config BOARD_AMD_OLIVEHILL - def_bool n - -if BOARD_AMD_OLIVEHILL - -config BOARD_SPECIFIC_OPTIONS - def_bool y - #select ROMCC_BOOTBLOCK - select CPU_AMD_AGESA_FAMILY16_KB - select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB - select SOUTHBRIDGE_AMD_AGESA_YANGTZE - select DEFAULT_POST_ON_LPC - select HAVE_OPTION_TABLE - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select HAVE_ACPI_RESUME - select HAVE_ACPI_TABLES - select BOARD_ROMSIZE_KB_4096 - select GFXUMA - -config MAINBOARD_DIR - string - default "amd/olivehill" - -config MAINBOARD_PART_NUMBER - string - default "DB-FT3" - -config HW_MEM_HOLE_SIZEK - hex - default 0x200000 - -config MAX_CPUS - int - default 4 - -config IRQ_SLOT_COUNT - int - default 11 - -config ONBOARD_VGA_IS_PRIMARY - bool - default y - -config HUDSON_LEGACY_FREE - bool - default y - -endif # BOARD_AMD_OLIVEHILL diff --git a/src/mainboard/amd/olivehill/Kconfig.name b/src/mainboard/amd/olivehill/Kconfig.name deleted file mode 100644 index d065472..0000000 --- a/src/mainboard/amd/olivehill/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -#config BOARD_AMD_OLIVEHILL -# bool"Olive Hill" diff --git a/src/mainboard/amd/olivehill/Makefile.inc b/src/mainboard/amd/olivehill/Makefile.inc deleted file mode 100644 index f8895fa..0000000 --- a/src/mainboard/amd/olivehill/Makefile.inc +++ /dev/null @@ -1,22 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2012 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -romstage-y += buildOpts.c -romstage-y += BiosCallOuts.c -romstage-y += OemCustomize.c - -ramstage-y += buildOpts.c -ramstage-y += BiosCallOuts.c -ramstage-y += OemCustomize.c diff --git a/src/mainboard/amd/olivehill/OemCustomize.c b/src/mainboard/amd/olivehill/OemCustomize.c deleted file mode 100644 index df13fa5..0000000 --- a/src/mainboard/amd/olivehill/OemCustomize.c +++ /dev/null @@ -1,152 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <AGESA.h> -#include <PlatformMemoryConfiguration.h> - -#include <northbridge/amd/agesa/state_machine.h> - -static const PCIe_PORT_DESCRIPTOR PortList[] = { - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 3, 3), - PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 5, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 0x01, 0) - }, - /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 2), - PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 4, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 0x02, 0) - }, - /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 1, 1), - PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 3, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 0x03, 0) - }, - /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 0), - PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 2, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 0x04, 0) - }, - /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */ - { - DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7), - PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 1, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 0x05, 0) - } -}; - -static const PCIe_DDI_DESCRIPTOR DdiList[] = { - /* DP0 to HDMI0/DP */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1) - }, - /* DP1 to FCH */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2) - }, - /* DP2 to HDMI1/DP */ - { - DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 16, 19), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeCrt, Aux3, Hdp3) - }, -}; - -static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { - .Flags = DESCRIPTOR_TERMINATE_LIST, - .SocketId = 0, - .PciePortList = PortList, - .DdiLinkList = DdiList -}; - -void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) -{ - FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface; - FchReset->Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); - FchReset->Xhci1Enable = FALSE; -} - -void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) -{ - InitEarly->GnbConfig.PcieComplexList = &PcieComplex; -} - -/*---------------------------------------------------------------------------------------- - * CUSTOMER OVERIDES MEMORY TABLE - *---------------------------------------------------------------------------------------- - */ - -/* - * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA - * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable - * is populated, AGESA will base its settings on the data from the table. Otherwise, it will - * use its default conservative settings. - */ -static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { - #define SEED_A 0x12 - HW_RXEN_SEED( - ANY_SOCKET, CHANNEL_A, ALL_DIMMS, - SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, - SEED_A), - - NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2), - NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1), - MOTHER_BOARD_LAYERS(LAYERS_4), - - MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00), - CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */ - ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), - CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00), - - PSO_END -}; - -void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) -{ - InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; -} - -void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) -{ - /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ - InitMid->GnbMidConfiguration.iGpuVgaMode = 0; -} diff --git a/src/mainboard/amd/olivehill/OptionsIds.h b/src/mainboard/amd/olivehill/OptionsIds.h deleted file mode 100644 index eaf2442..0000000 --- a/src/mainboard/amd/olivehill/OptionsIds.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDS_DEBUG_PORT - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_CONTROL_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE -#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE -//#define IDSOPT_PERF_ANALYSIS TRUE -#define IDSOPT_ASSERT_ENABLED TRUE -//#undef IDSOPT_DEBUG_ENABLED -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - -#endif diff --git a/src/mainboard/amd/olivehill/acpi/gpe.asl b/src/mainboard/amd/olivehill/acpi/gpe.asl deleted file mode 100644 index 87b0d21..0000000 --- a/src/mainboard/amd/olivehill/acpi/gpe.asl +++ /dev/null @@ -1,74 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Scope(\_GPE) { /* Start Scope GPE */ - - /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* Legacy PM event */ - Method(_L08) { - /* DBGO("\\_GPE\\_L08\n") */ - } - - /* Temp warning (TWarn) event */ - Method(_L09) { - /* DBGO("\\_GPE\\_L09\n") */ - /* Notify (\_TZ.TZ00, 0x80) */ - } - - /* USB controller PME# */ - Method(_L0B) { - /* DBGO("\\_GPE\\_L0B\n") */ - Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* ExtEvent0 SCI event */ - Method(_L10) { - /* DBGO("\\_GPE\\_L10\n") */ - } - - /* ExtEvent1 SCI event */ - Method(_L11) { - /* DBGO("\\_GPE\\_L11\n") */ - } - - /* GPIO0 or GEvent8 event */ - Method(_L18) { - /* DBGO("\\_GPE\\_L18\n") */ - Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* Azalia SCI event */ - Method(_L1B) { - /* DBGO("\\_GPE\\_L1B\n") */ - Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } -} /* End Scope GPE */ diff --git a/src/mainboard/amd/olivehill/acpi/ide.asl b/src/mainboard/amd/olivehill/acpi/ide.asl deleted file mode 100644 index e7f4625..0000000 --- a/src/mainboard/amd/olivehill/acpi/ide.asl +++ /dev/null @@ -1,246 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012-2013 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* No IDE functionality */ - -#if 0 -/* -Scope (_SB) { - Device(PCI0) { - Device(IDEC) { - Name(_ADR, 0x00140001) - #include "ide.asl" - } - } -} -*/ - -/* Some timing tables */ -Name(UDTT, Package(){ /* Udma timing table */ - 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */ -}) - -Name(MDTT, Package(){ /* MWDma timing table */ - 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */ -}) - -Name(POTT, Package(){ /* Pio timing table */ - 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */ -}) - -/* Some timing register value tables */ -Name(MDRT, Package(){ /* MWDma timing register table */ - 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */ -}) - -Name(PORT, Package(){ - 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */ -}) - -OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */ - Field(ICRG, AnyAcc, NoLock, Preserve) -{ - PPTS, 8, /* Primary PIO Slave Timing */ - PPTM, 8, /* Primary PIO Master Timing */ - OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */ - PMTM, 8, /* Primary MWDMA Master Timing */ - OFFSET(0x08), PPCR, 8, /* Primary PIO Control */ - OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */ - PPSM, 4, /* Primary PIO slave Mode */ - OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */ - OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */ - PDSM, 4, /* Primary UltraDMA Mode */ -} - -Method(GTTM, 1) /* get total time*/ -{ - Store(And(Arg0, 0x0F), Local0) /* Recovery Width */ - Increment(Local0) - Store(ShiftRight(Arg0, 4), Local1) /* Command Width */ - Increment(Local1) - Return(Multiply(30, Add(Local0, Local1))) -} - -Device(PRID) -{ - Name (_ADR, Zero) - Method(_GTM, 0) - { - NAME(OTBF, Buffer(20) { /* out buffer */ - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 - }) - - CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */ - CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */ - CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */ - CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */ - CreateDwordField(OTBF, 16, BFFG) /* buffer flags */ - - /* Just return if the channel is disabled */ - If(And(PPCR, 0x01)) { /* primary PIO control */ - Return(OTBF) - } - - /* Always tell them independent timing available and IOChannelReady used on both drives */ - Or(BFFG, 0x1A, BFFG) - - /* save total time of primary PIO master timing to PIO spd0 */ - Store(GTTM(PPTM), PSD0) - /* save total time of primary PIO slave Timing to PIO spd1 */ - Store(GTTM(PPTS), PSD1) - - If(And(PDCR, 0x01)) { /* It's under UDMA mode */ - Or(BFFG, 0x01, BFFG) - Store(DerefOf(Index(UDTT, PDMM)), DSD0) - } - Else { - Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */ - } - - If(And(PDCR, 0x02)) { /* It's under UDMA mode */ - Or(BFFG, 0x04, BFFG) - Store(DerefOf(Index(UDTT, PDSM)), DSD1) - } - Else { - Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */ - } - - Return(OTBF) /* out buffer */ - } /* End Method(_GTM) */ - - Method(_STM, 3, NotSerialized) - { - NAME(INBF, Buffer(20) { /* in buffer */ - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 - }) - - CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */ - CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */ - CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */ - CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */ - CreateDwordField(INBF, 16, BFFG) /*buffer flag */ - - Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0) - Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */ - Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1) - Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */ - - Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */ - Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */ - - If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0) - Divide(Local0, 7, PDMM,) - Or(PDCR, 0x01, PDCR) - } - Else { - If(LNotEqual(DSD0, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTM) - } - } - - If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0) - Divide(Local0, 7, PDSM,) - Or(PDCR, 0x02, PDCR) - } - Else { - If(LNotEqual(DSD1, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTS) - } - } - /* Return(INBF) */ - } /*End Method(_STM) */ - Device(MST) - { - Name(_ADR, 0) - Method(_GTF) { - Name(CMBF, Buffer(21) { - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 - }) - CreateByteField(CMBF, 1, POMD) - CreateByteField(CMBF, 8, DMMD) - CreateByteField(CMBF, 5, CMDA) - CreateByteField(CMBF, 12, CMDB) - CreateByteField(CMBF, 19, CMDC) - - Store(0xA0, CMDA) - Store(0xA0, CMDB) - Store(0xA0, CMDC) - - Or(PPMM, 0x08, POMD) - - If(And(PDCR, 0x01)) { - Or(PDMM, 0x40, DMMD) - } - Else { - Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) - } - } - Return(CMBF) - } - } /* End Device(MST) */ - - Device(SLAV) - { - Name(_ADR, 1) - Method(_GTF) { - Name(CMBF, Buffer(21) { - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 - }) - CreateByteField(CMBF, 1, POMD) - CreateByteField(CMBF, 8, DMMD) - CreateByteField(CMBF, 5, CMDA) - CreateByteField(CMBF, 12, CMDB) - CreateByteField(CMBF, 19, CMDC) - - Store(0xB0, CMDA) - Store(0xB0, CMDB) - Store(0xB0, CMDC) - - Or(PPSM, 0x08, POMD) - - If(And(PDCR, 0x02)) { - Or(PDSM, 0x40, DMMD) - } - Else { - Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) - } - } - Return(CMBF) - } - } /* End Device(SLAV) */ -} -#endif diff --git a/src/mainboard/amd/olivehill/acpi/mainboard.asl b/src/mainboard/amd/olivehill/acpi/mainboard.asl deleted file mode 100644 index 68609d8..0000000 --- a/src/mainboard/amd/olivehill/acpi/mainboard.asl +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Memory related values */ -Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ -Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ -Name(PBLN, 0x0) /* Length of BIOS area */ - -Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ -Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */ -Name(HPBA, 0xFED00000) /* Base address of HPET table */ - -/* Some global data */ -Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ -Name(OSV, Ones) /* Assume nothing */ -Name(PMOD, One) /* Assume APIC */ - -/* AcpiGpe0Blk */ -OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04) - Field(GP0B, ByteAcc, NoLock, Preserve) { - , 11, - USBS, 1, -} diff --git a/src/mainboard/amd/olivehill/acpi/routing.asl b/src/mainboard/amd/olivehill/acpi/routing.asl deleted file mode 100644 index 1fb4c1d..0000000 --- a/src/mainboard/amd/olivehill/acpi/routing.asl +++ /dev/null @@ -1,194 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* -#include <arch/acpi.h> -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 - ) - { - #include "routing.asl" - } -*/ - -/* Routing is in System Bus scope */ -Name(PR0, Package(){ - /* NB devices */ - /* Bus 0, Dev 0 - F16 Host Controller */ - - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ - /* Bus 0, Dev 1, Func 1 - HDMI Audio Controller */ - Package(){0x0001FFFF, 0, INTB, 0 }, - Package(){0x0001FFFF, 1, INTC, 0 }, - - - /* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */ - Package(){0x0002FFFF, 0, INTC, 0 }, - Package(){0x0002FFFF, 1, INTD, 0 }, - Package(){0x0002FFFF, 2, INTA, 0 }, - Package(){0x0002FFFF, 3, INTB, 0 }, - - /* FCH devices */ - /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */ - Package(){0x0014FFFF, 0, INTA, 0 }, - Package(){0x0014FFFF, 1, INTB, 0 }, - Package(){0x0014FFFF, 2, INTC, 0 }, - Package(){0x0014FFFF, 3, INTD, 0 }, - - /* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */ - /* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */ - Package(){0x0012FFFF, 0, INTC, 0 }, - Package(){0x0012FFFF, 1, INTB, 0 }, - - Package(){0x0013FFFF, 0, INTC, 0 }, - Package(){0x0013FFFF, 1, INTB, 0 }, - - Package(){0x0016FFFF, 0, INTC, 0 }, - Package(){0x0016FFFF, 1, INTB, 0 }, - - /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */ - Package(){0x0010FFFF, 0, INTC, 0 }, - Package(){0x0010FFFF, 1, INTB, 0 }, - - /* Bus 0, Dev 17 - SATA controller */ - Package(){0x0011FFFF, 0, INTD, 0 }, - -}) - -Name(APR0, Package(){ - /* NB devices in APIC mode */ - /* Bus 0, Dev 0 - F15 Host Controller */ - - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ - Package(){0x0001FFFF, 0, 0, 44 }, - Package(){0x0001FFFF, 1, 0, 45 }, - - /* Bus 0, Dev 2 - PCIe Bridges */ - Package(){0x0002FFFF, 0, 0, 24 }, - Package(){0x0002FFFF, 1, 0, 25 }, - Package(){0x0002FFFF, 2, 0, 26 }, - Package(){0x0002FFFF, 3, 0, 27 }, - - - /* SB devices in APIC mode */ - /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */ - Package(){0x0014FFFF, 0, 0, 16 }, - Package(){0x0014FFFF, 1, 0, 17 }, - Package(){0x0014FFFF, 2, 0, 18 }, - Package(){0x0014FFFF, 3, 0, 19 }, - - /* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */ - /* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */ - Package(){0x0012FFFF, 0, 0, 18 }, - Package(){0x0012FFFF, 1, 0, 17 }, - - Package(){0x0013FFFF, 0, 0, 18 }, - Package(){0x0013FFFF, 1, 0, 17 }, - - Package(){0x0016FFFF, 0, 0, 18 }, - Package(){0x0016FFFF, 1, 0, 17 }, - - /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */ - Package(){0x0010FFFF, 0, 0, 0x12}, - Package(){0x0010FFFF, 1, 0, 0x11}, - - /* Bus 0, Dev 17 - SATA controller */ - Package(){0x0011FFFF, 0, 0, 19 }, - -}) - -Name(PS2, Package(){ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, -}) -Name(APS2, Package(){ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, -}) - -/* GFX */ -Name(PS4, Package(){ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, -}) -Name(APS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, 0, 24 }, - Package(){0x0000FFFF, 1, 0, 25 }, - Package(){0x0000FFFF, 2, 0, 26 }, - Package(){0x0000FFFF, 3, 0, 27 }, -}) - -/* GPP 0 */ -Name(PS5, Package(){ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, -}) -Name(APS5, Package(){ - Package(){0x0000FFFF, 0, 0, 28 }, - Package(){0x0000FFFF, 1, 0, 29 }, - Package(){0x0000FFFF, 2, 0, 30 }, - Package(){0x0000FFFF, 3, 0, 31 }, -}) - -/* GPP 1 */ -Name(PS6, Package(){ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, -}) -Name(APS6, Package(){ - Package(){0x0000FFFF, 0, 0, 32 }, - Package(){0x0000FFFF, 1, 0, 33 }, - Package(){0x0000FFFF, 2, 0, 34 }, - Package(){0x0000FFFF, 3, 0, 35 }, -}) - -/* GPP 2 */ -Name(PS7, Package(){ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, -}) -Name(APS7, Package(){ - Package(){0x0000FFFF, 0, 0, 36 }, - Package(){0x0000FFFF, 1, 0, 37 }, - Package(){0x0000FFFF, 2, 0, 38 }, - Package(){0x0000FFFF, 3, 0, 39 }, -}) - -/* GPP 3 */ -Name(PS8, Package(){ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, -}) -Name(APS8, Package(){ - Package(){0x0000FFFF, 0, 0, 40 }, - Package(){0x0000FFFF, 1, 0, 41 }, - Package(){0x0000FFFF, 2, 0, 42 }, - Package(){0x0000FFFF, 3, 0, 43 }, -}) diff --git a/src/mainboard/amd/olivehill/acpi/sata.asl b/src/mainboard/amd/olivehill/acpi/sata.asl deleted file mode 100644 index 6755258..0000000 --- a/src/mainboard/amd/olivehill/acpi/sata.asl +++ /dev/null @@ -1,146 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012-2013 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* No SATA functionality */ - -#if 0 -/* -Scope (_SB) { - Device(PCI0) { - Device(SATA) { - Name(_ADR, 0x00110000) - #include "sata.asl" - } - } -} -*/ - -Name(STTM, Buffer(20) { - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x1f, 0x00, 0x00, 0x00 -}) - -/* Start by clearing the PhyRdyChg bits */ -Method(_INI) { - \_GPE._L1F() -} - -Device(PMRY) -{ - Name(_ADR, 0) - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(PMST) { - Name(_ADR, 0) - Method(_STA,0) { - if (LGreater(P0IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - }/* end of PMST */ - - Device(PSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (LGreater(P1IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of PSLA */ -} /* end of PMRY */ - -Device(SEDY) -{ - Name(_ADR, 1) /* IDE Scondary Channel */ - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(SMST) - { - Name(_ADR, 0) - Method(_STA,0) { - if (LGreater(P2IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SMST */ - - Device(SSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (LGreater(P3IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SSLA */ -} /* end of SEDY */ - -/* SATA Hot Plug Support */ -Scope(\_GPE) { - Method(_L1F,0x0,NotSerialized) { - if (\_SB.P0PR) { - if (LGreater(\_SB.P0IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P0PR) - } - - if (\_SB.P1PR) { - if (LGreater(\_SB.P1IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P1PR) - } - - if (\_SB.P2PR) { - if (LGreater(\_SB.P2IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P2PR) - } - - if (\_SB.P3PR) { - if (LGreater(\_SB.P3IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P3PR) - } - } -} -#endif diff --git a/src/mainboard/amd/olivehill/acpi/si.asl b/src/mainboard/amd/olivehill/acpi/si.asl deleted file mode 100644 index 2923471..0000000 --- a/src/mainboard/amd/olivehill/acpi/si.asl +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Scope(\_SI) { - Method(_SST, 1) { - /* DBGO("\\_SI\\_SST\n") */ - /* DBGO(" New Indicator state: ") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - } -} /* End Scope SI */ diff --git a/src/mainboard/amd/olivehill/acpi/sleep.asl b/src/mainboard/amd/olivehill/acpi/sleep.asl deleted file mode 100644 index 1225a62..0000000 --- a/src/mainboard/amd/olivehill/acpi/sleep.asl +++ /dev/null @@ -1,93 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Wake status package */ -Name(WKST,Package(){Zero, Zero}) - -/* -* \_PTS - Prepare to Sleep method -* -* Entry: -* Arg0=The value of the sleeping state S1=1, S2=2, etc -* -* Exit: -* -none- -* -* The _PTS control method is executed at the beginning of the sleep process -* for S1-S5. The sleeping value is passed to the _PTS control method. This -* control method may be executed a relatively long time before entering the -* sleep state and the OS may abort the operation without notification to -* the ACPI driver. This method cannot modify the configuration or power -* state of any device in the system. -*/ - -External(\_SB.APTS, MethodObj) -External(\_SB.AWAK, MethodObj) - -Method(_PTS, 1) { - /* DBGO("\\_PTS\n") */ - /* DBGO("From S0 to S") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - - /* Clear wake status structure. */ - Store(0, Index(WKST,0)) - Store(0, Index(WKST,1)) - Store(7, UPWS) - \_SB.APTS(Arg0) -} /* End Method(\_PTS) */ - -/* -* \_BFS OEM Back From Sleep method -* -* Entry: -* Arg0=The value of the sleeping state S1=1, S2=2 -* -* Exit: -* -none- -*/ -Method(\_BFS, 1) { - /* DBGO("\\_BFS\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ -} - -/* -* \_WAK System Wake method -* -* Entry: -* Arg0=The value of the sleeping state S1=1, S2=2 -* -* Exit: -* Return package of 2 DWords -* Dword 1 - Status -* 0x00000000 wake succeeded -* 0x00000001 Wake was signaled but failed due to lack of power -* 0x00000002 Wake was signaled but failed due to thermal condition -* Dword 2 - Power Supply state -* if non-zero the effective S-state the power supply entered -*/ -Method(\_WAK, 1) { - /* DBGO("\\_WAK\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - Store(1,USBS) - - \_SB.AWAK(Arg0) - - Return(WKST) -} /* End Method(\_WAK) */ diff --git a/src/mainboard/amd/olivehill/acpi/superio.asl b/src/mainboard/amd/olivehill/acpi/superio.asl deleted file mode 100644 index e69de29..0000000 --- a/src/mainboard/amd/olivehill/acpi/superio.asl +++ /dev/null diff --git a/src/mainboard/amd/olivehill/acpi/thermal.asl b/src/mainboard/amd/olivehill/acpi/thermal.asl deleted file mode 100644 index e69de29..0000000 --- a/src/mainboard/amd/olivehill/acpi/thermal.asl +++ /dev/null diff --git a/src/mainboard/amd/olivehill/acpi/usb_oc.asl b/src/mainboard/amd/olivehill/acpi/usb_oc.asl deleted file mode 100644 index 513d66d..0000000 --- a/src/mainboard/amd/olivehill/acpi/usb_oc.asl +++ /dev/null @@ -1,129 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* simple name description */ -/* -#include <arch/acpi.h> -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 - ) - { - #include "usb.asl" - } -*/ - -/* USB overcurrent mapping pins. */ -Name(UOM0, 0) -Name(UOM1, 2) -Name(UOM2, 0) -Name(UOM3, 7) -Name(UOM4, 2) -Name(UOM5, 2) -Name(UOM6, 6) -Name(UOM7, 2) -Name(UOM8, 6) -Name(UOM9, 6) - -/* USB Overcurrent GPEs */ - -#if 0 /* TODO: Update for Olivehill */ -Method(UCOC, 0) { - Sleep(20) - Store(0x13,CMTI) - Store(0,GPSL) -} - -/* USB Port 0 overcurrent uses Gpm 0 */ -If(LLessEqual(UOM0,9)) { - Scope (\_GPE) { - Method (_L13) { - } - } -} - -/* USB Port 1 overcurrent uses Gpm 1 */ -If (LLessEqual(UOM1,9)) { - Scope (\_GPE) { - Method (_L14) { - } - } -} - -/* USB Port 2 overcurrent uses Gpm 2 */ -If (LLessEqual(UOM2,9)) { - Scope (\_GPE) { - Method (_L15) { - } - } -} - -/* USB Port 3 overcurrent uses Gpm 3 */ -If (LLessEqual(UOM3,9)) { - Scope (\_GPE) { - Method (_L16) { - } - } -} - -/* USB Port 4 overcurrent uses Gpm 4 */ -If (LLessEqual(UOM4,9)) { - Scope (\_GPE) { - Method (_L19) { - } - } -} - -/* USB Port 5 overcurrent uses Gpm 5 */ -If (LLessEqual(UOM5,9)) { - Scope (\_GPE) { - Method (_L1A) { - } - } -} - -/* USB Port 6 overcurrent uses Gpm 6 */ -If (LLessEqual(UOM6,9)) { - Scope (\_GPE) { - /* Method (_L1C) { */ - Method (_L06) { - } - } -} - -/* USB Port 7 overcurrent uses Gpm 7 */ -If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { - /* Method (_L1D) { */ - Method (_L07) { - } - } -} - -/* USB Port 8 overcurrent uses Gpm 8 */ -If (LLessEqual(UOM8,9)) { - Scope (\_GPE) { - Method (_L17) { - } - } -} - -/* USB Port 9 overcurrent uses Gpm 9 */ -If (LLessEqual(UOM9,9)) { - Scope (\_GPE) { - Method (_L0E) { - } - } -} -#endif diff --git a/src/mainboard/amd/olivehill/acpi_tables.c b/src/mainboard/amd/olivehill/acpi_tables.c deleted file mode 100644 index 20509e9..0000000 --- a/src/mainboard/amd/olivehill/acpi_tables.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/acpi.h> -#include <arch/ioapic.h> - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); - - /* Write SB800 IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, - IO_APIC_ADDR, 0); - - /* TODO: Remove the hardcode */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS+1, - 0xFEC20000, 24); - - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xF); - /* 0: mean bus 0--->ISA */ - /* 0: PIC 0 */ - /* 2: APIC 2 */ - /* 5 mean: 0101 --> Edge-triggered, Active high */ - - /* create all subtables for processors */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1); - /* 1: LINT1 connect to NMI */ - - return current; -} diff --git a/src/mainboard/amd/olivehill/board_info.txt b/src/mainboard/amd/olivehill/board_info.txt deleted file mode 100644 index b351b8e..0000000 --- a/src/mainboard/amd/olivehill/board_info.txt +++ /dev/null @@ -1 +0,0 @@ -Category: eval diff --git a/src/mainboard/amd/olivehill/buildOpts.c b/src/mainboard/amd/olivehill/buildOpts.c deleted file mode 100644 index 65b86b8..0000000 --- a/src/mainboard/amd/olivehill/buildOpts.c +++ /dev/null @@ -1,342 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/** - * @file - * - * AMD User options selection for a Brazos platform solution system - * - * This file is placed in the user's platform directory and contains the - * build option selections desired for that platform. - * - * For Information about this file, see @ref platforminstall. - * - */ - -#include <stdlib.h> -#include <AGESA.h> - -#define INSTALL_FT3_SOCKET_SUPPORT TRUE -#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE - -#define INSTALL_G34_SOCKET_SUPPORT FALSE -#define INSTALL_C32_SOCKET_SUPPORT FALSE -#define INSTALL_S1G3_SOCKET_SUPPORT FALSE -#define INSTALL_S1G4_SOCKET_SUPPORT FALSE -#define INSTALL_ASB2_SOCKET_SUPPORT FALSE -#define INSTALL_FS1_SOCKET_SUPPORT FALSE -#define INSTALL_FM1_SOCKET_SUPPORT FALSE -#define INSTALL_FP2_SOCKET_SUPPORT FALSE -#define INSTALL_FT1_SOCKET_SUPPORT FALSE -#define INSTALL_AM3_SOCKET_SUPPORT FALSE -#define INSTALL_FM2_SOCKET_SUPPORT FALSE - - -#ifdef BLDOPT_REMOVE_FT3_SOCKET_SUPPORT - #if BLDOPT_REMOVE_FT3_SOCKET_SUPPORT == TRUE - #undef INSTALL_FT3_SOCKET_SUPPORT - #define INSTALL_FT3_SOCKET_SUPPORT FALSE - #endif -#endif - -//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE -//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE -#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE -#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE -#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE -//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE -#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE -//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE -#define BLDOPT_REMOVE_SRAT FALSE //TRUE -#define BLDOPT_REMOVE_SLIT FALSE //TRUE -#define BLDOPT_REMOVE_WHEA FALSE //TRUE -#define BLDOPT_REMOVE_CRAT TRUE -#define BLDOPT_REMOVE_CDIT TRUE -#define BLDOPT_REMOVE_DMI TRUE -//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE - -//This element selects whether P-States should be forced to be independent, -// as reported by the ACPI _PSD object. For single-link processors, -// setting TRUE for OS to support this feature. - -//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE - -#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER -/* Build configuration values here. - */ -#define BLDCFG_VRM_CURRENT_LIMIT 15000 -#define BLDCFG_VRM_NB_CURRENT_LIMIT 13000 -#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 21000 -#define BLDCFG_VRM_SVI_OCP_LEVEL BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT -#define BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT 17000 -#define BLDCFG_VRM_NB_SVI_OCP_LEVEL BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT -#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0 -#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 0 -#define BLDCFG_VRM_SLEW_RATE 10000 -#define BLDCFG_VRM_NB_SLEW_RATE BLDCFG_VRM_SLEW_RATE -#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE - -#define BLDCFG_PLAT_NUM_IO_APICS 3 -#define BLDCFG_GNB_IOAPIC_ADDRESS 0xFEC20000 -#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST -#define BLDCFG_MEM_INIT_PSTATE 0 -#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 // Specifies the IO addresses trapped by the - // core for C-state entry requests. A value - // of 0 in this field specifies that the core - // does not trap any IO addresses for C-state entry. - // Values greater than 0xFFF8 results in undefined behavior. -#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770 - -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE - -#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY -#define BLDCFG_MEMORY_MODE_UNGANGED TRUE -#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE -#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE -#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE -#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE -#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE -#define BLDCFG_MEMORY_POWER_DOWN TRUE -#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT -#define BLDCFG_ONLINE_SPARE FALSE -#define BLDCFG_BANK_SWIZZLE TRUE -#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#define BLDCFG_MEMORY_CLOCK_SELECT DDR1866_FREQUENCY -#define BLDCFG_DQS_TRAINING_CONTROL TRUE -#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE -#define BLDCFG_USE_BURST_MODE FALSE -#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE -#define BLDCFG_ENABLE_ECC_FEATURE TRUE -#define BLDCFG_ECC_REDIRECTION FALSE -#define BLDCFG_SCRUB_DRAM_RATE 0 -#define BLDCFG_SCRUB_L2_RATE 0 -#define BLDCFG_SCRUB_L3_RATE 0 -#define BLDCFG_SCRUB_IC_RATE 0 -#define BLDCFG_SCRUB_DC_RATE 0 -#define BLDCFG_ECC_SYNC_FLOOD TRUE -#define BLDCFG_ECC_SYMBOL_SIZE 4 -#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000ul -#define BLDCFG_1GB_ALIGN FALSE -#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED -#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO -#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeDisabled -#define BLDCFG_IOMMU_SUPPORT FALSE -#define OPTION_GFX_INIT_SVIEW FALSE -//#define BLDCFG_PLATFORM_POWER_POLICY_MODE BatteryLife - -//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL OEM_LCD_BACK_LIGHT_CONTROL -#define BLDCFG_CFG_ABM_SUPPORT TRUE - -#define BLDCFG_CFG_GNB_HD_AUDIO TRUE -//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID -//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID -//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID - -#ifdef PCIEX_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_BASE PCIEX_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_SIZE (PCIEX_LENGTH >> 20) -#endif - -#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P' -#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' -#define BLDCFG_PCIE_TRAINING_ALGORITHM PcieTrainingDistributed - -/* Process the options... - * This file include MUST occur AFTER the user option selection settings - */ -/* - * Customized OEM build configurations for FCH component - */ -// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00 -// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20 -// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00 -// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400 -// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404 -// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408 -// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410 -// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420 -// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000 -// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000 -// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000 -// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0 -// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00 -// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000 -// #define BLDCFG_AZALIA_SSID 0x780D1022 -// #define BLDCFG_SMBUS_SSID 0x780B1022 -// #define BLDCFG_IDE_SSID 0x780C1022 -// #define BLDCFG_SATA_AHCI_SSID 0x78011022 -// #define BLDCFG_SATA_IDE_SSID 0x78001022 -// #define BLDCFG_SATA_RAID5_SSID 0x78031022 -// #define BLDCFG_SATA_RAID_SSID 0x78021022 -// #define BLDCFG_EHCI_SSID 0x78081022 -// #define BLDCFG_OHCI_SSID 0x78071022 -// #define BLDCFG_LPC_SSID 0x780E1022 -// #define BLDCFG_SD_SSID 0x78061022 -// #define BLDCFG_XHCI_SSID 0x78121022 -// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE -// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE -// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4 -// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE - -CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = -{ - { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 }, - { CPU_LIST_TERMINAL } -}; - -#define BLDCFG_AP_MTRR_SETTINGS_LIST &KabiniApMtrrSettingsList - - -/* Include the files that instantiate the configuration definitions. */ -#include "cpuRegisters.h" -#include "cpuFamRegisters.h" -#include "cpuFamilyTranslation.h" -#include "AdvancedApi.h" -#include "heapManager.h" -#include "CreateStruct.h" -#include "cpuFeatures.h" -#include "Table.h" -#include "cpuEarlyInit.h" -#include "cpuLateInit.h" -#include "GnbInterface.h" - - // This is the delivery package title, "BrazosPI" - // This string MUST be exactly 8 characters long -#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} - - // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long -#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} - -/* MEMORY_BUS_SPEED */ -//#define DDR400_FREQUENCY 200 ///< DDR 400 -//#define DDR533_FREQUENCY 266 ///< DDR 533 -//#define DDR667_FREQUENCY 333 ///< DDR 667 -//#define DDR800_FREQUENCY 400 ///< DDR 800 -//#define DDR1066_FREQUENCY 533 ///< DDR 1066 -//#define DDR1333_FREQUENCY 667 ///< DDR 1333 -//#define DDR1600_FREQUENCY 800 ///< DDR 1600 -//#define DDR1866_FREQUENCY 933 ///< DDR 1866 -//#define DDR2100_FREQUENCY 1050 ///< DDR 2100 -//#define DDR2133_FREQUENCY 1066 ///< DDR 2133 -//#define DDR2400_FREQUENCY 1200 ///< DDR 2400 -//#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency -// -///* QUANDRANK_TYPE*/ -//#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -//#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM -// -///* USER_MEMORY_TIMING_MODE */ -//#define TIMING_MODE_AUTO 0 ///< Use best rate possible -//#define TIMING_MODE_LIMITED 1 ///< Set user top limit -//#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed -// -///* POWER_DOWN_MODE */ -//#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -//#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode - -/* - * Agesa optional capabilities selection. - * Uncomment and mark FALSE those features you wish to include in the build. - * Comment out or mark TRUE those features you want to REMOVE from the build. - */ - -#define DFLT_SMBUS0_BASE_ADDRESS 0xB00 -#define DFLT_SMBUS1_BASE_ADDRESS 0xB20 -#define DFLT_SIO_PME_BASE_ADDRESS 0xE00 -#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800 -#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804 -#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808 -#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810 -#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820 -#define DFLT_SPI_BASE_ADDRESS 0xFEC10000 -#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 -#define DFLT_HPET_BASE_ADDRESS 0xFED00000 -#define DFLT_SMI_CMD_PORT 0xB0 -#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 -#define DFLT_GEC_BASE_ADDRESS 0xFED61000 -#define DFLT_AZALIA_SSID 0x780D1022 -#define DFLT_SMBUS_SSID 0x780B1022 -#define DFLT_IDE_SSID 0x780C1022 -#define DFLT_SATA_AHCI_SSID 0x78011022 -#define DFLT_SATA_IDE_SSID 0x78001022 -#define DFLT_SATA_RAID5_SSID 0x78031022 -#define DFLT_SATA_RAID_SSID 0x78021022 -#define DFLT_EHCI_SSID 0x78081022 -#define DFLT_OHCI_SSID 0x78071022 -#define DFLT_LPC_SSID 0x780E1022 -#define DFLT_SD_SSID 0x78061022 -#define DFLT_XHCI_SSID 0x78121022 -#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE -#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE -#define DFLT_FCH_GPP_LINK_CONFIG PortA4 -#define DFLT_FCH_GPP_PORT0_PRESENT FALSE -#define DFLT_FCH_GPP_PORT1_PRESENT FALSE -#define DFLT_FCH_GPP_PORT2_PRESENT FALSE -#define DFLT_FCH_GPP_PORT3_PRESENT FALSE -#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE -//#define BLDCFG_IR_PIN_CONTROL 0x33 - -GPIO_CONTROL olivehill_gpio[] = { - {183, Function1, GpioIn | GpioOutEnB | PullUpB}, - {-1} -}; -//#define BLDCFG_FCH_GPIO_CONTROL_LIST (&olivehill_gpio[0]) - -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. -#define DFLT_SCRUB_DRAM_RATE (0) -#define DFLT_SCRUB_L2_RATE (0) -#define DFLT_SCRUB_L3_RATE (0) -#define DFLT_SCRUB_IC_RATE (0) -#define DFLT_SCRUB_DC_RATE (0) -#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define DFLT_VRM_SLEW_RATE (5000) - -#include <PlatformInstall.h> diff --git a/src/mainboard/amd/olivehill/cmos.layout b/src/mainboard/amd/olivehill/cmos.layout deleted file mode 100644 index e1dbd9a..0000000 --- a/src/mainboard/amd/olivehill/cmos.layout +++ /dev/null @@ -1,66 +0,0 @@ -#***************************************************************************** -# -# This file is part of the coreboot project. -# -# Copyright (C) 2012 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -#***************************************************************************** - -entries - -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#392 3 r 0 unused -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum -# Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% - -checksums - -checksum 392 983 984 diff --git a/src/mainboard/amd/olivehill/devicetree.cb b/src/mainboard/amd/olivehill/devicetree.cb deleted file mode 100644 index b29d327..0000000 --- a/src/mainboard/amd/olivehill/devicetree.cb +++ /dev/null @@ -1,64 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2013 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -chip northbridge/amd/agesa/family16kb/root_complex - device cpu_cluster 0 on - chip cpu/amd/agesa/family16kb - device lapic 0 on end - end - end - - device domain 0 on - subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/agesa/family16kb - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 - device pci 1.1 on end # Internal Multimedia - device pci 2.0 on end # PCIe Host Bridge - device pci 2.1 on end # x4 PCIe slot - device pci 2.2 on end # mPCIe slot - device pci 2.3 on end # Realtek NIC - device pci 2.4 on end # Edge Connector - device pci 2.5 on end # Edge Connector - end #chip northbridge/amd/agesa/family16kb - - chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus - device pci 10.0 on end # XHCI HC0 - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on end # SM - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on end # LPC 0x439d - device pci 14.7 on end # SD - end #chip southbridge/amd/agesa/hudson - - chip northbridge/amd/agesa/family16kb - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - register "spdAddrLookup" = " - { - { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses - { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses - }" - end - - end #domain -end #northbridge/amd/agesa/family16kb/root_complex diff --git a/src/mainboard/amd/olivehill/dsdt.asl b/src/mainboard/amd/olivehill/dsdt.asl deleted file mode 100644 index c4fc934..0000000 --- a/src/mainboard/amd/olivehill/dsdt.asl +++ /dev/null @@ -1,88 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* DefinitionBlock Statement */ -#include <arch/acpi.h> -DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - OEM_ID, - ACPI_TABLE_CREATOR, - 0x00010001 /* OEM Revision */ - ) -{ /* Start of ASL file */ - /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ - - /* Globals for the platform */ - #include "acpi/mainboard.asl" - - /* Describe the USB Overcurrent pins */ - #include "acpi/usb_oc.asl" - - /* PCI IRQ mapping for the Southbridge */ - #include <southbridge/amd/agesa/hudson/acpi/pcie.asl> - - /* Describe the processor tree (\_PR) */ - #include <cpu/amd/agesa/family16kb/acpi/cpu.asl> - - /* Contains the supported sleep states for this chipset */ - #include <southbridge/amd/common/acpi/sleepstates.asl> - - /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */ - #include "acpi/sleep.asl" - - /* System Bus */ - Scope(\_SB) { /* Start \_SB scope */ - /* global utility methods expected within the \_SB scope */ - #include <arch/x86/acpi/globutil.asl> - - /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ - #include "acpi/routing.asl" - - Device(PWRB) { - Name(_HID, EISAID("PNP0C0C")) - Name(_UID, 0xAA) - Name(_PRW, Package () {3, 0x04}) - Name(_STA, 0x0B) - } - - Device(PCI0) { - /* Describe the AMD Northbridge */ - #include <northbridge/amd/agesa/family16kb/acpi/northbridge.asl> - - /* Describe the AMD Fusion Controller Hub Southbridge */ - #include <southbridge/amd/agesa/hudson/acpi/fch.asl> - } - - /* Describe PCI INT[A-H] for the Southbridge */ - #include <southbridge/amd/agesa/hudson/acpi/pci_int.asl> - - } /* End \_SB scope */ - - /* Describe SMBUS for the Southbridge */ - #include <southbridge/amd/agesa/hudson/acpi/smbus.asl> - - /* Define the General Purpose Events for the platform */ - #include "acpi/gpe.asl" - - /* Define the Thermal zones and methods for the platform */ - #include "acpi/thermal.asl" - - /* Define the System Indicators for the platform */ - #include "acpi/si.asl" -} -/* End of ASL file */ diff --git a/src/mainboard/amd/olivehill/irq_tables.c b/src/mainboard/amd/olivehill/irq_tables.c deleted file mode 100644 index 530c132..0000000 --- a/src/mainboard/amd/olivehill/irq_tables.c +++ /dev/null @@ -1,100 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <string.h> -#include <stdint.h> -#include <arch/pirq_routing.h> - -static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, - u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, - u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, - u8 slot, u8 rfu) -{ - pirq_info->bus = bus; - pirq_info->devfn = devfn; - pirq_info->irq[0].link = link0; - pirq_info->irq[0].bitmap = bitmap0; - pirq_info->irq[1].link = link1; - pirq_info->irq[1].bitmap = bitmap1; - pirq_info->irq[2].link = link2; - pirq_info->irq[2].bitmap = bitmap2; - pirq_info->irq[3].link = link3; - pirq_info->irq[3].bitmap = bitmap3; - pirq_info->slot = slot; - pirq_info->rfu = rfu; -} - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - struct irq_routing_table *pirq; - struct irq_info *pirq_info; - u32 slot_num; - u8 *v; - - u8 sum = 0; - int i; - - /* Align the table to be 16 byte aligned. */ - addr += 15; - addr &= ~15; - - /* This table must be between 0xf0000 & 0x100000 */ - printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); - - pirq = (void *)(addr); - v = (u8 *) (addr); - - pirq->signature = PIRQ_SIGNATURE; - pirq->version = PIRQ_VERSION; - - pirq->rtr_bus = 0; - pirq->rtr_devfn = PCI_DEVFN(0x14, 4); - - pirq->exclusive_irqs = 0; - - pirq->rtr_vendor = 0x1002; - pirq->rtr_device = 0x4384; - - pirq->miniport_data = 0; - - memset(pirq->rfu, 0, sizeof(pirq->rfu)); - - pirq_info = (void *)(&pirq->checksum + 1); - slot_num = 0; - - /* pci bridge */ - write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), - 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, - 0); - pirq_info++; - - slot_num++; - - pirq->size = 32 + 16 * slot_num; - - for (i = 0; i < pirq->size; i++) - sum += v[i]; - - sum = pirq->checksum - sum; - - if (sum != pirq->checksum) { - pirq->checksum = sum; - } - - printk(BIOS_INFO, "write_pirq_routing_table done.\n"); - - return (unsigned long)pirq_info; -} diff --git a/src/mainboard/amd/olivehill/mainboard.c b/src/mainboard/amd/olivehill/mainboard.c deleted file mode 100644 index 65e838b..0000000 --- a/src/mainboard/amd/olivehill/mainboard.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/device.h> - -/********************************************** - * enable the dedicated function in mainboard. - **********************************************/ -static void mainboard_enable(struct device *dev) -{ - printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/amd/olivehill/mptable.c b/src/mainboard/amd/olivehill/mptable.c deleted file mode 100644 index 52374f1..0000000 --- a/src/mainboard/amd/olivehill/mptable.c +++ /dev/null @@ -1,187 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/smp/mpspec.h> -#include <arch/io.h> -#include <arch/ioapic.h> -#include <string.h> -#include <stdint.h> -#include <cpu/x86/lapic.h> -#include <southbridge/amd/agesa/hudson/hudson.h> - -u8 picr_data[0x54] = { - 0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - 0x1F,0x1F,0x1F,0x03,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x05,0x04,0x05,0x04,0x04,0x05,0x04,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x04,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x03,0x04,0x05,0x07 -}; -u8 intr_data[0x54] = { - 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x10,0x11,0x12,0x13 -}; - -static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) -{ - mc->mpc_length += length; - mc->mpc_entry_count++; -} - -static void my_smp_write_bus(struct mp_config_table *mc, - unsigned char id, const char *bustype) -{ - struct mpc_config_bus *mpc; - mpc = smp_next_mpc_entry(mc); - memset(mpc, '\0', sizeof(*mpc)); - mpc->mpc_type = MP_BUS; - mpc->mpc_busid = id; - memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); - smp_add_mpc_entry(mc, sizeof(*mpc)); -} - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - u8 byte; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - //mptable_write_buses(mc, NULL, &bus_isa); - my_smp_write_bus(mc, 0, "PCI "); - my_smp_write_bus(mc, 1, "PCI "); - bus_isa = 0x02; - my_smp_write_bus(mc, bus_isa, "ISA "); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000); - /* PIC IRQ routine */ - for (byte = 0x0; byte < sizeof(picr_data); byte ++) { - outb(byte, 0xC00); - outb(picr_data[byte], 0xC01); - } - - /* APIC IRQ routine */ - for (byte = 0x0; byte < sizeof(intr_data); byte ++) { - outb(byte | 0x80, 0xC00); - outb(intr_data[byte], 0xC01); - } - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) - - /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); - - /* SMBUS */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - - /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe Lan*/ - PCI_INT(0x0, 0x06, 0x0, 0x13); - - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c deleted file mode 100644 index 122bb19..0000000 --- a/src/mainboard/amd/olivehill/romstage.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <device/pci_def.h> -#include <arch/io.h> -#include <device/pci_ops.h> -#include <northbridge/amd/agesa/state_machine.h> -#include <southbridge/amd/agesa/hudson/hudson.h> - -void board_BeforeAgesa(struct sysinfo *cb) -{ - int i; - u32 val; - - /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for - * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA - * even though the register is not documented in the Kabini BKDG. - * Otherwise the serial output is bad code. - */ - outb(0xD2, 0xcd6); - outb(0x00, 0xcd7); - - /* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */ - outb(0xea, 0xcd6); - outb(0x1, 0xcd7); - - /* Set LPC decode enables. */ - pci_devfn_t dev = PCI_DEV(0, 0x14, 3); - pci_write_config32(dev, 0x44, 0xff03ffd5); - - /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */ - for (i = 0; i < 200000; i++) - val = inb(0xcd6); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/38114 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44280d8f078ea2fb662d4b1e23737ac0c86b8d9d Gerrit-Change-Number: 38114 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: mb/amd/lamar: Drop boards with ROMCC_BOOTBLOCK
by HAOUAS Elyes (Code Review) Jan. 7, 2020

Jan. 7, 2020

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38115 ) Change subject: mb/amd/lamar: Drop boards with ROMCC_BOOTBLOCK ...................................................................... mb/amd/lamar: Drop boards with ROMCC_BOOTBLOCK ROMCC_BOOTBLOCK is no more. Drop unsupported, unmaintained boards. Change-Id: Iaa68ca0fda295245a0af178b6e18ee31b0953cce Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- D src/mainboard/amd/lamar/BiosCallOuts.c D src/mainboard/amd/lamar/Kconfig D src/mainboard/amd/lamar/Kconfig.name D src/mainboard/amd/lamar/Makefile.inc D src/mainboard/amd/lamar/OemCustomize.c D src/mainboard/amd/lamar/acpi/gpe.asl D src/mainboard/amd/lamar/acpi/mainboard.asl D src/mainboard/amd/lamar/acpi/routing.asl D src/mainboard/amd/lamar/acpi/si.asl D src/mainboard/amd/lamar/acpi/sleep.asl D src/mainboard/amd/lamar/acpi/thermal.asl D src/mainboard/amd/lamar/acpi/usb_oc.asl D src/mainboard/amd/lamar/acpi_tables.c D src/mainboard/amd/lamar/board_info.txt D src/mainboard/amd/lamar/cmos.layout D src/mainboard/amd/lamar/devicetree.cb D src/mainboard/amd/lamar/dsdt.asl D src/mainboard/amd/lamar/irq_tables.c D src/mainboard/amd/lamar/mainboard.c D src/mainboard/amd/lamar/mptable.c D src/mainboard/amd/lamar/romstage.c 21 files changed, 0 insertions(+), 1,884 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/38115/1 diff --git a/src/mainboard/amd/lamar/BiosCallOuts.c b/src/mainboard/amd/lamar/BiosCallOuts.c deleted file mode 100644 index 8e49e8e..0000000 --- a/src/mainboard/amd/lamar/BiosCallOuts.c +++ /dev/null @@ -1,329 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 - 2014 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <AGESA.h> -#include <console/console.h> -#include <northbridge/amd/agesa/BiosCallOuts.h> -#include <FchPlatform.h> -#include <stdlib.h> -#include <device/azalia.h> - -#include "imc.h" -#include "hudson.h" - -static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr); - -const BIOS_CALLOUT_STRUCT BiosCallouts[] = -{ - {AGESA_READ_SPD, agesa_ReadSpd }, - {AGESA_DO_RESET, agesa_Reset }, - {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, - {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, - {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData }, - {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, - {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, - {AGESA_FCH_OEM_CALLOUT, Fch_Oem_config }, - {AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage } -}; -const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); - -/** - * Realtek ALC272 CODEC Verb Table - */ -static const CODEC_ENTRY Alc272_VerbTbl[] = { - { 0x11, 0x411111F0 }, /* - S/PDIF Output 2 */ - { 0x12, 0x411111F0 }, /* - Digital Mic 1/2 [GPIO0] */ - { 0x13, 0x411111F0 }, /* - Digital Mic 3/4 [GPIO1] */ - { 0x14, 0x411111F0 }, /* Port D - Front Panel headphone */ - { 0x15, 0x411111F0 }, /* Port A - Surround */ - { 0x17, 0x411111F0 }, /* Port H - Mono */ - { 0x18, /* Port B - MIC - pink jack */ - (AZALIA_PINCFG_PORT_JACK << 30) - | ((AZALIA_PINCFG_LOCATION_EXTERNAL | AZALIA_PINCFG_LOCATION_REAR) << 24) - | (AZALIA_PINCFG_DEVICE_MICROPHONE << 20) - | (AZALIA_PINCFG_CONN_MINI_HEADPHONE_JACK << 16) - | (AZALIA_PINCFG_COLOR_PINK << 12) - | (4 << 4) - | (0 << 0) - }, - { 0x19, 0x411111F0 }, /* Port F - Front Panel Mic */ - { 0x1A, /* Port C - LineIn1 - blue jack */ - (AZALIA_PINCFG_PORT_JACK << 30) - | ((AZALIA_PINCFG_LOCATION_EXTERNAL | AZALIA_PINCFG_LOCATION_REAR) << 24) - | (AZALIA_PINCFG_DEVICE_LINEIN << 20) - | (AZALIA_PINCFG_CONN_MINI_HEADPHONE_JACK << 16) - | (AZALIA_PINCFG_COLOR_BLUE << 12) - | (4 << 4) - | (0xF << 0) - }, - { 0x1B, 0x411111F0 }, /* Port E - Front Panel line-out */ - { 0x1D, 0x40251E05 }, /* PC Beep - (internal) */ - { 0x1E, /* S/PDIF - Internal Header */ - (AZALIA_PINCFG_PORT_JACK << 30) - | ((AZALIA_PINCFG_LOCATION_EXTERNAL | AZALIA_PINCFG_LOCATION_FRONT) << 24) - | (AZALIA_PINCFG_DEVICE_SPDIF_OUT << 20) - | (AZALIA_PINCFG_CONN_RCA << 16) - | (AZALIA_PINCFG_COLOR_BLACK << 12) - | (1 << 4) - | (0 << 0) - }, - { 0x21, /* Port I - HPout - green jack */ - (AZALIA_PINCFG_PORT_JACK << 30) - | ((AZALIA_PINCFG_LOCATION_EXTERNAL | AZALIA_PINCFG_LOCATION_REAR) << 24) - | (AZALIA_PINCFG_DEVICE_HP_OUT << 20) - | (AZALIA_PINCFG_CONN_MINI_HEADPHONE_JACK << 16) - | (AZALIA_PINCFG_COLOR_GREEN << 12) - | (4 << 4) - | (0 << 0) - }, - { 0xFF, 0xFFFFFFFF }, -}; - -static const CODEC_TBL_LIST CodecTableList[] = -{ - {0x10ec0272, (CODEC_ENTRY*)&Alc272_VerbTbl[0]}, - {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL} -}; - -#define FAN_INPUT_INTERNAL_DIODE 0 -#define FAN_INPUT_TEMP0 1 -#define FAN_INPUT_TEMP1 2 -#define FAN_INPUT_TEMP2 3 -#define FAN_INPUT_TEMP3 4 -#define FAN_INPUT_TEMP0_FILTER 5 -#define FAN_INPUT_ZERO 6 -#define FAN_INPUT_DISABLED 7 - -#define FAN_AUTOMODE (1 << 0) -#define FAN_LINEARMODE (1 << 1) -#define FAN_STEPMODE ~(1 << 1) -#define FAN_POLARITY_HIGH (1 << 2) -#define FAN_POLARITY_LOW ~(1 << 2) - -/* Normally, 4-wire fan runs at 25KHz and 3-wire fan runs at 100Hz */ -#define FREQ_28KHZ 0x0 -#define FREQ_25KHZ 0x1 -#define FREQ_23KHZ 0x2 -#define FREQ_21KHZ 0x3 -#define FREQ_29KHZ 0x4 -#define FREQ_18KHZ 0x5 -#define FREQ_100HZ 0xF7 -#define FREQ_87HZ 0xF8 -#define FREQ_58HZ 0xF9 -#define FREQ_44HZ 0xFA -#define FREQ_35HZ 0xFB -#define FREQ_29HZ 0xFC -#define FREQ_22HZ 0xFD -#define FREQ_14HZ 0xFE -#define FREQ_11HZ 0xFF - -/* - * Hardware Monitor Fan Control - * Hardware limitation: - * HWM will fail to read the input temperature via I2C if other - * software switches the I2C address. AMD recommends using IMC - * to control fans, instead of HWM. - */ -static void oem_fan_control(FCH_DATA_BLOCK *FchParams) -{ - FCH_HWM_FAN_CTR oem_factl[5] = { - /*temperature input, fan mode, frequency, low_duty, med_duty, multiplier, lowtemp, medtemp, hightemp, LinearRange, LinearHoldCount */ - /* FanOUT0 Fan header J32 */ - {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, - /* FanOUT1 Fan header J31*/ - {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, - {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, - {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, - {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, - }; - LibAmdMemCopy ((VOID *)(FchParams->Hwm.HwmFanControl), &oem_factl, (sizeof(FCH_HWM_FAN_CTR) * 5), FchParams->StdHeader); - - /* Enable IMC fan control. the recommended way */ - if (CONFIG(HUDSON_IMC_FWM)) { - imc_reg_init(); - - /* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */ - FchParams->Hwm.HwMonitorEnable = TRUE; - FchParams->Hwm.HwmFchtsiAutoPoll = FALSE; /* 0 disable, 1 enable TSI Auto Polling */ - - FchParams->Imc.ImcEnable = TRUE; - FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */ - FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ - - LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader); - - /* Thermal Zone Parameter */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; /* BIT0 | BIT2 | BIT5 */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x0e; /* 6 | BIT3 */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x54; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg7 = 0x02; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg8 = 0x01; /* PWM steping rate in unit of PWM level percentage */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg9 = 0x00; - - /* IMC Fan Policy temperature thresholds */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x46; /* AC0 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0x3c; /* AC1 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0x32; /* AC2 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff; /* AC3 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0xff; /* AC4 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0xff; /* AC5 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0xff; /* AC6 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0xff; /* AC7 lowest threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegA = 0x4b; /* critical threshold* in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegB = 0x00; - - /* IMC Fan Policy PWM Settings */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg2 = 0x5a; /* AL0 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg3 = 0x46; /* AL1 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg4 = 0x28; /* AL2 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg5 = 0xff; /* AL3 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg6 = 0xff; /* AL4 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg7 = 0xff; /* AL5 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0xff; /* AL6 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0xff; /* AL7 percentage */ - - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg1 = 0x01; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg2 = 0x55; /* BIT0 | BIT2 | BIT5 */ - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg3 = 0x17; - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg4 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg5 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg6 = 0x90; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg7 = 0; - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg8 = 0; /* PWM steping rate in unit of PWM level percentage */ - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg9 = 0; - - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg1 = 0x01; /* zone */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg2 = 60; /* AC0 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg3 = 40; /* AC1 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg4 = 0; /* AC2 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg5 = 0; /* AC3 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg6 = 0; /* AC4 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg7 = 0; /* AC5 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg8 = 0; /* AC6 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg9 = 0; /* AC7 lowest threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgRegA = 0; /* critical threshold* in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgRegB = 0x00; - - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg1 = 0x01; /* Zone */ - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg2 = 0; /* AL0 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg3 = 0; /* AL1 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg4 = 0; /* AL2 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg5 = 0x00; /* AL3 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg6 = 0x00; /* AL4 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg7 = 0x00; /* AL5 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg8 = 0x00; /* AL6 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg9 = 0x00; /* AL7 percentage */ - - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg1 = 0x2; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg2 = 0x0; /* BIT0 | BIT2 | BIT5 */ - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg3 = 0x0; - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg4 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg5 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg7 = 2; - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg8 = 5; /* PWM steping rate in unit of PWM level percentage */ - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg9 = 0; - - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg1 = 0x3; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg2 = 0x0; /* BIT0 | BIT2 | BIT5 */ - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg3 = 0x0; - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg4 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg5 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg6 = 0x0; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg7 = 0; - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg8 = 0; /* PWM steping rate in unit of PWM level percentage */ - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg9 = 0; - - /* IMC Function */ - FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x333;/* BIT0 | BIT4 |BIT8 */ - - /* NOTE: - * FchInitLateHwm will overwrite the EcStruct with EcDefaultMessage, - * AGESA put EcDefaultMessage as global data in ROM, so we can't override it. - * so we remove it from AGESA code. Please See FchInitLateHwm. - */ - } else { - /* HWM fan control, using the alternative method */ - FchParams->Imc.ImcEnable = FALSE; - FchParams->Hwm.HwMonitorEnable = TRUE; - FchParams->Hwm.HwmFchtsiAutoPoll = TRUE;/* 1 enable, 0 disable TSI Auto Polling */ - } -} - -/** - * Fch Oem setting callback - * - * Configure platform specific Hudson device, - * such Azalia, SATA, IMC etc. - */ -static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr) -{ - AMD_CONFIG_PARAMS *StdHeader = (AMD_CONFIG_PARAMS *)ConfigPtr; - if (StdHeader->Func == AMD_INIT_RESET) { - FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *) FchData; - printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); - - FchParams->LegacyFree = CONFIG(HUDSON_LEGACY_FREE); - - /* Turn on FCH GPP slots */ - FchParams->FchReset.GppEnable = TRUE; - FchParams->Gpp.GppFunctionEnable = TRUE; - FchParams->Gpp.GppLinkConfig = PortA1B1C1D1; - FchParams->Gpp.PortCfg[0].PortPresent = TRUE; - FchParams->Gpp.PortCfg[1].PortPresent = TRUE; - FchParams->Gpp.PortCfg[2].PortPresent = TRUE; - FchParams->Gpp.PortCfg[3].PortPresent = TRUE; - FchParams->FchReset.SataEnable = (CONFIG_HUDSON_SATA_MODE == 0) || (CONFIG_HUDSON_SATA_MODE == 2); - FchParams->FchReset.IdeEnable = (CONFIG_HUDSON_SATA_MODE == 0) || (CONFIG_HUDSON_SATA_MODE == 3); - - } else if (StdHeader->Func == AMD_INIT_ENV) { - FCH_DATA_BLOCK *FchParams = (FCH_DATA_BLOCK *)FchData; - printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); - - /* Turn on FCH GPP slots */ - FchParams->Gpp.GppFunctionEnable = TRUE; - FchParams->Gpp.GppLinkConfig = PortA1B1C1D1; - - /* Azalia Controller OEM Codec Table Pointer */ - FchParams->Azalia.AzaliaPinCfg = TRUE; - FchParams->Azalia.AzaliaConfig = (const AZALIA_PIN){ - .AzaliaSdin0 = (CONFIG_AZ_PIN >> 0) & 0x03, - .AzaliaSdin1 = (CONFIG_AZ_PIN >> 2) & 0x03, - .AzaliaSdin2 = (CONFIG_AZ_PIN >> 4) & 0x03, - .AzaliaSdin3 = (CONFIG_AZ_PIN >> 6) & 0x03 - }; - FchParams->Azalia.AzaliaOemCodecTablePtr = CodecTableList; - /* Azalia Controller Front Panel OEM Table Pointer */ - - /* Fan Control */ - oem_fan_control(FchParams); - } - printk(BIOS_DEBUG, "Done\n"); - - return AGESA_SUCCESS; -} diff --git a/src/mainboard/amd/lamar/Kconfig b/src/mainboard/amd/lamar/Kconfig deleted file mode 100644 index c856534..0000000 --- a/src/mainboard/amd/lamar/Kconfig +++ /dev/null @@ -1,82 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2012 - 2014 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -config BOARD_AMD_LAMAR - def_bool n - -if BOARD_AMD_LAMAR - -config BOARD_SPECIFIC_OPTIONS - def_bool y - #select BINARYPI_LEGACY_WRAPPER - #select ROMCC_BOOTBLOCK - select CPU_AMD_PI_00630F01 - select NORTHBRIDGE_AMD_PI_00630F01 - select SOUTHBRIDGE_AMD_PI_BOLTON - select DEFAULT_POST_ON_LPC - select SUPERIO_FINTEK_F81216H - select HAVE_OPTION_TABLE - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select HAVE_ACPI_TABLES - select BOARD_ROMSIZE_KB_8192 - select GFXUMA - -config MAINBOARD_DIR - string - default "amd/lamar" - -config MAINBOARD_PART_NUMBER - string - default "DB-FP3" - -config MAINBOARD_SERIAL_NUMBER - string - default "52198A" - -config MAX_CPUS - int - default 4 - -config IRQ_SLOT_COUNT - int - default 11 - -config ONBOARD_VGA_IS_PRIMARY - bool - default y - -config HUDSON_XHCI_FWM_FILE - string - default "3rdparty/blobs/southbridge/amd/bolton/xhci.bin" - -config AZ_PIN - hex - default 0x02 - -config ENABLE_DP3_DAUGHTER_CARD_IN_J120 - bool "Use J120 as an additional graphics port" - default n - help - The PCI Express slot at J120 can be configured as an additional - DisplayPort connector using an adapter card from AMD or as a normal - PCI Express (x4) slot. - - By default, the connector is configured as a PCI Express (x4) slot. - - Select this option to enable the slot for use with one of AMD's - passive graphics port expander cards (only available from AMD). - -endif # BOARD_AMD_LAMAR diff --git a/src/mainboard/amd/lamar/Kconfig.name b/src/mainboard/amd/lamar/Kconfig.name deleted file mode 100644 index 75eec04..0000000 --- a/src/mainboard/amd/lamar/Kconfig.name +++ /dev/null @@ -1,3 +0,0 @@ -# Disabled -#config BOARD_AMD_LAMAR -# bool "Lamar" diff --git a/src/mainboard/amd/lamar/Makefile.inc b/src/mainboard/amd/lamar/Makefile.inc deleted file mode 100644 index 37c1dce..0000000 --- a/src/mainboard/amd/lamar/Makefile.inc +++ /dev/null @@ -1,20 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2012 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -romstage-y += BiosCallOuts.c -romstage-y += OemCustomize.c - -ramstage-y += BiosCallOuts.c -ramstage-y += OemCustomize.c diff --git a/src/mainboard/amd/lamar/OemCustomize.c b/src/mainboard/amd/lamar/OemCustomize.c deleted file mode 100644 index 4c1832b..0000000 --- a/src/mainboard/amd/lamar/OemCustomize.c +++ /dev/null @@ -1,133 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * 2013 - 2014 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <AGESA.h> - - -static const PCIe_PORT_DESCRIPTOR PortList[] = { - - /* - * Lanes to pins to PCI device mapping can be found in section 2.12 of the - * BIOS and Kernel Developer's Guide for AMD Family 15h Models 30h-3Fh - */ - - { /* PCIe x16 Connector J119, DP4/5/6, GFX[15:0], Lanes [31:16], PCI 00:02.1 */ - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 16, 31), - PCIE_PORT_DATA_INITIALIZER_V2( - PortEnabled, - ChannelTypeExt6db, 0, 0, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, - 175, - 0 - ) - }, - - { /* PCIe x4 Connector J118, GPP[3:0], Lanes [11:8], PCI 00:03.2 */ - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 11), - PCIE_PORT_DATA_INITIALIZER_V2( - PortEnabled, - ChannelTypeExt6db, 0, 0, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, - 176, - 0 - ) - }, - - { /* PCIe x4 Connector J120, GPP[7:4], Lanes [15:12] */ - DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER( - CONFIG(ENABLE_DP3_DAUGHTER_CARD_IN_J120) ? PcieUnusedEngine : PciePortEngine, - 12, 15 - ), - PCIE_PORT_DATA_INITIALIZER_V2( - PortEnabled, - ChannelTypeExt6db, 0, 0, - HotplugDisabled, - PcieGenMaxSupported, PcieGenMaxSupported, - AspmDisabled, - 177, - 0 - ) - }, - -}; - -static const PCIe_DDI_DESCRIPTOR DdiList[] = { - { /* DP3 */ - 0, - PCIE_ENGINE_DATA_INITIALIZER( - CONFIG(ENABLE_DP3_DAUGHTER_CARD_IN_J120) ? PcieDdiEngine : PcieUnusedEngine, - 12, 15 - ), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux4, Hdp4) - }, - - { /* DP2 */ - 0, - PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 36, 39), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux3, Hdp3) - }, - - { /* DP1 */ - 0, - PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 32, 35), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2) - }, - - { /* DP0 */ - DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 4, 7), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1) - }, -}; - -static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { - .Flags = DESCRIPTOR_TERMINATE_LIST, - .SocketId = 0, - .PciePortList = PortList, - .DdiLinkList = DdiList -}; - -/*---------------------------------------------------------------------------------------*/ -/** - * OemCustomizeInitEarly - * - * Description: - * This stub function will call the host environment through the binary block - * interface (call-out port) to provide a user hook opportunity - * - * Parameters: - * @param[in] *InitEarly - * - * @retval VOID - * - **/ -/*---------------------------------------------------------------------------------------*/ -VOID -OemCustomizeInitEarly ( - IN OUT AMD_EARLY_PARAMS *InitEarly - ) -{ - InitEarly->GnbConfig.PcieComplexList = &PcieComplex; -} diff --git a/src/mainboard/amd/lamar/acpi/gpe.asl b/src/mainboard/amd/lamar/acpi/gpe.asl deleted file mode 100644 index 297d9b4..0000000 --- a/src/mainboard/amd/lamar/acpi/gpe.asl +++ /dev/null @@ -1,73 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 - 2014 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Scope(\_GPE) { /* Start Scope GPE */ - - /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* Legacy PM event */ - Method(_L08) { - /* DBGO("\\_GPE\\_L08\n") */ - } - - /* Temp warning (TWarn) event */ - Method(_L09) { - /* DBGO("\\_GPE\\_L09\n") */ - /* Notify (\_TZ.TZ00, 0x80) */ - } - - /* USB controller PME# */ - Method(_L0B) { - /* DBGO("\\_GPE\\_L0B\n") */ - Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* ExtEvent0 SCI event */ - Method(_L10) { - /* DBGO("\\_GPE\\_L10\n") */ - } - - - /* ExtEvent1 SCI event */ - Method(_L11) { - /* DBGO("\\_GPE\\_L11\n") */ - } - - /* GPIO0 or GEvent8 event */ - Method(_L18) { - /* DBGO("\\_GPE\\_L18\n") */ - Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR3, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* Azalia SCI event */ - Method(_L1B) { - /* DBGO("\\_GPE\\_L1B\n") */ - Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } -} /* End Scope GPE */ diff --git a/src/mainboard/amd/lamar/acpi/mainboard.asl b/src/mainboard/amd/lamar/acpi/mainboard.asl deleted file mode 100644 index d251657..0000000 --- a/src/mainboard/amd/lamar/acpi/mainboard.asl +++ /dev/null @@ -1,37 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 - 2014 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - /* Data to be patched by the BIOS during POST */ - /* FIXME the patching is not done yet! */ - /* Memory related values */ - Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ - Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ - Name(PBLN, 0x0) /* Length of BIOS area */ - - Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ - Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */ - Name(HPBA, 0xFED00000) /* Base address of HPET table */ - - /* Some global data */ - Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ - Name(OSV, Ones) /* Assume nothing */ - Name(PMOD, One) /* Assume APIC */ - - /* AcpiGpe0Blk */ - OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04) - Field(GP0B, ByteAcc, NoLock, Preserve) { - , 11, - USBS, 1, - } diff --git a/src/mainboard/amd/lamar/acpi/routing.asl b/src/mainboard/amd/lamar/acpi/routing.asl deleted file mode 100644 index 531ceea..0000000 --- a/src/mainboard/amd/lamar/acpi/routing.asl +++ /dev/null @@ -1,300 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * 2013 - 2014 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - /* Routing is in System Bus scope */ - Name(PR0, Package(){ - /* NB devices */ - /* Bus 0, Dev 0 - F15 Host Controller */ - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ - Package(){0x0001FFFF, 0, INTB, 0 }, - Package(){0x0001FFFF, 1, INTC, 0 }, - - /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){0x0002FFFF, 0, INTC, 0 }, - Package(){0x0002FFFF, 1, INTD, 0 }, - Package(){0x0002FFFF, 2, INTA, 0 }, - Package(){0x0002FFFF, 3, INTB, 0 }, - - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - Package(){0x0003FFFF, 0, INTD, 0 }, - Package(){0x0003FFFF, 1, INTA, 0 }, - Package(){0x0003FFFF, 2, INTB, 0 }, - Package(){0x0003FFFF, 3, INTC, 0 }, - - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, INTA, 0 }, - Package(){0x0004FFFF, 1, INTB, 0 }, - Package(){0x0004FFFF, 2, INTC, 0 }, - Package(){0x0004FFFF, 3, INTD, 0 }, - - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - Package(){0x0005FFFF, 0, INTB, 0 }, - Package(){0x0005FFFF, 1, INTC, 0 }, - Package(){0x0005FFFF, 2, INTD, 0 }, - Package(){0x0005FFFF, 3, INTA, 0 }, - - /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ - Package(){0x0006FFFF, 0, INTC, 0 }, - Package(){0x0006FFFF, 1, INTD, 0 }, - Package(){0x0006FFFF, 2, INTA, 0 }, - Package(){0x0006FFFF, 3, INTB, 0 }, - - /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ - Package(){0x0007FFFF, 0, INTD, 0 }, - Package(){0x0007FFFF, 1, INTA, 0 }, - Package(){0x0007FFFF, 2, INTB, 0 }, - Package(){0x0007FFFF, 3, INTC, 0 }, - - /* Bus 0, Dev 8 - Southbridge port (normally hidden) */ - - /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */ - Package(){0x0014FFFF, 0, INTA, 0 }, - Package(){0x0014FFFF, 1, INTB, 0 }, - Package(){0x0014FFFF, 2, INTC, 0 }, - Package(){0x0014FFFF, 3, INTD, 0 }, - - /* SB devices */ - /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0 - * EHCI @ func 2 */ - Package(){0x0012FFFF, 0, INTC, 0 }, - Package(){0x0012FFFF, 1, INTB, 0 }, - - Package(){0x0013FFFF, 0, INTC, 0 }, - Package(){0x0013FFFF, 1, INTB, 0 }, - - Package(){0x0016FFFF, 0, INTC, 0 }, - Package(){0x0016FFFF, 1, INTB, 0 }, - - /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */ - Package(){0x0010FFFF, 0, INTC, 0 }, - Package(){0x0010FFFF, 1, INTB, 0 }, - - /* Bus 0, Dev 17 - SATA controller */ - Package(){0x0011FFFF, 0, INTD, 0 }, - - /* Bus 0, Dev 21 Pcie Bridge */ - Package(){0x0015FFFF, 0, INTA, 0 }, - Package(){0x0015FFFF, 1, INTB, 0 }, - Package(){0x0015FFFF, 2, INTC, 0 }, - Package(){0x0015FFFF, 3, INTD, 0 }, - }) - - Name(APR0, Package(){ - /* NB devices in APIC mode */ - /* Bus 0, Dev 0 - F15 Host Controller */ - - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ - Package(){0x0001FFFF, 0, 0, 17 }, - Package(){0x0001FFFF, 1, 0, 18 }, - - /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){0x0002FFFF, 0, 0, 18 }, - Package(){0x0002FFFF, 1, 0, 19 }, - Package(){0x0002FFFF, 2, 0, 16 }, - Package(){0x0002FFFF, 3, 0, 17 }, - - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - Package(){0x0003FFFF, 0, 0, 19 }, - Package(){0x0003FFFF, 1, 0, 16 }, - Package(){0x0003FFFF, 2, 0, 17 }, - Package(){0x0003FFFF, 3, 0, 18 }, - - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, 0, 16 }, - Package(){0x0004FFFF, 1, 0, 17 }, - Package(){0x0004FFFF, 2, 0, 18 }, - Package(){0x0004FFFF, 3, 0, 19 }, - - /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ - Package(){0x0014FFFF, 0, 0, 16 }, - Package(){0x0014FFFF, 1, 0, 17 }, - Package(){0x0014FFFF, 2, 0, 18 }, - Package(){0x0014FFFF, 3, 0, 19 }, - - /* SB devices in APIC mode */ - /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0 - * EHCI @ func 2 */ - Package(){0x0012FFFF, 0, 0, 18 }, - Package(){0x0012FFFF, 1, 0, 17 }, - - Package(){0x0013FFFF, 0, 0, 18 }, - Package(){0x0013FFFF, 1, 0, 17 }, - - Package(){0x0016FFFF, 0, 0, 18 }, - Package(){0x0016FFFF, 1, 0, 17 }, - - /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */ - Package(){0x0010FFFF, 0, 0, 0x12}, - Package(){0x0010FFFF, 1, 0, 0x11}, - - /* Bus 0, Dev 17 - SATA controller */ - Package(){0x0011FFFF, 0, 0, 19 }, - - /* Bus0, Dev 21 PCIE Bridge */ - Package(){0x0015FFFF, 0, 0, 16 }, - Package(){0x0015FFFF, 1, 0, 17 }, - Package(){0x0015FFFF, 2, 0, 18 }, - Package(){0x0015FFFF, 3, 0, 19 }, - }) - - Name(PS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - Name(APS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PS3, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, - }) - Name(APS3, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, - }) - - Name(PS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, - }) - Name(APS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - - Name(PS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - Name(APS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PS7, Package(){ - /* The onboard Ethernet chip - Dev 7 Parmer Hooked to RTK8111E Ethernet Card x1 Device7-GPP3 J16B*/ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - Name(APS7, Package(){ - /* The onboard Ethernet chip - Dev 7 Parmer Hooked to RTK8111E Ethernet Card x1 Device7-GPP3 J16B*/ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, - }) - - Name(PE0, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 0*/ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, - }) - Name(APE0, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 0*/ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, - }) - - Name(PE1, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 1*/ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, - }) - Name(APE1, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 1*/ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - - Name(PE2, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 2*/ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - Name(APE2, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 2*/ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PE3, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 3 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - Name(APE3, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 3*/ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, - }) - - /* SB PCI Bridge J21, J22 */ - Name(PCIB, Package(){ - /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */ - Package(){0x0005FFFF, 0, 0, 0x14 }, - Package(){0x0005FFFF, 1, 0, 0x15 }, - Package(){0x0005FFFF, 2, 0, 0x16 }, - Package(){0x0005FFFF, 3, 0, 0x17 }, - - Package(){0x0006FFFF, 0, 0, 0x15 }, - Package(){0x0006FFFF, 1, 0, 0x16 }, - Package(){0x0006FFFF, 2, 0, 0x17 }, - Package(){0x0006FFFF, 3, 0, 0x14 }, - }) diff --git a/src/mainboard/amd/lamar/acpi/si.asl b/src/mainboard/amd/lamar/acpi/si.asl deleted file mode 100644 index bec166c..0000000 --- a/src/mainboard/amd/lamar/acpi/si.asl +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 - 2014 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - Scope(\_SI) { - Method(_SST, 1) { - /* DBGO("\\_SI\\_SST\n") */ - /* DBGO(" New Indicator state: ") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - } - } /* End Scope SI */ diff --git a/src/mainboard/amd/lamar/acpi/sleep.asl b/src/mainboard/amd/lamar/acpi/sleep.asl deleted file mode 100644 index f7edfb9..0000000 --- a/src/mainboard/amd/lamar/acpi/sleep.asl +++ /dev/null @@ -1,99 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 - 2014 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Wake status package */ -Name(WKST,Package(){Zero, Zero}) - -/* -* \_PTS - Prepare to Sleep method -* -* Entry: -* Arg0=The value of the sleeping state S1=1, S2=2, etc -* -* Exit: -* -none- -* -* The _PTS control method is executed at the beginning of the sleep process -* for S1-S5. The sleeping value is passed to the _PTS control method. This -* control method may be executed a relatively long time before entering the -* sleep state and the OS may abort the operation without notification to -* the ACPI driver. This method cannot modify the configuration or power -* state of any device in the system. -*/ -Method(\_PTS, 1) { - /* DBGO("\\_PTS\n") */ - /* DBGO("From S0 to S") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - - /* Clear sleep SMI status flag and enable sleep SMI trap. */ - /*Store(One, CSSM) - Store(One, SSEN)*/ - - /* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(\_SB.SBRI, 0x13)) { - * Store(0,\_SB.PWDE) - *} - */ - - /* Clear wake status structure. */ - Store(0, Index(WKST,0)) - Store(0, Index(WKST,1)) - - Store (0x07, UPWS) -} /* End Method(\_PTS) */ - -/* -* \_BFS OEM Back From Sleep method -* -* Entry: -* Arg0=The value of the sleeping state S1=1, S2=2 -* -* Exit: -* -none- -*/ -Method(\_BFS, 1) { - /* DBGO("\\_BFS\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ -} - -/* -* \_WAK System Wake method -* -* Entry: -* Arg0=The value of the sleeping state S1=1, S2=2 -* -* Exit: -* Return package of 2 DWords -* Dword 1 - Status -* 0x00000000 wake succeeded -* 0x00000001 Wake was signaled but failed due to lack of power -* 0x00000002 Wake was signaled but failed due to thermal condition -* Dword 2 - Power Supply state -* if non-zero the effective S-state the power supply entered -*/ -Method(\_WAK, 1) { - /* DBGO("\\_WAK\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - - /* Re-enable HPET */ - Store(1,USBS) - - Return(WKST) -} /* End Method(\_WAK) */ diff --git a/src/mainboard/amd/lamar/acpi/thermal.asl b/src/mainboard/amd/lamar/acpi/thermal.asl deleted file mode 100644 index 73077ac..0000000 --- a/src/mainboard/amd/lamar/acpi/thermal.asl +++ /dev/null @@ -1,2 +0,0 @@ -/* No license required */ -/* No thermal zone functionality */ diff --git a/src/mainboard/amd/lamar/acpi/usb_oc.asl b/src/mainboard/amd/lamar/acpi/usb_oc.asl deleted file mode 100644 index 4254e7e..0000000 --- a/src/mainboard/amd/lamar/acpi/usb_oc.asl +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2013 - 2014 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* USB overcurrent mapping pins. */ -Name(UOM0, 0) -Name(UOM1, 2) -Name(UOM2, 0) -Name(UOM3, 7) -Name(UOM4, 2) -Name(UOM5, 2) -Name(UOM6, 6) -Name(UOM7, 2) -Name(UOM8, 6) -Name(UOM9, 6) diff --git a/src/mainboard/amd/lamar/acpi_tables.c b/src/mainboard/amd/lamar/acpi_tables.c deleted file mode 100644 index 65e74ba..0000000 --- a/src/mainboard/amd/lamar/acpi_tables.c +++ /dev/null @@ -1,45 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 - 2014 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/acpi.h> -#include <arch/ioapic.h> - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); - - /* Write southbridge IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, - IO_APIC_ADDR, 0); - - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS+1, - 0xFEC20000, 24); - - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xF); - /* 0: mean bus 0--->ISA */ - /* 0: PIC 0 */ - /* 2: APIC 2 */ - /* 5 mean: 0101 --> Edge-triggered, Active high */ - - /* create all subtables for processors */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1); - /* 1: LINT1 connect to NMI */ - - return current; -} diff --git a/src/mainboard/amd/lamar/board_info.txt b/src/mainboard/amd/lamar/board_info.txt deleted file mode 100644 index 8bce92e..0000000 --- a/src/mainboard/amd/lamar/board_info.txt +++ /dev/null @@ -1,5 +0,0 @@ -Board name: DB-FP3 (Lamar) -Category: eval -ROM package: SOIC-8 -ROM protocol: SPI -ROM socketed: n diff --git a/src/mainboard/amd/lamar/cmos.layout b/src/mainboard/amd/lamar/cmos.layout deleted file mode 100644 index dc9b789..0000000 --- a/src/mainboard/amd/lamar/cmos.layout +++ /dev/null @@ -1,59 +0,0 @@ -#***************************************************************************** -# -# This file is part of the coreboot project. -# -# Copyright (C) 2012 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -#***************************************************************************** - -entries - -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#392 3 r 0 unused -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -444 1 e 1 nmi -728 256 h 0 user_data -984 16 h 0 check_sum -# Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% - -checksums - -checksum 392 983 984 diff --git a/src/mainboard/amd/lamar/devicetree.cb b/src/mainboard/amd/lamar/devicetree.cb deleted file mode 100644 index 5c88a3c..0000000 --- a/src/mainboard/amd/lamar/devicetree.cb +++ /dev/null @@ -1,101 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2012 Advanced Micro Devices, Inc. -# 2013 - 2014 Sage Electronic Engineering, LLC -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -chip northbridge/amd/pi/00630F01/root_complex - device cpu_cluster 0 on - chip cpu/amd/pi/00630F01 - device lapic 10 on end - end - end - - device domain 0 on - subsystemid 0x1022 0x1410 inherit - - chip northbridge/amd/pi/00630F01 - device pci 0.0 on end # 0x1422 Root Complex - device pci 0.2 off end # 0x1423 IOMMU - device pci 1.0 on end # 0x13XX Internal Graphics - device pci 1.1 on end # 0x1308 DisplayPort/HDMI Audio - device pci 2.0 on end # 0x1424 GFX PCIe Host Bridge - device pci 2.1 on end # 0x1425 P2P Bridge for GFX PCIe Port 0 (PCIe x16 slot J119) - device pci 2.2 off end # 0x1425 P2P Bridge for GFX PCIe Port 1 - device pci 3.0 on end # 0x1424 GPP PCIe Host Bridge - device pci 3.1 on end # 0x1426 P2P Bridge for GPP PCIe Port 0 (PCIe x4 slot J118) - device pci 3.2 on end # 0x1426 P2P Bridge for GPP PCIe Port 1 (PCIe x4 slot J120) - device pci 3.3 off end # 0x1426 P2P Bridge for GPP PCIe Port 2 - device pci 3.4 off end # 0x1426 P2P Bridge for GPP PCIe Port 3 - device pci 3.5 off end # 0x1426 P2P Bridge for GPP PCIe Port 4 - device pci 4.0 on end # 0x1424 UMI PCIe Host Bridge -# device pci 4.1 on end # 0x1426 P2P bridge for UMI link -# device pci 4.2 off end # 0x1426 Virtual P2P bridge for SB PCIe Port 3 -# device pci 4.3 off end # 0x1426 Virtual P2P bridge for SB PCIe Port 2 -# device pci 4.4 off end # 0x1426 Virtual P2P bridge for SB PCIe Port 1 -# device pci 4.5 off end # 0x1426 Virtual P2P bridge for SB PCIe Port 0 - end #chip northbridge/amd/pi/00630F01 - - chip southbridge/amd/pi/hudson - device pci 10.0 on end # 0x7814 XHCI HC0 - device pci 10.1 on end # 0x7814 XHCI HC1 - device pci 11.0 on end # 0x7800-0x7805 SATA (device ID depends on mode) - device pci 12.0 on end # 0x7807 USB OHCI - device pci 12.2 on end # 0x7808 USB EHCI - device pci 13.0 on end # 0x7807 USB OHCI - device pci 13.2 on end # 0x7808 USB EHCI - device pci 14.0 on end # SM - device pci 14.1 on end # 0x780C IDE - device pci 14.2 on end # 0x780D HDA - device pci 14.3 on # 0x780E LPC - chip superio/fintek/f81216h - register "conf_key_mode" = "0x77" - device pnp 4e.0 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 4e.1 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 4e.2 off end # COM3 - device pnp 4e.3 off end # COM4 - device pnp 4e.8 off end # WDT - end # f81865f - end #LPC - device pci 14.4 on end # 0x780F PCI :: PCI-b conflict with GPIO. - device pci 14.5 on end # 0x7809 USB OHCI - device pci 14.7 on end # 0x7806 SD Flash Controller - device pci 15.0 on end # 0x43A0 SB GPP Port 0 (Integrated Realtek GbE Controller) - device pci 15.1 on end # 0x43A1 SB GPP Port 1 (mPCIe slot J122) - device pci 15.2 on end # 0x43A2 SB GPP Port 2 (mPCIe slot J123) - device pci 15.3 off end # 0x43A3 SB GPP Port 3 - register "gpp_configuration" = "4" - device pci 16.0 on end # 0x7809 USB OHCI (when the xHCI device is disabled) - end #southbridge/amd/pi/hudson - - chip northbridge/amd/pi/00630F01 - device pci 18.0 on end # 0x141A HT Configuration - device pci 18.1 on end # 0x141B Address Maps - device pci 18.2 on end # 0x141C DRAM Configuration - device pci 18.3 on end # 0x141D Miscellaneous - device pci 18.4 on end # 0x141E Power Management - device pci 18.5 on end # 0x141F Northbridge - - register "spdAddrLookup" = " - { - { {0xA0, 0xA4}, {0xA2, 0xA6}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses - }" - end - - end #domain -end #northbridge/amd/pi/00630F01/root_complex diff --git a/src/mainboard/amd/lamar/dsdt.asl b/src/mainboard/amd/lamar/dsdt.asl deleted file mode 100644 index 1db743d..0000000 --- a/src/mainboard/amd/lamar/dsdt.asl +++ /dev/null @@ -1,88 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2013 - 2014 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* DefinitionBlock Statement */ -#include <arch/acpi.h> -DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - OEM_ID, - ACPI_TABLE_CREATOR, - 0x00010001 /* OEM Revision */ - ) -{ /* Start of ASL file */ - /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ - - /* Globals for the platform */ - #include "acpi/mainboard.asl" - - /* Describe the USB Overcurrent pins */ - #include "acpi/usb_oc.asl" - - /* PCI IRQ mapping for the Southbridge */ - #include <southbridge/amd/pi/hudson/acpi/pcie.asl> - - /* Describe the processor tree (\_PR) */ - #include <cpu/amd/pi/00630F01/acpi/cpu.asl> - - /* Contains the supported sleep states for this chipset */ - #include <southbridge/amd/common/acpi/sleepstates.asl> - - /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */ - #include "acpi/sleep.asl" - - /* System Bus */ - Scope(\_SB) { /* Start \_SB scope */ - /* global utility methods expected within the \_SB scope */ - #include <arch/x86/acpi/globutil.asl> - - /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ - #include "acpi/routing.asl" - - Device(PWRB) { - Name(_HID, EISAID("PNP0C0C")) - Name(_UID, 0xAA) - Name(_PRW, Package () {3, 0x04}) - Name(_STA, 0x0B) - } - - Device(PCI0) { - /* Describe the AMD Northbridge */ - #include <northbridge/amd/pi/00630F01/acpi/northbridge.asl> - - /* Describe the AMD Fusion Controller Hub Southbridge */ - #include <southbridge/amd/pi/hudson/acpi/fch.asl> - } - - /* Describe PCI INT[A-H] for the Southbridge */ - #include <southbridge/amd/pi/hudson/acpi/pci_int.asl> - - } /* End \_SB scope */ - - /* Describe SMBUS for the Southbridge */ - #include <southbridge/amd/pi/hudson/acpi/smbus.asl> - - /* Define the General Purpose Events for the platform */ - #include "acpi/gpe.asl" - - /* Define the Thermal zones and methods for the platform */ - #include "acpi/thermal.asl" - - /* Define the System Indicators for the platform */ - #include "acpi/si.asl" -} -/* End of ASL file */ diff --git a/src/mainboard/amd/lamar/irq_tables.c b/src/mainboard/amd/lamar/irq_tables.c deleted file mode 100644 index 9cc27f7..0000000 --- a/src/mainboard/amd/lamar/irq_tables.c +++ /dev/null @@ -1,100 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 - 2014 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <string.h> -#include <stdint.h> -#include <arch/pirq_routing.h> - -static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, - u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, - u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, - u8 slot, u8 rfu) -{ - pirq_info->bus = bus; - pirq_info->devfn = devfn; - pirq_info->irq[0].link = link0; - pirq_info->irq[0].bitmap = bitmap0; - pirq_info->irq[1].link = link1; - pirq_info->irq[1].bitmap = bitmap1; - pirq_info->irq[2].link = link2; - pirq_info->irq[2].bitmap = bitmap2; - pirq_info->irq[3].link = link3; - pirq_info->irq[3].bitmap = bitmap3; - pirq_info->slot = slot; - pirq_info->rfu = rfu; -} - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - struct irq_routing_table *pirq; - struct irq_info *pirq_info; - u32 slot_num; - u8 *v; - - u8 sum = 0; - int i; - - /* Align the table to be 16 byte aligned. */ - addr += 15; - addr &= ~15; - - /* This table must be between 0xf0000 & 0x100000 */ - printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); - - pirq = (void *)(addr); - v = (u8 *) (addr); - - pirq->signature = PIRQ_SIGNATURE; - pirq->version = PIRQ_VERSION; - - pirq->rtr_bus = 0; - pirq->rtr_devfn = PCI_DEVFN(0x14, 4); - - pirq->exclusive_irqs = 0; - - pirq->rtr_vendor = 0x1002; - pirq->rtr_device = 0x4384; - - pirq->miniport_data = 0; - - memset(pirq->rfu, 0, sizeof(pirq->rfu)); - - pirq_info = (void *)(&pirq->checksum + 1); - slot_num = 0; - - /* pci bridge */ - write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), - 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, - 0); - pirq_info++; - - slot_num++; - - pirq->size = 32 + 16 * slot_num; - - for (i = 0; i < pirq->size; i++) - sum += v[i]; - - sum = pirq->checksum - sum; - - if (sum != pirq->checksum) { - pirq->checksum = sum; - } - - printk(BIOS_INFO, "write_pirq_routing_table done.\n"); - - return (unsigned long)pirq_info; -} diff --git a/src/mainboard/amd/lamar/mainboard.c b/src/mainboard/amd/lamar/mainboard.c deleted file mode 100644 index 2f716d0..0000000 --- a/src/mainboard/amd/lamar/mainboard.c +++ /dev/null @@ -1,151 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 - 2014 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci_def.h> -#include <cpu/x86/msr.h> -#include <cpu/amd/mtrr.h> -#include <northbridge/amd/pi/00630F01/pci_devs.h> -#include <southbridge/amd/pi/hudson/amd_pci_int_defs.h> -#include <southbridge/amd/pi/hudson/hudson.h> -#include <southbridge/amd/pi/hudson/pci_devs.h> -#include <southbridge/amd/common/amd_pci_util.h> - -/*********************************************************** - * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. - * This table is responsible for physically routing the PIC and - * IOAPIC IRQs to the different PCI devices on the system. It - * is read and written via registers 0xC00/0xC01 as an - * Index/Data pair. These values are chipset and mainboard - * dependent and should be updated accordingly. - * - * These values are used by the PCI configuration space, - * MP Tables. TODO: Make ACPI use these values too. - */ -const u8 mainboard_picr_data[] = { - /* INTA# - INTH# */ - [0x00] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B, - /* Misc-nil,0,1,2, INT from Serial irq */ - [0x08] = 0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon, SD */ - [0x10] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A, - [0x18] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, - /* IMC INT0 - 5 */ - [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, - [0x28] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, - /* USB Devs 18/19/22 INTA-C */ - [0x30] = 0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x1F, - [0x38] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, - /* [40..41] IDE, SATA */ - [0x40] = 0x1F,0x0F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, - [0x48] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, - /* [50..53] GPPInt0 - 3 */ - [0x50] = 0x0A,0x0B,0x0A,0x0B, - [0x58] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, - [0x60] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, - [0x68] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, - [0x70] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, - [0x78] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, - /* [80..81] Northbridge devices (indices above C00/C01 range) */ - [0x80] = 0x0C,0x1F, -}; - -const u8 mainboard_intr_data[] = { - /* INTA# - INTH# */ - [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, - /* Misc-nil,0,1,2, INT from Serial irq */ - [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon, SD */ - [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x1F,0x1F,0x10, - [0x18] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, - /* IMC INT0 - 5 */ - [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, - [0x28] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, - /* USB Devs 18/19/20/22 INTA-C */ - [0x30] = 0x11,0x12,0x11,0x12,0x11,0x12,0x11,0x1F, - [0x38] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, - /* SATA */ - [0x40] = 0x11,0x13,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, - [0x48] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, - /* [50..53] GPPInt0 - 3 */ - [0x50] = 0x10,0x11,0x12,0x13, - [0x58] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, - [0x60] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, - [0x68] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, - [0x70] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, - [0x78] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, - /* [80..81] Northbridge devices (indices above C00/C01 range) */ - [0x80] = 0x17,0x10, -}; - -/* - * This table defines the index into the picr/intr_data - * tables for each device. Any enabled device and slot - * that uses hardware interrupts should have an entry - * in this table to define its index into the FCH - * PCI_INTR register 0xC00/0xC01. This index will define - * the interrupt that it should use. Putting PIRQ_A into - * the PIN A index for a device will tell that device to - * use PIC IRQ 10 if it uses PIN A for its hardware INT. - */ -static const struct pirq_struct mainboard_pirq_data[] = { - {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* PCIe J119: 02.1 */ - {NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* PCIe J118: 03.1 */ - {NB_PCIE_PORT4_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* PCIe J120: 03.2 */ - {XHCI_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* XHCI: 10.0 */ - {XHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}}, /* XHCI: 10.1 */ - {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SATA: 11.0 */ - {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1: 12.0 */ - {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1: 12.2 */ - {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2: 13.0 */ - {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2: 13.2 */ - {SMBUS_DEVFN, {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SMBUS: 14.0 */ - {IDE_DEVFN, {PIRQ_NC, PIRQ_IDE, PIRQ_NC, PIRQ_NC}}, /* IDE: 14.1 */ - {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* HDA: 14.2 */ - {SB_PCI_PORT_DEVFN, {PIRQ_H, PIRQ_E, PIRQ_F, PIRQ_G}}, /* PCI: 14.4 */ - {OHCI4_DEVFN, {PIRQ_NC, PIRQ_NC, PIRQ_OHCI4, PIRQ_NC}}, /* OHCI4: 14.5 */ - {SD_DEVFN, {PIRQ_SD, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SD: 14.7 */ - {SB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* LAN: 15.0 */ - {SB_PCIE_PORT2_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A}}, /* mPCIe J122: 15.1 */ - {SB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* mPCIe J123: 15.2 */ - {SB_PCIE_PORT4_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A}}, /* unused 15.3 */ - {OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI3: 16.0 (same device as xHCI 10.0) */ - {EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}}, /* EHCI3: 16.2 (same device as xHCI 10.1) */ -}; - -/* PIRQ Setup */ -static void pirq_setup(void) -{ - pirq_data_ptr = mainboard_pirq_data; - pirq_data_size = FCH_INT_TABLE_SIZE /* FIXME sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct) */; - intr_data_ptr = mainboard_intr_data; - picr_data_ptr = mainboard_picr_data; -} - -/************************************************* - * enable the dedicated function in lamar board. - *************************************************/ -static void mainboard_enable(struct device *dev) -{ - printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - - /* Initialize the PIRQ data structures for consumption */ - pirq_setup(); -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/amd/lamar/mptable.c b/src/mainboard/amd/lamar/mptable.c deleted file mode 100644 index 1f2093d..0000000 --- a/src/mainboard/amd/lamar/mptable.c +++ /dev/null @@ -1,151 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 - 2014 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <stdint.h> -#include <cpu/x86/lapic.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <drivers/generic/ioapic/chip.h> -#include <southbridge/amd/pi/hudson/amd_pci_int_defs.h> -#include <northbridge/amd/pi/00630F01/pci_devs.h> - -#define NB_APIC_ADDR ((u8 *)0xFEC20000) - -#define PCI_INT(bus, dev, fn, apic, pin) \ - if (((pin) != 0x00) && ((pin) != 0x1F)) \ - { \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apic, (pin)); \ - } - -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* Initialize the MP_Table */ - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - /* - * Type 0: Processor Entries: - * LAPIC ID, LAPIC Version, CPU Flags:EN/BP, - * CPU Signature (Stepping, Model, Family), - * Feature Flags - */ - smp_write_processors(mc); - - /* - * Type 1: Bus Entries: - * Bus ID, Bus Type - */ - mptable_write_buses(mc, NULL, &bus_isa); - - /* - * Type 2: I/O APICs: - * APIC ID, Version, APIC Flags:EN, Address - */ - - u8 apicid_nb = (io_apic_read(NB_APIC_ADDR, 0x00) >> 24); /* Get the GNB IOAPIC ID */ - u8 apicver_nb = (io_apic_read(NB_APIC_ADDR, 0x01) & 0xFF); /* Get the GNB IOAPIC version */ - - smp_write_ioapic(mc, apicid_nb, apicver_nb, NB_APIC_ADDR); - - u8 apicid_sb = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); /* Get the southbridge IOAPIC ID */ - u8 apicver_sb = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); /* Get the southbridge IOAPIC version */ - - smp_write_ioapic(mc, apicid_sb, apicver_sb, VIO_APIC_VADDR); - - /* - * Type 3: I/O Interrupt Table Entries: - * Int Type, Int Polarity, Int Level, Source Bus ID, - * Source Bus IRQ, Dest APIC ID, Dest PIN# - */ - mptable_add_isa_interrupts(mc, bus_isa, apicid_nb, 0); - mptable_add_isa_interrupts(mc, bus_isa, apicid_sb, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ - - /* APU Internal Graphic Device */ - PCI_INT(0x0, 0x01, 0x0, apicid_nb, intr_data_ptr[PIRQ_GFX]); - PCI_INT(0x0, 0x01, 0x1, apicid_nb, intr_data_ptr[PIRQ_ACTL]); - - /* SMBUS / ACPI */ - PCI_INT(0x0, 0x14, 0x0, apicid_sb, intr_data_ptr[PIRQ_SMBUS]); - - /* Southbridge HD Audio */ - PCI_INT(0x0, 0x14, 0x2, apicid_sb, intr_data_ptr[PIRQ_HDA]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, apicid_sb, intr_data_ptr[PIRQ_OHCI1]); - PCI_INT(0x0, 0x12, 0x2, apicid_sb, intr_data_ptr[PIRQ_EHCI1]); - PCI_INT(0x0, 0x13, 0x0, apicid_sb, intr_data_ptr[PIRQ_OHCI2]); - PCI_INT(0x0, 0x13, 0x2, apicid_sb, intr_data_ptr[PIRQ_EHCI2]); - PCI_INT(0x0, 0x16, 0x0, apicid_sb, intr_data_ptr[PIRQ_OHCI3]); - PCI_INT(0x0, 0x16, 0x2, apicid_sb, intr_data_ptr[PIRQ_EHCI3]); - PCI_INT(0x0, 0x14, 0x5, apicid_sb, intr_data_ptr[PIRQ_OHCI4]); - - /* SATA */ - PCI_INT(0x0, 0x11, 0x0, apicid_sb, intr_data_ptr[PIRQ_SATA]); - - /* IDE */ - PCI_INT(0x0, 0x14, 0x1, apicid_sb, intr_data_ptr[PIRQ_IDE]); - - /* PCI slots */ - /* NB Gfx PCIe Bridges */ - PCI_INT(0, 0x2, 0x1, apicid_nb, intr_data_ptr[PIRQ_A]); - PCI_INT(0, 0x2, 0x2, apicid_nb, intr_data_ptr[PIRQ_A]); - - /* NB GPP PCIe Bridges */ - PCI_INT(0, 0x3, 0x1, apicid_nb, intr_data_ptr[PIRQ_A]); - PCI_INT(0, 0x3, 0x2, apicid_nb, intr_data_ptr[PIRQ_A]); - PCI_INT(0, 0x3, 0x3, apicid_nb, intr_data_ptr[PIRQ_A]); - PCI_INT(0, 0x3, 0x4, apicid_nb, intr_data_ptr[PIRQ_A]); - PCI_INT(0, 0x3, 0x5, apicid_nb, intr_data_ptr[PIRQ_A]); - - /* PCI slots */ - PCI_INT(0, 0x14, 0x4, apicid_sb, intr_data_ptr[PIRQ_A]); - - /* FCH GPP PCIe Bridges */ - PCI_INT(0x0, 0x15, 0x0, apicid_sb, intr_data_ptr[PIRQ_A]); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, apicid_sb, intr_data_ptr[PIRQ_A]); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, apicid_sb, intr_data_ptr[PIRQ_A]); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, apicid_sb, intr_data_ptr[PIRQ_A]); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */ - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/amd/lamar/romstage.c b/src/mainboard/amd/lamar/romstage.c deleted file mode 100644 index a22b247..0000000 --- a/src/mainboard/amd/lamar/romstage.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 - 2014 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <device/pci_def.h> -#include <arch/io.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> -#include <console/console.h> -#include <northbridge/amd/agesa/state_machine.h> -#include <southbridge/amd/common/amd_defs.h> -#include <southbridge/amd/pi/hudson/hudson.h> -#include <superio/fintek/f81216h/f81216h.h> - -#define SERIAL_DEV PNP_DEV(0x4e, F81216H_SP1) - -static void romstage_main_template(void) -{ - u32 val; - - /* - * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for - * LpcClk[1:0]". This following register setting has been - * replicated in every reference design since Parmer, so it is - * believed to be required even though it is not documented in - * the SoC BKDGs. Without this setting, there is no serial - * output. - */ - outb(0xD2, 0xcd6); - outb(0x00, 0xcd7); - - hudson_lpc_decode(); - - outb(0x24, 0xCD6); - outb(0x01, 0xCD7); - *(volatile u32 *) (AMD_SB_ACPI_MMIO_ADDR + 0xE00 + 0x28) |= 1 << 18; /* 24Mhz */ - *(volatile u32 *) (AMD_SB_ACPI_MMIO_ADDR + 0xE00 + 0x40) &= ~(1 << 2); /* 24Mhz */ - - if (!cpu_init_detectedx) { - post_code(0x30); - f81216h_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE, MODE_7777); - post_code(0x31); - console_init(); - } -} -- To view, visit https://review.coreboot.org/c/coreboot/+/38115 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa68ca0fda295245a0af178b6e18ee31b0953cce Gerrit-Change-Number: 38115 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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