January 2020 - coreboot-gerrit

Change in coreboot[master]: sb/intel/common/acpi: Update _OSI strings and OSYS values
by HAOUAS Elyes (Code Review) Jan. 7, 2020

Jan. 7, 2020

HAOUAS Elyes has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/30221 ) Change subject: sb/intel/common/acpi: Update _OSI strings and OSYS values ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/30221 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b0cb0a516df43f7b9d6dbac89b7f8f32723ac41 Gerrit-Change-Number: 30221 Gerrit-PatchSet: 6 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: nb/intel/i440bx: Remove never used 'dra' value
by HAOUAS Elyes (Code Review) Jan. 7, 2020

Jan. 7, 2020

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34558 ) Change subject: nb/intel/i440bx: Remove never used 'dra' value ...................................................................... nb/intel/i440bx: Remove never used 'dra' value Change-Id: I65c41f56d7a0639eac821844e653e5644aca4f0c Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i440bx/raminit.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/34558/1 diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c index 91959c7..3a1b66a 100644 --- a/src/northbridge/intel/i440bx/raminit.c +++ b/src/northbridge/intel/i440bx/raminit.c @@ -799,7 +799,6 @@ } /* "DRA" is our RPS for the two rows on this DIMM. */ - dra = 0; /* Columns */ col = spd_read_byte(device, SPD_NUM_COLUMNS); -- To view, visit https://review.coreboot.org/c/coreboot/+/34558 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65c41f56d7a0639eac821844e653e5644aca4f0c Gerrit-Change-Number: 34558 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/x4x/gma: Store 'vga_disable' if MAINBOARD_USE_LIBGFXINIT
by HAOUAS Elyes (Code Review) Jan. 7, 2020

Jan. 7, 2020

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34434 ) Change subject: nb/intel/x4x/gma: Store 'vga_disable' if MAINBOARD_USE_LIBGFXINIT ...................................................................... nb/intel/x4x/gma: Store 'vga_disable' if MAINBOARD_USE_LIBGFXINIT Found-by: scan-build 7.0.1-8 Change-Id: I6feaa3a19d44b1d6f650bc7bc72dc575b032f4b1 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/x4x/gma.c 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/34434/1 diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c index 61731fe..6577153 100644 --- a/src/northbridge/intel/x4x/gma.c +++ b/src/northbridge/intel/x4x/gma.c @@ -68,9 +68,8 @@ /* configure GMBUSFREQ */ pci_update_config16(dev, 0xcc, ~0x1ff, 0xbc); - int vga_disable = (pci_read_config16(dev, D0F0_GGC) & 2) >> 1; - if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) { + int vga_disable = (pci_read_config16(dev, D0F0_GGC) & 2) >> 1; if (vga_disable) { printk(BIOS_INFO, "IGD is not decoding legacy VGA MEM and IO: skipping NATIVE graphic init\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/34434 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6feaa3a19d44b1d6f650bc7bc72dc575b032f4b1 Gerrit-Change-Number: 34434 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/i82801gx: Remove superfluous tabs
by HAOUAS Elyes (Code Review) Jan. 7, 2020

Jan. 7, 2020

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36928 ) Change subject: sb/intel/i82801gx: Remove superfluous tabs ...................................................................... sb/intel/i82801gx: Remove superfluous tabs Change-Id: Ia12836c6a3bb412afc3c0f0089704c1298da6d16 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/i82801gx/chip.h M src/southbridge/intel/i82801gx/i82801gx.h 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/36928/1 diff --git a/src/southbridge/intel/i82801gx/chip.h b/src/southbridge/intel/i82801gx/chip.h index 75b9575..1fca400 100644 --- a/src/southbridge/intel/i82801gx/chip.h +++ b/src/southbridge/intel/i82801gx/chip.h @@ -88,4 +88,4 @@ uint32_t gen4_dec; }; -#endif /* SOUTHBRIDGE_INTEL_I82801GX_CHIP_H */ +#endif /* SOUTHBRIDGE_INTEL_I82801GX_CHIP_H */ diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 3d27faa..f28d2b2 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -356,4 +356,4 @@ #define TCO1_CNT 0x68 #endif /* __ACPI__ */ -#endif /* SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H */ +#endif /* SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/36928 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia12836c6a3bb412afc3c0f0089704c1298da6d16 Gerrit-Change-Number: 36928 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: lib/ubsan: Drop GNUC < 6 guard
by HAOUAS Elyes (Code Review) Jan. 7, 2020

Jan. 7, 2020

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37890 ) Change subject: lib/ubsan: Drop GNUC < 6 guard ...................................................................... lib/ubsan: Drop GNUC < 6 guard We currently use GCC-8.3.0 Change-Id: I57bae238cc65af34ff0bbf653de156bf0d0181d0 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/lib/ubsan.c 1 file changed, 0 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/37890/1 diff --git a/src/lib/ubsan.c b/src/lib/ubsan.c index 1283400..8ab67f0 100644 --- a/src/lib/ubsan.c +++ b/src/lib/ubsan.c @@ -242,15 +242,6 @@ ABORT_VARIANT_VP_VP(vla_bound_not_positive); struct ubsan_float_cast_overflow_data { -/* -* TODO: Remove this GCC 5.x compatibility after switching to GCC 6.x. The -* GCC developers accidentally forgot the source location. Their -* libubsan probes to see if it looks like a path, but we don't need -* to maintain compatibility with multiple gcc releases. See below. -*/ -#if !(defined(__GNUC__) && __GNUC__ < 6) - struct ubsan_source_location location; -#endif struct ubsan_type_descriptor *from_type; struct ubsan_type_descriptor *to_type; }; @@ -261,11 +252,7 @@ (struct ubsan_float_cast_overflow_data *)data_raw; ubsan_value_handle_t from = (ubsan_value_handle_t)from_raw; (void) from; -#if !(defined(__GNUC__) && __GNUC__ < 6) - ubsan_abort(&data->location, "float cast overflow"); -#else ubsan_abort(((void) data, &unknown_location), "float cast overflow"); -#endif } ABORT_VARIANT_VP_VP(float_cast_overflow); -- To view, visit https://review.coreboot.org/c/coreboot/+/37890 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I57bae238cc65af34ff0bbf653de156bf0d0181d0 Gerrit-Change-Number: 37890 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/{commonlib,cpu}: Remove unused '#include <device/pci.h>'
by HAOUAS Elyes (Code Review) Jan. 7, 2020

Jan. 7, 2020

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37524 ) Change subject: src/{commonlib,cpu}: Remove unused '#include <device/pci.h>' ...................................................................... src/{commonlib,cpu}: Remove unused '#include <device/pci.h>' Change-Id: Ide1cd1e6a6645d545ba31fe19dbf293b386fe072 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/commonlib/storage/pci_sdhci.c M src/cpu/amd/pi/00630F01/model_15_init.c M src/cpu/amd/pi/00660F01/model_15_init.c M src/cpu/amd/pi/00730F01/model_16_init.c M src/cpu/intel/haswell/smmrelocate.c M src/cpu/intel/smm/gen1/smmrelocate.c 6 files changed, 0 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/37524/1 diff --git a/src/commonlib/storage/pci_sdhci.c b/src/commonlib/storage/pci_sdhci.c index 380f2db..abade3d 100644 --- a/src/commonlib/storage/pci_sdhci.c +++ b/src/commonlib/storage/pci_sdhci.c @@ -13,7 +13,6 @@ */ #include <commonlib/sdhci.h> -#include <device/pci.h> #include <device/pci_ops.h> #include <stdint.h> #include <string.h> diff --git a/src/cpu/amd/pi/00630F01/model_15_init.c b/src/cpu/amd/pi/00630F01/model_15_init.c index f1dd58e..82d1f31 100644 --- a/src/cpu/amd/pi/00630F01/model_15_init.c +++ b/src/cpu/amd/pi/00630F01/model_15_init.c @@ -18,7 +18,6 @@ #include <cpu/amd/mtrr.h> #include <cpu/x86/smm.h> #include <device/device.h> -#include <device/pci.h> #include <cpu/x86/pae.h> #include <cpu/x86/lapic.h> #include <cpu/cpu.h> diff --git a/src/cpu/amd/pi/00660F01/model_15_init.c b/src/cpu/amd/pi/00660F01/model_15_init.c index 78f3ce0..9714c2f 100644 --- a/src/cpu/amd/pi/00660F01/model_15_init.c +++ b/src/cpu/amd/pi/00660F01/model_15_init.c @@ -17,7 +17,6 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/mtrr.h> #include <device/device.h> -#include <device/pci.h> #include <cpu/x86/pae.h> #include <cpu/x86/lapic.h> #include <cpu/cpu.h> diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c index 8edf0d9..c7f36dd 100644 --- a/src/cpu/amd/pi/00730F01/model_16_init.c +++ b/src/cpu/amd/pi/00730F01/model_16_init.c @@ -18,7 +18,6 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/mtrr.h> #include <device/device.h> -#include <device/pci.h> #include <cpu/x86/pae.h> #include <cpu/x86/lapic.h> #include <cpu/cpu.h> diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c index d259460..7d7922e 100644 --- a/src/cpu/intel/haswell/smmrelocate.c +++ b/src/cpu/intel/haswell/smmrelocate.c @@ -14,7 +14,6 @@ #include <types.h> #include <string.h> #include <device/device.h> -#include <device/pci.h> #include <device/pci_ops.h> #include <cpu/x86/cache.h> #include <cpu/x86/lapic.h> diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c index 834ec04..2920822 100644 --- a/src/cpu/intel/smm/gen1/smmrelocate.c +++ b/src/cpu/intel/smm/gen1/smmrelocate.c @@ -17,7 +17,6 @@ #include <types.h> #include <string.h> #include <device/device.h> -#include <device/pci.h> #include <commonlib/helpers.h> #include <cpu/x86/cache.h> #include <cpu/x86/mp.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/37524 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide1cd1e6a6645d545ba31fe19dbf293b386fe072 Gerrit-Change-Number: 37524 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/{arch,lib}: Remove unused '#include <device/pci.h>'
by HAOUAS Elyes (Code Review) Jan. 7, 2020

Jan. 7, 2020

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37525 ) Change subject: src/{arch,lib}: Remove unused '#include <device/pci.h>' ...................................................................... src/{arch,lib}: Remove unused '#include <device/pci.h>' Change-Id: I8646a56a9190b4b5ab13be2bfa058429e5c4ddaf Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/x86/acpi.c M src/lib/hardwaremain.c M src/lib/reg_script.c 3 files changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/37525/1 diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index 2f793b4..5b5e587 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -28,7 +28,6 @@ #include <arch/acpi.h> #include <arch/acpi_ivrs.h> #include <arch/acpigen.h> -#include <device/pci.h> #include <cbmem.h> #include <commonlib/helpers.h> #include <cpu/x86/lapic_def.h> diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index 3fcf882..bffb0ff 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -27,7 +27,6 @@ #include <cbmem.h> #include <version.h> #include <device/device.h> -#include <device/pci.h> #include <delay.h> #include <stdlib.h> #include <boot/tables.h> diff --git a/src/lib/reg_script.c b/src/lib/reg_script.c index 299fd75..8eeda05 100644 --- a/src/lib/reg_script.c +++ b/src/lib/reg_script.c @@ -20,7 +20,6 @@ #include <delay.h> #include <device/device.h> #include <device/resource.h> -#include <device/pci.h> #include <stdint.h> #include <reg_script.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/37525 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8646a56a9190b4b5ab13be2bfa058429e5c4ddaf Gerrit-Change-Number: 37525 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP] src: Remove unused 'include <stddef.h>
by HAOUAS Elyes (Code Review) Jan. 7, 2020

Jan. 7, 2020

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37414 ) Change subject: [WIP] src: Remove unused 'include <stddef.h> ...................................................................... [WIP] src: Remove unused 'include <stddef.h> Change-Id: I64d0d63a93b625e9792790c93b07851e4491ab34 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/riscv/arch_timer.c M src/arch/riscv/misaligned.c M src/arch/riscv/smp.c M src/arch/x86/include/arch/ebda.h M src/arch/x86/include/smm.h M src/commonlib/include/commonlib/rmodule-defs.h M src/console/printk.c M src/cpu/ti/am335x/cbmem.c M src/cpu/ti/am335x/header.c M src/drivers/elog/boot_count.c M src/drivers/intel/fsp2_0/include/fsp/api.h M src/drivers/intel/fsp2_0/include/fsp/soc_binding.h M src/drivers/tpm/tpm.c M src/drivers/usb/ehci_debug.c M src/drivers/usb/gadget.c M src/drivers/usb/pci_ehci.c M src/include/device/pci_rom.h M src/include/list.h M src/include/thread.h M src/lib/edid.c M src/lib/timer_queue.c M src/lib/timestamp.c M src/mainboard/google/daisy/memory.c M src/mainboard/google/eve/romstage.c M src/mainboard/google/kukui/boardid.c M src/mainboard/google/peach_pit/memory.c M src/mainboard/intel/baskingridge/romstage.c M src/mainboard/razer/blade_stealth_kbl/romstage.c M src/northbridge/amd/agesa/agesa_helper.h M src/northbridge/intel/gm45/igd.c M src/northbridge/intel/gm45/pcie.c M src/northbridge/intel/gm45/pm.c M src/northbridge/intel/gm45/thermal.c M src/security/vboot/vboot_common.c M src/soc/amd/picasso/chip.h M src/soc/intel/baytrail/romstage/pmc.c M src/soc/intel/baytrail/romstage/raminit.c M src/soc/intel/baytrail/romstage/romstage.c M src/soc/intel/braswell/romstage/romstage.c M src/soc/intel/broadwell/romstage/romstage.c M src/soc/intel/cannonlake/include/soc/gpio_defs.h M src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h M src/soc/intel/icelake/include/soc/gpio_defs.h M src/soc/intel/skylake/include/soc/gpio_defs.h M src/soc/intel/tigerlake/include/soc/gpio_defs.h M src/soc/mediatek/common/cbmem.c M src/soc/mediatek/common/ddp.c M src/soc/mediatek/common/include/soc/gpio_common.h M src/soc/mediatek/common/include/soc/usb_common.h M src/soc/mediatek/common/mtcmos.c M src/soc/mediatek/mt8173/ddp.c M src/soc/mediatek/mt8173/include/soc/addressmap.h M src/soc/mediatek/mt8173/include/soc/dramc_register.h M src/soc/mediatek/mt8173/include/soc/spm.h M src/soc/mediatek/mt8183/ddp.c M src/soc/mediatek/mt8183/pll.c M src/soc/nvidia/tegra/dc.h M src/soc/nvidia/tegra124/dma.c M src/soc/nvidia/tegra124/include/soc/addressmap.h M src/soc/nvidia/tegra124/include/soc/emc.h M src/soc/nvidia/tegra124/include/soc/mc.h M src/soc/nvidia/tegra124/include/soc/sdram_param.h M src/soc/nvidia/tegra124/include/soc/spi.h M src/soc/nvidia/tegra210/dma.c M src/soc/nvidia/tegra210/include/soc/clk_rst.h M src/soc/nvidia/tegra210/include/soc/emc.h M src/soc/nvidia/tegra210/include/soc/mc.h M src/soc/nvidia/tegra210/include/soc/sdram_param.h M src/soc/nvidia/tegra210/include/soc/spi.h M src/soc/rockchip/common/include/soc/spi.h M src/soc/rockchip/common/vop.c M src/soc/rockchip/rk3288/display.c M src/soc/rockchip/rk3288/soc.c M src/soc/rockchip/rk3399/display.c M src/soc/rockchip/rk3399/soc.c M src/soc/samsung/exynos5250/cbmem.c M src/soc/samsung/exynos5250/cpu.c M src/soc/samsung/exynos5420/cbmem.c M src/soc/samsung/exynos5420/cpu.c M src/soc/samsung/exynos5420/i2c.c M src/soc/sifive/fu540/otp.c M src/soc/sifive/fu540/uart.c M src/southbridge/amd/cimx/sb800/SBPLATFORM.h M src/southbridge/intel/lynxpoint/pcie.c 84 files changed, 0 insertions(+), 84 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/37414/1 diff --git a/src/arch/riscv/arch_timer.c b/src/arch/riscv/arch_timer.c index 55b1f72..0467f68 100644 --- a/src/arch/riscv/arch_timer.c +++ b/src/arch/riscv/arch_timer.c @@ -16,7 +16,6 @@ #include <device/mmio.h> #include <arch/encoding.h> #include <console/console.h> -#include <stddef.h> #include <timer.h> #include <mcall.h> diff --git a/src/arch/riscv/misaligned.c b/src/arch/riscv/misaligned.c index ebff2d6..4e3bd48 100644 --- a/src/arch/riscv/misaligned.c +++ b/src/arch/riscv/misaligned.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <stddef.h> #include <stdint.h> #include <vm.h> #include <arch/exception.h> diff --git a/src/arch/riscv/smp.c b/src/arch/riscv/smp.c index b32e4b8..61b9353 100644 --- a/src/arch/riscv/smp.c +++ b/src/arch/riscv/smp.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <stddef.h> #include <arch/encoding.h> #include <arch/smp/smp.h> #include <arch/smp/spinlock.h> diff --git a/src/arch/x86/include/arch/ebda.h b/src/arch/x86/include/arch/ebda.h index 6ee3332..083d687 100644 --- a/src/arch/x86/include/arch/ebda.h +++ b/src/arch/x86/include/arch/ebda.h @@ -16,7 +16,6 @@ #define __ARCH_EBDA_H #include <stdint.h> -#include <stddef.h> #define X86_BDA_SIZE 0x200 #define X86_BDA_BASE ((void *)0x400) diff --git a/src/arch/x86/include/smm.h b/src/arch/x86/include/smm.h index 320bac6..63c93eb 100644 --- a/src/arch/x86/include/smm.h +++ b/src/arch/x86/include/smm.h @@ -11,7 +11,6 @@ * GNU General Public License for more details. */ -#include <stddef.h> #include <stdint.h> #include <cpu/x86/smm.h> diff --git a/src/commonlib/include/commonlib/rmodule-defs.h b/src/commonlib/include/commonlib/rmodule-defs.h index de06941..00cc449 100644 --- a/src/commonlib/include/commonlib/rmodule-defs.h +++ b/src/commonlib/include/commonlib/rmodule-defs.h @@ -14,7 +14,6 @@ #define RMODULE_DEFS_H #include <stdint.h> -#include <stddef.h> #define RMODULE_MAGIC 0xf8fe #define RMODULE_VERSION_1 1 diff --git a/src/console/printk.c b/src/console/printk.c index a08dd2f..f2f6e9a 100644 --- a/src/console/printk.c +++ b/src/console/printk.c @@ -19,7 +19,6 @@ #include <console/vtxprintf.h> #include <smp/spinlock.h> #include <smp/node.h> -#include <stddef.h> #include <trace.h> #include <timer.h> diff --git a/src/cpu/ti/am335x/cbmem.c b/src/cpu/ti/am335x/cbmem.c index 2ecca65..37ff7bf 100644 --- a/src/cpu/ti/am335x/cbmem.c +++ b/src/cpu/ti/am335x/cbmem.c @@ -11,7 +11,6 @@ * GNU General Public License for more details. */ -#include <stddef.h> #include <cbmem.h> #include <symbols.h> diff --git a/src/cpu/ti/am335x/header.c b/src/cpu/ti/am335x/header.c index bef1e56..13d5935 100644 --- a/src/cpu/ti/am335x/header.c +++ b/src/cpu/ti/am335x/header.c @@ -12,7 +12,6 @@ * GNU General Public License for more details. */ -#include <stddef.h> #include <stdint.h> #include <symbols.h> diff --git a/src/drivers/elog/boot_count.c b/src/drivers/elog/boot_count.c index a6efb01..d927e4a 100644 --- a/src/drivers/elog/boot_count.c +++ b/src/drivers/elog/boot_count.c @@ -14,7 +14,6 @@ #include <console/console.h> #include <ip_checksum.h> #include <pc80/mc146818rtc.h> -#include <stddef.h> #include <stdint.h> #include <elog.h> diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index b63cd04..e4c2e47 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -15,7 +15,6 @@ #ifndef _FSP2_0_API_H_ #define _FSP2_0_API_H_ -#include <stddef.h> #include <stdint.h> #include <fsp/soc_binding.h> #include <soc/intel/common/mma.h> diff --git a/src/drivers/intel/fsp2_0/include/fsp/soc_binding.h b/src/drivers/intel/fsp2_0/include/fsp/soc_binding.h index 931e427..72f5c90 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/soc_binding.h +++ b/src/drivers/intel/fsp2_0/include/fsp/soc_binding.h @@ -14,7 +14,6 @@ #ifndef _FSP2_0_SOC_BINDING_H_ #define _FSP2_0_SOC_BINDING_H_ -#include <stddef.h> #pragma pack(push) /* diff --git a/src/drivers/tpm/tpm.c b/src/drivers/tpm/tpm.c index b654666..6c91b7b 100644 --- a/src/drivers/tpm/tpm.c +++ b/src/drivers/tpm/tpm.c @@ -12,7 +12,6 @@ */ #include <types.h> -#include <stddef.h> #include <bootstate.h> #include <security/tpm/tspi.h> diff --git a/src/drivers/usb/ehci_debug.c b/src/drivers/usb/ehci_debug.c index 318dfe7..c62715d 100644 --- a/src/drivers/usb/ehci_debug.c +++ b/src/drivers/usb/ehci_debug.c @@ -11,7 +11,6 @@ * GNU General Public License for more details. */ -#include <stddef.h> #include <console/console.h> #include <console/usb.h> #include <arch/io.h> diff --git a/src/drivers/usb/gadget.c b/src/drivers/usb/gadget.c index 61e1031..913f56b 100644 --- a/src/drivers/usb/gadget.c +++ b/src/drivers/usb/gadget.c @@ -11,7 +11,6 @@ * GNU General Public License for more details. */ -#include <stddef.h> #include <console/console.h> #include <string.h> diff --git a/src/drivers/usb/pci_ehci.c b/src/drivers/usb/pci_ehci.c index dfc78cc..74b6c61 100644 --- a/src/drivers/usb/pci_ehci.c +++ b/src/drivers/usb/pci_ehci.c @@ -11,7 +11,6 @@ * GNU General Public License for more details. */ -#include <stddef.h> #include <console/console.h> #include <device/pci_ehci.h> #include <device/mmio.h> diff --git a/src/include/device/pci_rom.h b/src/include/device/pci_rom.h index 82f3c40..e88e7a5 100644 --- a/src/include/device/pci_rom.h +++ b/src/include/device/pci_rom.h @@ -1,7 +1,6 @@ #ifndef PCI_ROM_H #define PCI_ROM_H #include <endian.h> -#include <stddef.h> #include <arch/acpi.h> #define PCI_ROM_HDR 0xAA55 diff --git a/src/include/list.h b/src/include/list.h index 201a8d3..c75d947 100644 --- a/src/include/list.h +++ b/src/include/list.h @@ -18,7 +18,6 @@ #ifndef __LIST_H__ #define __LIST_H__ -#include <stddef.h> #include <stdint.h> struct list_node { diff --git a/src/include/thread.h b/src/include/thread.h index b66803e..284a749 100644 --- a/src/include/thread.h +++ b/src/include/thread.h @@ -15,7 +15,6 @@ #ifndef THREAD_H_ #define THREAD_H_ -#include <stddef.h> #include <stdint.h> #include <bootstate.h> #include <arch/cpu.h> diff --git a/src/lib/edid.c b/src/lib/edid.c index fd7f5ba..8cbb279 100644 --- a/src/lib/edid.c +++ b/src/lib/edid.c @@ -29,7 +29,6 @@ */ #include <assert.h> -#include <stddef.h> #include <console/console.h> #include <ctype.h> #include <stdint.h> diff --git a/src/lib/timer_queue.c b/src/lib/timer_queue.c index 5eaaa93..a29ff1b 100644 --- a/src/lib/timer_queue.c +++ b/src/lib/timer_queue.c @@ -12,7 +12,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ -#include <stddef.h> #include <timer.h> #define MAX_TIMER_QUEUE_ENTRIES 64 diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c index 7c7210c..c589d37 100644 --- a/src/lib/timestamp.c +++ b/src/lib/timestamp.c @@ -15,7 +15,6 @@ */ #include <assert.h> -#include <stddef.h> #include <stdint.h> #include <console/console.h> #include <cbmem.h> diff --git a/src/mainboard/google/daisy/memory.c b/src/mainboard/google/daisy/memory.c index c5b752c..6a084bd 100644 --- a/src/mainboard/google/daisy/memory.c +++ b/src/mainboard/google/daisy/memory.c @@ -19,7 +19,6 @@ #include <soc/setup.h> #include <soc/dmc.h> #include <soc/clk.h> -#include <stddef.h> const struct mem_timings mem_timings[] = { { diff --git a/src/mainboard/google/eve/romstage.c b/src/mainboard/google/eve/romstage.c index 7114715..d4d80b42 100644 --- a/src/mainboard/google/eve/romstage.c +++ b/src/mainboard/google/eve/romstage.c @@ -16,7 +16,6 @@ #include <boardid.h> #include <string.h> -#include <stddef.h> #include <fsp/soc_binding.h> #include <soc/romstage.h> #include <console/console.h> diff --git a/src/mainboard/google/kukui/boardid.c b/src/mainboard/google/kukui/boardid.c index ad7fb36..a23e7b2 100644 --- a/src/mainboard/google/kukui/boardid.c +++ b/src/mainboard/google/kukui/boardid.c @@ -18,7 +18,6 @@ #include <console/console.h> #include <soc/auxadc.h> #include <ec/google/chromeec/ec.h> -#include <stddef.h> /* For CBI un-provisioned/corrupted Flapjack board. */ #define FLAPJACK_UNDEF_SKU_ID 0 diff --git a/src/mainboard/google/peach_pit/memory.c b/src/mainboard/google/peach_pit/memory.c index 541e3b0..94236b0 100644 --- a/src/mainboard/google/peach_pit/memory.c +++ b/src/mainboard/google/peach_pit/memory.c @@ -18,7 +18,6 @@ #include <soc/dmc.h> #include <soc/gpio.h> #include <soc/setup.h> -#include <stddef.h> const struct mem_timings mem_timings = { .mem_manuf = MEM_MANUF_SAMSUNG, diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c index 1a10931..b75265b 100644 --- a/src/mainboard/intel/baskingridge/romstage.c +++ b/src/mainboard/intel/baskingridge/romstage.c @@ -15,7 +15,6 @@ */ #include <stdint.h> -#include <stddef.h> #include <arch/romstage.h> #include <cpu/intel/haswell/haswell.h> #include <northbridge/intel/haswell/haswell.h> diff --git a/src/mainboard/razer/blade_stealth_kbl/romstage.c b/src/mainboard/razer/blade_stealth_kbl/romstage.c index 445f620..d970ac1 100644 --- a/src/mainboard/razer/blade_stealth_kbl/romstage.c +++ b/src/mainboard/razer/blade_stealth_kbl/romstage.c @@ -23,7 +23,6 @@ #include "spd/spd.h" #include <ec/acpi/ec.h> #include <stdint.h> -#include <stddef.h> #define SPD_4X_2GB 0 #define SPD_4X_4GB 1 diff --git a/src/northbridge/amd/agesa/agesa_helper.h b/src/northbridge/amd/agesa/agesa_helper.h index dcc3360..933efca 100644 --- a/src/northbridge/amd/agesa/agesa_helper.h +++ b/src/northbridge/amd/agesa/agesa_helper.h @@ -16,7 +16,6 @@ #ifndef _AGESA_HELPER_H_ #define _AGESA_HELPER_H_ -#include <stddef.h> #include <arch/romstage.h> enum { diff --git a/src/northbridge/intel/gm45/igd.c b/src/northbridge/intel/gm45/igd.c index b1ce1be..3200a37 100644 --- a/src/northbridge/intel/gm45/igd.c +++ b/src/northbridge/intel/gm45/igd.c @@ -15,7 +15,6 @@ */ #include <stdint.h> -#include <stddef.h> #include <device/pci_ops.h> #include <device/pci_def.h> #include <console/console.h> diff --git a/src/northbridge/intel/gm45/pcie.c b/src/northbridge/intel/gm45/pcie.c index 4199274..9a643df 100644 --- a/src/northbridge/intel/gm45/pcie.c +++ b/src/northbridge/intel/gm45/pcie.c @@ -15,7 +15,6 @@ */ #include <stdint.h> -#include <stddef.h> #include <device/pci_ops.h> #include <device/pci_def.h> #include <console/console.h> diff --git a/src/northbridge/intel/gm45/pm.c b/src/northbridge/intel/gm45/pm.c index d96bcf4..ba4340b 100644 --- a/src/northbridge/intel/gm45/pm.c +++ b/src/northbridge/intel/gm45/pm.c @@ -15,7 +15,6 @@ */ #include <stdint.h> -#include <stddef.h> #include <device/pci_def.h> #include <cpu/x86/msr.h> #include <cpu/intel/speedstep.h> diff --git a/src/northbridge/intel/gm45/thermal.c b/src/northbridge/intel/gm45/thermal.c index 1629a67..623da7f 100644 --- a/src/northbridge/intel/gm45/thermal.c +++ b/src/northbridge/intel/gm45/thermal.c @@ -15,7 +15,6 @@ */ #include <stdint.h> -#include <stddef.h> #include <device/pci_def.h> #include <spd.h> diff --git a/src/security/vboot/vboot_common.c b/src/security/vboot/vboot_common.c index 458ed87..de735f4 100644 --- a/src/security/vboot/vboot_common.c +++ b/src/security/vboot/vboot_common.c @@ -18,7 +18,6 @@ #include <console/cbmem_console.h> #include <fmap.h> #include <reset.h> -#include <stddef.h> #include <security/vboot/misc.h> #include <security/vboot/vboot_common.h> #include <security/vboot/vbnv.h> diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index 4e9e18b..f34044c 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -16,7 +16,6 @@ #ifndef __PICASSO_CHIP_H__ #define __PICASSO_CHIP_H__ -#include <stddef.h> #include <stdint.h> #include <commonlib/helpers.h> #include <drivers/i2c/designware/dw_i2c.h> diff --git a/src/soc/intel/baytrail/romstage/pmc.c b/src/soc/intel/baytrail/romstage/pmc.c index 11b3b0f..d6f10ef 100644 --- a/src/soc/intel/baytrail/romstage/pmc.c +++ b/src/soc/intel/baytrail/romstage/pmc.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <stddef.h> #include <device/pci_ops.h> #include <console/console.h> #include <device/device.h> diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c index 62f8e42..9d1fbb2 100644 --- a/src/soc/intel/baytrail/romstage/raminit.c +++ b/src/soc/intel/baytrail/romstage/raminit.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <stddef.h> #include <arch/acpi.h> #include <assert.h> #include <cbfs.h> diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 25cb661..f8f5da6 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <stddef.h> #include <arch/io.h> #include <arch/romstage.h> #include <device/mmio.h> diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c index 38a0c2e..c03f7d6 100644 --- a/src/soc/intel/braswell/romstage/romstage.c +++ b/src/soc/intel/braswell/romstage/romstage.c @@ -16,7 +16,6 @@ */ #include <cbmem.h> -#include <stddef.h> #include <arch/io.h> #include <device/mmio.h> #include <console/console.h> diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 96218f4..557cfed 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <stddef.h> #include <stdint.h> #include <arch/cbfs.h> #include <arch/romstage.h> diff --git a/src/soc/intel/cannonlake/include/soc/gpio_defs.h b/src/soc/intel/cannonlake/include/soc/gpio_defs.h index 5c12e4c..b9b34f9 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio_defs.h +++ b/src/soc/intel/cannonlake/include/soc/gpio_defs.h @@ -17,7 +17,6 @@ #define _SOC_CANNONLAKE_GPIO_DEFS_H_ #ifndef __ACPI__ -#include <stddef.h> #endif #include <soc/gpio_common.h> #include <soc/gpio_soc_defs.h> diff --git a/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h b/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h index d03723d..987db1e 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h +++ b/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h @@ -17,7 +17,6 @@ #define _SOC_CANNONLAKE_GPIO_DEFS_CNP_H_H_ #ifndef __ACPI__ -#include <stddef.h> #endif #include <soc/gpio_common.h> #include <soc/gpio_soc_defs_cnp_h.h> diff --git a/src/soc/intel/icelake/include/soc/gpio_defs.h b/src/soc/intel/icelake/include/soc/gpio_defs.h index 6ecda85..3f8697c 100644 --- a/src/soc/intel/icelake/include/soc/gpio_defs.h +++ b/src/soc/intel/icelake/include/soc/gpio_defs.h @@ -17,7 +17,6 @@ #define _SOC_ICELAKE_GPIO_DEFS_H_ #ifndef __ACPI__ -#include <stddef.h> #endif #include <soc/gpio_soc_defs.h> diff --git a/src/soc/intel/skylake/include/soc/gpio_defs.h b/src/soc/intel/skylake/include/soc/gpio_defs.h index 321d3c2..8ccda49 100644 --- a/src/soc/intel/skylake/include/soc/gpio_defs.h +++ b/src/soc/intel/skylake/include/soc/gpio_defs.h @@ -16,7 +16,6 @@ #ifndef _SOC_GPIO_DEFS_H_ #define _SOC_GPIO_DEFS_H_ #ifndef __ACPI__ -#include <stddef.h> #endif #if CONFIG(SKYLAKE_SOC_PCH_H) # include <soc/gpio_pch_h_defs.h> diff --git a/src/soc/intel/tigerlake/include/soc/gpio_defs.h b/src/soc/intel/tigerlake/include/soc/gpio_defs.h index bffebcd..7e7a949 100644 --- a/src/soc/intel/tigerlake/include/soc/gpio_defs.h +++ b/src/soc/intel/tigerlake/include/soc/gpio_defs.h @@ -17,7 +17,6 @@ #define _SOC_TIGERLAKE_GPIO_DEFS_H_ #ifndef __ACPI__ -#include <stddef.h> #endif #include <soc/gpio_soc_defs.h> diff --git a/src/soc/mediatek/common/cbmem.c b/src/soc/mediatek/common/cbmem.c index 1a55d01..2ca1d55 100644 --- a/src/soc/mediatek/common/cbmem.c +++ b/src/soc/mediatek/common/cbmem.c @@ -14,7 +14,6 @@ */ #include <cbmem.h> -#include <stddef.h> #include <stdlib.h> #include <symbols.h> #include <soc/emi.h> diff --git a/src/soc/mediatek/common/ddp.c b/src/soc/mediatek/common/ddp.c index 463fd3f..d48d5ef 100644 --- a/src/soc/mediatek/common/ddp.c +++ b/src/soc/mediatek/common/ddp.c @@ -15,7 +15,6 @@ #include <device/mmio.h> #include <edid.h> -#include <stddef.h> #include <soc/addressmap.h> #include <soc/ddp.h> diff --git a/src/soc/mediatek/common/include/soc/gpio_common.h b/src/soc/mediatek/common/include/soc/gpio_common.h index 374c810..18a7f52 100644 --- a/src/soc/mediatek/common/include/soc/gpio_common.h +++ b/src/soc/mediatek/common/include/soc/gpio_common.h @@ -17,7 +17,6 @@ #define SOC_MEDIATEK_COMMON_GPIO_H #include <soc/gpio_base.h> -#include <stddef.h> #include <stdint.h> enum pull_enable { diff --git a/src/soc/mediatek/common/include/soc/usb_common.h b/src/soc/mediatek/common/include/soc/usb_common.h index 22704e7..2cfb79a 100644 --- a/src/soc/mediatek/common/include/soc/usb_common.h +++ b/src/soc/mediatek/common/include/soc/usb_common.h @@ -16,7 +16,6 @@ #ifndef SOC_MEDIATEK_USB_COMMON_H #define SOC_MEDIATEK_USB_COMMON_H -#include <stddef.h> /* ip_pw_ctrl0 */ #define CTRL0_IP_SW_RST (0x1 << 0) diff --git a/src/soc/mediatek/common/mtcmos.c b/src/soc/mediatek/common/mtcmos.c index fa0b23a..4b0109b 100644 --- a/src/soc/mediatek/common/mtcmos.c +++ b/src/soc/mediatek/common/mtcmos.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <stddef.h> #include <device/mmio.h> #include <soc/mtcmos.h> diff --git a/src/soc/mediatek/mt8173/ddp.c b/src/soc/mediatek/mt8173/ddp.c index 7e18a76..109c6ef 100644 --- a/src/soc/mediatek/mt8173/ddp.c +++ b/src/soc/mediatek/mt8173/ddp.c @@ -15,7 +15,6 @@ #include <device/mmio.h> #include <edid.h> -#include <stddef.h> #include <soc/addressmap.h> #include <soc/ddp.h> #include <types.h> diff --git a/src/soc/mediatek/mt8173/include/soc/addressmap.h b/src/soc/mediatek/mt8173/include/soc/addressmap.h index 90834a3..2ee23b2 100644 --- a/src/soc/mediatek/mt8173/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8173/include/soc/addressmap.h @@ -16,7 +16,6 @@ #ifndef __SOC_MEDIATEK_MT8173_INCLUDE_SOC_ADDRESS_MAP_H__ #define __SOC_MEDIATEK_MT8173_INCLUDE_SOC_ADDRESS_MAP_H__ -#include <stddef.h> #include <stdint.h> enum { diff --git a/src/soc/mediatek/mt8173/include/soc/dramc_register.h b/src/soc/mediatek/mt8173/include/soc/dramc_register.h index ce65173..67897f9 100644 --- a/src/soc/mediatek/mt8173/include/soc/dramc_register.h +++ b/src/soc/mediatek/mt8173/include/soc/dramc_register.h @@ -16,7 +16,6 @@ #ifndef _DRAMC_REGISTER_H_ #define _DRAMC_REGISTER_H_ -#include <stddef.h> #include <types.h> #define DRIVING_DS2_0 7 /* DS[2:0] 7->6 */ diff --git a/src/soc/mediatek/mt8173/include/soc/spm.h b/src/soc/mediatek/mt8173/include/soc/spm.h index 133c8a3..142dd13 100644 --- a/src/soc/mediatek/mt8173/include/soc/spm.h +++ b/src/soc/mediatek/mt8173/include/soc/spm.h @@ -17,7 +17,6 @@ #define __SOC_MEDIATEK_MT8173_SPM_H__ #include <soc/addressmap.h> -#include <stddef.h> enum { SPM_PROJECT_CODE = 0xb16 diff --git a/src/soc/mediatek/mt8183/ddp.c b/src/soc/mediatek/mt8183/ddp.c index 2d67de2..32632ae 100644 --- a/src/soc/mediatek/mt8183/ddp.c +++ b/src/soc/mediatek/mt8183/ddp.c @@ -15,7 +15,6 @@ #include <device/mmio.h> #include <edid.h> -#include <stddef.h> #include <soc/addressmap.h> #include <soc/ddp.h> diff --git a/src/soc/mediatek/mt8183/pll.c b/src/soc/mediatek/mt8183/pll.c index 5368077..b443a2b 100644 --- a/src/soc/mediatek/mt8183/pll.c +++ b/src/soc/mediatek/mt8183/pll.c @@ -15,7 +15,6 @@ #include <device/mmio.h> #include <delay.h> -#include <stddef.h> #include <soc/addressmap.h> #include <soc/infracfg.h> diff --git a/src/soc/nvidia/tegra/dc.h b/src/soc/nvidia/tegra/dc.h index 56332e4..421379b 100644 --- a/src/soc/nvidia/tegra/dc.h +++ b/src/soc/nvidia/tegra/dc.h @@ -17,7 +17,6 @@ #ifndef __SOC_NVIDIA_TEGRA_DC_H #define __SOC_NVIDIA_TEGRA_DC_H #include <device/device.h> -#include <stddef.h> #include <types.h> /* Register definitions for the Tegra display controller */ diff --git a/src/soc/nvidia/tegra124/dma.c b/src/soc/nvidia/tegra124/dma.c index ca4c969..6ee3a20 100644 --- a/src/soc/nvidia/tegra124/dma.c +++ b/src/soc/nvidia/tegra124/dma.c @@ -20,7 +20,6 @@ #include <stdint.h> #include <soc/addressmap.h> #include <soc/dma.h> -#include <stddef.h> struct apb_dma * const apb_dma = (struct apb_dma *)TEGRA_APB_DMA_BASE; diff --git a/src/soc/nvidia/tegra124/include/soc/addressmap.h b/src/soc/nvidia/tegra124/include/soc/addressmap.h index bb95051..0c2cb2c 100644 --- a/src/soc/nvidia/tegra124/include/soc/addressmap.h +++ b/src/soc/nvidia/tegra124/include/soc/addressmap.h @@ -20,7 +20,6 @@ #ifndef __SOC_NVIDIA_TEGRA124_INCLUDE_SOC_ADDRESS_MAP_H__ #define __SOC_NVIDIA_TEGRA124_INCLUDE_SOC_ADDRESS_MAP_H__ -#include <stddef.h> enum { TEGRA_SRAM_BASE = 0x40000000, diff --git a/src/soc/nvidia/tegra124/include/soc/emc.h b/src/soc/nvidia/tegra124/include/soc/emc.h index 8e190f9..5d01277 100644 --- a/src/soc/nvidia/tegra124/include/soc/emc.h +++ b/src/soc/nvidia/tegra124/include/soc/emc.h @@ -17,7 +17,6 @@ #ifndef __SOC_NVIDIA_TEGRA124_EMC_H__ #define __SOC_NVIDIA_TEGRA124_EMC_H__ -#include <stddef.h> #include <stdint.h> enum { diff --git a/src/soc/nvidia/tegra124/include/soc/mc.h b/src/soc/nvidia/tegra124/include/soc/mc.h index f249ecc..726d529 100644 --- a/src/soc/nvidia/tegra124/include/soc/mc.h +++ b/src/soc/nvidia/tegra124/include/soc/mc.h @@ -17,7 +17,6 @@ #ifndef __SOC_NVIDIA_TEGRA124_MC_H__ #define __SOC_NVIDIA_TEGRA124_MC_H__ -#include <stddef.h> #include <stdint.h> // Memory Controller registers we need/care about diff --git a/src/soc/nvidia/tegra124/include/soc/sdram_param.h b/src/soc/nvidia/tegra124/include/soc/sdram_param.h index 938d655c..03e2664 100644 --- a/src/soc/nvidia/tegra124/include/soc/sdram_param.h +++ b/src/soc/nvidia/tegra124/include/soc/sdram_param.h @@ -24,7 +24,6 @@ #ifndef __SOC_NVIDIA_TEGRA124_SDRAM_PARAM_H__ #define __SOC_NVIDIA_TEGRA124_SDRAM_PARAM_H__ -#include <stddef.h> #include <stdint.h> enum { diff --git a/src/soc/nvidia/tegra124/include/soc/spi.h b/src/soc/nvidia/tegra124/include/soc/spi.h index 875e880..d358ebb 100644 --- a/src/soc/nvidia/tegra124/include/soc/spi.h +++ b/src/soc/nvidia/tegra124/include/soc/spi.h @@ -18,7 +18,6 @@ #include <spi-generic.h> #include <soc/dma.h> -#include <stddef.h> struct tegra_spi_regs { u32 command1; /* 0x000: SPI_COMMAND1 */ diff --git a/src/soc/nvidia/tegra210/dma.c b/src/soc/nvidia/tegra210/dma.c index 9e4882f..2b7c6d2 100644 --- a/src/soc/nvidia/tegra210/dma.c +++ b/src/soc/nvidia/tegra210/dma.c @@ -20,7 +20,6 @@ #include <stdint.h> #include <soc/addressmap.h> #include <soc/dma.h> -#include <stddef.h> struct apb_dma * const apb_dma = (struct apb_dma *)TEGRA_APB_DMA_BASE; diff --git a/src/soc/nvidia/tegra210/include/soc/clk_rst.h b/src/soc/nvidia/tegra210/include/soc/clk_rst.h index 42eebed..f635290 100644 --- a/src/soc/nvidia/tegra210/include/soc/clk_rst.h +++ b/src/soc/nvidia/tegra210/include/soc/clk_rst.h @@ -16,7 +16,6 @@ #ifndef _TEGRA210_CLK_RST_H_ #define _TEGRA210_CLK_RST_H_ #include <stdint.h> -#include <stddef.h> /* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */ struct __packed clk_rst_ctlr { diff --git a/src/soc/nvidia/tegra210/include/soc/emc.h b/src/soc/nvidia/tegra210/include/soc/emc.h index 289aa72..8a1be1a 100644 --- a/src/soc/nvidia/tegra210/include/soc/emc.h +++ b/src/soc/nvidia/tegra210/include/soc/emc.h @@ -17,7 +17,6 @@ #ifndef __SOC_NVIDIA_TEGRA210_EMC_H__ #define __SOC_NVIDIA_TEGRA210_EMC_H__ -#include <stddef.h> #include <stdint.h> enum { diff --git a/src/soc/nvidia/tegra210/include/soc/mc.h b/src/soc/nvidia/tegra210/include/soc/mc.h index b78305a..9fd134c 100644 --- a/src/soc/nvidia/tegra210/include/soc/mc.h +++ b/src/soc/nvidia/tegra210/include/soc/mc.h @@ -17,7 +17,6 @@ #ifndef __SOC_NVIDIA_TEGRA210_MC_H__ #define __SOC_NVIDIA_TEGRA210_MC_H__ -#include <stddef.h> #include <stdint.h> // Memory Controller registers we need/care about diff --git a/src/soc/nvidia/tegra210/include/soc/sdram_param.h b/src/soc/nvidia/tegra210/include/soc/sdram_param.h index 0b6f7a0..47882dd 100644 --- a/src/soc/nvidia/tegra210/include/soc/sdram_param.h +++ b/src/soc/nvidia/tegra210/include/soc/sdram_param.h @@ -24,7 +24,6 @@ #ifndef __SOC_NVIDIA_TEGRA210_SDRAM_PARAM_H__ #define __SOC_NVIDIA_TEGRA210_SDRAM_PARAM_H__ -#include <stddef.h> #include <stdint.h> enum { diff --git a/src/soc/nvidia/tegra210/include/soc/spi.h b/src/soc/nvidia/tegra210/include/soc/spi.h index 46c1c3c..b87a4d3 100644 --- a/src/soc/nvidia/tegra210/include/soc/spi.h +++ b/src/soc/nvidia/tegra210/include/soc/spi.h @@ -19,7 +19,6 @@ #include <soc/dma.h> #include <spi-generic.h> -#include <stddef.h> struct tegra_spi_regs { u32 command1; /* 0x000: SPI_COMMAND1 */ diff --git a/src/soc/rockchip/common/include/soc/spi.h b/src/soc/rockchip/common/include/soc/spi.h index ce5de83..ba46134 100644 --- a/src/soc/rockchip/common/include/soc/spi.h +++ b/src/soc/rockchip/common/include/soc/spi.h @@ -18,7 +18,6 @@ /* This driver serves as a CBFS media source. */ #include <spi-generic.h> -#include <stddef.h> struct rockchip_spi { u32 ctrlr0; diff --git a/src/soc/rockchip/common/vop.c b/src/soc/rockchip/common/vop.c index f617b4a..1faa555 100644 --- a/src/soc/rockchip/common/vop.c +++ b/src/soc/rockchip/common/vop.c @@ -14,7 +14,6 @@ */ #include <device/mmio.h> -#include <stddef.h> #include <soc/addressmap.h> #include <soc/clock.h> #include <soc/edp.h> diff --git a/src/soc/rockchip/rk3288/display.c b/src/soc/rockchip/rk3288/display.c index a66b2d4..98cab05 100644 --- a/src/soc/rockchip/rk3288/display.c +++ b/src/soc/rockchip/rk3288/display.c @@ -20,7 +20,6 @@ #include <delay.h> #include <edid.h> #include <gpio.h> -#include <stddef.h> #include <string.h> #include <soc/addressmap.h> #include <soc/clock.h> diff --git a/src/soc/rockchip/rk3288/soc.c b/src/soc/rockchip/rk3288/soc.c index 31c9998..6477d65 100644 --- a/src/soc/rockchip/rk3288/soc.c +++ b/src/soc/rockchip/rk3288/soc.c @@ -21,7 +21,6 @@ #include <soc/display.h> #include <soc/soc.h> #include <soc/sdram.h> -#include <stddef.h> #include <symbols.h> #include "chip.h" diff --git a/src/soc/rockchip/rk3399/display.c b/src/soc/rockchip/rk3399/display.c index 9cd4053..d1f07af 100644 --- a/src/soc/rockchip/rk3399/display.c +++ b/src/soc/rockchip/rk3399/display.c @@ -21,7 +21,6 @@ #include <delay.h> #include <edid.h> #include <gpio.h> -#include <stddef.h> #include <soc/addressmap.h> #include <soc/clock.h> #include <soc/display.h> diff --git a/src/soc/rockchip/rk3399/soc.c b/src/soc/rockchip/rk3399/soc.c index 807a7bc..df62bc7 100644 --- a/src/soc/rockchip/rk3399/soc.c +++ b/src/soc/rockchip/rk3399/soc.c @@ -22,7 +22,6 @@ #include <soc/display.h> #include <soc/sdram.h> #include <soc/symbols.h> -#include <stddef.h> #include <symbols.h> void bootmem_platform_add_ranges(void) diff --git a/src/soc/samsung/exynos5250/cbmem.c b/src/soc/samsung/exynos5250/cbmem.c index 31463b1..60e454c 100644 --- a/src/soc/samsung/exynos5250/cbmem.c +++ b/src/soc/samsung/exynos5250/cbmem.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <stddef.h> #include <cbmem.h> #include <soc/cpu.h> diff --git a/src/soc/samsung/exynos5250/cpu.c b/src/soc/samsung/exynos5250/cpu.c index 5f99899..cf721cd 100644 --- a/src/soc/samsung/exynos5250/cpu.c +++ b/src/soc/samsung/exynos5250/cpu.c @@ -22,7 +22,6 @@ #include <soc/cpu.h> #include <soc/dp-core.h> #include <soc/fimd.h> -#include <stddef.h> #include <string.h> #include "chip.h" diff --git a/src/soc/samsung/exynos5420/cbmem.c b/src/soc/samsung/exynos5420/cbmem.c index ffed589e..60e454c 100644 --- a/src/soc/samsung/exynos5420/cbmem.c +++ b/src/soc/samsung/exynos5420/cbmem.c @@ -15,7 +15,6 @@ #include <cbmem.h> #include <soc/cpu.h> -#include <stddef.h> void *cbmem_top_chipset(void) { diff --git a/src/soc/samsung/exynos5420/cpu.c b/src/soc/samsung/exynos5420/cpu.c index 375b370..2758549 100644 --- a/src/soc/samsung/exynos5420/cpu.c +++ b/src/soc/samsung/exynos5420/cpu.c @@ -23,7 +23,6 @@ #include <soc/fimd.h> #include <soc/cpu.h> #include <soc/clk.h> -#include <stddef.h> #include <string.h> #include "chip.h" diff --git a/src/soc/samsung/exynos5420/i2c.c b/src/soc/samsung/exynos5420/i2c.c index 4dd9caa..5af868d 100644 --- a/src/soc/samsung/exynos5420/i2c.c +++ b/src/soc/samsung/exynos5420/i2c.c @@ -23,7 +23,6 @@ #include <soc/i2c.h> #include <soc/periph.h> #include <soc/pinmux.h> -#include <stddef.h> #include <timer.h> struct __packed i2c_regs diff --git a/src/soc/sifive/fu540/otp.c b/src/soc/sifive/fu540/otp.c index 10647f4..eae530b 100644 --- a/src/soc/sifive/fu540/otp.c +++ b/src/soc/sifive/fu540/otp.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <stddef.h> #include <delay.h> #include <device/mmio.h> #include <console/console.h> diff --git a/src/soc/sifive/fu540/uart.c b/src/soc/sifive/fu540/uart.c index b59b789..2100f56 100644 --- a/src/soc/sifive/fu540/uart.c +++ b/src/soc/sifive/fu540/uart.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <stddef.h> #include <stdint.h> #include <console/uart.h> #include <soc/addressmap.h> diff --git a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h index 7ea2caa..bb9ed25 100644 --- a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h +++ b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h @@ -20,7 +20,6 @@ #ifndef _AMD_SBPLATFORM_H_ #define _AMD_SBPLATFORM_H_ -#include <stddef.h> typedef unsigned long long PLACEHOLDER; diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 92dd02e..385b897 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -25,7 +25,6 @@ #include <device/pci_ops.h> #include "pch.h" #include <southbridge/intel/common/gpio.h> -#include <stddef.h> #include <stdint.h> #include "chip.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/37414 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I64d0d63a93b625e9792790c93b07851e4491ab34 Gerrit-Change-Number: 37414 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: mb/ibase/mb899: Reformat code
by HAOUAS Elyes (Code Review) Jan. 7, 2020

Jan. 7, 2020

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38127 ) Change subject: mb/ibase/mb899: Reformat code ...................................................................... mb/ibase/mb899: Reformat code Change-Id: Ic8c131b8dc6308ed813820f67477d157ccea5b05 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/ibase/mb899/early_init.c M src/mainboard/ibase/mb899/mainboard.c M src/mainboard/ibase/mb899/superio_hwm.c 3 files changed, 50 insertions(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/38127/1 diff --git a/src/mainboard/ibase/mb899/early_init.c b/src/mainboard/ibase/mb899/early_init.c index fd96f66..997cf04 100644 --- a/src/mainboard/ibase/mb899/early_init.c +++ b/src/mainboard/ibase/mb899/early_init.c @@ -14,12 +14,12 @@ */ #include <bootblock_common.h> -#include <stdint.h> -#include <device/pnp_ops.h> #include <cpu/x86/lapic.h> #include <device/pnp_def.h> +#include <device/pnp_ops.h> #include <northbridge/intel/i945/i945.h> #include <southbridge/intel/i82801gx/i82801gx.h> +#include <stdint.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627ehg/w83627ehg.h> @@ -65,7 +65,7 @@ pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0x60); pnp_set_iobase(dev, PNP_IDX_IO1, 0x64); - //pnp_write_config(dev, 0xf0, 0x82); + // pnp_write_config(dev, 0xf0, 0x82); pnp_set_enable(dev, 1); dev = PNP_DEV(0x4e, W83627EHG_GPIO2); diff --git a/src/mainboard/ibase/mb899/mainboard.c b/src/mainboard/ibase/mb899/mainboard.c index d4d05c3..ada5fa3 100644 --- a/src/mainboard/ibase/mb899/mainboard.c +++ b/src/mainboard/ibase/mb899/mainboard.c @@ -15,6 +15,7 @@ #include <device/device.h> #include <drivers/intel/gma/int15.h> + #include "superio_hwm.h" // mainboard_enable is executed as first thing after @@ -22,7 +23,9 @@ static void mainboard_enable(struct device *dev) { - install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 3); + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 3); hwm_setup(); } diff --git a/src/mainboard/ibase/mb899/superio_hwm.c b/src/mainboard/ibase/mb899/superio_hwm.c index 175c9a0..3bf3314 100644 --- a/src/mainboard/ibase/mb899/superio_hwm.c +++ b/src/mainboard/ibase/mb899/superio_hwm.c @@ -14,22 +14,22 @@ * GNU General Public License for more details. */ -#include <types.h> #include <console/console.h> #include <device/device.h> #include <pc80/mc146818rtc.h> #include <superio/hwm5_conf.h> #include <superio/nuvoton/common/hwm.h> +#include <types.h> #include "superio_hwm.h" /* Hardware Monitor */ -#define FAN_CRUISE_CONTROL_DISABLED 0 -#define FAN_CRUISE_CONTROL_SPEED 1 -#define FAN_CRUISE_CONTROL_THERMAL 2 +#define FAN_CRUISE_CONTROL_DISABLED 0 +#define FAN_CRUISE_CONTROL_SPEED 1 +#define FAN_CRUISE_CONTROL_THERMAL 2 -#define FAN_SPEED_5625 0 +#define FAN_SPEED_5625 0 //#define FAN_TEMPERATURE_30DEGC 0 #define HWM_BASE 0x290 @@ -42,11 +42,11 @@ // FANIN Target Speed Register // FANIN = 337500 / RPM struct fan_speed fan_speeds[] = { - { 0x3c, 5625 }, { 0x41, 5192 }, { 0x47, 4753 }, { 0x4e, 4326 }, - { 0x56, 3924 }, { 0x5f, 3552 }, { 0x69, 3214 }, { 0x74, 2909 }, - { 0x80, 2636 }, { 0x8d, 2393 }, { 0x9b, 2177 }, { 0xaa, 1985 }, - { 0xba, 1814 }, { 0xcb, 1662 }, { 0xdd, 1527 }, { 0xf0, 1406 } -}; + {0x3c, 5625}, {0x41, 5192}, {0x47, 4753}, {0x4e, 4326}, + {0x56, 3924}, {0x5f, 3552}, {0x69, 3214}, {0x74, 2909}, + {0x80, 2636}, {0x8d, 2393}, {0x9b, 2177}, {0xaa, 1985}, + {0xba, 1814}, {0xcb, 1662}, {0xdd, 1527}, {0xf0, 1406} + }; struct temperature { u8 deg_celsius; @@ -54,11 +54,11 @@ }; struct temperature temperatures[] = { - { 30, 86 }, { 33, 91 }, { 36, 96 }, { 39, 102 }, - { 42, 107 }, { 45, 113 }, { 48, 118 }, { 51, 123 }, - { 54, 129 }, { 57, 134 }, { 60, 140 }, { 63, 145 }, - { 66, 150 }, { 69, 156 }, { 72, 161 }, { 75, 167 } -}; + {30, 86}, {33, 91}, {36, 96}, {39, 102}, + {42, 107}, {45, 113}, {48, 118}, {51, 123}, + {54, 129}, {57, 134}, {60, 140}, {63, 145}, + {66, 150}, {69, 156}, {72, 161}, {75, 167} + }; void hwm_setup(void) { @@ -70,15 +70,15 @@ get_option(&cpufan_control, "cpufan_cruise_control"); cpufan_speed = FAN_SPEED_5625; get_option(&cpufan_speed, "cpufan_speed"); - //cpufan_temperature = FAN_TEMPERATURE_30DEGC; - //get_option(&cpufan_temperature, "cpufan_temperature"); + // cpufan_temperature = FAN_TEMPERATURE_30DEGC; + // get_option(&cpufan_temperature, "cpufan_temperature"); sysfan_control = FAN_CRUISE_CONTROL_DISABLED; get_option(&sysfan_control, "sysfan_cruise_control"); sysfan_speed = FAN_SPEED_5625; get_option(&sysfan_speed, "sysfan_speed"); - //sysfan_temperature = FAN_TEMPERATURE_30DEGC; - //get_option(&sysfan_temperature, "sysfan_temperature"); + // sysfan_temperature = FAN_TEMPERATURE_30DEGC; + // get_option(&sysfan_temperature, "sysfan_temperature"); // pnp_write_hwm5_index(HWM_BASE, 0x31, 0x20); // AVCC high limit // pnp_write_hwm5_index(HWM_BASE, 0x34, 0x06); // VIN2 low limit @@ -99,12 +99,20 @@ // 01 FANOUT is Thermal Cruise Mode // 10 FANOUT is Fan Speed Cruise Mode switch (cpufan_control) { - case FAN_CRUISE_CONTROL_SPEED: fan_config |= (2 << 4); break; - case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 4); break; + case FAN_CRUISE_CONTROL_SPEED: + fan_config |= (2 << 4); + break; + case FAN_CRUISE_CONTROL_THERMAL: + fan_config |= (1 << 4); + break; } switch (sysfan_control) { - case FAN_CRUISE_CONTROL_SPEED: fan_config |= (2 << 2); break; - case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 2); break; + case FAN_CRUISE_CONTROL_SPEED: + fan_config |= (2 << 2); + break; + case FAN_CRUISE_CONTROL_THERMAL: + fan_config |= (1 << 2); + break; } // This register must be written first pnp_write_hwm5_index(HWM_BASE, 0x04, fan_config); @@ -112,13 +120,14 @@ switch (cpufan_control) { case FAN_CRUISE_CONTROL_SPEED: /* CPUFANIN target speed */ printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to %d RPM\n", - fan_speeds[cpufan_speed].fan_speed); + fan_speeds[cpufan_speed].fan_speed); pnp_write_hwm5_index(HWM_BASE, 0x06, fan_speeds[cpufan_speed].fan_in); break; case FAN_CRUISE_CONTROL_THERMAL: /* CPUFANIN target temperature */ - printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to activation at %d deg C/%d deg F\n", - temperatures[cpufan_temperature].deg_celsius, - temperatures[cpufan_temperature].deg_fahrenheit); + printk(BIOS_DEBUG, + "Fan Cruise Control setting CPU fan to activation at %d deg C/%d deg F\n", + temperatures[cpufan_temperature].deg_celsius, + temperatures[cpufan_temperature].deg_fahrenheit); pnp_write_hwm5_index(HWM_BASE, 0x06, temperatures[cpufan_temperature].deg_celsius); break; @@ -127,15 +136,16 @@ switch (sysfan_control) { case FAN_CRUISE_CONTROL_SPEED: /* SYSFANIN target speed */ printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to %d RPM\n", - fan_speeds[sysfan_speed].fan_speed); + fan_speeds[sysfan_speed].fan_speed); pnp_write_hwm5_index(HWM_BASE, 0x05, fan_speeds[sysfan_speed].fan_in); break; case FAN_CRUISE_CONTROL_THERMAL: /* SYSFANIN target temperature */ - printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to activation at %d deg C/%d deg F\n", - temperatures[sysfan_temperature].deg_celsius, - temperatures[sysfan_temperature].deg_fahrenheit); - pnp_write_hwm5_index(HWM_BASE, - 0x05, temperatures[sysfan_temperature].deg_celsius); + printk(BIOS_DEBUG, + "Fan Cruise Control setting system fan to activation at %d deg C/%d deg F\n", + temperatures[sysfan_temperature].deg_celsius, + temperatures[sysfan_temperature].deg_fahrenheit); + pnp_write_hwm5_index(HWM_BASE, 0x05, + temperatures[sysfan_temperature].deg_celsius); break; } -- To view, visit https://review.coreboot.org/c/coreboot/+/38127 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8c131b8dc6308ed813820f67477d157ccea5b05 Gerrit-Change-Number: 38127 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: device/dram/ddr2.c: Code re-formating
by HAOUAS Elyes (Code Review) Jan. 7, 2020

Jan. 7, 2020

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36858 ) Change subject: device/dram/ddr2.c: Code re-formating ...................................................................... device/dram/ddr2.c: Code re-formating Change-Id: I937aadca21ddaa9ab4ae354c3a1324a222ae0ff6 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/device/dram/ddr2.c 1 file changed, 47 insertions(+), 73 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/36858/1 diff --git a/src/device/dram/ddr2.c b/src/device/dram/ddr2.c index 5319806..299a590 100644 --- a/src/device/dram/ddr2.c +++ b/src/device/dram/ddr2.c @@ -12,7 +12,7 @@ * GNU General Public License for more details. */ -/** +/* * @file ddr2.c * * \brief Utilities for decoding DDR2 SPDs @@ -29,7 +29,7 @@ * = DDR2 SPD decoding helpers *----------------------------------------------------------------------------*/ -/** +/* * \brief Checks if the DIMM is Registered based on byte[20] of the SPD * * Tells if the DIMM type is registered or not. @@ -38,15 +38,15 @@ */ int spd_dimm_is_registered_ddr2(enum spd_dimm_type_ddr2 type) { - if ((type == SPD_DDR2_DIMM_TYPE_RDIMM) - || (type == SPD_DDR2_DIMM_TYPE_72B_SO_RDIMM) - || (type == SPD_DDR2_DIMM_TYPE_MINI_RDIMM)) + if ((type == SPD_DDR2_DIMM_TYPE_RDIMM) || + (type == SPD_DDR2_DIMM_TYPE_72B_SO_RDIMM) || + (type == SPD_DDR2_DIMM_TYPE_MINI_RDIMM)) return 1; return 0; } -/** +/* * \brief Calculate the checksum of a DDR2 SPD unique identifier * * @param spd pointer to raw SPD data @@ -69,7 +69,7 @@ return c; } -/** +/* * \brief Calculate the CRC of a DDR2 SPD unique identifier * * @param spd pointer to raw SPD data @@ -93,7 +93,7 @@ return ddr_crc16(id_bytes, 15); } -/** +/* * \brief Return size of SPD. * * Returns size of SPD. Usually 128 Byte. @@ -103,7 +103,7 @@ return MIN(byte0, SPD_SIZE_MAX_DDR2); } -/** +/* * \brief Return size of eeprom. * * Returns size of eeprom. Usually 256 Byte. @@ -119,7 +119,7 @@ return 1 << byte1; } -/** +/* * \brief Return index of MSB set * * Returns the index of MSB set. @@ -129,7 +129,7 @@ return log2(c); } -/** +/* * \brief Decode SPD tck cycle time * * Decodes a raw SPD data from a DDR2 DIMM. @@ -156,8 +156,7 @@ break; case 0xe: case 0xf: - printk(BIOS_WARNING, "Invalid tck setting. " - "lower nibble is 0x%x\n", c & 0xf); + printk(BIOS_WARNING, "Invalid tck setting. lower nibble is 0x%x\n", c & 0xf); return CB_ERR; default: low = (c & 0xf) * 10; @@ -167,7 +166,7 @@ return CB_SUCCESS; } -/** +/* * \brief Decode SPD bcd style timings * * Decodes a raw SPD data from a DDR2 DIMM. @@ -186,7 +185,7 @@ return CB_SUCCESS; } -/** +/* * \brief Decode SPD tRP, tRRP cycle time * * Decodes a raw SPD data from a DDR2 DIMM. @@ -202,7 +201,7 @@ return ((high * 100 + low) << 8) / 100; } -/** +/* * \brief Decode SPD tRR time * * Decodes a raw SPD data from a DDR2 DIMM. @@ -236,7 +235,7 @@ return CB_SUCCESS; } -/** +/* * \brief Decode SPD tRC,tRFC time * * Decodes a raw SPD data from a DDR2 DIMM. @@ -301,7 +300,7 @@ *tRFC = (*tRFC << 8) / 100; } -/** +/* * \brief Decode the raw SPD data * * Decodes a raw SPD data from a DDR2 DIMM, and organizes it into a @@ -348,9 +347,8 @@ reg8 = spd[62]; if ((reg8 & 0xf0) != 0x10) { - printk(BIOS_WARNING, - "ERROR: Unsupported SPD revision %01x.%01x\n", - reg8 >> 4, reg8 & 0xf); + printk(BIOS_WARNING, "ERROR: Unsupported SPD revision %01x.%01x\n", reg8 >> 4, + reg8 & 0xf); dimm->dram_type = SPD_MEMORY_TYPE_UNDEFINED; return SPD_STATUS_INVALID; } @@ -368,18 +366,15 @@ dimm->row_bits = spd[3]; printram(" Rows : %u\n", dimm->row_bits); - if ((dimm->row_bits > 31) || - ((dimm->row_bits > 15) && (dimm->rev < 0x13))) { - printk(BIOS_WARNING, - "SPD decode: invalid number of memory rows\n"); + if ((dimm->row_bits > 31) || ((dimm->row_bits > 15) && (dimm->rev < 0x13))) { + printk(BIOS_WARNING, "SPD decode: invalid number of memory rows\n"); ret = SPD_STATUS_INVALID_FIELD; } dimm->col_bits = spd[4]; printram(" Columns : %u\n", dimm->col_bits); if (dimm->col_bits > 15) { - printk(BIOS_WARNING, - "SPD decode: invalid number of memory columns\n"); + printk(BIOS_WARNING, "SPD decode: invalid number of memory columns\n"); ret = SPD_STATUS_INVALID_FIELD; } @@ -403,8 +398,7 @@ dimm->banks = spd[17]; printram(" Banks : %u\n", dimm->banks); if (!dimm->banks) { - printk(BIOS_WARNING, - "SPD decode: invalid module banks count\n"); + printk(BIOS_WARNING, "SPD decode: invalid module banks count\n"); ret = SPD_STATUS_INVALID_FIELD; } @@ -440,20 +434,17 @@ dimm->cas_supported = spd[18]; if ((dimm->cas_supported & 0x3) || !dimm->cas_supported) { - printk(BIOS_WARNING, - "SPD decode: invalid CAS support advertised.\n"); + printk(BIOS_WARNING, "SPD decode: invalid CAS support advertised.\n"); ret = SPD_STATUS_INVALID_FIELD; } printram(" Supported CAS mask : 0x%x\n", dimm->cas_supported); if ((dimm->rev < 0x13) && (dimm->cas_supported & 0x80)) { - printk(BIOS_WARNING, - "SPD decode: invalid CAS support advertised.\n"); + printk(BIOS_WARNING, "SPD decode: invalid CAS support advertised.\n"); ret = SPD_STATUS_INVALID_FIELD; } if ((dimm->rev < 0x12) && (dimm->cas_supported & 0x40)) { - printk(BIOS_WARNING, - "SPD decode: invalid CAS support advertised.\n"); + printk(BIOS_WARNING, "SPD decode: invalid CAS support advertised.\n"); ret = SPD_STATUS_INVALID_FIELD; } @@ -462,59 +453,43 @@ /* SDRAM Cycle time at Maximum Supported CAS Latency (CL), CL=X */ if (spd_decode_tck_time(&dimm->cycle_time[cl], spd[9]) != CB_SUCCESS) { - printk(BIOS_WARNING, - "SPD decode: invalid min tCL for CAS%d\n", cl); + printk(BIOS_WARNING, "SPD decode: invalid min tCL for CAS%d\n", cl); ret = SPD_STATUS_INVALID_FIELD; } /* SDRAM Access from Clock */ - if (spd_decode_bcd_time(&dimm->access_time[cl], spd[10]) - != CB_SUCCESS) { - printk(BIOS_WARNING, - "SPD decode: invalid min tAC for CAS%d\n", cl); + if (spd_decode_bcd_time(&dimm->access_time[cl], spd[10]) != CB_SUCCESS) { + printk(BIOS_WARNING, "SPD decode: invalid min tAC for CAS%d\n", cl); ret = SPD_STATUS_INVALID_FIELD; } if (dimm->cas_supported & (1 << (cl - 1))) { /* Minimum Clock Cycle at CLX-1 */ - if (spd_decode_tck_time(&dimm->cycle_time[cl - 1], spd[23]) - != CB_SUCCESS) { - printk(BIOS_WARNING, - "SPD decode: invalid min tCL for CAS%d\n", - cl - 1); + if (spd_decode_tck_time(&dimm->cycle_time[cl - 1], spd[23]) != CB_SUCCESS) { + printk(BIOS_WARNING, "SPD decode: invalid min tCL for CAS%d\n", cl - 1); ret = SPD_STATUS_INVALID_FIELD; } /* Maximum Data Access Time (tAC) from Clock at CLX-1 */ - if (spd_decode_bcd_time(&dimm->access_time[cl - 1], spd[24]) - != CB_SUCCESS) { - printk(BIOS_WARNING, - "SPD decode: invalid min tAC for CAS%d\n", - cl - 1); + if (spd_decode_bcd_time(&dimm->access_time[cl - 1], spd[24]) != CB_SUCCESS) { + printk(BIOS_WARNING, "SPD decode: invalid min tAC for CAS%d\n", cl - 1); ret = SPD_STATUS_INVALID_FIELD; } } if (dimm->cas_supported & (1 << (cl - 2))) { /* Minimum Clock Cycle at CLX-2 */ - if (spd_decode_tck_time(&dimm->cycle_time[cl - 2], spd[25]) - != CB_SUCCESS) { - printk(BIOS_WARNING, - "SPD decode: invalid min tCL for CAS%d\n", - cl - 2); + if (spd_decode_tck_time(&dimm->cycle_time[cl - 2], spd[25]) != CB_SUCCESS) { + printk(BIOS_WARNING, "SPD decode: invalid min tCL for CAS%d\n", cl - 2); ret = SPD_STATUS_INVALID_FIELD; } /* Maximum Data Access Time (tAC) from Clock at CLX-2 */ - if (spd_decode_bcd_time(&dimm->access_time[cl - 2], spd[26]) - != CB_SUCCESS) { - printk(BIOS_WARNING, - "SPD decode: invalid min tAC for CAS%d\n", - cl - 2); + if (spd_decode_bcd_time(&dimm->access_time[cl - 2], spd[26]) != CB_SUCCESS) { + printk(BIOS_WARNING, "SPD decode: invalid min tAC for CAS%d\n", cl - 2); ret = SPD_STATUS_INVALID_FIELD; } } reg8 = (spd[31] >> 5) | (spd[31] << 3); if (!reg8) { - printk(BIOS_WARNING, - "SPD decode: invalid rank density.\n"); + printk(BIOS_WARNING, "SPD decode: invalid rank density.\n"); ret = SPD_STATUS_INVALID_FIELD; } @@ -611,8 +586,7 @@ printram(" ECC support : %x\n", dimm->flags.is_ecc); dimm->flags.stacked = !!(spd[5] & 0x10); - printram(" Package : %s\n", - dimm->flags.stacked ? "stack" : "planar"); + printram(" Package : %s\n", dimm->flags.stacked ? "stack" : "planar"); if (spd_size > 71) { memcpy(&dimm->manufacturer_id, &spd[64], 4); @@ -662,14 +636,14 @@ printk(BIOS_INFO, "%s%3u.%.3u us\n", msg, mant, fp); } -/** -* \brief Print the info in DIMM -* -* Print info about the DIMM. Useful to use when CONFIG_DEBUG_RAM_SETUP is -* selected, or for a purely informative output. -* -* @param dimm pointer to already decoded @ref dimm_attr structure -*/ +/* + * \brief Print the info in DIMM + * + * Print info about the DIMM. Useful to use when CONFIG_DEBUG_RAM_SETUP is + * selected, or for a purely informative output. + * + * @param dimm pointer to already decoded @ref dimm_attr structure + */ void dram_print_spd_ddr2(const struct dimm_attr_ddr2_st *dimm) { char buf[32]; -- To view, visit https://review.coreboot.org/c/coreboot/+/36858 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I937aadca21ddaa9ab4ae354c3a1324a222ae0ff6 Gerrit-Change-Number: 36858 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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