coreboot-gerrit January 2020

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Change in coreboot[master]: soc/intel/common/block/cse: Add boot partition related APIs
by Sridhar Siricilla (Code Review) 07 Jan '20

07 Jan '20

Hello Patrick Rudolph, Subrata Banik, Balaji Manigandan, Aamir Bohra, Sridhar Siricilla, Rizwan Qureshi, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, V Sowmya, Nico Huber, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35402 to look at the new patch set (#45). Change subject: soc/intel/common/block/cse: Add boot partition related APIs ...................................................................... soc/intel/common/block/cse: Add boot partition related APIs The CSE region is logically divided into 3 boot partitions when redundancy is enabled. These boot partitions are represented by BP1, BP2 and BP3. In chrome platforms, CSE can boot from either BP1 or BP2. The CSE image layout appears as below.. ------------- ------------------ -------------------------- |CSE REGION | => | RO | RW | => | BP1 | BP2 + BP3 + DATA | ------------- ------------------ -------------------------- In order to support CSE FW update to RW region, below APIs help coreboot to get info about the boot partitions, and allows coreboot to set CSE to boot from required boot partition (either BP1(RO) or BP2). GET_BOOT_PARTITION_INFO - provides info on available partitions in the CSE region. The API provides info on boot partitions like start/end offsets of a partition within CSE region, and their version and partition status. SET_BOOT_PARTITION_INFO - Sets the next boot partition to boot for CSE. With the HECI API, firmware can notify CSE to boot from BP1 or BP2 on next boot. BUG=b:145809764 Change-Id: Iaa62409c0616d5913d21374a8a6804f82258eb4f Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- M src/soc/intel/common/block/cse/Makefile.inc A src/soc/intel/common/block/cse/cse_bp.c M src/soc/intel/common/block/include/intelblocks/cse.h 3 files changed, 489 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/35402/45 -- To view, visit https://review.coreboot.org/c/coreboot/+/35402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa62409c0616d5913d21374a8a6804f82258eb4f Gerrit-Change-Number: 35402 Gerrit-PatchSet: 45 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <anpetrov(a)fb.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/block/cse: Minor clean up some late comments
by Sridhar Siricilla (Code Review) 07 Jan '20

07 Jan '20

Sridhar Siricilla has uploaded a new patch set (#15) to the change originally created by Rizwan Qureshi. ( https://review.coreboot.org/c/coreboot/+/35546 ) Change subject: soc/intel/common/block/cse: Minor clean up some late comments ...................................................................... soc/intel/common/block/cse: Minor clean up some late comments Made some changes based on comments received on merged patches. * Fix up HFSTS1 inconsistency between APL/GKL and rest of the platforms. TEST=Build and Boot hatch board. Change-Id: If7ea6043d7b5473d0c16e83d7b2d4b620c125652 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- M src/soc/intel/common/block/include/intelblocks/cse.h 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/35546/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/35546 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7ea6043d7b5473d0c16e83d7b2d4b620c125652 Gerrit-Change-Number: 35546 Gerrit-PatchSet: 15 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <riz.pro(a)gmail.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/pc80/rtc: Refactor some USE_OPTION_TABLE
by Kyösti Mälkki (Code Review) 07 Jan '20

07 Jan '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38183 ) Change subject: drivers/pc80/rtc: Refactor some USE_OPTION_TABLE ...................................................................... drivers/pc80/rtc: Refactor some USE_OPTION_TABLE Change-Id: I3a5004db021af6127de2f058bec9d84a985bae67 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/drivers/pc80/rtc/mc146818rtc_boot.c M src/include/pc80/mc146818rtc.h 2 files changed, 4 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/38183/1 diff --git a/src/drivers/pc80/rtc/mc146818rtc_boot.c b/src/drivers/pc80/rtc/mc146818rtc_boot.c index fd0095e..c009d67 100644 --- a/src/drivers/pc80/rtc/mc146818rtc_boot.c +++ b/src/drivers/pc80/rtc/mc146818rtc_boot.c @@ -16,13 +16,12 @@ #include <option.h> #include <pc80/mc146818rtc.h> #include <fallback.h> + #if CONFIG(USE_OPTION_TABLE) #include <option_table.h> -#endif -int cmos_chksum_valid(void) +static int cmos_chksum_valid(void) { -#if CONFIG(USE_OPTION_TABLE) unsigned char addr; u16 sum, old_sum; @@ -36,9 +35,6 @@ old_sum |= cmos_read(LB_CKS_LOC + 1); return sum == old_sum; -#else - return 0; -#endif } void sanitize_cmos(void) @@ -58,6 +54,7 @@ } } } +#endif #if CONFIG_MAX_REBOOT_CNT > 15 #error "CONFIG_MAX_REBOOT_CNT too high" @@ -87,7 +84,7 @@ { unsigned char byte; - if (cmos_error() || !cmos_chksum_valid()) { + if (!CONFIG(USE_OPTION_TABLE) || cmos_error() || !cmos_chksum_valid()) { /* Invalid CMOS checksum detected! * Force fallback boot... */ diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h index e3bd63a..b064461 100644 --- a/src/include/pc80/mc146818rtc.h +++ b/src/include/pc80/mc146818rtc.h @@ -176,7 +176,6 @@ void cmos_init(bool invalid); void cmos_check_update_date(void); int cmos_error(void); -int cmos_chksum_valid(void); enum cb_err set_option(const char *name, void *val); enum cb_err get_option(void *dest, const char *name); -- To view, visit https://review.coreboot.org/c/coreboot/+/38183 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a5004db021af6127de2f058bec9d84a985bae67 Gerrit-Change-Number: 38183 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/pc80/rtc: Refactor clear_cmos variable
by Kyösti Mälkki (Code Review) 07 Jan '20

07 Jan '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38185 ) Change subject: drivers/pc80/rtc: Refactor clear_cmos variable ...................................................................... drivers/pc80/rtc: Refactor clear_cmos variable After refactoring it is more a status variable rather than a request. Change-Id: I50b8099a08b556129416cea50f0ce6fafe6c14cc Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/drivers/pc80/rtc/mc146818rtc.c 1 file changed, 6 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/38185/1 diff --git a/src/drivers/pc80/rtc/mc146818rtc.c b/src/drivers/pc80/rtc/mc146818rtc.c index f151910..c8ba568 100644 --- a/src/drivers/pc80/rtc/mc146818rtc.c +++ b/src/drivers/pc80/rtc/mc146818rtc.c @@ -96,7 +96,7 @@ { bool cmos_invalid; bool checksum_invalid = false; - bool clear_cmos; + bool cleared_cmos = false; size_t i; uint8_t x; @@ -119,22 +119,19 @@ /* See if there is a CMOS checksum error */ checksum_invalid = !cmos_checksum_valid(PC_CKS_RANGE_START, PC_CKS_RANGE_END, PC_CKS_LOC); - - clear_cmos = false; - } else { - clear_cmos = true; } if (cmos_invalid || invalid) cmos_write(cmos_read(RTC_CONTROL) | RTC_SET, RTC_CONTROL); if (invalid || cmos_invalid || checksum_invalid) { - if (clear_cmos) { + if (!CONFIG(USE_OPTION_TABLE)) { cmos_write(0, 0x01); cmos_write(0, 0x03); cmos_write(0, 0x05); for (i = 10; i < 128; i++) cmos_write(0, i); + cleared_cmos = true; } if (cmos_invalid || invalid) @@ -144,9 +141,8 @@ invalid ? " Clear requested":"", cmos_invalid ? " Power Problem":"", checksum_invalid ? " Checksum invalid":"", - clear_cmos ? " zeroing cmos":""); - } else - clear_cmos = false; + cleared_cmos ? " zeroing cmos":""); + } /* Setup the real time clock */ cmos_write(RTC_CONTROL_DEFAULT, RTC_CONTROL); @@ -169,7 +165,7 @@ /* Clear any pending interrupts */ cmos_read(RTC_INTR_FLAGS); - return clear_cmos; + return cleared_cmos; } static void cmos_init_vbnv(bool invalid) -- To view, visit https://review.coreboot.org/c/coreboot/+/38185 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50b8099a08b556129416cea50f0ce6fafe6c14cc Gerrit-Change-Number: 38185 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/pc80/rtc: Remove stub for sanitize_cmos()
by Kyösti Mälkki (Code Review) 07 Jan '20

07 Jan '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38182 ) Change subject: drivers/pc80/rtc: Remove stub for sanitize_cmos() ...................................................................... drivers/pc80/rtc: Remove stub for sanitize_cmos() We only have a single call-site for this. Change-Id: I7ab19c6ea4ef01334f4d229c5636b64f99c86119 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/drivers/pc80/rtc/mc146818rtc_boot.c M src/include/option.h M src/include/pc80/mc146818rtc.h M src/lib/bootblock.c 4 files changed, 21 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/38182/1 diff --git a/src/drivers/pc80/rtc/mc146818rtc_boot.c b/src/drivers/pc80/rtc/mc146818rtc_boot.c index c2ab707..fd0095e 100644 --- a/src/drivers/pc80/rtc/mc146818rtc_boot.c +++ b/src/drivers/pc80/rtc/mc146818rtc_boot.c @@ -13,6 +13,7 @@ #include <stdint.h> #include <cbfs.h> +#include <option.h> #include <pc80/mc146818rtc.h> #include <fallback.h> #if CONFIG(USE_OPTION_TABLE) @@ -40,7 +41,6 @@ #endif } -#if CONFIG(USE_OPTION_TABLE) void sanitize_cmos(void) { if (cmos_error() || !cmos_chksum_valid() || @@ -58,7 +58,6 @@ } } } -#endif #if CONFIG_MAX_REBOOT_CNT > 15 #error "CONFIG_MAX_REBOOT_CNT too high" diff --git a/src/include/option.h b/src/include/option.h index 3a20dcf..7afedac 100644 --- a/src/include/option.h +++ b/src/include/option.h @@ -1,6 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + #ifndef _OPTION_H_ #define _OPTION_H_ +#include <types.h> + +void sanitize_cmos(void); + /* * FIXME: get_option() needs to be abstracted better so that other non-volatile * storage can be used. This will benefit machines without CMOS as well as those @@ -9,7 +26,6 @@ #if CONFIG(USE_OPTION_TABLE) #include <pc80/mc146818rtc.h> #else -#include <types.h> static inline enum cb_err get_option(void *dest, const char *name) { return CB_CMOS_OTABLE_DISABLED; diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h index 6d12940..e3bd63a 100644 --- a/src/include/pc80/mc146818rtc.h +++ b/src/include/pc80/mc146818rtc.h @@ -215,14 +215,6 @@ static inline void cmos_post_log(void) {} #endif /* CONFIG_CMOS_POST */ -#if CONFIG(USE_OPTION_TABLE) -void sanitize_cmos(void); -#else -static inline void sanitize_cmos(void) {} -#endif /* CONFIG_USE_OPTION_TABLE */ - -#else /* !CONFIG_ARCH_X86 */ -static inline void sanitize_cmos(void) {} #endif /* CONFIG_ARCH_X86 */ void cmos_post_init(void); diff --git a/src/lib/bootblock.c b/src/lib/bootblock.c index 6d40bc0..386f4e3 100644 --- a/src/lib/bootblock.c +++ b/src/lib/bootblock.c @@ -18,6 +18,7 @@ #include <bootblock_common.h> #include <console/console.h> #include <delay.h> +#include <option.h> #include <pc80/mc146818rtc.h> #include <program_loading.h> #include <symbols.h> @@ -56,7 +57,8 @@ bootblock_soc_early_init(); bootblock_mainboard_early_init(); - sanitize_cmos(); + if (CONFIG(USE_OPTION_TABLE)) + sanitize_cmos(); if (CONFIG(CMOS_POST)) cmos_post_init(); -- To view, visit https://review.coreboot.org/c/coreboot/+/38182 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ab19c6ea4ef01334f4d229c5636b64f99c86119 Gerrit-Change-Number: 38182 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/pc80/rtc: Remove stub for cmos_post_init()
by Kyösti Mälkki (Code Review) 07 Jan '20

07 Jan '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38181 ) Change subject: drivers/pc80/rtc: Remove stub for cmos_post_init() ...................................................................... drivers/pc80/rtc: Remove stub for cmos_post_init() We only have a single call-site for this. Change-Id: Ia05a762691351b37cc59b39222fec737b29e913c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/include/pc80/mc146818rtc.h M src/lib/bootblock.c 2 files changed, 5 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/38181/1 diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h index 88c9cc2..6d12940 100644 --- a/src/include/pc80/mc146818rtc.h +++ b/src/include/pc80/mc146818rtc.h @@ -211,10 +211,8 @@ #define CMOS_POST_EXTRA_DEV_PATH 0x01 void cmos_post_log(void); -void cmos_post_init(void); #else static inline void cmos_post_log(void) {} -static inline void cmos_post_init(void) {} #endif /* CONFIG_CMOS_POST */ #if CONFIG(USE_OPTION_TABLE) @@ -224,8 +222,9 @@ #endif /* CONFIG_USE_OPTION_TABLE */ #else /* !CONFIG_ARCH_X86 */ -static inline void cmos_post_init(void) {} static inline void sanitize_cmos(void) {} #endif /* CONFIG_ARCH_X86 */ +void cmos_post_init(void); + #endif /* PC80_MC146818RTC_H */ diff --git a/src/lib/bootblock.c b/src/lib/bootblock.c index 5fb6067..6d40bc0 100644 --- a/src/lib/bootblock.c +++ b/src/lib/bootblock.c @@ -57,7 +57,9 @@ bootblock_mainboard_early_init(); sanitize_cmos(); - cmos_post_init(); + + if (CONFIG(CMOS_POST)) + cmos_post_init(); if (CONFIG(BOOTBLOCK_CONSOLE)) { console_init(); -- To view, visit https://review.coreboot.org/c/coreboot/+/38181 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia05a762691351b37cc59b39222fec737b29e913c Gerrit-Change-Number: 38181 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/pc80/rtc: Clean up some headers
by Kyösti Mälkki (Code Review) 07 Jan '20

07 Jan '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38180 ) Change subject: drivers/pc80/rtc: Clean up some headers ...................................................................... drivers/pc80/rtc: Clean up some headers Change-Id: I5b3f1da6581dd80264aaa9618227ac64e1966e8d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/bootblock_normal.c M src/include/fallback.h M src/include/pc80/mc146818rtc.h 3 files changed, 6 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/38180/1 diff --git a/src/arch/x86/bootblock_normal.c b/src/arch/x86/bootblock_normal.c index 8001ed0..b6b31af 100644 --- a/src/arch/x86/bootblock_normal.c +++ b/src/arch/x86/bootblock_normal.c @@ -12,7 +12,7 @@ */ #include <cbfs.h> -#include <pc80/mc146818rtc.h> +#include <fallback.h> #include <program_loading.h> #include <stddef.h> #include <string.h> diff --git a/src/include/fallback.h b/src/include/fallback.h index 3a7225e..1cf183f 100644 --- a/src/include/fallback.h +++ b/src/include/fallback.h @@ -1,13 +1,8 @@ #ifndef FALLBACK_H #define FALLBACK_H -#if !defined(__ASSEMBLER__) - void boot_successful(void); void set_boot_successful(void); - -#endif /* __ASSEMBLER__ */ - -#define RTC_BOOT_BYTE 48 +int do_normal_boot(void); #endif /* FALLBACK_H */ diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h index aadfae22..88c9cc2 100644 --- a/src/include/pc80/mc146818rtc.h +++ b/src/include/pc80/mc146818rtc.h @@ -25,8 +25,6 @@ **********************************************************************/ #define RTC_FREQ_SELECT RTC_REG_A -#define RTC_BOOT_NORMAL 0x1 - /* update-in-progress - set to "1" 244 microsecs before RTC goes off the bus, * reset after update (may take 1.984ms @ 32768Hz RefClock) is complete, * totaling to a max high interval of 2.228 ms. @@ -103,6 +101,10 @@ #define PC_CKS_RANGE_END 45 #define PC_CKS_LOC 46 +/* Tracking of fallback/normal boot. */ +#define RTC_BOOT_BYTE 48 +#define RTC_BOOT_NORMAL 0x1 + static inline unsigned char cmos_read(unsigned char addr) { int offs = 0; @@ -179,8 +181,6 @@ enum cb_err set_option(const char *name, void *val); enum cb_err get_option(void *dest, const char *name); -int do_normal_boot(void); - #if CONFIG(CMOS_POST) #if CONFIG(USE_OPTION_TABLE) # include "option_table.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/38180 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b3f1da6581dd80264aaa9618227ac64e1966e8d Gerrit-Change-Number: 38180 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/pc80/rtc: Clean up some inlined functions
by Kyösti Mälkki (Code Review) 07 Jan '20

07 Jan '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38179 ) Change subject: drivers/pc80/rtc: Clean up some inlined functions ...................................................................... drivers/pc80/rtc: Clean up some inlined functions Change-Id: Ie73797b4e9a09605a0685f0b03cb85e9a3be93ad Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/drivers/pc80/rtc/mc146818rtc.c M src/drivers/pc80/rtc/mc146818rtc_boot.c M src/include/pc80/mc146818rtc.h 3 files changed, 42 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/38179/1 diff --git a/src/drivers/pc80/rtc/mc146818rtc.c b/src/drivers/pc80/rtc/mc146818rtc.c index 2029b1e..f151910 100644 --- a/src/drivers/pc80/rtc/mc146818rtc.c +++ b/src/drivers/pc80/rtc/mc146818rtc.c @@ -81,6 +81,14 @@ cmos_write(((sum >> 0) & 0x0ff), cks_loc + 1); } +int cmos_error(void) +{ + unsigned char reg_d; + /* See if the cmos error condition has been flagged */ + reg_d = cmos_read(RTC_REG_D); + return (reg_d & RTC_VRT) == 0; +} + #define RTC_CONTROL_DEFAULT (RTC_24H) #define RTC_FREQ_SELECT_DEFAULT (RTC_REF_CLCK_32KHZ | RTC_RATE_1024HZ) @@ -406,6 +414,16 @@ return CB_SUCCESS; } +/* Upon return the caller is guaranteed 244 microseconds to complete any + * RTC operations. wait_uip may be called a single time prior to multiple + * accesses, but sequences requiring more time should call wait_uip again. + */ +static void wait_uip(void) +{ + while (cmos_read(RTC_REG_A) & RTC_UIP) + ; +} + /* * If the CMOS is cleared, the rtc_reg has the invalid date. That * hurts some OSes. Even if we don't set USE_OPTION_TABLE, we need diff --git a/src/drivers/pc80/rtc/mc146818rtc_boot.c b/src/drivers/pc80/rtc/mc146818rtc_boot.c index 3000946..c2ab707 100644 --- a/src/drivers/pc80/rtc/mc146818rtc_boot.c +++ b/src/drivers/pc80/rtc/mc146818rtc_boot.c @@ -19,14 +19,6 @@ #include <option_table.h> #endif -int cmos_error(void) -{ - unsigned char reg_d; - /* See if the cmos error condition has been flagged */ - reg_d = cmos_read(RTC_REG_D); - return (reg_d & RTC_VRT) == 0; -} - int cmos_chksum_valid(void) { #if CONFIG(USE_OPTION_TABLE) @@ -72,22 +64,22 @@ #error "CONFIG_MAX_REBOOT_CNT too high" #endif -static inline int boot_count(uint8_t rtc_byte) +static int boot_count(uint8_t rtc_byte) { return rtc_byte >> 4; } -static inline uint8_t increment_boot_count(uint8_t rtc_byte) +static uint8_t increment_boot_count(uint8_t rtc_byte) { return rtc_byte + (1 << 4); } -static inline uint8_t boot_set_fallback(uint8_t rtc_byte) +static uint8_t boot_set_fallback(uint8_t rtc_byte) { return rtc_byte & ~RTC_BOOT_NORMAL; } -static inline int boot_use_normal(uint8_t rtc_byte) +static int boot_use_normal(uint8_t rtc_byte) { return rtc_byte & RTC_BOOT_NORMAL; } diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h index a8221c7..aadfae22 100644 --- a/src/include/pc80/mc146818rtc.h +++ b/src/include/pc80/mc146818rtc.h @@ -114,16 +114,6 @@ return inb(RTC_BASE_PORT + offs + 1); } -/* Upon return the caller is guaranteed 244 microseconds to complete any - * RTC operations. wait_uip may be called a single time prior to multiple - * accesses, but sequences requiring more time should call wait_uip again. - */ -static inline void wait_uip(void) -{ - while (cmos_read(RTC_REG_A) & RTC_UIP) - ; -} - static inline void cmos_write_inner(unsigned char val, unsigned char addr) { int offs = 0; @@ -135,31 +125,34 @@ outb(val, RTC_BASE_PORT + offs + 1); } -static inline void cmos_write(unsigned char val, unsigned char addr) -{ - u8 control_state = cmos_read(RTC_CONTROL); - /* There are various places where RTC bits might be hiding, - * eg. the Century / AltCentury byte. So to be safe, disable - * RTC before changing any value. - */ - if ((addr != RTC_CONTROL) && !(control_state & RTC_SET)) - cmos_write_inner(control_state | RTC_SET, RTC_CONTROL); - cmos_write_inner(val, addr); - /* reset to prior configuration */ - if ((addr != RTC_CONTROL) && !(control_state & RTC_SET)) - cmos_write_inner(control_state, RTC_CONTROL); -} - static inline void cmos_disable_rtc(void) { u8 control_state = cmos_read(RTC_CONTROL); - cmos_write(control_state | RTC_SET, RTC_CONTROL); + if (!(control_state & RTC_SET)) + cmos_write_inner(control_state | RTC_SET, RTC_CONTROL); } static inline void cmos_enable_rtc(void) { u8 control_state = cmos_read(RTC_CONTROL); - cmos_write(control_state & ~RTC_SET, RTC_CONTROL); + if (control_state & RTC_SET) + cmos_write_inner(control_state & ~RTC_SET, RTC_CONTROL); +} + +static inline void cmos_write(unsigned char val, unsigned char addr) +{ + /* There are various places where RTC bits might be hiding, + * eg. the Century / AltCentury byte. So to be safe, disable + * RTC before changing any value. + */ + if (addr != RTC_CONTROL) + cmos_disable_rtc(); + + cmos_write_inner(val, addr); + + /* reset to prior configuration */ + if (addr != RTC_CONTROL) + cmos_enable_rtc(); } static inline u32 cmos_read32(u8 offset) -- To view, visit https://review.coreboot.org/c/coreboot/+/38179 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie73797b4e9a09605a0685f0b03cb85e9a3be93ad Gerrit-Change-Number: 38179 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/{beltino,jecht}: Drop SIO configuration lines
by Nico Huber (Code Review) 07 Jan '20

07 Jan '20

Hello Matt DeVillier, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/38032 to review the following change. Change subject: mb/google/{beltino,jecht}: Drop SIO configuration lines ...................................................................... mb/google/{beltino,jecht}: Drop SIO configuration lines These are meaningless for boards without SIO devices. Change-Id: I252bba6ff1a2547fd0661ad3076470376e95bdd6 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/mainboard/google/beltino/devicetree.cb M src/mainboard/google/jecht/devicetree.cb 2 files changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/38032/1 diff --git a/src/mainboard/google/beltino/devicetree.cb b/src/mainboard/google/beltino/devicetree.cb index 89758dd..f4c9e85 100644 --- a/src/mainboard/google/beltino/devicetree.cb +++ b/src/mainboard/google/beltino/devicetree.cb @@ -55,10 +55,6 @@ register "sata_port_map" = "0x1" register "sata_devslp_disable" = "0x1" - register "sio_acpi_mode" = "0" - register "sio_i2c0_voltage" = "0" # 3.3V - register "sio_i2c1_voltage" = "0" # 3.3V - # Force enable ASPM for PCIe Port 4 register "pcie_port_force_aspm" = "0x10" diff --git a/src/mainboard/google/jecht/devicetree.cb b/src/mainboard/google/jecht/devicetree.cb index d34bf7a..19d0c48 100644 --- a/src/mainboard/google/jecht/devicetree.cb +++ b/src/mainboard/google/jecht/devicetree.cb @@ -30,10 +30,6 @@ register "sata_port_map" = "0x1" register "sata_devslp_disable" = "0x1" - register "sio_acpi_mode" = "0" - register "sio_i2c0_voltage" = "0" # 3.3V - register "sio_i2c1_voltage" = "0" # 3.3V - # Force enable ASPM for PCIe Port 4 register "pcie_port_force_aspm" = "0x10" -- To view, visit https://review.coreboot.org/c/coreboot/+/38032 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I252bba6ff1a2547fd0661ad3076470376e95bdd6 Gerrit-Change-Number: 38032 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: soc/intel/tigerlake: Update GPIO config
by Shaunak Saha (Code Review) 07 Jan '20

07 Jan '20

Shaunak Saha has uploaded a new patch set (#15) to the change originally created by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/37427 ) Change subject: soc/intel/tigerlake: Update GPIO config ...................................................................... soc/intel/tigerlake: Update GPIO config Add tigerlake SOC specific GPIO definitions and ASL setting. GPIOs are divided into different communities. Each community consists of one or more GPIO groups. We need to configure the groups from coreboot so that they are mapped properly. BUG=b:144680462 BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Change-Id: I585100375feee39b5a9105bdf6d9f5ca3a5bb2fa --- M src/soc/intel/tigerlake/acpi/gpio.asl M src/soc/intel/tigerlake/gpio.c M src/soc/intel/tigerlake/include/soc/gpio.h M src/soc/intel/tigerlake/include/soc/gpio_defs.h M src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h M src/soc/intel/tigerlake/include/soc/pmc.h 6 files changed, 793 insertions(+), 607 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/37427/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/37427 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I585100375feee39b5a9105bdf6d9f5ca3a5bb2fa Gerrit-Change-Number: 37427 Gerrit-PatchSet: 15 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Venkata Krishna Nimmagadda Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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