coreboot-gerrit January 2020

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Change in coreboot[master]: soc/intel/tigerlake: Update Kconfig
by Wonkyu Kim (Code Review) 08 Jan '20

08 Jan '20

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37426 ) Change subject: soc/intel/tigerlake: Update Kconfig ...................................................................... Patch Set 16: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/37426 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I04020d55f1063d521b15f8d0dabbd6f1dabf577c Gerrit-Change-Number: 37426 Gerrit-PatchSet: 16 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Venkata Krishna Nimmagadda Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Wed, 08 Jan 2020 07:02:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Fix PMC config
by Ravishankar Sarawadi (Code Review) 08 Jan '20

08 Jan '20

Ravishankar Sarawadi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37784 ) Change subject: soc/intel/tigerlake: Fix PMC config ...................................................................... soc/intel/tigerlake: Fix PMC config Fix PMC base address for tigerlake. BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Change-Id: Id13222eb5498a5704c11d6b4d1e83212bd8b2723 --- M src/soc/intel/tigerlake/bootblock/pch.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/37784/1 diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c index 1ef4928..62c6dd1 100644 --- a/src/soc/intel/tigerlake/bootblock/pch.c +++ b/src/soc/intel/tigerlake/bootblock/pch.c @@ -37,7 +37,7 @@ #include <soc/pcr_ids.h> #include <soc/pm.h> -#define PCR_PSF3_TO_SHDW_PMC_REG_BASE 0x0600 +#define PCR_PSF3_TO_SHDW_PMC_REG_BASE 0x1100 #define PCR_PSFX_TO_SHDW_BAR0 0 #define PCR_PSFX_TO_SHDW_BAR1 0x4 #define PCR_PSFX_TO_SHDW_BAR2 0x8 -- To view, visit https://review.coreboot.org/c/coreboot/+/37784 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id13222eb5498a5704c11d6b4d1e83212bd8b2723 Gerrit-Change-Number: 37784 Gerrit-PatchSet: 1 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-MessageType: newchange

5 6

Change in coreboot[master]: mb/google/hatch: Remove fixed IccMax values
by Jamie Chen (Code Review) 08 Jan '20

08 Jan '20

Jamie Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38237 ) Change subject: mb/google/hatch: Remove fixed IccMax values ...................................................................... mb/google/hatch: Remove fixed IccMax values Remove fixed IccMax values for all domains. IccMax will be selected by CPU SKU in vr_config. BUG=b:145094963 BRANCH=None TEST=build coreboot and fsp with enabled fw_debug. Flashed to device and checked the log. Signed-off-by: Jamie Chen <jamie.chen(a)intel.com> Change-Id: I3f623d143f66c4f6ec63705844c9be7173feeb52 --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb 1 file changed, 7 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/38237/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index d944dcd..b4d7afd 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -58,6 +58,9 @@ register "PmTimerDisabled" = "1" + # Select CPU PL2/PL4 config + register "cpu_pl2_4_cfg" = "baseline" + # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ #| Domain/Setting | SA | IA | GTUS | GTS | @@ -83,7 +86,7 @@ .psi4enable = 1, .imon_slope = 0x0, .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(6), + .icc_max = 0, .voltage_limit = 1520, .ac_loadline = 1030, .dc_loadline = 1030, @@ -98,7 +101,7 @@ .psi4enable = 1, .imon_slope = 0x0, .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(70), + .icc_max = 0, .voltage_limit = 1520, .ac_loadline = 180, .dc_loadline = 180, @@ -113,7 +116,7 @@ .psi4enable = 1, .imon_slope = 0x0, .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(31), + .icc_max = 0, .voltage_limit = 1520, .ac_loadline = 310, .dc_loadline = 310, @@ -128,7 +131,7 @@ .psi4enable = 1, .imon_slope = 0x0, .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(31), + .icc_max = 0, .voltage_limit = 1520, .ac_loadline = 310, .dc_loadline = 310, -- To view, visit https://review.coreboot.org/c/coreboot/+/38237 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f623d143f66c4f6ec63705844c9be7173feeb52 Gerrit-Change-Number: 38237 Gerrit-PatchSet: 1 Gerrit-Owner: Jamie Chen <jamie.chen(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/cannonlake: Add VR config for CML
by Jamie Chen (Code Review) 08 Jan '20

08 Jan '20

Jamie Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37874 ) Change subject: soc/intel/cannonlake: Add VR config for CML ...................................................................... soc/intel/cannonlake: Add VR config for CML Add VR config TdcPowerLimit ,IccMax, DC and AC loadline defaults Add cpu_pl2_4_cfg to switch two kinds of VR design BUG:b:145094963 BRANCH:none TEST:build coreboot and fsp with enabled fw_debug. Flashed to device and checked the log. All VR configs were set correctly. Change-Id: I3922bfad5c21dafc64fb05c7d9343b9835b58752 Signed-off-by: Jamie Chen <jamie.chen(a)intel.com> --- M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/include/soc/vr_config.h M src/soc/intel/cannonlake/vr_config.c 3 files changed, 250 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/37874/1 diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 85c33db..5b99430 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -218,6 +218,14 @@ uint8_t TcoIrqSelect; uint8_t TcoIrqEnable; + /* CPU PL2/4 Config + * Performance: Maximum PLs for maximum performance. + * Baseline: Baseline PLs for balanced performance at lower power. */ + enum { + baseline, + performance + } cpu_pl2_4_cfg; + /* VrConfig Settings for 5 domains * 0 = System Agent, 1 = IA Core, 2 = Ring, * 3 = GT unsliced, 4 = GT sliced */ diff --git a/src/soc/intel/cannonlake/include/soc/vr_config.h b/src/soc/intel/cannonlake/include/soc/vr_config.h index 4cb35a0..8b74cb7 100644 --- a/src/soc/intel/cannonlake/include/soc/vr_config.h +++ b/src/soc/intel/cannonlake/include/soc/vr_config.h @@ -53,9 +53,12 @@ /* AC and DC Loadline in 1/100 mOhms. Range is 0-6249 */ uint16_t ac_loadline; uint16_t dc_loadline; + + uint16_t tdc_powerlimit; }; #define VR_CFG_AMP(i) ((i) * 4) +#define VR_CFG_TDC_AMP(i) ((i) * 8) #define VR_CFG_MOHMS(i) (uint16_t)((i) * 100) /* VrConfig Settings for 4 domains @@ -85,6 +88,14 @@ [VR_GT_SLICED] = VR_CFG_MOHMS(gt_sl), \ } +#define VR_CFG_ALL_DOMAINS_TDC(sa, ia, gt_unsl, gt_sl) \ + { \ + [VR_SYSTEM_AGENT] = VR_CFG_TDC_AMP(sa), \ + [VR_IA_CORE] = VR_CFG_TDC_AMP(ia), \ + [VR_GT_UNSLICED] = VR_CFG_TDC_AMP(gt_unsl), \ + [VR_GT_SLICED] = VR_CFG_TDC_AMP(gt_sl), \ + } + void fill_vr_domain_config(void *params, int domain, const struct vr_config *cfg); diff --git a/src/soc/intel/cannonlake/vr_config.c b/src/soc/intel/cannonlake/vr_config.c index 42c1325..dccc3bd 100644 --- a/src/soc/intel/cannonlake/vr_config.c +++ b/src/soc/intel/cannonlake/vr_config.c @@ -77,6 +77,7 @@ static uint16_t get_sku_icc_max(int domain) { const uint16_t tdp = cpu_get_power_max(); + config_t *cfg = config_of_soc(); static uint16_t mch_id = 0, igd_id = 0; if (!mch_id) { @@ -91,6 +92,7 @@ /* * Iccmax table from Doc #337344 Section 7.2 DC Specifications for CFL. * Iccmax table from Doc #338023 Section 7.2 DC Specifications for WHL. + * Iccmax table from Doc #606599 Section 7.2 DC Specifications for CML. * * Platform Segment SA IA GT (GT/GTx) * --------------------------------------------------------------------- @@ -123,7 +125,30 @@ * WHL-U (15W) GT2 quad 6 70 31 * WHL-U (15W) GT2 dual 6 35 31 * + * CML-U v1/v2 (15W) GT2 hex 6 85(70) 31 + * CML-U v1/v2 (15W) GT2 quad 6 85(70) 31 + * CML-U v1/v2 (15W) GT2 dual 6 35 31 + * + * CML-H (65W) GT2 octa 11.1 192(165) 32 + * CML-H (45W) GT2 octa 11.1 165(140) 32 + * CML-H (45W) GT2 hex 11.1 140(128) 32 + * CML-H (45W) GT2 quad 11.1 105(86) 32 + * + * CML-S (125W)GT2 deca 11.1 245(210) 35 + * CML-S (125W)GT2 octa 11.1 245(210) 35 + * CML-S (125W)GT2 hex 11.1 140 35 + * CML-S XeonW (80W) GT2 deca 11.1 210 35 + * CML-S XeonW (80W) GT2 octa 11.1 210 35 + * CML-S XeonW (80W) GT2 hex 11.1 140 35 + * CML-S (65W) GT2 deca 11.1 210(175) 35 + * CML-S (65W) GT2 octa 11.1 210(175) 35 + * CML-S (65W) GT2 hex 11.1 140 35 + * CML-S (35W) GT2 deca 11.1 140(104) 35 + * CML-S (35W) GT2 octa 11.1 140(104) 35 + * CML-S (35W) GT2 hex 11.1 104 35 + * * GT0 versions are the same as GT2/GT3, but have GT/GTx set to 0. + * () values when PL2_4_Config is baseline. */ if (igd_id == 0xffff && ((domain == VR_GT_SLICED) || (domain == VR_GT_UNSLICED))) @@ -215,6 +240,82 @@ return icc_max[domain]; } + case PCI_DEVICE_ID_INTEL_CML_ULT: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_CML_ULT_6_2: { + uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(6, 85, 31, 31); + if (cfg->cpu_pl2_4_cfg == baseline) + icc_max[VR_IA_CORE] = VR_CFG_AMP(70); + + return icc_max[domain]; + } + case PCI_DEVICE_ID_INTEL_CML_ULT_2_2: { + uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(6, 35, 31, 31); + + return icc_max[domain]; + } + case PCI_DEVICE_ID_INTEL_CML_H_8_2: { + uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(11.1, 192, 32, 32); + if (tdp >= 65) { /* 65W */ + if (cfg->cpu_pl2_4_cfg == baseline) + icc_max[VR_IA_CORE] = VR_CFG_AMP(165); + else + icc_max[VR_IA_CORE] = VR_CFG_AMP(192); + } else { /* 45W */ + if (cfg->cpu_pl2_4_cfg == baseline) + icc_max[VR_IA_CORE] = VR_CFG_AMP(140); + else + icc_max[VR_IA_CORE] = VR_CFG_AMP(165); + } + return icc_max[domain]; + } + case PCI_DEVICE_ID_INTEL_CML_H: { + uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(11.1, 140, 32, 32); + + if (cfg->cpu_pl2_4_cfg == baseline) + icc_max[VR_IA_CORE] = VR_CFG_AMP(128); + + return icc_max[domain]; + } + case PCI_DEVICE_ID_INTEL_CML_H_4_2: { + uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(11.1, 105, 32, 32); + + if (cfg->cpu_pl2_4_cfg == baseline) + icc_max[VR_IA_CORE] = VR_CFG_AMP(86); + + return icc_max[domain]; + } + case PCI_DEVICE_ID_INTEL_CML_S_P0P1_8_2: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2: { + uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(11.1, 140, 35, 35); + if (tdp >= 125) /* 125W */ + if (cfg->cpu_pl2_4_cfg == baseline) + icc_max[VR_IA_CORE] = VR_CFG_AMP(210); + else + icc_max[VR_IA_CORE] = VR_CFG_AMP(245); + else if (tdp >= 80) /* 80W */ + icc_max[VR_IA_CORE] = VR_CFG_AMP(210); + else if (tdp >= 65) /* 65W */ + if (cfg->cpu_pl2_4_cfg == baseline) + icc_max[VR_IA_CORE] = VR_CFG_AMP(175); + else + icc_max[VR_IA_CORE] = VR_CFG_AMP(210); + else /* 35W */ + if (cfg->cpu_pl2_4_cfg == baseline) + icc_max[VR_IA_CORE] = VR_CFG_AMP(104); + else + icc_max[VR_IA_CORE] = VR_CFG_AMP(140); + + return icc_max[domain]; + } + case PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2: { + uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(11.1, 104, 35, 35); + if (tdp >= 65) /* 125W or 80W or 65W */ + icc_max[VR_IA_CORE] = VR_CFG_AMP(140); + else /* 35W */ + icc_max[VR_IA_CORE] = VR_CFG_AMP(104); + + return icc_max[domain]; + } default: printk(BIOS_ERR, "ERROR: Unknown MCH (0x%x) in VR-config\n", mch_id); } @@ -223,6 +324,7 @@ static uint16_t get_sku_ac_dc_loadline(const int domain) { + const uint16_t tdp = cpu_get_power_max(); static uint16_t mch_id = 0; if (!mch_id) { struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); @@ -271,6 +373,39 @@ VR_CFG_ALL_DOMAINS_LOADLINE(11.1, 2.1, 3.1, 3.1); return loadline[domain]; } + case PCI_DEVICE_ID_INTEL_CML_ULT_2_2: { + const uint16_t loadline[NUM_VR_DOMAINS] = + VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.4, 3.1, 3.1); + return loadline[domain]; + } + case PCI_DEVICE_ID_INTEL_CML_ULT: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_CML_ULT_6_2: { + const uint16_t loadline[NUM_VR_DOMAINS] = + VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.8, 3.1, 3.1); + return loadline[domain]; + } + case PCI_DEVICE_ID_INTEL_CML_H_4_2: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_CML_H: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_CML_H_8_2: { + const uint16_t loadline[NUM_VR_DOMAINS] = + VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.1, 2.7, 2.7); + return loadline[domain]; + } + case PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2: { + uint16_t loadline[NUM_VR_DOMAINS] = + VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.7, 4.0, 4.0); + if (tdp >= 125) + loadline[VR_IA_CORE] = VR_CFG_MOHMS(1.1); + return loadline[domain]; + } + case PCI_DEVICE_ID_INTEL_CML_S_P0P1_8_2: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2: { + uint16_t loadline[NUM_VR_DOMAINS] = + VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.1, 4.0, 4.0); + if (tdp <= 35) + loadline[VR_IA_CORE] = VR_CFG_MOHMS(1.7); + return loadline[domain]; + } default: printk(BIOS_ERR, "ERROR: Unknown MCH (0x%x) in VR-config\n", mch_id); } @@ -282,6 +417,97 @@ return 1520; } +static uint16_t get_sku_tdc_powerlimit(int domain) +{ + const uint16_t tdp = cpu_get_power_max(); + config_t *cfg = config_of_soc(); + + static uint16_t mch_id = 0; + if (!mch_id) { + struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); + mch_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff; + } + + switch (mch_id) { + case PCI_DEVICE_ID_INTEL_CML_ULT: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_CML_ULT_6_2: { + uint16_t tdc[NUM_VR_DOMAINS] = + VR_CFG_ALL_DOMAINS_TDC(4, 58, 22, 22); + + if (cfg->cpu_pl2_4_cfg == baseline) + tdc[VR_IA_CORE] = VR_CFG_TDC_AMP(48); + + return tdc[domain]; + } + case PCI_DEVICE_ID_INTEL_CML_ULT_2_2: { + const uint16_t tdc[NUM_VR_DOMAINS] = + VR_CFG_ALL_DOMAINS_TDC(4, 24, 22, 22); + return tdc[domain]; + } + case PCI_DEVICE_ID_INTEL_CML_H_4_2: { + uint16_t tdc[NUM_VR_DOMAINS] = + VR_CFG_ALL_DOMAINS_TDC(10, 80, 25, 25); + + if (cfg->cpu_pl2_4_cfg == baseline) + tdc[VR_IA_CORE] = VR_CFG_TDC_AMP(60); + + return tdc[domain]; + } + case PCI_DEVICE_ID_INTEL_CML_H: { + uint16_t tdc[NUM_VR_DOMAINS] = + VR_CFG_ALL_DOMAINS_TDC(10, 92, 25, 25); + + if (cfg->cpu_pl2_4_cfg == baseline) + tdc[VR_IA_CORE] = VR_CFG_TDC_AMP(80); + + return tdc[domain]; + } + case PCI_DEVICE_ID_INTEL_CML_H_8_2: { + uint16_t tdc[NUM_VR_DOMAINS] = + VR_CFG_ALL_DOMAINS_TDC(10, 125, 25, 25); + + if (tdp >= 65) /* 65W */ + if (cfg->cpu_pl2_4_cfg == baseline) + tdc[VR_IA_CORE] = VR_CFG_TDC_AMP(117); + else + tdc[VR_IA_CORE] = VR_CFG_TDC_AMP(146); + else /* 45W */ + if (cfg->cpu_pl2_4_cfg == baseline) + tdc[VR_IA_CORE] = VR_CFG_TDC_AMP(86); + else + tdc[VR_IA_CORE] = VR_CFG_TDC_AMP(125); + + return tdc[domain]; + } + case PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2: { + uint16_t tdc[NUM_VR_DOMAINS] = + VR_CFG_ALL_DOMAINS_TDC(10, 74, 28, 28); + + if (tdp >= 125) /* 125W */ + tdc[VR_IA_CORE] = VR_CFG_TDC_AMP(132); + else if (tdp >= 65) /* 80W or 65W */ + tdc[VR_IA_CORE] = VR_CFG_TDC_AMP(104); + else /* 35W */ + tdc[VR_IA_CORE] = VR_CFG_TDC_AMP(74); + + return tdc[domain]; + } + case PCI_DEVICE_ID_INTEL_CML_S_P0P1_8_2: + case PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2: { + uint16_t tdc[NUM_VR_DOMAINS] = + VR_CFG_ALL_DOMAINS_TDC(10, 100, 28, 28); + + if (tdp > 35) /* 125W or 80W or 65W */ + tdc[VR_IA_CORE] = VR_CFG_TDC_AMP(175); + + return tdc[domain]; + } + default: + printk(BIOS_ERR, "ERROR: Unknown MCH (0x%x) in VR-config\n", mch_id); + } + return 0; +} + void fill_vr_domain_config(void *params, int domain, const struct vr_config *chip_cfg) { @@ -326,4 +552,9 @@ vr_params->DcLoadline[domain] = cfg->dc_loadline; else vr_params->DcLoadline[domain] = get_sku_ac_dc_loadline(domain); + + if (cfg->tdc_powerlimit) + vr_params->TdcPowerLimit[domain] = cfg->tdc_powerlimit; + else + vr_params->TdcPowerLimit[domain] = get_sku_tdc_powerlimit(domain); } -- To view, visit https://review.coreboot.org/c/coreboot/+/37874 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3922bfad5c21dafc64fb05c7d9343b9835b58752 Gerrit-Change-Number: 37874 Gerrit-PatchSet: 1 Gerrit-Owner: Jamie Chen <jamie.chen(a)intel.com> Gerrit-MessageType: newchange

6 15

Change in coreboot[master]: src/soc/intel: Add Cometlake-H 4+2 DID
by Jamie Chen (Code Review) 08 Jan '20

08 Jan '20

Jamie Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37873 ) Change subject: src/soc/intel: Add Cometlake-H 4+2 DID ...................................................................... src/soc/intel: Add Cometlake-H 4+2 DID This patch adds CML-H 4 Core Host Device ID. According to doc #605546: CML-H (4+2) R1: 9B64h BUG:none BRANCH:none TEST:build no error Change-Id: I5bac6173a84a11abd2ce17f82854fbb14fb8558b Signed-off-by: Jamie Chen <jamie.chen(a)intel.com> --- M src/include/device/pci_ids.h M src/soc/intel/cannonlake/bootblock/report_platform.c M src/soc/intel/common/block/systemagent/systemagent.c 3 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/37873/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index bd5b3a5..fab4d35 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3403,6 +3403,7 @@ #define PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2 0x9B35 #define PCI_DEVICE_ID_INTEL_CML_S_P0P1_8_2 0x9B43 #define PCI_DEVICE_ID_INTEL_CML_H 0x9B54 +#define PCI_DEVICE_ID_INTEL_CML_H_4_2 0x9B64 #define PCI_DEVICE_ID_INTEL_CML_H_8_2 0x9B44 #define PCI_DEVICE_ID_INTEL_TGL_ID_U 0x9A14 #define PCI_DEVICE_ID_INTEL_TGL_ID_U_1 0x9A12 diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c index 8cdf38e..dcb0969 100644 --- a/src/soc/intel/cannonlake/bootblock/report_platform.c +++ b/src/soc/intel/cannonlake/bootblock/report_platform.c @@ -83,6 +83,7 @@ { PCI_DEVICE_ID_INTEL_CML_S_P0P1_8_2, "CometLake-S P0/P1 (8+2)" }, { PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2, "CometLake-S P0/P1 (10+2)" }, { PCI_DEVICE_ID_INTEL_CML_H, "CometLake-H (6+2)" }, + { PCI_DEVICE_ID_INTEL_CML_H_4_2, "CometLake-H (4+2)" }, { PCI_DEVICE_ID_INTEL_CML_H_8_2, "CometLake-H (8+2)" }, }; diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 2019ef6..2da3992 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -363,6 +363,7 @@ PCI_DEVICE_ID_INTEL_CML_S_P0P1_8_2, PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2, PCI_DEVICE_ID_INTEL_CML_H, + PCI_DEVICE_ID_INTEL_CML_H_4_2, PCI_DEVICE_ID_INTEL_CML_H_8_2, PCI_DEVICE_ID_INTEL_TGL_ID_U, PCI_DEVICE_ID_INTEL_TGL_ID_U_1, -- To view, visit https://review.coreboot.org/c/coreboot/+/37873 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5bac6173a84a11abd2ce17f82854fbb14fb8558b Gerrit-Change-Number: 37873 Gerrit-PatchSet: 1 Gerrit-Owner: Jamie Chen <jamie.chen(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: Update Kconfig
by Wonkyu Kim (Code Review) 08 Jan '20

08 Jan '20

Wonkyu Kim has uploaded a new patch set (#16) to the change originally created by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/37426 ) Change subject: soc/intel/tigerlake: Update Kconfig ...................................................................... soc/intel/tigerlake: Update Kconfig Update Kconfig: - use CAR NEM mode for tigerlake only as NEM Enhanced is under debug - update GSPI, RP max device #s according to PCH EDS#576591 vol1 rev1.2 - update UART M/N setting according to new PCH baseclock BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Change-Id: I04020d55f1063d521b15f8d0dabbd6f1dabf577c Signed-off-by: Wonkyu Kim <wonkyu.kim(a)intel.com> --- M src/soc/intel/tigerlake/Kconfig 1 file changed, 17 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/37426/16 -- To view, visit https://review.coreboot.org/c/coreboot/+/37426 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I04020d55f1063d521b15f8d0dabbd6f1dabf577c Gerrit-Change-Number: 37426 Gerrit-PatchSet: 16 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Venkata Krishna Nimmagadda Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/block/cse: Minor clean up some late comments
by Subrata Banik (Code Review) 08 Jan '20

08 Jan '20

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35546 ) Change subject: soc/intel/common/block/cse: Minor clean up some late comments ...................................................................... Patch Set 15: (1 comment) https://review.coreboot.org/c/coreboot/+/35546/15/src/soc/intel/common/bloc… File src/soc/intel/common/block/include/intelblocks/cse.h: https://review.coreboot.org/c/coreboot/+/35546/15/src/soc/intel/common/bloc… PS15, Line 47: #if CONFIG(SOC_INTEL_APOLLOLAKE) i don't think in common code we had any soc check so far -- To view, visit https://review.coreboot.org/c/coreboot/+/35546 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7ea6043d7b5473d0c16e83d7b2d4b620c125652 Gerrit-Change-Number: 35546 Gerrit-PatchSet: 15 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <riz.pro(a)gmail.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 08 Jan 2020 03:27:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/hatch/var/kindred: Update PL2 power limit value
by David Wu (Code Review) 08 Jan '20

08 Jan '20

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37823 ) Change subject: mb/google/hatch/var/kindred: Update PL2 power limit value ...................................................................... mb/google/hatch/var/kindred: Update PL2 power limit value Update PL2 power limit value to 29W. BUG=b:140127035 TEST=Build and Boot kindred DVT Change-Id: Iaefab3011224d6dcf561b437bd34f54a62cf1287 Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> --- M src/mainboard/google/hatch/variants/kindred/include/variant/acpi/dptf.asl M src/mainboard/google/hatch/variants/kindred/overridetree.cb 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/37823/1 diff --git a/src/mainboard/google/hatch/variants/kindred/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/kindred/include/variant/acpi/dptf.asl index 43c1b08..aa0ea78 100644 --- a/src/mainboard/google/hatch/variants/kindred/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/kindred/include/variant/acpi/dptf.asl @@ -125,7 +125,7 @@ Package () { /* Power Limit 2 */ 1, /* PowerLimitIndex, 1 for Power Limit 2 */ 15000, /* PowerLimitMinimum */ - 51000, /* PowerLimitMaximum */ + 29000, /* PowerLimitMaximum */ 28000, /* TimeWindowMinimum */ 32000, /* TimeWindowMaximum */ 1000 /* StepSize */ diff --git a/src/mainboard/google/hatch/variants/kindred/overridetree.cb b/src/mainboard/google/hatch/variants/kindred/overridetree.cb index 1122609..1c99200 100644 --- a/src/mainboard/google/hatch/variants/kindred/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kindred/overridetree.cb @@ -1,6 +1,6 @@ chip soc/intel/cannonlake register "tdp_pl1_override" = "15" - register "tdp_pl2_override" = "51" + register "tdp_pl2_override" = "29" register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, -- To view, visit https://review.coreboot.org/c/coreboot/+/37823 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaefab3011224d6dcf561b437bd34f54a62cf1287 Gerrit-Change-Number: 37823 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

6 19

Change in coreboot[master]: drivers/spi/flashconsole: Fix shadowing local variable
by Mimoja (Code Review) 07 Jan '20

07 Jan '20

Mimoja has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38171 ) Change subject: drivers/spi/flashconsole: Fix shadowing local variable ...................................................................... drivers/spi/flashconsole: Fix shadowing local variable Commit c9b13594eb8d425e54a126b5c10e3f6fbc41528b removed the g_ prefix from global variables, leaving the local "offset" variable shadowing the global one. This commit partially reverts this by adding a l_ prefix to its two occations. Change-Id: I246ebdcfd3b973e6a4aa3c15fc5f32497dcf8398 Signed-off-by: Johanna Schander <coreboot(a)mimoja.de> --- M src/drivers/spi/flashconsole.c 1 file changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/38171/1 diff --git a/src/drivers/spi/flashconsole.c b/src/drivers/spi/flashconsole.c index 80c63e0..020d282 100644 --- a/src/drivers/spi/flashconsole.c +++ b/src/drivers/spi/flashconsole.c @@ -32,9 +32,9 @@ { uint8_t buffer[READ_BUFFER_SIZE]; size_t size; - size_t offset = 0; size_t len = READ_BUFFER_SIZE; size_t i; + size_t l_offset = 0; if (fmap_locate_area_as_rdev_rw("CONSOLE", &rdev)) { printk(BIOS_INFO, "Can't find 'CONSOLE' area in FMAP\n"); @@ -60,12 +60,12 @@ return; } if (buffer[i] == 0xff) { - offset += i; + l_offset += i; break; } // If we're done, repeat the process for the next sector if (++i == READ_BUFFER_SIZE) { - offset += len; + l_offset += len; i = 0; } } @@ -75,7 +75,7 @@ return; } - offset = offset; + offset = l_offset; rdev_ptr = &rdev; } @@ -96,7 +96,7 @@ void flashconsole_tx_flush(void) { - size_t offset = offset; + size_t l_offset = offset; size_t len = line_offset; size_t region_size; static int busy; @@ -112,17 +112,17 @@ busy = 1; region_size = region_device_sz(rdev_ptr); - if (offset + len >= region_size) + if (l_offset + len >= region_size) len = region_size - offset; if (rdev_writeat(&rdev, line_buffer, offset, len) != len) return; // If the region is full, stop future write attempts - if (offset + len >= region_size) + if (l_offset + len >= region_size) return; - offset = offset + len; + offset = l_offset + len; line_offset = 0; busy = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/38171 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I246ebdcfd3b973e6a4aa3c15fc5f32497dcf8398 Gerrit-Change-Number: 38171 Gerrit-PatchSet: 1 Gerrit-Owner: Mimoja <coreboot(a)mimoja.de> Gerrit-MessageType: newchange

5 15

Change in coreboot[master]: soc/intel/common/block/cse: Minor clean up some late comments
by Sridhar Siricilla (Code Review) 07 Jan '20

07 Jan '20

Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35546 ) Change subject: soc/intel/common/block/cse: Minor clean up some late comments ...................................................................... Patch Set 15: (7 comments) https://review.coreboot.org/c/coreboot/+/35546/14/src/soc/intel/common/bloc… File src/soc/intel/common/block/cse/cse.c: https://review.coreboot.org/c/coreboot/+/35546/14/src/soc/intel/common/bloc… PS14, Line 78: GR_ORIGIN_BIOS_POST > Is this a command id or group id? From the name and the comment, it is not really clear to me what t […] It's not command id or group id. It's one of the value of request_origin field of GLOBAL_RESET command request. https://review.coreboot.org/c/coreboot/+/35546/14/src/soc/intel/common/bloc… PS14, Line 84: operation and working modes > Actually, this should be CWS = Current Working State and COM = Current Operation Mode Modified the comment in the patch: https://review.coreboot.org/c/coreboot/+/38247/1 https://review.coreboot.org/c/coreboot/+/35546/14/src/soc/intel/common/bloc… PS14, Line 85: HFS > I think it would be better to add HFSTS1 or HFS1 to indicate that this is a field in HFSTS1 register […] Implemented the comment in the patch - https://review.coreboot.org/c/coreboot/+/38247/1 https://review.coreboot.org/c/coreboot/+/35546/14/src/soc/intel/common/bloc… PS14, Line 86: MODE > I think it would be better to call this COM = Current Operation Mode. […] Implemented the comment in the patch - https://review.coreboot.org/c/coreboot/+/38247/1 https://review.coreboot.org/c/coreboot/+/35546/14/src/soc/intel/common/bloc… PS14, Line 678: } > Why is resp. […] comment is addressed in the patch - https://review.coreboot.org/c/coreboot/+/37283 https://review.coreboot.org/c/coreboot/+/35546/14/src/soc/intel/common/bloc… File src/soc/intel/common/block/include/intelblocks/cse.h: https://review.coreboot.org/c/coreboot/+/35546/14/src/soc/intel/common/bloc… PS14, Line 143: > nit: extra blank line not required. Implemented in the patch : https://review.coreboot.org/c/coreboot/+/38248 https://review.coreboot.org/c/coreboot/+/35546/14/src/soc/intel/common/bloc… PS14, Line 152: * > nit: space after * Change is done in the patch - https://review.coreboot.org/c/coreboot/+/38248 -- To view, visit https://review.coreboot.org/c/coreboot/+/35546 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7ea6043d7b5473d0c16e83d7b2d4b620c125652 Gerrit-Change-Number: 35546 Gerrit-PatchSet: 15 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <riz.pro(a)gmail.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 07 Jan 2020 19:36:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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