coreboot-gerrit January 2020

coreboot-gerrit@coreboot.org

1 participants
1869 discussions

Change in coreboot[master]: soc/intel/common/basecode: Implement CSE update flow
by Sridhar Siricilla (Code Review) 08 Jan '20

08 Jan '20

Hello Patrick Rudolph, Subrata Banik, Balaji Manigandan, Aamir Bohra, Sridhar Siricilla, Rizwan Qureshi, build bot (Jenkins), Patrick Georgi, Furquan Shaikh, V Sowmya, Andrey Petrov, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35403 to look at the new patch set (#40). Change subject: soc/intel/common/basecode: Implement CSE update flow ...................................................................... soc/intel/common/basecode: Implement CSE update flow This is the core patch that implement CSE FW update flow. To enable the FW update flow the following are required: * Descriptor change to accommodate a larger CSME region The CSME size is 4.1MB. * FMAP changes to accommodate ME update binary in RW CBFSes & larger CSE binary. Due to the increased CSME binary size and to accommodate the extra CSME RW binaries (which are ~2.5 MB) in RW CBFSes, the board FMAP has to be modified. * The new CSE binary with new partitions and respective RW area binaries. The following changes have been done in this patch: * Implement Update flow Get the partition info containing version of ME RW using GET_BOOT_PARTITION_INFO HECI command Get the me_rw.version from the currently selected RW slot. If the version from the above 2 locations don't match start the update - Set the CSE's next boot partition to RO using SET_BOOT_PARTITION HECI command. - Send global reset command to reset only the CSME - Wait for CSME to enter SOFT_TEMP_DISABLE operation mode (indicated by HFSTS1 register bit 19:16) - Enable HMRFPO (Host ME Region Flash Protection Override) using the HMRFPO_ENABLE HECI command - Erase and Copy the CBFS ME RW to ME RW partition - Set the CSE's next boot partition to RW using SET_BOOT_PARTITION HECI command - Trigger global reset The system should boot with the Updated ME Verified basic update flows on Cometlake RVP and hatch. BUG=b:111330995 Change-Id: I12f6bba3324069d65edabaccd234006b0840e700 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: V Sowmya <v.sowmya(a)intel.com> Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- A Documentation/soc/intel/cse_fw_update/Layout_after.svg A Documentation/soc/intel/cse_fw_update/Layout_before.svg A Documentation/soc/intel/cse_fw_update/cse_fw_update.md M Documentation/soc/intel/index.md A src/soc/intel/common/basecode/fw_update/Kconfig A src/soc/intel/common/basecode/fw_update/Makefile.inc A src/soc/intel/common/basecode/fw_update/cse_update.c A src/soc/intel/common/basecode/include/intelbasecode/cse_update.h 8 files changed, 857 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/35403/40 -- To view, visit https://review.coreboot.org/c/coreboot/+/35403 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12f6bba3324069d65edabaccd234006b0840e700 Gerrit-Change-Number: 35403 Gerrit-PatchSet: 40 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: util/inteltool: Add GPIO dumping capabilites for Ice Lake U systems
by Mimoja (Code Review) 08 Jan '20

08 Jan '20

Mimoja has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38175 ) Change subject: util/inteltool: Add GPIO dumping capabilites for Ice Lake U systems ...................................................................... Patch Set 9: (1 comment) https://review.coreboot.org/c/coreboot/+/38175/8//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/38175/8//COMMIT_MSG@7 PS8, Line 7: Icelake > Ice Lake Done -- To view, visit https://review.coreboot.org/c/coreboot/+/38175 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib40f1dbae57169678e92ea9ad0df60ff91b5b22c Gerrit-Change-Number: 38175 Gerrit-PatchSet: 9 Gerrit-Owner: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jeremy Soller <jeremy(a)system76.com> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Wed, 08 Jan 2020 18:00:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: util/inteltool: Add GPIO dumping capabilites for Ice Lake U systems
by Mimoja (Code Review) 08 Jan '20

08 Jan '20

Hello Paul Menzel, Stefan Reinauer, Philipp Deppenwiese, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/38175 to look at the new patch set (#9). Change subject: util/inteltool: Add GPIO dumping capabilites for Ice Lake U systems ...................................................................... util/inteltool: Add GPIO dumping capabilites for Ice Lake U systems This GPIO dumping was implemented using the Document Number: 341080-001 Intel® 495 Series Chipset Family On-Package Platform Controller Hub Volume 1 of 2 datasheet. The GPIO community ports can be found in table 36-1, while the community and pin descriptions are taken from linux/pinctrl/intel/pinctrl-icelake.c . This commit was tested on the late 2019 Razer Blade Stealth with 1065G7 and Chipset 495 PCH and the output manually compared against linux/pinctrl-intel. Change-Id: Ib40f1dbae57169678e92ea9ad0df60ff91b5b22c Signed-off-by: Johanna Schander <coreboot(a)mimoja.de> --- M util/inteltool/gpio.c M util/inteltool/gpio_groups.c M util/inteltool/pcr.c 3 files changed, 478 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/38175/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/38175 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib40f1dbae57169678e92ea9ad0df60ff91b5b22c Gerrit-Change-Number: 38175 Gerrit-PatchSet: 9 Gerrit-Owner: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jeremy Soller <jeremy(a)system76.com> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: drivers/spi: remove SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B option
by Aaron Durbin (Code Review) 08 Jan '20

08 Jan '20

Aaron Durbin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38166 ) Change subject: drivers/spi: remove SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B option ...................................................................... drivers/spi: remove SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B option The SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B option is no longer being used in the code. There's a runtime check for supporting fast read dual output mode of the spi flash. Remove the references to SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B. Change-Id: Ie7d9d3f91f29a700f07ab33feaf427a872bbf7df Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- M src/drivers/spi/Kconfig M src/mainboard/google/nyan/Kconfig M src/mainboard/google/nyan_big/Kconfig M src/mainboard/google/nyan_blaze/Kconfig 4 files changed, 0 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/38166/1 diff --git a/src/drivers/spi/Kconfig b/src/drivers/spi/Kconfig index 8300026..a4be84d 100644 --- a/src/drivers/spi/Kconfig +++ b/src/drivers/spi/Kconfig @@ -149,15 +149,6 @@ Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by Winbond. -config SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B - bool - default n - depends on SPI_FLASH - help - Select this option if your SPI flash supports the fast read dual- - output command (opcode 0x3b) where the opcode and address are sent - to the chip on MOSI and data is received on both MOSI and MISO. - config SPI_FLASH_HAS_VOLATILE_GROUP bool default n diff --git a/src/mainboard/google/nyan/Kconfig b/src/mainboard/google/nyan/Kconfig index c617545..cc649e6 100644 --- a/src/mainboard/google/nyan/Kconfig +++ b/src/mainboard/google/nyan/Kconfig @@ -27,7 +27,6 @@ select SPI_FLASH select SPI_FLASH_GIGADEVICE select SPI_FLASH_WINBOND - select SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES diff --git a/src/mainboard/google/nyan_big/Kconfig b/src/mainboard/google/nyan_big/Kconfig index f02f694..87e39aa 100644 --- a/src/mainboard/google/nyan_big/Kconfig +++ b/src/mainboard/google/nyan_big/Kconfig @@ -27,7 +27,6 @@ select SPI_FLASH select SPI_FLASH_GIGADEVICE select SPI_FLASH_WINBOND - select SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B select MAINBOARD_HAS_I2C_TPM_GENERIC select MAINBOARD_HAS_TPM1 diff --git a/src/mainboard/google/nyan_blaze/Kconfig b/src/mainboard/google/nyan_blaze/Kconfig index 8de957d..82a28ed 100644 --- a/src/mainboard/google/nyan_blaze/Kconfig +++ b/src/mainboard/google/nyan_blaze/Kconfig @@ -27,7 +27,6 @@ select SPI_FLASH select SPI_FLASH_GIGADEVICE select SPI_FLASH_WINBOND - select SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B select MAINBOARD_HAS_I2C_TPM_GENERIC select MAINBOARD_HAS_TPM1 -- To view, visit https://review.coreboot.org/c/coreboot/+/38166 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie7d9d3f91f29a700f07ab33feaf427a872bbf7df Gerrit-Change-Number: 38166 Gerrit-PatchSet: 1 Gerrit-Owner: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: Make: Add supermicro/smcbiosinfo to tools
by Patrick Rudolph (Code Review) 08 Jan '20

08 Jan '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38270 ) Change subject: Make: Add supermicro/smcbiosinfo to tools ...................................................................... Make: Add supermicro/smcbiosinfo to tools Build the smcbiosinfo tool with other tools. Fixes possible race condition on jenkins. Change-Id: I38f7ee2fdef2818ad685b3de53ad74f7da50600f Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M Makefile.inc M util/supermicro/Makefile.inc 2 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/38270/1 diff --git a/Makefile.inc b/Makefile.inc index a54e57b..002d3e7 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -641,7 +641,7 @@ include util/crossgcc/Makefile.inc .PHONY: tools -tools: $(objutil)/kconfig/conf $(objutil)/kconfig/toada $(CBFSTOOL) $(objutil)/cbfstool/cbfs-compression-tool $(FMAPTOOL) $(RMODTOOL) $(IFWITOOL) $(objutil)/nvramtool/nvramtool $(objutil)/sconfig/sconfig $(IFDTOOL) $(CBOOTIMAGE) $(AMDFWTOOL) $(AMDCOMPRESS) $(FUTILITY) $(BINCFG) $(IFITTOOL) +tools: $(objutil)/kconfig/conf $(objutil)/kconfig/toada $(CBFSTOOL) $(objutil)/cbfstool/cbfs-compression-tool $(FMAPTOOL) $(RMODTOOL) $(IFWITOOL) $(objutil)/nvramtool/nvramtool $(objutil)/sconfig/sconfig $(IFDTOOL) $(CBOOTIMAGE) $(AMDFWTOOL) $(AMDCOMPRESS) $(FUTILITY) $(BINCFG) $(IFITTOOL) $(objutil)/supermicro/smcbiosinfo ########################################################################### # Common recipes for all stages diff --git a/util/supermicro/Makefile.inc b/util/supermicro/Makefile.inc index e71cfbd..1aa5bcb 100644 --- a/util/supermicro/Makefile.inc +++ b/util/supermicro/Makefile.inc @@ -1,6 +1,3 @@ -ifeq ($(CONFIG_VENDOR_SUPERMICRO),y) -ifneq ($(call strip_quotes, $(CONFIG_SUPERMICRO_BOARDID)),) - SMCBIOSINFOTOOL:= $(objutil)/supermicro/smcbiosinfo $(SMCBIOSINFOTOOL): $(dir)/smcbiosinfo/smcbiosinfo.c @@ -8,6 +5,9 @@ mkdir -p $(objutil)/supermicro $(HOSTCC) $< -o $@ +ifeq ($(CONFIG_VENDOR_SUPERMICRO),y) +ifneq ($(call strip_quotes, $(CONFIG_SUPERMICRO_BOARDID)),) + cbfs-files-y += smcbiosinfo.bin smcbiosinfo.bin-file := $(obj)/mainboard/$(MAINBOARDDIR)/smcbiosinfo.bin -- To view, visit https://review.coreboot.org/c/coreboot/+/38270 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38f7ee2fdef2818ad685b3de53ad74f7da50600f Gerrit-Change-Number: 38270 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

6 7

Change in coreboot[master]: [WIP] fix autoport
by Angel Pons (Code Review) 08 Jan '20

08 Jan '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37730 ) Change subject: [WIP] fix autoport ...................................................................... [WIP] fix autoport Change-Id: I8d1a6af6f1d70268f17692bee130c08502082c97 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M util/autoport/azalia.go M util/autoport/bd82x6x.go 2 files changed, 13 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/37730/1 diff --git a/util/autoport/azalia.go b/util/autoport/azalia.go index c525189..e00f457 100644 --- a/util/autoport/azalia.go +++ b/util/autoport/azalia.go @@ -20,13 +20,12 @@ `) for _, codec := range ctx.InfoSource.GetAzaliaCodecs() { - fmt.Fprintf(az, "\t0x%08x, /* Codec Vendor / Device ID: %s */\n", + fmt.Fprintf(az, "\t0x%08x,\t/* Codec Vendor / Device ID: %s */\n", codec.VendorID, codec.Name) - fmt.Fprintf(az, "\t0x%08x, /* Subsystem ID */\n", + fmt.Fprintf(az, "\t0x%08x,\t/* Subsystem ID */\n", codec.SubsystemID) - fmt.Fprintf(az, "\n\t0x%08x, /* Number of 4 dword sets */\n", + fmt.Fprintf(az, "\n\t%d,\t\t/* Number of 4 dword sets */\n", len(codec.PinConfig)+1) - fmt.Fprintf(az, "\t/* NID 0x01: Subsystem ID. */\n") fmt.Fprintf(az, "\tAZALIA_SUBVENDOR(0x%x, 0x%08x),\n", codec.CodecNo, codec.SubsystemID) @@ -38,7 +37,6 @@ sort.Ints(keys) for _, nid := range keys { - fmt.Fprintf(az, "\n\t/* NID 0x%02x. */\n", nid) fmt.Fprintf(az, "\tAZALIA_PIN_CFG(0x%x, 0x%02x, 0x%08x),\n", codec.CodecNo, nid, codec.PinConfig[nid]) } diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go index fbe0c3a..1cee9f2 100644 --- a/util/autoport/bd82x6x.go +++ b/util/autoport/bd82x6x.go @@ -276,7 +276,7 @@ } PutPCIChip(addr, cur) - PutPCIDevParent(addr, "PCI-LPC bridge", "lpc") + PutPCIDevParent(addr, "LPC bridge", "lpc") DSDTIncludes = append(DSDTIncludes, DSDTInclude{ File: "southbridge/intel/bd82x6x/acpi/platform.asl", @@ -286,13 +286,13 @@ Comment: "global NVS and variables", }) DSDTIncludes = append(DSDTIncludes, DSDTInclude{ - File: "southbridge/intel/bd82x6x/acpi/sleepstates.asl", + File: "southbridge/intel/common/acpi/sleepstates.asl", }) DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{ File: "southbridge/intel/bd82x6x/acpi/pch.asl", }) - sb := Create(ctx, "romstage.c") + sb := Create(ctx, "early_init.c") defer sb.Close() Add_gpl(sb) sb.WriteString(`/* FIXME: Check if all includes are needed. */ @@ -310,20 +310,7 @@ #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> -void pch_enable_lpc(void) -{ `) - RestorePCI16Simple(sb, addr, 0x82) - - RestorePCI16Simple(sb, addr, 0x80) - - sb.WriteString(`} - -void mainboard_rcba_config(void) -{ -`) - sb.WriteString("}\n\n") - sb.WriteString("const struct southbridge_usb_port mainboard_usb_ports[] = {\n") currentMap := map[uint32]int{ @@ -360,12 +347,13 @@ guessedMap := GuessSPDMap(ctx) sb.WriteString(` -void mainboard_early_init(int s3resume) -{ -} +void bootblock_mainboard_early_init(void) +{`) + RestorePCI16Simple(sb, addr, 0x82) -void mainboard_config_superio(void) -{ + RestorePCI16Simple(sb, addr, 0x80) + + sb.WriteString(` } /* FIXME: Put proper SPD map here. */ @@ -394,7 +382,7 @@ gnvs->s5u0 = 0; gnvs->s5u1 = 0; - // the lid is open by default. + /* The lid is open by default. */ gnvs->lids = 1; gnvs->tcrt = 100; -- To view, visit https://review.coreboot.org/c/coreboot/+/37730 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d1a6af6f1d70268f17692bee130c08502082c97 Gerrit-Change-Number: 37730 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

4 14

Change in coreboot[master]: CANCELLED - please accept https://review.coreboot.org/#/c/20637/ patch
by Mike Banon (Code Review) 08 Jan '20

08 Jan '20

Mike Banon has removed a vote from this change. ( https://review.coreboot.org/c/coreboot/+/17507 ) Change subject: CANCELLED - please accept https://review.coreboot.org/#/c/20637/ patch ...................................................................... Removed Code-Review-1 by Mike Banon <mikebdp2(a)gmail.com> -- To view, visit https://review.coreboot.org/c/coreboot/+/17507 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I98f0ccdb19d6b195572941cf87ce3221f57db7c5 Gerrit-Change-Number: 17507 Gerrit-PatchSet: 3 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Uwe Hermann <uwe(a)hermann-uwe.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: deleteVote

1 0

Change in coreboot[master]: util/inteltool: Add GPIO dumping capabilites for Icelake U systems
by Paul Menzel (Code Review) 08 Jan '20

08 Jan '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38175 ) Change subject: util/inteltool: Add GPIO dumping capabilites for Icelake U systems ...................................................................... Patch Set 8: Code-Review+1 (1 comment) Very nice! https://review.coreboot.org/c/coreboot/+/38175/8//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/38175/8//COMMIT_MSG@7 PS8, Line 7: Icelake Ice Lake -- To view, visit https://review.coreboot.org/c/coreboot/+/38175 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib40f1dbae57169678e92ea9ad0df60ff91b5b22c Gerrit-Change-Number: 38175 Gerrit-PatchSet: 8 Gerrit-Owner: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jeremy Soller <jeremy(a)system76.com> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Wed, 08 Jan 2020 13:07:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/tigerlake: Update GPIO config
by Paul Menzel (Code Review) 08 Jan '20

08 Jan '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37427 ) Change subject: soc/intel/tigerlake: Update GPIO config ...................................................................... Patch Set 16: (1 comment) https://review.coreboot.org/c/coreboot/+/37427/16//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/37427/16//COMMIT_MSG@9 PS16, Line 9: tigerlake Tiger Lake -- To view, visit https://review.coreboot.org/c/coreboot/+/37427 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I585100375feee39b5a9105bdf6d9f5ca3a5bb2fa Gerrit-Change-Number: 37427 Gerrit-PatchSet: 16 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Venkata Krishna Nimmagadda Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 08 Jan 2020 12:59:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: nb/amd/pi: Fix typos
by HAOUAS Elyes (Code Review) 08 Jan '20

08 Jan '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38244 ) Change subject: nb/amd/pi: Fix typos ...................................................................... nb/amd/pi: Fix typos Change-Id: I79ec3a346edde0a63cf344352e58dfb78556dfd8 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/amd/pi/00630F01/northbridge.c M src/northbridge/amd/pi/00660F01/northbridge.c M src/northbridge/amd/pi/00730F01/northbridge.c 3 files changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/38244/1 diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index b55b23c..2295cd6 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -860,7 +860,7 @@ u32 lapicid_start = 0; /* - * APIC ID calucation is tightly coupled with AGESA v5 code. + * APIC ID calculation is tightly coupled with AGESA v5 code. * This calculation MUST match the assignment calculation done * in LocalApicInitializationAtEarly() function. * And reference GetLocalApicIdForCore() diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c index 7dc338e..16b5734 100644 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -645,7 +645,7 @@ base_k = ((resource_t)(d.base & 0x1fffff00)) <<9; if (base_k > 4 *1024 * 1024) break; // don't need to go to check if (limitk_pri != base_k) { // we find the hole - mem_hole.hole_startk = (unsigned int)limitk_pri; // must beblow 4G + mem_hole.hole_startk = (unsigned int)limitk_pri; // must be below 4G mem_hole.node_id = i; break; //only one hole } @@ -858,7 +858,7 @@ u32 lapicid_start = 0; /* - * APIC ID calucation is tightly coupled with AGESA v5 code. + * APIC ID calculation is tightly coupled with AGESA v5 code. * This calculation MUST match the assignment calculation done * in LocalApicInitializationAtEarly() function. * And reference GetLocalApicIdForCore() diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 8da3f0a..e5a75e8 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -869,7 +869,7 @@ base_k = ((resource_t)(d.base & 0x1fffff00)) <<9; if (base_k > 4 *1024 * 1024) break; // don't need to go to check if (limitk_pri != base_k) { // we find the hole - mem_hole.hole_startk = (unsigned int)limitk_pri; // must beblow 4G + mem_hole.hole_startk = (unsigned int)limitk_pri; // must be below 4G mem_hole.node_id = i; break; //only one hole } @@ -1097,7 +1097,7 @@ u32 lapicid_start = 0; /* - * APIC ID calucation is tightly coupled with AGESA v5 code. + * APIC ID calculation is tightly coupled with AGESA v5 code. * This calculation MUST match the assignment calculation done * in LocalApicInitializationAtEarly() function. * And reference GetLocalApicIdForCore() -- To view, visit https://review.coreboot.org/c/coreboot/+/38244 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79ec3a346edde0a63cf344352e58dfb78556dfd8 Gerrit-Change-Number: 38244 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

5 5

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit January 2020