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Change in coreboot[master]: acpi: Be more ACPI compliant when generating _UID
by Patrick Rudolph (Code Review) 09 Jan '20

09 Jan '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37695 ) Change subject: acpi: Be more ACPI compliant when generating _UID ...................................................................... acpi: Be more ACPI compliant when generating _UID Use the ACPI path of devices to calculate a unique _UID that doesn't change accross reboots. Add a CRC32 generator and add a function to write the _UID based on a device's ACPI path. Change-Id: I47cd5396060d325f9ce338afced6af021e7ff2b4 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/arch/x86/acpi_device.c M src/arch/x86/include/arch/acpi_device.h M src/drivers/crb/tis.c M src/drivers/net/r8168.c M src/drivers/pc80/tpm/tis.c M src/drivers/wifi/generic.c M src/lib/Makefile.inc A src/lib/crc32.c M src/superio/common/ssdt.c 9 files changed, 193 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/37695/1 diff --git a/src/arch/x86/acpi_device.c b/src/arch/x86/acpi_device.c index 5c77953..a496832 100644 --- a/src/arch/x86/acpi_device.c +++ b/src/arch/x86/acpi_device.c @@ -18,6 +18,8 @@ #include <device/device.h> #include <device/path.h> #include <stdlib.h> +#include <crc32.h> + #if CONFIG(GENERIC_GPIO_LIB) #include <gpio.h> #endif @@ -98,6 +100,16 @@ return NULL; } +/* Generate unique ID bases on ACPI path. Collisions on the same _HID are possible but unlikely */ +uint32_t acpi_device_uid(struct device *dev) +{ + const char *path = acpi_device_path(dev); + if (!path) + return 0; + + return xcrc32 ((unsigned char *)path, strlen(path), ~0); +} + /* Recursive function to find the root device and print a path from there */ static ssize_t acpi_device_path_fill(const struct device *dev, char *buf, size_t buf_len, size_t cur) @@ -192,6 +204,13 @@ return ACPI_STATUS_DEVICE_ALL_ON; } + +/* Write the unique _UID based on ACPI device path. */ +void acpi_device_write_uid(struct device *dev) +{ + acpigen_write_name_integer("_UID", acpi_device_uid(dev)); +} + /* ACPI 6.1 section 6.4.3.6: Extended Interrupt Descriptor */ void acpi_device_write_interrupt(const struct acpi_irq *irq) { diff --git a/src/arch/x86/include/arch/acpi_device.h b/src/arch/x86/include/arch/acpi_device.h index 382ef15..0a702c9 100644 --- a/src/arch/x86/include/arch/acpi_device.h +++ b/src/arch/x86/include/arch/acpi_device.h @@ -62,10 +62,12 @@ struct device; const char *acpi_device_name(const struct device *dev); const char *acpi_device_hid(const struct device *dev); +uint32_t acpi_device_uid(struct device *dev); const char *acpi_device_path(const struct device *dev); const char *acpi_device_scope(const struct device *dev); const char *acpi_device_path_join(const struct device *dev, const char *name); int acpi_device_status(const struct device *dev); +void acpi_device_write_uid(struct device *dev); /* * ACPI Descriptor for extended Interrupt() diff --git a/src/drivers/crb/tis.c b/src/drivers/crb/tis.c index f2aba48..b1fbad0 100644 --- a/src/drivers/crb/tis.c +++ b/src/drivers/crb/tis.c @@ -117,7 +117,7 @@ acpigen_write_name_string("_HID", "MSFT0101"); acpigen_write_name_string("_CID", "MSFT0101"); - acpigen_write_name_integer("_UID", 1); + acpi_device_write_uid(dev); acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); diff --git a/src/drivers/net/r8168.c b/src/drivers/net/r8168.c index bc0132f..1bca879 100644 --- a/src/drivers/net/r8168.c +++ b/src/drivers/net/r8168.c @@ -312,7 +312,8 @@ acpigen_write_scope(path); acpigen_write_device(acpi_device_name(dev)); acpigen_write_name_string("_HID", R8168_ACPI_HID); - acpigen_write_name_integer("_UID", 0); + acpi_device_write_uid(dev); + if (dev->chip_ops) acpigen_write_name_string("_DDN", dev->chip_ops->name); diff --git a/src/drivers/pc80/tpm/tis.c b/src/drivers/pc80/tpm/tis.c index 39fa70d..24944ea 100644 --- a/src/drivers/pc80/tpm/tis.c +++ b/src/drivers/pc80/tpm/tis.c @@ -902,7 +902,7 @@ acpigen_write_name("_CID"); acpigen_emit_eisaid("PNP0C31"); - acpigen_write_name_integer("_UID", 1); + acpi_device_write_uid(dev); u32 did_vid = tpm_read_did_vid(0); if (did_vid > 0 && did_vid < 0xffffffff) diff --git a/src/drivers/wifi/generic.c b/src/drivers/wifi/generic.c index 9f9f4fa..fe2e39d 100644 --- a/src/drivers/wifi/generic.c +++ b/src/drivers/wifi/generic.c @@ -187,7 +187,8 @@ /* Device */ acpigen_write_scope(path); acpigen_write_device(acpi_device_name(dev)); - acpigen_write_name_integer("_UID", 0); + acpi_device_write_uid(dev); + if (dev->chip_ops) acpigen_write_name_string("_DDN", dev->chip_ops->name); diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index b444ea3..4a3289d 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -133,6 +133,7 @@ postcar-$(CONFIG_TRACE) += trace.c ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c ramstage-$(CONFIG_COVERAGE) += libgcov.c +ramstage-y += crc32.c ramstage-y += edid.c ifneq ($(CONFIG_NO_EDID_FILL_FB),y) ramstage-y += edid_fill_fb.c diff --git a/src/lib/crc32.c b/src/lib/crc32.c new file mode 100644 index 0000000..7c2c61d --- /dev/null +++ b/src/lib/crc32.c @@ -0,0 +1,163 @@ +/* + * Copyright (C) 2009-2019 Free Software Foundation, Inc. + * + * This file is part of the libiberty library. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <crc32.h> + +/* This table was generated by the following program. + + #include <stdio.h> + + int + main () + { + unsigned int i, j; + unsigned int c; + int table[256]; + + for (i = 0; i < 256; i++) + { + for (c = i << 24, j = 8; j > 0; --j) + c = c & 0x80000000 ? (c << 1) ^ 0x04c11db7 : (c << 1); + table[i] = c; + } + + printf ("static const unsigned int crc32_table[] =\n{\n"); + for (i = 0; i < 256; i += 4) + { + printf (" 0x%08x, 0x%08x, 0x%08x, 0x%08x", + table[i + 0], table[i + 1], table[i + 2], table[i + 3]); + if (i + 4 < 256) + putchar (','); + putchar ('\n'); + } + printf ("};\n"); + return 0; + } + + For more information on CRC, see, e.g., + http://www.ross.net/crc/download/crc_v3.txt. */ + +static const unsigned int crc32_table[] = +{ + 0x00000000, 0x04c11db7, 0x09823b6e, 0x0d4326d9, + 0x130476dc, 0x17c56b6b, 0x1a864db2, 0x1e475005, + 0x2608edb8, 0x22c9f00f, 0x2f8ad6d6, 0x2b4bcb61, + 0x350c9b64, 0x31cd86d3, 0x3c8ea00a, 0x384fbdbd, + 0x4c11db70, 0x48d0c6c7, 0x4593e01e, 0x4152fda9, + 0x5f15adac, 0x5bd4b01b, 0x569796c2, 0x52568b75, + 0x6a1936c8, 0x6ed82b7f, 0x639b0da6, 0x675a1011, + 0x791d4014, 0x7ddc5da3, 0x709f7b7a, 0x745e66cd, + 0x9823b6e0, 0x9ce2ab57, 0x91a18d8e, 0x95609039, + 0x8b27c03c, 0x8fe6dd8b, 0x82a5fb52, 0x8664e6e5, + 0xbe2b5b58, 0xbaea46ef, 0xb7a96036, 0xb3687d81, + 0xad2f2d84, 0xa9ee3033, 0xa4ad16ea, 0xa06c0b5d, + 0xd4326d90, 0xd0f37027, 0xddb056fe, 0xd9714b49, + 0xc7361b4c, 0xc3f706fb, 0xceb42022, 0xca753d95, + 0xf23a8028, 0xf6fb9d9f, 0xfbb8bb46, 0xff79a6f1, + 0xe13ef6f4, 0xe5ffeb43, 0xe8bccd9a, 0xec7dd02d, + 0x34867077, 0x30476dc0, 0x3d044b19, 0x39c556ae, + 0x278206ab, 0x23431b1c, 0x2e003dc5, 0x2ac12072, + 0x128e9dcf, 0x164f8078, 0x1b0ca6a1, 0x1fcdbb16, + 0x018aeb13, 0x054bf6a4, 0x0808d07d, 0x0cc9cdca, + 0x7897ab07, 0x7c56b6b0, 0x71159069, 0x75d48dde, + 0x6b93dddb, 0x6f52c06c, 0x6211e6b5, 0x66d0fb02, + 0x5e9f46bf, 0x5a5e5b08, 0x571d7dd1, 0x53dc6066, + 0x4d9b3063, 0x495a2dd4, 0x44190b0d, 0x40d816ba, + 0xaca5c697, 0xa864db20, 0xa527fdf9, 0xa1e6e04e, + 0xbfa1b04b, 0xbb60adfc, 0xb6238b25, 0xb2e29692, + 0x8aad2b2f, 0x8e6c3698, 0x832f1041, 0x87ee0df6, + 0x99a95df3, 0x9d684044, 0x902b669d, 0x94ea7b2a, + 0xe0b41de7, 0xe4750050, 0xe9362689, 0xedf73b3e, + 0xf3b06b3b, 0xf771768c, 0xfa325055, 0xfef34de2, + 0xc6bcf05f, 0xc27dede8, 0xcf3ecb31, 0xcbffd686, + 0xd5b88683, 0xd1799b34, 0xdc3abded, 0xd8fba05a, + 0x690ce0ee, 0x6dcdfd59, 0x608edb80, 0x644fc637, + 0x7a089632, 0x7ec98b85, 0x738aad5c, 0x774bb0eb, + 0x4f040d56, 0x4bc510e1, 0x46863638, 0x42472b8f, + 0x5c007b8a, 0x58c1663d, 0x558240e4, 0x51435d53, + 0x251d3b9e, 0x21dc2629, 0x2c9f00f0, 0x285e1d47, + 0x36194d42, 0x32d850f5, 0x3f9b762c, 0x3b5a6b9b, + 0x0315d626, 0x07d4cb91, 0x0a97ed48, 0x0e56f0ff, + 0x1011a0fa, 0x14d0bd4d, 0x19939b94, 0x1d528623, + 0xf12f560e, 0xf5ee4bb9, 0xf8ad6d60, 0xfc6c70d7, + 0xe22b20d2, 0xe6ea3d65, 0xeba91bbc, 0xef68060b, + 0xd727bbb6, 0xd3e6a601, 0xdea580d8, 0xda649d6f, + 0xc423cd6a, 0xc0e2d0dd, 0xcda1f604, 0xc960ebb3, + 0xbd3e8d7e, 0xb9ff90c9, 0xb4bcb610, 0xb07daba7, + 0xae3afba2, 0xaafbe615, 0xa7b8c0cc, 0xa379dd7b, + 0x9b3660c6, 0x9ff77d71, 0x92b45ba8, 0x9675461f, + 0x8832161a, 0x8cf30bad, 0x81b02d74, 0x857130c3, + 0x5d8a9099, 0x594b8d2e, 0x5408abf7, 0x50c9b640, + 0x4e8ee645, 0x4a4ffbf2, 0x470cdd2b, 0x43cdc09c, + 0x7b827d21, 0x7f436096, 0x7200464f, 0x76c15bf8, + 0x68860bfd, 0x6c47164a, 0x61043093, 0x65c52d24, + 0x119b4be9, 0x155a565e, 0x18197087, 0x1cd86d30, + 0x029f3d35, 0x065e2082, 0x0b1d065b, 0x0fdc1bec, + 0x3793a651, 0x3352bbe6, 0x3e119d3f, 0x3ad08088, + 0x2497d08d, 0x2056cd3a, 0x2d15ebe3, 0x29d4f654, + 0xc5a92679, 0xc1683bce, 0xcc2b1d17, 0xc8ea00a0, + 0xd6ad50a5, 0xd26c4d12, 0xdf2f6bcb, 0xdbee767c, + 0xe3a1cbc1, 0xe760d676, 0xea23f0af, 0xeee2ed18, + 0xf0a5bd1d, 0xf464a0aa, 0xf9278673, 0xfde69bc4, + 0x89b8fd09, 0x8d79e0be, 0x803ac667, 0x84fbdbd0, + 0x9abc8bd5, 0x9e7d9662, 0x933eb0bb, 0x97ffad0c, + 0xafb010b1, 0xab710d06, 0xa6322bdf, 0xa2f33668, + 0xbcb4666d, 0xb8757bda, 0xb5365d03, 0xb1f740b4 +}; + +/* + +@deftypefn Extension {unsigned int} crc32 (const unsigned char *@var{buf}, @ + int @var{len}, unsigned int @var{init}) + +Compute the 32-bit CRC of @var{buf} which has length @var{len}. The +starting value is @var{init}; this may be used to compute the CRC of +data split across multiple buffers by passing the return value of each +call as the @var{init} parameter of the next. + +This is used by the @command{gdb} remote protocol for the @samp{qCRC} +command. In order to get the same results as gdb for a block of data, +you must pass the first CRC parameter as @code{0xffffffff}. + +This CRC can be specified as: + + Width : 32 + Poly : 0x04c11db7 + Init : parameter, typically 0xffffffff + RefIn : false + RefOut : false + XorOut : 0 + +This differs from the "standard" CRC-32 algorithm in that the values +are not reflected, and there is no final XOR value. These differences +make it easy to compose the values of multiple blocks. + +@end deftypefn + +*/ + +unsigned int +xcrc32 (const unsigned char *buf, int len, unsigned int init) +{ + unsigned int crc = init; + while (len--) + { + crc = (crc << 8) ^ crc32_table[((crc >> 24) ^ *buf) & 255]; + buf++; + } + return crc; +} + diff --git a/src/superio/common/ssdt.c b/src/superio/common/ssdt.c index a919aa5..6912140 100644 --- a/src/superio/common/ssdt.c +++ b/src/superio/common/ssdt.c @@ -196,7 +196,8 @@ /* Device */ acpigen_write_device(name); - acpigen_write_name_byte("_UID", 0); + acpi_device_write_uid(dev); + acpigen_write_name_byte("LDN", ldn); acpigen_write_name_byte("VLDN", vldn); -- To view, visit https://review.coreboot.org/c/coreboot/+/37695 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47cd5396060d325f9ce338afced6af021e7ff2b4 Gerrit-Change-Number: 37695 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

7 15

Change in coreboot[master]: superio/common/ssdt: Make disabled PNP devices ACPI compliant
by Patrick Rudolph (Code Review) 09 Jan '20

09 Jan '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37692 ) Change subject: superio/common/ssdt: Make disabled PNP devices ACPI compliant ...................................................................... superio/common/ssdt: Make disabled PNP devices ACPI compliant Always write a _HID, even for disabled PNP devices. Fixes a BSOD on Windows 10. Change-Id: I419a08bd6a3570fb4e1ae31bef4f9ccd6836fe1b Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/superio/common/ssdt.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/37692/1 diff --git a/src/superio/common/ssdt.c b/src/superio/common/ssdt.c index a919aa5..563178c 100644 --- a/src/superio/common/ssdt.c +++ b/src/superio/common/ssdt.c @@ -203,6 +203,9 @@ acpigen_write_STA(dev->enabled ? 0xf : 0); if (!dev->enabled) { + /* To be ACPI compliant, always write a _HID */ + acpigen_write_name_string("_HID", ACPI_HID_PNP); + acpigen_pop_len(); /* Device */ acpigen_pop_len(); /* Scope */ return; -- To view, visit https://review.coreboot.org/c/coreboot/+/37692 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I419a08bd6a3570fb4e1ae31bef4f9ccd6836fe1b Gerrit-Change-Number: 37692 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

6 10

Change in coreboot[master]: Documentation/tutorial/part1.md: Apply review comments
by Patrik Tesarik (Code Review) 09 Jan '20

09 Jan '20

Patrik Tesarik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38302 ) Change subject: Documentation/tutorial/part1.md: Apply review comments ...................................................................... Documentation/tutorial/part1.md: Apply review comments Signed-off-by: Patrik Tesarik <mail(a)patrik-tesarik.de> Change-Id: I2eb60f507bc67b3bbacaf62f958d069dc7fa0201 --- D 3rdparty/amd_blobs M Documentation/tutorial/part1.md 2 files changed, 10 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/38302/1 diff --git a/3rdparty/amd_blobs b/3rdparty/amd_blobs deleted file mode 160000 index cf22731..0000000 --- a/3rdparty/amd_blobs +++ /dev/null @@ -1 +0,0 @@ -Subproject commit cf227316b0fbd3995854ce21e81a63270b29bfb5 diff --git a/Documentation/tutorial/part1.md b/Documentation/tutorial/part1.md index 14f7604..cb0640e 100644 --- a/Documentation/tutorial/part1.md +++ b/Documentation/tutorial/part1.md @@ -9,9 +9,8 @@ ### Step 1 - Install tools and libraries needed for coreboot $ sudo apt-get install -y bison build-essential curl flex git gnat libncurses5-dev m4 zlib1g-dev - $ sudo pacman -S base-devel curl git gcc-ada ncurses zlib - $ sudo dnf install git make gcc-gnat flex bison xz bzip2 gcc g++ ncurses-devel -wget zlib-devel + $ sudo pacman -S base-devel curl git gcc-ada ncurses zlib + $ sudo dnf install git make gcc-gnat flex bison xz bzip2 gcc g++ ncurses-devel wget zlib-devel ### Step 2 - Download coreboot source tree $ git clone https://review.coreboot.org/coreboot @@ -85,12 +84,12 @@ $ sudo dnf install qemu ### Step 8 - Run QEMU -Start QEMU and point it to the ROM you just built: +Start QEMU, and point it to the ROM you just built: $ qemu-system-x86_64 -bios build/coreboot.rom -serial stdio $ qemu-system-i386 -bios build/coreboot.rom -serial stdio -You should see the serial output of coreboot in the original console window and +You should see the serial output of coreboot in the original console window and, a new window will appear running the coreinfo payload. Summary @@ -99,7 +98,7 @@ ### Step 1 summary - Install tools and libraries needed for coreboot You installed the minimum additional requirements either for Debian, CentOS or Arch based distributions to download and -build coreboot. Ubuntu and ArchLinux already has most of the other tools that +build coreboot. Ubuntu and ArchLinux already has most of the other tools that would be required installed by default. * `build-essential` or `base-devel` are the basic tools for doing builds. It @@ -110,8 +109,8 @@ are needed to build the coreboot toolchain. `gcc` and `gnat` have to be of the same version. -If you started with a different distribution that does not use apt, yum or -pacman as its package manager, you might need to install other packages. +If you started with a different distribution that does not use apt, yum or +pacman as its package manager, you might need to install other packages. Most likely they are named differently depending on your distribution. ### Step 2 summary - Download coreboot source tree @@ -162,8 +161,8 @@ displayed the contents of the rom file. ### Step 7 summary - Install QEMU -QEMU is a processor emulator which we can use to show the coreboot boot -process in a virtualised environment. +QEMU is a processor emulator which we can use to show the coreboot boot +process in a virtualised environment. ### Step 8 summary - Run QEMU Here's the command line broken down: @@ -171,7 +170,7 @@ This starts the QEMU emulator with the i440FX host PCI bridge and PIIX3 PCI to ISA bridge. * `-bios build/coreboot.rom` -Use the bios rom image that we just built. If this flag is left out, the +Use the bios rom image that we just built. If this flag is left out, the standard SeaBIOS image that comes with QEMU is used. * `-serial stdio` Send the serial output to the console. This allows you to view the coreboot -- To view, visit https://review.coreboot.org/c/coreboot/+/38302 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2eb60f507bc67b3bbacaf62f958d069dc7fa0201 Gerrit-Change-Number: 38302 Gerrit-PatchSet: 1 Gerrit-Owner: Patrik Tesarik Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: nb/intel/sandybridge: Make MCHBAR arithmetics consistent
by Angel Pons (Code Review) 09 Jan '20

09 Jan '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38206 ) Change subject: nb/intel/sandybridge: Make MCHBAR arithmetics consistent ...................................................................... nb/intel/sandybridge: Make MCHBAR arithmetics consistent Ensure that the operation order is always the same. This results in changes to the binary, but the effective result is the same. Change-Id: I9772832c60089b35889df7298e20a2bd02b35b00 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/raminit_ivy.c M src/northbridge/intel/sandybridge/raminit_sandy.c 3 files changed, 393 insertions(+), 396 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/38206/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 4d1c748..da12718 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -58,7 +58,7 @@ * Controls the idle time after issuing this DRAM command * Bit 16-32: number of clock-cylces to idle * - * DEFAULT_MCHBAR + 0x4284 + 0x400 * channel: execute command queue + * DEFAULT_MCHBAR + 0x4284 + channel * 0x400: execute command queue * Starts to execute all queued commands * Bit 0 : start DRAM command execution * Bit 18-19 : number of queued commands - 1 @@ -179,15 +179,15 @@ FOR_ALL_CHANNELS { // enable xover clk reg = get_XOVER_CLK(ctrl->rankmap[channel]); - printram("XOVER CLK [%x] = %x\n", channel * 0x100 + 0xc14, + printram("XOVER CLK [%x] = %x\n", 0xc14 + channel * 0x100, reg); - MCHBAR32(channel * 0x100 + 0xc14) = reg; + MCHBAR32(0xc14 + channel * 0x100) = reg; // enable xover ctl & xover cmd reg = get_XOVER_CMD(ctrl->rankmap[channel]); - printram("XOVER CMD [%x] = %x\n", 0x100 * channel + 0x320c, + printram("XOVER CMD [%x] = %x\n", 0x320c + channel * 0x100, reg); - MCHBAR32(0x100 * channel + 0x320c) = reg; + MCHBAR32(0x320c + channel * 0x100) = reg; } } @@ -202,14 +202,14 @@ if (IS_SANDY_CPU(cpu) && IS_SANDY_CPU_C(cpu)) { if (stretch == 2) stretch = 3; - addr = 0x401c + 0x400 * channel; + addr = 0x401c + channel * 0x400; MCHBAR32_AND_OR(addr, 0xffffc3ff, (stretch << 12) | (stretch << 10)); printk(RAM_DEBUG, "OTHP Workaround [%x] = %x\n", addr, MCHBAR32(addr)); } else { // OTHP - addr = 0x400c + 0x400 * channel; + addr = 0x400c + channel * 0x400; MCHBAR32_AND_OR(addr, 0xfff0ffff, (stretch << 16) | (stretch << 18)); printk(RAM_DEBUG, "OTHP [%x] = %x\n", addr, MCHBAR32(addr)); @@ -229,8 +229,8 @@ reg |= (ctrl->CAS << 8); reg |= (ctrl->CWL << 12); reg |= (ctrl->tRAS << 16); - printram("DBP [%x] = %x\n", TC_DBP_C0 + 0x400 * channel, reg); - MCHBAR32(TC_DBP_C0 + 0x400 * channel) = reg; + printram("DBP [%x] = %x\n", TC_DBP_C0 + channel * 0x400, reg); + MCHBAR32(TC_DBP_C0 + channel * 0x400) = reg; // RAP reg = 0; @@ -241,11 +241,11 @@ reg |= (ctrl->tFAW << 16); reg |= (ctrl->tWR << 24); reg |= (3 << 30); - printram("RAP [%x] = %x\n", TC_RAP_C0 + 0x400 * channel, reg); - MCHBAR32(TC_RAP_C0 + 0x400 * channel) = reg; + printram("RAP [%x] = %x\n", TC_RAP_C0 + channel * 0x400, reg); + MCHBAR32(TC_RAP_C0 + channel * 0x400) = reg; // OTHP - addr = 0x400 * channel + 0x400c; + addr = 0x400c + channel * 0x400; reg = 0; reg |= ctrl->tXPDLL; reg |= (ctrl->tXP << 5); @@ -254,7 +254,7 @@ printram("OTHP [%x] = %x\n", addr, reg); MCHBAR32(addr) = reg; - MCHBAR32(0x400 * channel + 0x4014) = 0; + MCHBAR32(0x4014 + channel * 0x400) = 0; MCHBAR32_OR(addr, 0x00020000); @@ -271,10 +271,10 @@ reg = ((ctrl->tREFI & 0xffff) << 0) | ((ctrl->tRFC & 0x1ff) << 16) | (((val32 / 1024) & 0x7f) << 25); - printram("REFI [%x] = %x\n", TC_RFTP_C0 + 0x400 * channel, reg); - MCHBAR32(TC_RFTP_C0 + 0x400 * channel) = reg; + printram("REFI [%x] = %x\n", TC_RFTP_C0 + channel * 0x400, reg); + MCHBAR32(TC_RFTP_C0 + channel * 0x400) = reg; - MCHBAR32_OR(TC_RFP_C0 + 0x400 * channel, 0xff); + MCHBAR32_OR(TC_RFP_C0 + channel * 0x400, 0xff); // SRFTP reg = 0; @@ -286,9 +286,9 @@ reg = (reg & ~0x3ff0000) | (val32 << 16); val32 = ctrl->tMOD - 8; reg = (reg & ~0xf0000000) | (val32 << 28); - printram("SRFTP [%x] = %x\n", 0x400 * channel + 0x42a4, + printram("SRFTP [%x] = %x\n", 0x42a4 + channel * 0x400, reg); - MCHBAR32(0x400 * channel + 0x42a4) = reg; + MCHBAR32(0x42a4 + channel * 0x400) = reg; } } @@ -618,7 +618,7 @@ static void wait_428c(int channel) { while (1) { - if (MCHBAR32(0x428c + (channel << 10)) & 0x50) + if (MCHBAR32(0x428c + channel * 0x400) & 0x50) return; } } @@ -636,13 +636,13 @@ slotrank = (ctrl->rankmap[channel] & 1) ? 0 : 2; /* DRAM command ZQCS */ - MCHBAR32(0x4220 + 0x400 * channel) = 0x0f003; - MCHBAR32(0x4230 + 0x400 * channel) = 0x80c01; - MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x60000; - MCHBAR32(0x4210 + 0x400 * channel) = 0; + MCHBAR32(0x4220 + channel * 0x400) = 0x0f003; + MCHBAR32(0x4230 + channel * 0x400) = 0x80c01; + MCHBAR32(0x4200 + channel * 0x400) = (slotrank << 24) | 0x60000; + MCHBAR32(0x4210 + channel * 0x400) = 0; // execute command queue - why is bit 22 set here?! - MCHBAR32(0x4284 + 0x400 * channel) = (1 << 22) | RUN_QUEUE_4284(1); + MCHBAR32(0x4284 + channel * 0x400) = (1 << 22) | RUN_QUEUE_4284(1); wait_428c(channel); } @@ -685,13 +685,13 @@ FOR_ALL_CHANNELS { // Set valid rank CKE reg = ctrl->rankmap[channel]; - MCHBAR32(0x42a0 + 0x400 * channel) = reg; + MCHBAR32(0x42a0 + channel * 0x400) = reg; // Wait 10ns for ranks to settle //udelay(0.01); reg = (reg & ~0xf0) | (ctrl->rankmap[channel] << 4); - MCHBAR32(0x42a0 + 0x400 * channel) = reg; + MCHBAR32(0x42a0 + channel * 0x400) = reg; // Write reset using a NOP write_reset(ctrl); @@ -726,28 +726,28 @@ } /* DRAM command MRS */ - MCHBAR32(0x4220 + 0x400 * channel) = 0x0f000; - MCHBAR32(0x4230 + 0x400 * channel) = 0x41001; - MCHBAR32(0x4200 + 0x400 * channel) = + MCHBAR32(0x4220 + channel * 0x400) = 0x0f000; + MCHBAR32(0x4230 + channel * 0x400) = 0x41001; + MCHBAR32(0x4200 + channel * 0x400) = (slotrank << 24) | (reg << 20) | val | 0x60000; - MCHBAR32(0x4210 + 0x400 * channel) = 0; + MCHBAR32(0x4210 + channel * 0x400) = 0; /* DRAM command MRS */ - MCHBAR32(0x4224 + 0x400 * channel) = 0x1f000; - MCHBAR32(0x4234 + 0x400 * channel) = 0x41001; - MCHBAR32(0x4204 + 0x400 * channel) = + MCHBAR32(0x4224 + channel * 0x400) = 0x1f000; + MCHBAR32(0x4234 + channel * 0x400) = 0x41001; + MCHBAR32(0x4204 + channel * 0x400) = (slotrank << 24) | (reg << 20) | val | 0x60000; - MCHBAR32(0x4214 + 0x400 * channel) = 0; + MCHBAR32(0x4214 + channel * 0x400) = 0; /* DRAM command MRS */ - MCHBAR32(0x4228 + 0x400 * channel) = 0x0f000; - MCHBAR32(0x4238 + 0x400 * channel) = 0x1001 | (ctrl->tMOD << 16); - MCHBAR32(0x4208 + 0x400 * channel) = + MCHBAR32(0x4228 + channel * 0x400) = 0x0f000; + MCHBAR32(0x4238 + channel * 0x400) = 0x1001 | (ctrl->tMOD << 16); + MCHBAR32(0x4208 + channel * 0x400) = (slotrank << 24) | (reg << 20) | val | 0x60000; - MCHBAR32(0x4218 + 0x400 * channel) = 0; + MCHBAR32(0x4218 + channel * 0x400) = 0; // execute command queue - MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(3); + MCHBAR32(0x4284 + channel * 0x400) = RUN_QUEUE_4284(3); } static u32 make_mr0(ramctr_timing * ctrl, u8 rank) @@ -894,7 +894,7 @@ MCHBAR32_OR(0x5030, 8); FOR_ALL_POPULATED_CHANNELS { - MCHBAR32_AND(0x4020 + 0x400 * channel, ~0x200000); + MCHBAR32_AND(0x4020 + channel * 0x400, ~0x200000); wait_428c(channel); @@ -904,14 +904,14 @@ wait_428c(channel); /* DRAM command ZQCS */ - MCHBAR32(0x4220 + 0x400 * channel) = 0x0f003; - MCHBAR32(0x4230 + 0x400 * channel) = 0x659001; - MCHBAR32(0x4200 + 0x400 * channel) = + MCHBAR32(0x4220 + channel * 0x400) = 0x0f003; + MCHBAR32(0x4230 + channel * 0x400) = 0x659001; + MCHBAR32(0x4200 + channel * 0x400) = (slotrank << 24) | 0x60000; - MCHBAR32(0x4210 + 0x400 * channel) = 0x3e0; + MCHBAR32(0x4210 + channel * 0x400) = 0x3e0; // execute command queue - MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(1); + MCHBAR32(0x4284 + channel * 0x400) = RUN_QUEUE_4284(1); // Drain wait_428c(channel); @@ -967,7 +967,7 @@ reg32 |= (slot320c[1] & 0x7f) << 18; reg32 |= (full_shift & 0x3f) | ((full_shift & 0x40) << 6); - MCHBAR32(0x320c + 0x100 * channel) = reg32; + MCHBAR32(0x320c + channel * 0x100) = reg32; /* enable CLK XOVER */ reg_c14 = get_XOVER_CLK(ctrl->rankmap[channel]); @@ -988,7 +988,7 @@ MCHBAR32(0xc14 + channel * 0x100) = reg_c14; MCHBAR32(0xc18 + channel * 0x100) = reg_c18; - reg_io_latency = MCHBAR32(SC_IO_LATENCY_C0 + 0x400 * channel); + reg_io_latency = MCHBAR32(SC_IO_LATENCY_C0 + channel * 0x400); reg_io_latency &= 0xffff0000; reg_4024 = 0; @@ -1033,7 +1033,7 @@ shift_402x) << (8 * slotrank); FOR_ALL_LANES { - MCHBAR32(lane_registers[lane] + 0x10 + 0x100 * channel + + MCHBAR32(lane_registers[lane] + 0x10 + channel * 0x100 + 4 * slotrank) = (((ctrl->timings[channel][slotrank].lanes[lane]. @@ -1048,7 +1048,7 @@ | ((ctrl->timings[channel][slotrank].lanes[lane]. falling + shift) << 20)); - MCHBAR32(lane_registers[lane] + 0x20 + 0x100 * channel + + MCHBAR32(lane_registers[lane] + 0x20 + channel * 0x100 + 4 * slotrank) = (((ctrl->timings[channel][slotrank].lanes[lane]. @@ -1064,8 +1064,8 @@ timC + shift) & 0x40) << 13)); } } - MCHBAR32(0x4024 + 0x400 * channel) = reg_4024; - MCHBAR32(SC_IO_LATENCY_C0 + 0x400 * channel) = reg_io_latency; + MCHBAR32(0x4024 + channel * 0x400) = reg_4024; + MCHBAR32(SC_IO_LATENCY_C0 + channel * 0x400) = reg_io_latency; } static void test_timA(ramctr_timing * ctrl, int channel, int slotrank) @@ -1076,32 +1076,32 @@ * write MR3 MPR enable * in this mode only RD and RDA are allowed * all reads return a predefined pattern */ - MCHBAR32(0x4220 + 0x400 * channel) = 0x1f000; - MCHBAR32(0x4230 + 0x400 * channel) = (0xc01 | (ctrl->tMOD << 16)); - MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x360004; - MCHBAR32(0x4210 + 0x400 * channel) = 0; + MCHBAR32(0x4220 + channel * 0x400) = 0x1f000; + MCHBAR32(0x4230 + channel * 0x400) = (0xc01 | (ctrl->tMOD << 16)); + MCHBAR32(0x4200 + channel * 0x400) = (slotrank << 24) | 0x360004; + MCHBAR32(0x4210 + channel * 0x400) = 0; /* DRAM command RD */ - MCHBAR32(0x4224 + 0x400 * channel) = 0x1f105; - MCHBAR32(0x4234 + 0x400 * channel) = 0x4040c01; - MCHBAR32(0x4204 + 0x400 * channel) = (slotrank << 24); - MCHBAR32(0x4214 + 0x400 * channel) = 0; + MCHBAR32(0x4224 + channel * 0x400) = 0x1f105; + MCHBAR32(0x4234 + channel * 0x400) = 0x4040c01; + MCHBAR32(0x4204 + channel * 0x400) = (slotrank << 24); + MCHBAR32(0x4214 + channel * 0x400) = 0; /* DRAM command RD */ - MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105; - MCHBAR32(0x4238 + 0x400 * channel) = 0x100f | ((ctrl->CAS + 36) << 16); - MCHBAR32(0x4208 + 0x400 * channel) = (slotrank << 24) | 0x60000; - MCHBAR32(0x4218 + 0x400 * channel) = 0; + MCHBAR32(0x4228 + channel * 0x400) = 0x1f105; + MCHBAR32(0x4238 + channel * 0x400) = 0x100f | ((ctrl->CAS + 36) << 16); + MCHBAR32(0x4208 + channel * 0x400) = (slotrank << 24) | 0x60000; + MCHBAR32(0x4218 + channel * 0x400) = 0; /* DRAM command MRS * write MR3 MPR disable */ - MCHBAR32(0x422c + 0x400 * channel) = 0x1f000; - MCHBAR32(0x423c + 0x400 * channel) = 0xc01 | (ctrl->tMOD << 16); - MCHBAR32(0x420c + 0x400 * channel) = (slotrank << 24) | 0x360000; - MCHBAR32(0x421c + 0x400 * channel) = 0; + MCHBAR32(0x422c + channel * 0x400) = 0x1f000; + MCHBAR32(0x423c + channel * 0x400) = 0xc01 | (ctrl->tMOD << 16); + MCHBAR32(0x420c + channel * 0x400) = (slotrank << 24) | 0x360000; + MCHBAR32(0x421c + channel * 0x400) = 0; // execute command queue - MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(4); + MCHBAR32(0x4284 + channel * 0x400) = RUN_QUEUE_4284(4); wait_428c(channel); } @@ -1357,13 +1357,13 @@ wait_428c(channel); /* DRAM command PREA */ - MCHBAR32(0x4220 + 0x400 * channel) = 0x1f002; - MCHBAR32(0x4230 + 0x400 * channel) = 0xc01 | (ctrl->tRP << 16); - MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x60400; - MCHBAR32(0x4210 + 0x400 * channel) = 0; + MCHBAR32(0x4220 + channel * 0x400) = 0x1f002; + MCHBAR32(0x4230 + channel * 0x400) = 0xc01 | (ctrl->tRP << 16); + MCHBAR32(0x4200 + channel * 0x400) = (slotrank << 24) | 0x60400; + MCHBAR32(0x4210 + channel * 0x400) = 0; // execute command queue - MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(1); + MCHBAR32(0x4284 + channel * 0x400) = RUN_QUEUE_4284(1); MCHBAR32(0x3400) = (slotrank << 2) | 0x8001; @@ -1442,7 +1442,7 @@ program_timings(ctrl, channel); } FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - MCHBAR32(0x4080 + 0x400 * channel + 4 * lane) = 0; + MCHBAR32(0x4080 + channel * 0x400 + lane * 4) = 0; } return 0; } @@ -1452,73 +1452,73 @@ int lane; FOR_ALL_LANES { - MCHBAR32(0x4340 + 0x400 * channel + 4 * lane) = 0; - MCHBAR32(0x4140 + 0x400 * channel + 4 * lane); + MCHBAR32(0x4340 + channel * 0x400 + lane * 4) = 0; + MCHBAR32(0x4140 + channel * 0x400 + lane * 4); } wait_428c(channel); /* DRAM command ACT */ - MCHBAR32(0x4220 + 0x400 * channel) = 0x1f006; - MCHBAR32(0x4230 + 0x400 * channel) = + MCHBAR32(0x4220 + channel * 0x400) = 0x1f006; + MCHBAR32(0x4230 + channel * 0x400) = (MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD) << 10) | 4 | (ctrl->tRCD << 16); - MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | (6 << 16); - MCHBAR32(0x4210 + 0x400 * channel) = 0x244; + MCHBAR32(0x4200 + channel * 0x400) = (slotrank << 24) | (6 << 16); + MCHBAR32(0x4210 + channel * 0x400) = 0x244; /* DRAM command NOP */ - MCHBAR32(0x4224 + 0x400 * channel) = 0x1f207; - MCHBAR32(0x4234 + 0x400 * channel) = 0x8041001; - MCHBAR32(0x4204 + 0x400 * channel) = (slotrank << 24) | 8; - MCHBAR32(0x4214 + 0x400 * channel) = 0x3e0; + MCHBAR32(0x4224 + channel * 0x400) = 0x1f207; + MCHBAR32(0x4234 + channel * 0x400) = 0x8041001; + MCHBAR32(0x4204 + channel * 0x400) = (slotrank << 24) | 8; + MCHBAR32(0x4214 + channel * 0x400) = 0x3e0; /* DRAM command WR */ - MCHBAR32(0x4228 + 0x400 * channel) = 0x1f201; - MCHBAR32(0x4238 + 0x400 * channel) = 0x80411f4; - MCHBAR32(0x4208 + 0x400 * channel) = slotrank << 24; - MCHBAR32(0x4218 + 0x400 * channel) = 0x242; + MCHBAR32(0x4228 + channel * 0x400) = 0x1f201; + MCHBAR32(0x4238 + channel * 0x400) = 0x80411f4; + MCHBAR32(0x4208 + channel * 0x400) = slotrank << 24; + MCHBAR32(0x4218 + channel * 0x400) = 0x242; /* DRAM command NOP */ - MCHBAR32(0x422c + 0x400 * channel) = 0x1f207; - MCHBAR32(0x423c + 0x400 * channel) = + MCHBAR32(0x422c + channel * 0x400) = 0x1f207; + MCHBAR32(0x423c + channel * 0x400) = 0x8000c01 | ((ctrl->CWL + ctrl->tWTR + 5) << 16); - MCHBAR32(0x420c + 0x400 * channel) = (slotrank << 24) | 8; - MCHBAR32(0x421c + 0x400 * channel) = 0x3e0; + MCHBAR32(0x420c + channel * 0x400) = (slotrank << 24) | 8; + MCHBAR32(0x421c + channel * 0x400) = 0x3e0; // execute command queue - MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(4); + MCHBAR32(0x4284 + channel * 0x400) = RUN_QUEUE_4284(4); wait_428c(channel); /* DRAM command PREA */ - MCHBAR32(0x4220 + 0x400 * channel) = 0x1f002; - MCHBAR32(0x4230 + 0x400 * channel) = 0xc01 | (ctrl->tRP << 16); - MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x60400; - MCHBAR32(0x4210 + 0x400 * channel) = 0x240; + MCHBAR32(0x4220 + channel * 0x400) = 0x1f002; + MCHBAR32(0x4230 + channel * 0x400) = 0xc01 | (ctrl->tRP << 16); + MCHBAR32(0x4200 + channel * 0x400) = (slotrank << 24) | 0x60400; + MCHBAR32(0x4210 + channel * 0x400) = 0x240; /* DRAM command ACT */ - MCHBAR32(0x4224 + 0x400 * channel) = 0x1f006; - MCHBAR32(0x4234 + 0x400 * channel) = + MCHBAR32(0x4224 + channel * 0x400) = 0x1f006; + MCHBAR32(0x4234 + channel * 0x400) = (MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1) << 10) | 8 | (ctrl->CAS << 16); - MCHBAR32(0x4204 + 0x400 * channel) = (slotrank << 24) | 0x60000; - MCHBAR32(0x4214 + 0x400 * channel) = 0x244; + MCHBAR32(0x4204 + channel * 0x400) = (slotrank << 24) | 0x60000; + MCHBAR32(0x4214 + channel * 0x400) = 0x244; /* DRAM command RD */ - MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105; - MCHBAR32(0x4238 + 0x400 * channel) = + MCHBAR32(0x4228 + channel * 0x400) = 0x1f105; + MCHBAR32(0x4238 + channel * 0x400) = 0x40011f4 | (MAX(ctrl->tRTP, 8) << 16); - MCHBAR32(0x4208 + 0x400 * channel) = (slotrank << 24); - MCHBAR32(0x4218 + 0x400 * channel) = 0x242; + MCHBAR32(0x4208 + channel * 0x400) = (slotrank << 24); + MCHBAR32(0x4218 + channel * 0x400) = 0x242; /* DRAM command PREA */ - MCHBAR32(0x422c + 0x400 * channel) = 0x1f002; - MCHBAR32(0x423c + 0x400 * channel) = 0xc01 | (ctrl->tRP << 16); - MCHBAR32(0x420c + 0x400 * channel) = (slotrank << 24) | 0x60400; - MCHBAR32(0x421c + 0x400 * channel) = 0x240; + MCHBAR32(0x422c + channel * 0x400) = 0x1f002; + MCHBAR32(0x423c + channel * 0x400) = 0xc01 | (ctrl->tRP << 16); + MCHBAR32(0x420c + channel * 0x400) = (slotrank << 24) | 0x60400; + MCHBAR32(0x421c + channel * 0x400) = 0x240; // execute command queue - MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(4); + MCHBAR32(0x4284 + channel * 0x400) = RUN_QUEUE_4284(4); wait_428c(channel); } @@ -1550,13 +1550,13 @@ wait_428c(channel); /* DRAM command PREA */ - MCHBAR32(0x4220 + 0x400 * channel) = 0x1f002; - MCHBAR32(0x4230 + 0x400 * channel) = 0xc01 | (ctrl->tRP << 16); - MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x60400; - MCHBAR32(0x4210 + 0x400 * channel) = 0x240; + MCHBAR32(0x4220 + channel * 0x400) = 0x1f002; + MCHBAR32(0x4230 + channel * 0x400) = 0xc01 | (ctrl->tRP << 16); + MCHBAR32(0x4200 + channel * 0x400) = (slotrank << 24) | 0x60400; + MCHBAR32(0x4210 + channel * 0x400) = 0x240; // execute command queue - MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(1); + MCHBAR32(0x4284 + channel * 0x400) = RUN_QUEUE_4284(1); for (timC = 0; timC <= MAX_TIMC; timC++) { FOR_ALL_LANES ctrl->timings[channel][slotrank].lanes[lane]. @@ -1567,7 +1567,7 @@ FOR_ALL_LANES { statistics[lane][timC] = - MCHBAR32(0x4340 + 4 * lane + 0x400 * channel); + MCHBAR32(0x4340 + channel * 0x400 + lane * 4); } } FOR_ALL_LANES { @@ -1656,39 +1656,39 @@ * write MR3 MPR enable * in this mode only RD and RDA are allowed * all reads return a predefined pattern */ - MCHBAR32(0x4220 + 0x400 * channel) = 0x1f000; - MCHBAR32(0x4230 + 0x400 * channel) = + MCHBAR32(0x4220 + channel * 0x400) = 0x1f000; + MCHBAR32(0x4230 + channel * 0x400) = 0xc01 | (ctrl->tMOD << 16); - MCHBAR32(0x4200 + 0x400 * channel) = + MCHBAR32(0x4200 + channel * 0x400) = (slotrank << 24) | 0x360004; - MCHBAR32(0x4210 + 0x400 * channel) = 0; + MCHBAR32(0x4210 + channel * 0x400) = 0; /* DRAM command RD */ - MCHBAR32(0x4224 + 0x400 * channel) = 0x1f105; - MCHBAR32(0x4234 + 0x400 * channel) = 0x4041003; - MCHBAR32(0x4204 + 0x400 * channel) = + MCHBAR32(0x4224 + channel * 0x400) = 0x1f105; + MCHBAR32(0x4234 + channel * 0x400) = 0x4041003; + MCHBAR32(0x4204 + channel * 0x400) = (slotrank << 24) | 0; - MCHBAR32(0x4214 + 0x400 * channel) = 0; + MCHBAR32(0x4214 + channel * 0x400) = 0; /* DRAM command RD */ - MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105; - MCHBAR32(0x4238 + 0x400 * channel) = + MCHBAR32(0x4228 + channel * 0x400) = 0x1f105; + MCHBAR32(0x4238 + channel * 0x400) = 0x1001 | ((ctrl->CAS + 8) << 16); - MCHBAR32(0x4208 + 0x400 * channel) = + MCHBAR32(0x4208 + channel * 0x400) = (slotrank << 24) | 0x60000; - MCHBAR32(0x4218 + 0x400 * channel) = 0; + MCHBAR32(0x4218 + channel * 0x400) = 0; /* DRAM command MRS * write MR3 MPR disable */ - MCHBAR32(0x422c + 0x400 * channel) = 0x1f000; - MCHBAR32(0x423c + 0x400 * channel) = + MCHBAR32(0x422c + channel * 0x400) = 0x1f000; + MCHBAR32(0x423c + channel * 0x400) = 0xc01 | (ctrl->tMOD << 16); - MCHBAR32(0x420c + 0x400 * channel) = + MCHBAR32(0x420c + channel * 0x400) = (slotrank << 24) | 0x360000; - MCHBAR32(0x421c + 0x400 * channel) = 0; + MCHBAR32(0x421c + channel * 0x400) = 0; // execute command queue - MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(4); + MCHBAR32(0x4284 + channel * 0x400) = RUN_QUEUE_4284(4); wait_428c(channel); } @@ -1708,39 +1708,39 @@ * write MR3 MPR enable * in this mode only RD and RDA are allowed * all reads return a predefined pattern */ - MCHBAR32(0x4220 + 0x400 * channel) = 0x1f000; - MCHBAR32(0x4230 + 0x400 * channel) = + MCHBAR32(0x4220 + channel * 0x400) = 0x1f000; + MCHBAR32(0x4230 + channel * 0x400) = 0xc01 | (ctrl->tMOD << 16); - MCHBAR32(0x4200 + 0x400 * channel) = + MCHBAR32(0x4200 + channel * 0x400) = (slotrank << 24) | 0x360004; - MCHBAR32(0x4210 + 0x400 * channel) = 0; + MCHBAR32(0x4210 + channel * 0x400) = 0; /* DRAM command RD */ - MCHBAR32(0x4224 + 0x400 * channel) = 0x1f105; - MCHBAR32(0x4234 + 0x400 * channel) = 0x4041003; - MCHBAR32(0x4204 + 0x400 * channel) = + MCHBAR32(0x4224 + channel * 0x400) = 0x1f105; + MCHBAR32(0x4234 + channel * 0x400) = 0x4041003; + MCHBAR32(0x4204 + channel * 0x400) = (slotrank << 24) | 0; - MCHBAR32(0x4214 + 0x400 * channel) = 0; + MCHBAR32(0x4214 + channel * 0x400) = 0; /* DRAM command RD */ - MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105; - MCHBAR32(0x4238 + 0x400 * channel) = + MCHBAR32(0x4228 + channel * 0x400) = 0x1f105; + MCHBAR32(0x4238 + channel * 0x400) = 0x1001 | ((ctrl->CAS + 8) << 16); - MCHBAR32(0x4208 + 0x400 * channel) = + MCHBAR32(0x4208 + channel * 0x400) = (slotrank << 24) | 0x60000; - MCHBAR32(0x4218 + 0x400 * channel) = 0; + MCHBAR32(0x4218 + channel * 0x400) = 0; /* DRAM command MRS * write MR3 MPR disable */ - MCHBAR32(0x422c + 0x400 * channel) = 0x1f000; - MCHBAR32(0x423c + 0x400 * channel) = + MCHBAR32(0x422c + channel * 0x400) = 0x1f000; + MCHBAR32(0x423c + channel * 0x400) = 0xc01 | (ctrl->tMOD << 16); - MCHBAR32(0x420c + 0x400 * channel) = + MCHBAR32(0x420c + channel * 0x400) = (slotrank << 24) | 0x360000; - MCHBAR32(0x421c + 0x400 * channel) = 0; + MCHBAR32(0x421c + channel * 0x400) = 0; // execute command queue - MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(4); + MCHBAR32(0x4284 + channel * 0x400) = RUN_QUEUE_4284(4); wait_428c(channel); } @@ -1755,21 +1755,21 @@ wait_428c(channel); /* DRAM command NOP */ - MCHBAR32(0x4220 + 0x400 * channel) = 0x1f207; - MCHBAR32(0x4230 + 0x400 * channel) = + MCHBAR32(0x4220 + channel * 0x400) = 0x1f207; + MCHBAR32(0x4230 + channel * 0x400) = 0x8000c01 | ((ctrl->CWL + ctrl->tWLO) << 16); - MCHBAR32(0x4200 + 0x400 * channel) = 8 | (slotrank << 24); - MCHBAR32(0x4210 + 0x400 * channel) = 0; + MCHBAR32(0x4200 + channel * 0x400) = 8 | (slotrank << 24); + MCHBAR32(0x4210 + channel * 0x400) = 0; /* DRAM command NOP */ - MCHBAR32(0x4224 + 0x400 * channel) = 0x1f107; - MCHBAR32(0x4234 + 0x400 * channel) = + MCHBAR32(0x4224 + channel * 0x400) = 0x1f107; + MCHBAR32(0x4234 + channel * 0x400) = 0x4000c01 | ((ctrl->CAS + 38) << 16); - MCHBAR32(0x4204 + 0x400 * channel) = (slotrank << 24) | 4; - MCHBAR32(0x4214 + 0x400 * channel) = 0; + MCHBAR32(0x4204 + channel * 0x400) = (slotrank << 24) | 4; + MCHBAR32(0x4214 + channel * 0x400) = 0; // execute command queue - MCHBAR32(0x400 * channel + 0x4284) = RUN_QUEUE_4284(2); + MCHBAR32(0x4284 + channel * 0x400) = RUN_QUEUE_4284(2); wait_428c(channel); @@ -1856,76 +1856,76 @@ MCHBAR32(0x3400) = 0x200; FOR_ALL_POPULATED_CHANNELS { fill_pattern1(ctrl, channel); - MCHBAR32(0x4288 + (channel << 10)) = 1; + MCHBAR32(0x4288 + channel * 0x400) = 1; } FOR_ALL_POPULATED_CHANNELS FOR_ALL_POPULATED_RANKS { - MCHBAR32(0x4288 + 0x400 * channel) = 0x10001; + MCHBAR32(0x4288 + channel * 0x400) = 0x10001; wait_428c(channel); /* DRAM command ACT */ - MCHBAR32(0x4220 + 0x400 * channel) = 0x1f006; - MCHBAR32(0x4230 + 0x400 * channel) = 0xc01 | (ctrl->tRCD << 16); - MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x60000; - MCHBAR32(0x4210 + 0x400 * channel) = 0; + MCHBAR32(0x4220 + channel * 0x400) = 0x1f006; + MCHBAR32(0x4230 + channel * 0x400) = 0xc01 | (ctrl->tRCD << 16); + MCHBAR32(0x4200 + channel * 0x400) = (slotrank << 24) | 0x60000; + MCHBAR32(0x4210 + channel * 0x400) = 0; /* DRAM command NOP */ - MCHBAR32(0x4224 + 0x400 * channel) = 0x1f207; - MCHBAR32(0x4234 + 0x400 * channel) = 0x8040c01; - MCHBAR32(0x4204 + 0x400 * channel) = (slotrank << 24) | 0x8; - MCHBAR32(0x4214 + 0x400 * channel) = 0x3e0; + MCHBAR32(0x4224 + channel * 0x400) = 0x1f207; + MCHBAR32(0x4234 + channel * 0x400) = 0x8040c01; + MCHBAR32(0x4204 + channel * 0x400) = (slotrank << 24) | 0x8; + MCHBAR32(0x4214 + channel * 0x400) = 0x3e0; /* DRAM command WR */ - MCHBAR32(0x4228 + 0x400 * channel) = 0x1f201; - MCHBAR32(0x4238 + 0x400 * channel) = 0x8041003; - MCHBAR32(0x4208 + 0x400 * channel) = (slotrank << 24); - MCHBAR32(0x4218 + 0x400 * channel) = 0x3e2; + MCHBAR32(0x4228 + channel * 0x400) = 0x1f201; + MCHBAR32(0x4238 + channel * 0x400) = 0x8041003; + MCHBAR32(0x4208 + channel * 0x400) = (slotrank << 24); + MCHBAR32(0x4218 + channel * 0x400) = 0x3e2; /* DRAM command NOP */ - MCHBAR32(0x422c + 0x400 * channel) = 0x1f207; - MCHBAR32(0x423c + 0x400 * channel) = + MCHBAR32(0x422c + channel * 0x400) = 0x1f207; + MCHBAR32(0x423c + channel * 0x400) = 0x8000c01 | ((ctrl->CWL + ctrl->tWTR + 5) << 16); - MCHBAR32(0x420c + 0x400 * channel) = (slotrank << 24) | 0x8; - MCHBAR32(0x421c + 0x400 * channel) = 0x3e0; + MCHBAR32(0x420c + channel * 0x400) = (slotrank << 24) | 0x8; + MCHBAR32(0x421c + channel * 0x400) = 0x3e0; // execute command queue - MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(4); + MCHBAR32(0x4284 + channel * 0x400) = RUN_QUEUE_4284(4); wait_428c(channel); /* DRAM command PREA */ - MCHBAR32(0x4220 + 0x400 * channel) = 0x1f002; - MCHBAR32(0x4230 + 0x400 * channel) = + MCHBAR32(0x4220 + channel * 0x400) = 0x1f002; + MCHBAR32(0x4230 + channel * 0x400) = 0xc01 | ((ctrl->tRP) << 16); - MCHBAR32(0x4200 + 0x400 * channel) = + MCHBAR32(0x4200 + channel * 0x400) = (slotrank << 24) | 0x60400; - MCHBAR32(0x4210 + 0x400 * channel) = 0x240; + MCHBAR32(0x4210 + channel * 0x400) = 0x240; /* DRAM command ACT */ - MCHBAR32(0x4224 + 0x400 * channel) = 0x1f006; - MCHBAR32(0x4234 + 0x400 * channel) = + MCHBAR32(0x4224 + channel * 0x400) = 0x1f006; + MCHBAR32(0x4234 + channel * 0x400) = 0xc01 | ((ctrl->tRCD) << 16); - MCHBAR32(0x4204 + 0x400 * channel) = (slotrank << 24) | 0x60000; - MCHBAR32(0x4214 + 0x400 * channel) = 0; + MCHBAR32(0x4204 + channel * 0x400) = (slotrank << 24) | 0x60000; + MCHBAR32(0x4214 + channel * 0x400) = 0; /* DRAM command RD */ - MCHBAR32(0x4228 + 0x400 * channel) = 0x3f105; - MCHBAR32(0x4238 + 0x400 * channel) = 0x4000c01 | ((ctrl->tRP + + MCHBAR32(0x4228 + channel * 0x400) = 0x3f105; + MCHBAR32(0x4238 + channel * 0x400) = 0x4000c01 | ((ctrl->tRP + ctrl->timings[channel][slotrank].val_4024 + ctrl->timings[channel][slotrank].io_latency) << 16); - MCHBAR32(0x4208 + 0x400 * channel) = (slotrank << 24) | 0x60008; - MCHBAR32(0x4218 + 0x400 * channel) = 0; + MCHBAR32(0x4208 + channel * 0x400) = (slotrank << 24) | 0x60008; + MCHBAR32(0x4218 + channel * 0x400) = 0; // execute command queue - MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(3); + MCHBAR32(0x4284 + channel * 0x400) = RUN_QUEUE_4284(3); wait_428c(channel); FOR_ALL_LANES { u64 res = MCHBAR32(lane_registers[lane] + - 0x100 * channel + 4); + channel * 0x100 + 4); res |= ((u64) MCHBAR32(lane_registers[lane] + - 0x100 * channel + 8)) << 32; + channel * 0x100 + 8)) << 32; old = ctrl->timings[channel][slotrank].lanes[lane].timB; ctrl->timings[channel][slotrank].lanes[lane].timB += get_timB_high_adjust(res) * 64; @@ -1950,13 +1950,13 @@ slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; /* DRAM command ACT */ - MCHBAR32(0x4220 + 0x400 * channel) = 0x0f003; - MCHBAR32(0x4230 + 0x400 * channel) = 0x41001; - MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x60000; - MCHBAR32(0x4210 + 0x400 * channel) = 0x3e0; + MCHBAR32(0x4220 + channel * 0x400) = 0x0f003; + MCHBAR32(0x4230 + channel * 0x400) = 0x41001; + MCHBAR32(0x4200 + channel * 0x400) = (slotrank << 24) | 0x60000; + MCHBAR32(0x4210 + channel * 0x400) = 0x3e0; // execute command queue - MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(1); + MCHBAR32(0x4284 + channel * 0x400) = RUN_QUEUE_4284(1); wait_428c(channel); } @@ -1979,11 +1979,11 @@ int err; FOR_ALL_POPULATED_CHANNELS - MCHBAR32_OR(0x4008 + 0x400 * channel, 0x8000000); + MCHBAR32_OR(0x4008 + channel * 0x400, 0x8000000); FOR_ALL_POPULATED_CHANNELS { write_op(ctrl, channel); - MCHBAR32_OR(0x4020 + 0x400 * channel, 0x200000); + MCHBAR32_OR(0x4020 + channel * 0x400, 0x200000); } /* refresh disable */ @@ -2025,18 +2025,18 @@ MCHBAR32_OR(0x5030, 8); FOR_ALL_POPULATED_CHANNELS { - MCHBAR32_AND(0x4020 + 0x400 * channel, ~0x00200000); - MCHBAR32(0x428c + 0x400 * channel); + MCHBAR32_AND(0x4020 + channel * 0x400, ~0x00200000); + MCHBAR32(0x428c + channel * 0x400); wait_428c(channel); /* DRAM command ZQCS */ - MCHBAR32(0x4220 + 0x400 * channel) = 0x0f003; - MCHBAR32(0x4230 + 0x400 * channel) = 0x659001; - MCHBAR32(0x4200 + 0x400 * channel) = 0x60000; - MCHBAR32(0x4210 + 0x400 * channel) = 0x3e0; + MCHBAR32(0x4220 + channel * 0x400) = 0x0f003; + MCHBAR32(0x4230 + channel * 0x400) = 0x659001; + MCHBAR32(0x4200 + channel * 0x400) = 0x60000; + MCHBAR32(0x4210 + channel * 0x400) = 0x3e0; // execute command queue - MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(1); + MCHBAR32(0x4284 + channel * 0x400) = RUN_QUEUE_4284(1); wait_428c(channel); } @@ -2048,12 +2048,12 @@ printram("CPF\n"); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - MCHBAR32_AND(0x4080 + 0x400 * channel + 4 * lane, 0); + MCHBAR32_AND(0x4080 + channel * 0x400 + lane * 4, 0); } FOR_ALL_POPULATED_CHANNELS { fill_pattern0(ctrl, channel, 0xaaaaaaaa, 0x55555555); - MCHBAR32(0x4288 + (channel << 10)) = 0; + MCHBAR32(0x4288 + channel * 0x400) = 0; } FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { @@ -2072,7 +2072,7 @@ program_timings(ctrl, channel); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - MCHBAR32_AND(0x4080 + 0x400 * channel + 4 * lane, 0); + MCHBAR32_AND(0x4080 + channel * 0x400 + lane * 4, 0); } return 0; } @@ -2095,46 +2095,46 @@ MCHBAR32(4 * lane + 0x4f40) = 0; } - MCHBAR32(0x4288 + 0x400 * channel) = 0x1f; + MCHBAR32(0x4288 + channel * 0x400) = 0x1f; wait_428c(channel); /* DRAM command ACT */ - MCHBAR32(0x4220 + 0x400 * channel) = 0x1f006; - MCHBAR32(0x4230 + 0x400 * channel) = + MCHBAR32(0x4220 + channel * 0x400) = 0x1f006; + MCHBAR32(0x4230 + channel * 0x400) = ((MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1)) << 10) | 8 | (ctrl->tRCD << 16); - MCHBAR32(0x4200 + 0x400 * channel) = + MCHBAR32(0x4200 + channel * 0x400) = (slotrank << 24) | ctr | 0x60000; - MCHBAR32(0x4210 + 0x400 * channel) = 0x244; + MCHBAR32(0x4210 + channel * 0x400) = 0x244; /* DRAM command WR */ - MCHBAR32(0x4224 + 0x400 * channel) = 0x1f201; - MCHBAR32(0x4234 + 0x400 * channel) = + MCHBAR32(0x4224 + channel * 0x400) = 0x1f201; + MCHBAR32(0x4234 + channel * 0x400) = 0x8001020 | ((ctrl->CWL + ctrl->tWTR + 8) << 16); - MCHBAR32(0x4204 + 0x400 * channel) = (slotrank << 24); - MCHBAR32(0x4244 + 0x400 * channel) = 0x389abcd; - MCHBAR32(0x4214 + 0x400 * channel) = 0x20e42; + MCHBAR32(0x4204 + channel * 0x400) = (slotrank << 24); + MCHBAR32(0x4244 + channel * 0x400) = 0x389abcd; + MCHBAR32(0x4214 + channel * 0x400) = 0x20e42; /* DRAM command RD */ - MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105; - MCHBAR32(0x4238 + 0x400 * channel) = + MCHBAR32(0x4228 + channel * 0x400) = 0x1f105; + MCHBAR32(0x4238 + channel * 0x400) = 0x4001020 | (MAX(ctrl->tRTP, 8) << 16); - MCHBAR32(0x4208 + 0x400 * channel) = (slotrank << 24); - MCHBAR32(0x4248 + 0x400 * channel) = 0x389abcd; - MCHBAR32(0x4218 + 0x400 * channel) = 0x20e42; + MCHBAR32(0x4208 + channel * 0x400) = (slotrank << 24); + MCHBAR32(0x4248 + channel * 0x400) = 0x389abcd; + MCHBAR32(0x4218 + channel * 0x400) = 0x20e42; /* DRAM command PRE */ - MCHBAR32(0x422c + 0x400 * channel) = 0x1f002; - MCHBAR32(0x423c + 0x400 * channel) = 0xf1001; - MCHBAR32(0x420c + 0x400 * channel) = (slotrank << 24) | 0x60400; - MCHBAR32(0x421c + 0x400 * channel) = 0x240; + MCHBAR32(0x422c + channel * 0x400) = 0x1f002; + MCHBAR32(0x423c + channel * 0x400) = 0xf1001; + MCHBAR32(0x420c + channel * 0x400) = (slotrank << 24) | 0x60400; + MCHBAR32(0x421c + channel * 0x400) = 0x240; // execute command queue - MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(4); + MCHBAR32(0x4284 + channel * 0x400) = RUN_QUEUE_4284(4); wait_428c(channel); FOR_ALL_LANES { - u32 r32 = MCHBAR32(0x4340 + 4 * lane + 0x400 * channel); + u32 r32 = MCHBAR32(0x4340 + channel * 0x400 + lane * 4); if (r32 == 0) lanes_ok |= 1 << lane; @@ -2192,16 +2192,16 @@ slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; /* DRAM command ZQCS */ - MCHBAR32(0x4220 + 0x400 * channel) = 0x0f003; - MCHBAR32(0x4230 + 0x400 * channel) = 0x41001; - MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x60000; - MCHBAR32(0x4210 + 0x400 * channel) = 0x3e0; + MCHBAR32(0x4220 + channel * 0x400) = 0x0f003; + MCHBAR32(0x4230 + channel * 0x400) = 0x41001; + MCHBAR32(0x4200 + channel * 0x400) = (slotrank << 24) | 0x60000; + MCHBAR32(0x4210 + channel * 0x400) = 0x3e0; // execute command queue - MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(1); + MCHBAR32(0x4284 + channel * 0x400) = RUN_QUEUE_4284(1); wait_428c(channel); - MCHBAR32_OR(0x4020 + 0x400 * channel, 0x200000); + MCHBAR32_OR(0x4020 + channel * 0x400, 0x200000); } /* refresh disable */ @@ -2213,13 +2213,13 @@ slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; /* DRAM command ZQCS */ - MCHBAR32(0x4220 + 0x400 * channel) = 0x0f003; - MCHBAR32(0x4230 + 0x400 * channel) = 0x41001; - MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x60000; - MCHBAR32(0x4210 + 0x400 * channel) = 0x3e0; + MCHBAR32(0x4220 + channel * 0x400) = 0x0f003; + MCHBAR32(0x4230 + channel * 0x400) = 0x41001; + MCHBAR32(0x4200 + channel * 0x400) = (slotrank << 24) | 0x60000; + MCHBAR32(0x4210 + channel * 0x400) = 0x3e0; // execute command queue - MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(1); + MCHBAR32(0x4284 + channel * 0x400) = RUN_QUEUE_4284(1); wait_428c(channel); } @@ -2251,7 +2251,7 @@ ctrl->cmd_stretch[channel] = cmd_stretch; - MCHBAR32(0x4004 + 0x400 * channel) = + MCHBAR32(0x4004 + channel * 0x400) = ctrl->tRRD | (ctrl->tRTP << 4) | (ctrl->tCKE << 8) @@ -2307,7 +2307,7 @@ FOR_ALL_POPULATED_CHANNELS { fill_pattern5(ctrl, channel, 0); - MCHBAR32(0x4288 + 0x400 * channel) = 0x1f; + MCHBAR32(0x4288 + channel * 0x400) = 0x1f; } FOR_ALL_POPULATED_CHANNELS { @@ -2371,8 +2371,8 @@ program_timings(ctrl, channel); FOR_ALL_LANES { - MCHBAR32(0x4340 + 0x400 * channel + 4 * lane) = 0; - MCHBAR32(0x400 * channel + 4 * lane + 0x4140); + MCHBAR32(0x4340 + channel * 0x400 + lane * 4) = 0; + MCHBAR32(0x4140 + channel * 0x400 + lane * 4); } wait_428c(channel); @@ -2380,41 +2380,41 @@ * write MR3 MPR enable * in this mode only RD and RDA are allowed * all reads return a predefined pattern */ - MCHBAR32(0x4220 + 0x400 * channel) = 0x1f000; - MCHBAR32(0x4230 + 0x400 * channel) = 0xc01 | (ctrl->tMOD << 16); - MCHBAR32(0x4200 + 0x400 * channel) = + MCHBAR32(0x4220 + channel * 0x400) = 0x1f000; + MCHBAR32(0x4230 + channel * 0x400) = 0xc01 | (ctrl->tMOD << 16); + MCHBAR32(0x4200 + channel * 0x400) = (slotrank << 24) | 0x360004; - MCHBAR32(0x4210 + 0x400 * channel) = 0; + MCHBAR32(0x4210 + channel * 0x400) = 0; /* DRAM command RD */ - MCHBAR32(0x4224 + 0x400 * channel) = 0x1f105; - MCHBAR32(0x4234 + 0x400 * channel) = 0x40411f4; - MCHBAR32(0x4204 + 0x400 * channel) = slotrank << 24; - MCHBAR32(0x4214 + 0x400 * channel) = 0; + MCHBAR32(0x4224 + channel * 0x400) = 0x1f105; + MCHBAR32(0x4234 + channel * 0x400) = 0x40411f4; + MCHBAR32(0x4204 + channel * 0x400) = slotrank << 24; + MCHBAR32(0x4214 + channel * 0x400) = 0; /* DRAM command RD */ - MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105; - MCHBAR32(0x4238 + 0x400 * channel) = + MCHBAR32(0x4228 + channel * 0x400) = 0x1f105; + MCHBAR32(0x4238 + channel * 0x400) = 0x1001 | ((ctrl->CAS + 8) << 16); - MCHBAR32(0x4208 + 0x400 * channel) = (slotrank << 24) | 0x60000; - MCHBAR32(0x4218 + 0x400 * channel) = 0; + MCHBAR32(0x4208 + channel * 0x400) = (slotrank << 24) | 0x60000; + MCHBAR32(0x4218 + channel * 0x400) = 0; /* DRAM command MRS * MR3 disable MPR */ - MCHBAR32(0x422c + 0x400 * channel) = 0x1f000; - MCHBAR32(0x423c + 0x400 * channel) = 0xc01 | (ctrl->tMOD << 16); - MCHBAR32(0x420c + 0x400 * channel) = + MCHBAR32(0x422c + channel * 0x400) = 0x1f000; + MCHBAR32(0x423c + channel * 0x400) = 0xc01 | (ctrl->tMOD << 16); + MCHBAR32(0x420c + channel * 0x400) = (slotrank << 24) | 0x360000; - MCHBAR32(0x421c + 0x400 * channel) = 0; + MCHBAR32(0x421c + channel * 0x400) = 0; // execute command queue - MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(4); + MCHBAR32(0x4284 + channel * 0x400) = RUN_QUEUE_4284(4); wait_428c(channel); FOR_ALL_LANES { statistics[lane][edge] = - MCHBAR32(0x4340 + 0x400 * channel + lane * 4); + MCHBAR32(0x4340 + channel * 0x400 + lane * 4); } } FOR_ALL_LANES { @@ -2444,14 +2444,14 @@ toggle_io_reset(); FOR_ALL_POPULATED_CHANNELS FOR_ALL_LANES { - MCHBAR32(4 * lane + 0x400 * channel + 0x4080) = 0; + MCHBAR32(0x4080 + channel * 0x400 + lane * 4) = 0; } FOR_ALL_POPULATED_CHANNELS { fill_pattern0(ctrl, channel, 0, 0); - MCHBAR32(0x4288 + (channel << 10)) = 0; + MCHBAR32(0x4288 + channel * 0x400) = 0; FOR_ALL_LANES { - MCHBAR32(0x400 * channel + lane * 4 + 0x4140); + MCHBAR32(0x4140 + channel * 0x400 + lane * 4); } FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { @@ -2471,39 +2471,39 @@ * write MR3 MPR enable * in this mode only RD and RDA are allowed * all reads return a predefined pattern */ - MCHBAR32(0x4220 + 0x400 * channel) = 0x1f000; - MCHBAR32(0x4230 + 0x400 * channel) = + MCHBAR32(0x4220 + channel * 0x400) = 0x1f000; + MCHBAR32(0x4230 + channel * 0x400) = 0xc01 | (ctrl->tMOD << 16); - MCHBAR32(0x4200 + 0x400 * channel) = + MCHBAR32(0x4200 + channel * 0x400) = (slotrank << 24) | 0x360004; - MCHBAR32(0x4210 + 0x400 * channel) = 0; + MCHBAR32(0x4210 + channel * 0x400) = 0; /* DRAM command RD */ - MCHBAR32(0x4224 + 0x400 * channel) = 0x1f105; - MCHBAR32(0x4234 + 0x400 * channel) = 0x4041003; - MCHBAR32(0x4204 + 0x400 * channel) = + MCHBAR32(0x4224 + channel * 0x400) = 0x1f105; + MCHBAR32(0x4234 + channel * 0x400) = 0x4041003; + MCHBAR32(0x4204 + channel * 0x400) = (slotrank << 24) | 0; - MCHBAR32(0x4214 + 0x400 * channel) = 0; + MCHBAR32(0x4214 + channel * 0x400) = 0; /* DRAM command RD */ - MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105; - MCHBAR32(0x4238 + 0x400 * channel) = + MCHBAR32(0x4228 + channel * 0x400) = 0x1f105; + MCHBAR32(0x4238 + channel * 0x400) = 0x1001 | ((ctrl->CAS + 8) << 16); - MCHBAR32(0x4208 + 0x400 * channel) = + MCHBAR32(0x4208 + channel * 0x400) = (slotrank << 24) | 0x60000; - MCHBAR32(0x4218 + 0x400 * channel) = 0; + MCHBAR32(0x4218 + channel * 0x400) = 0; /* DRAM command MRS * MR3 disable MPR */ - MCHBAR32(0x422c + 0x400 * channel) = 0x1f000; - MCHBAR32(0x423c + 0x400 * channel) = + MCHBAR32(0x422c + channel * 0x400) = 0x1f000; + MCHBAR32(0x423c + channel * 0x400) = 0xc01 | (ctrl->tMOD << 16); - MCHBAR32(0x420c + 0x400 * channel) = + MCHBAR32(0x420c + channel * 0x400) = (slotrank << 24) | 0x360000; - MCHBAR32(0x421c + 0x400 * channel) = 0; + MCHBAR32(0x421c + channel * 0x400) = 0; // execute command queue - MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(4); + MCHBAR32(0x4284 + channel * 0x400) = RUN_QUEUE_4284(4); wait_428c(channel); } @@ -2527,39 +2527,39 @@ * write MR3 MPR enable * in this mode only RD and RDA are allowed * all reads return a predefined pattern */ - MCHBAR32(0x4220 + 0x400 * channel) = 0x1f000; - MCHBAR32(0x4230 + 0x400 * channel) = + MCHBAR32(0x4220 + channel * 0x400) = 0x1f000; + MCHBAR32(0x4230 + channel * 0x400) = 0xc01 | (ctrl->tMOD << 16); - MCHBAR32(0x4200 + 0x400 * channel) = + MCHBAR32(0x4200 + channel * 0x400) = (slotrank << 24) | 0x360004; - MCHBAR32(0x4210 + 0x400 * channel) = 0; + MCHBAR32(0x4210 + channel * 0x400) = 0; /* DRAM command RD */ - MCHBAR32(0x4224 + 0x400 * channel) = 0x1f105; - MCHBAR32(0x4234 + 0x400 * channel) = 0x4041003; - MCHBAR32(0x4204 + 0x400 * channel) = + MCHBAR32(0x4224 + channel * 0x400) = 0x1f105; + MCHBAR32(0x4234 + channel * 0x400) = 0x4041003; + MCHBAR32(0x4204 + channel * 0x400) = (slotrank << 24) | 0; - MCHBAR32(0x4214 + 0x400 * channel) = 0; + MCHBAR32(0x4214 + channel * 0x400) = 0; /* DRAM command RD */ - MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105; - MCHBAR32(0x4238 + 0x400 * channel) = + MCHBAR32(0x4228 + channel * 0x400) = 0x1f105; + MCHBAR32(0x4238 + channel * 0x400) = 0x1001 | ((ctrl->CAS + 8) << 16); - MCHBAR32(0x4208 + 0x400 * channel) = + MCHBAR32(0x4208 + channel * 0x400) = (slotrank << 24) | 0x60000; - MCHBAR32(0x4218 + 0x400 * channel) = 0; + MCHBAR32(0x4218 + channel * 0x400) = 0; /* DRAM command MRS * MR3 disable MPR */ - MCHBAR32(0x422c + 0x400 * channel) = 0x1f000; - MCHBAR32(0x423c + 0x400 * channel) = + MCHBAR32(0x422c + channel * 0x400) = 0x1f000; + MCHBAR32(0x423c + channel * 0x400) = 0xc01 | (ctrl->tMOD << 16); - MCHBAR32(0x420c + 0x400 * channel) = + MCHBAR32(0x420c + channel * 0x400) = (slotrank << 24) | 0x360000; - MCHBAR32(0x421c + 0x400 * channel) = 0; + MCHBAR32(0x421c + channel * 0x400) = 0; // execute command queue - MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(4); + MCHBAR32(0x4284 + channel * 0x400) = RUN_QUEUE_4284(4); wait_428c(channel); } @@ -2567,13 +2567,13 @@ /* XXX: check any measured value ? */ FOR_ALL_LANES { - MCHBAR32(0x4080 + 0x400 * channel + lane * 4) = - ~MCHBAR32(0x4040 + 0x400 * channel + lane * 4) + MCHBAR32(0x4080 + channel * 0x400 + lane * 4) = + ~MCHBAR32(0x4040 + channel * 0x400 + lane * 4) & 0xff; } fill_pattern0(ctrl, channel, 0, 0xffffffff); - MCHBAR32(0x4288 + (channel << 10)) = 0; + MCHBAR32(0x4288 + channel * 0x400) = 0; } /* FIXME: under some conditions (older chipsets?) vendor BIOS sets both edges to the same value. */ @@ -2611,7 +2611,7 @@ } FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - MCHBAR32(0x4080 + 0x400 * channel + 4 * lane) = 0; + MCHBAR32(0x4080 + channel * 0x400 + lane * 4) = 0; } return 0; } @@ -2634,12 +2634,12 @@ } for (i = 0; i < 3; i++) { - MCHBAR32(0x3000 + 0x100 * channel) = reg3000b24[i] << 24; + MCHBAR32(0x3000 + channel * 0x100) = reg3000b24[i] << 24; printram("[%x] = 0x%08x\n", - 0x3000 + 0x100 * channel, reg3000b24[i] << 24); + 0x3000 + channel * 0x100, reg3000b24[i] << 24); for (pat = 0; pat < NUM_PATTERNS; pat++) { fill_pattern5(ctrl, channel, pat); - MCHBAR32(0x4288 + 0x400 * channel) = 0x1f; + MCHBAR32(0x4288 + channel * 0x400) = 0x1f; printram("using pattern %d\n", pat); for (edge = 0; edge <= MAX_EDGE_TIMING; edge++) { FOR_ALL_LANES { @@ -2651,59 +2651,56 @@ program_timings(ctrl, channel); FOR_ALL_LANES { - MCHBAR32(0x4340 + 0x400 * channel + - 4 * lane) = 0; - MCHBAR32(0x400 * channel + - 4 * lane + 0x4140); + MCHBAR32(0x4340 + channel * 0x400 + lane * 4) = 0; + MCHBAR32(0x4140 + channel * 0x400 + lane * 4); } wait_428c(channel); /* DRAM command ACT */ - MCHBAR32(0x4220 + 0x400 * channel) = 0x1f006; - MCHBAR32(0x4230 + 0x400 * channel) = + MCHBAR32(0x4220 + channel * 0x400) = 0x1f006; + MCHBAR32(0x4230 + channel * 0x400) = 0x4 | (ctrl->tRCD << 16) | (MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1) << 10); - MCHBAR32(0x4200 + 0x400 * channel) = + MCHBAR32(0x4200 + channel * 0x400) = (slotrank << 24) | 0x60000; - MCHBAR32(0x4210 + 0x400 * channel) = 0x240; + MCHBAR32(0x4210 + channel * 0x400) = 0x240; /* DRAM command WR */ - MCHBAR32(0x4224 + 0x400 * channel) = 0x1f201; - MCHBAR32(0x4234 + 0x400 * channel) = 0x8005020 | + MCHBAR32(0x4224 + channel * 0x400) = 0x1f201; + MCHBAR32(0x4234 + channel * 0x400) = 0x8005020 | ((ctrl->tWTR + ctrl->CWL + 8) << 16); - MCHBAR32(0x4204 + 0x400 * channel) = + MCHBAR32(0x4204 + channel * 0x400) = slotrank << 24; - MCHBAR32(0x4214 + 0x400 * channel) = 0x242; + MCHBAR32(0x4214 + channel * 0x400) = 0x242; /* DRAM command RD */ - MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105; - MCHBAR32(0x4238 + 0x400 * channel) = + MCHBAR32(0x4228 + channel * 0x400) = 0x1f105; + MCHBAR32(0x4238 + channel * 0x400) = 0x4005020 | (MAX(ctrl->tRTP, 8) << 16); - MCHBAR32(0x4208 + 0x400 * channel) = + MCHBAR32(0x4208 + channel * 0x400) = slotrank << 24; - MCHBAR32(0x4218 + 0x400 * channel) = 0x242; + MCHBAR32(0x4218 + channel * 0x400) = 0x242; /* DRAM command PRE */ - MCHBAR32(0x422c + 0x400 * channel) = 0x1f002; - MCHBAR32(0x423c + 0x400 * channel) = + MCHBAR32(0x422c + channel * 0x400) = 0x1f002; + MCHBAR32(0x423c + channel * 0x400) = 0xc01 | (ctrl->tRP << 16); - MCHBAR32(0x420c + 0x400 * channel) = + MCHBAR32(0x420c + channel * 0x400) = (slotrank << 24) | 0x60400; - MCHBAR32(0x421c + 0x400 * channel) = 0; + MCHBAR32(0x421c + channel * 0x400) = 0; // execute command queue - MCHBAR32(0x4284 + 0x400 * channel) = + MCHBAR32(0x4284 + channel * 0x400) = RUN_QUEUE_4284(4); wait_428c(channel); FOR_ALL_LANES { - MCHBAR32(0x4340 + - 0x400 * channel + lane * 4); + MCHBAR32(0x4340 + channel * 0x400 + lane * 4); } raw_statistics[edge] = - MCHBAR32(0x436c + 0x400 * channel); + MCHBAR32(0x436c + channel * 0x400); } FOR_ALL_LANES { struct run rn; @@ -2776,7 +2773,7 @@ program_timings(ctrl, channel); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - MCHBAR32(0x4080 + 0x400 * channel + 4 * lane) = 0; + MCHBAR32(0x4080 + channel * 0x400 + lane * 4) = 0; } return 0; } @@ -2785,36 +2782,36 @@ { wait_428c(channel); /* DRAM command ACT */ - MCHBAR32(0x4220 + 0x400 * channel) = 0x1f006; - MCHBAR32(0x4230 + 0x400 * channel) = + MCHBAR32(0x4220 + channel * 0x400) = 0x1f006; + MCHBAR32(0x4230 + channel * 0x400) = (MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD) << 10) | (ctrl->tRCD << 16) | 4; - MCHBAR32(0x4200 + 0x400 * channel) = + MCHBAR32(0x4200 + channel * 0x400) = (slotrank << 24) | 0x60000; - MCHBAR32(0x4210 + 0x400 * channel) = 0x244; + MCHBAR32(0x4210 + channel * 0x400) = 0x244; /* DRAM command WR */ - MCHBAR32(0x4224 + 0x400 * channel) = 0x1f201; - MCHBAR32(0x4234 + 0x400 * channel) = + MCHBAR32(0x4224 + channel * 0x400) = 0x1f201; + MCHBAR32(0x4234 + channel * 0x400) = 0x80011e0 | ((ctrl->tWTR + ctrl->CWL + 8) << 16); - MCHBAR32(0x4204 + 0x400 * channel) = slotrank << 24; - MCHBAR32(0x4214 + 0x400 * channel) = 0x242; + MCHBAR32(0x4204 + channel * 0x400) = slotrank << 24; + MCHBAR32(0x4214 + channel * 0x400) = 0x242; /* DRAM command RD */ - MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105; - MCHBAR32(0x4238 + 0x400 * channel) = + MCHBAR32(0x4228 + channel * 0x400) = 0x1f105; + MCHBAR32(0x4238 + channel * 0x400) = 0x40011e0 | (MAX(ctrl->tRTP, 8) << 16); - MCHBAR32(0x4208 + 0x400 * channel) = slotrank << 24; - MCHBAR32(0x4218 + 0x400 * channel) = 0x242; + MCHBAR32(0x4208 + channel * 0x400) = slotrank << 24; + MCHBAR32(0x4218 + channel * 0x400) = 0x242; /* DRAM command PRE */ - MCHBAR32(0x422c + 0x400 * channel) = 0x1f002; - MCHBAR32(0x423c + 0x400 * channel) = 0x1001 | (ctrl->tRP << 16); - MCHBAR32(0x420c + 0x400 * channel) = (slotrank << 24) | 0x60400; - MCHBAR32(0x421c + 0x400 * channel) = 0; + MCHBAR32(0x422c + channel * 0x400) = 0x1f002; + MCHBAR32(0x423c + channel * 0x400) = 0x1001 | (ctrl->tRP << 16); + MCHBAR32(0x420c + channel * 0x400) = (slotrank << 24) | 0x60400; + MCHBAR32(0x421c + channel * 0x400) = 0; // execute command queue - MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(4); + MCHBAR32(0x4284 + channel * 0x400) = RUN_QUEUE_4284(4); wait_428c(channel); } @@ -2851,7 +2848,7 @@ statistics[MAX_TIMC] = 1; fill_pattern5(ctrl, channel, pat); - MCHBAR32(0x4288 + 0x400 * channel) = + MCHBAR32(0x4288 + channel * 0x400) = 0x1f; for (timC = 0; timC < MAX_TIMC; timC++) { FOR_ALL_LANES @@ -2861,7 +2858,7 @@ test_timC_write (ctrl, channel, slotrank); raw_statistics[timC] = - MCHBAR32(0x436c + 0x400 * channel); + MCHBAR32(0x436c + channel * 0x400); } FOR_ALL_LANES { struct run rn; @@ -2895,7 +2892,7 @@ } FOR_ALL_CHANNELS { - MCHBAR32_AND((channel * 0x100) + 0xe3c, ~0x3f000000); + MCHBAR32_AND(0xe3c + (channel * 0x100), ~0x3f000000); udelay(2); } @@ -2949,9 +2946,9 @@ int channel, slotrank; FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { - MCHBAR32(0x0004 + (channel << 8) + lane_registers[slotrank]) = + MCHBAR32(0x0004 + channel * 0x100 + lane_registers[slotrank]) = make_mr0(ctrl, slotrank); - MCHBAR32(0x0008 + (channel << 8) + lane_registers[slotrank]) = + MCHBAR32(0x0008 + channel * 0x100 + lane_registers[slotrank]) = make_mr1(ctrl, slotrank, channel); } } @@ -2962,7 +2959,7 @@ slotrank = 0; FOR_ALL_POPULATED_CHANNELS - if (MCHBAR32(0x42a0 + (channel << 10)) & 0xa000) { + if (MCHBAR32(0x42a0 + channel * 0x400) & 0xa000) { printk(BIOS_EMERG, "Mini channel test failed (1): %d\n", channel); return MAKE_ERR; @@ -2970,7 +2967,7 @@ FOR_ALL_POPULATED_CHANNELS { fill_pattern0(ctrl, channel, 0x12345678, 0x98765432); - MCHBAR32(0x4288 + (channel << 10)) = 0; + MCHBAR32(0x4288 + channel * 0x400) = 0; } for (slotrank = 0; slotrank < 4; slotrank++) @@ -2983,39 +2980,39 @@ wait_428c(channel); /* DRAM command ACT */ - MCHBAR32(0x4220 + (channel << 10)) = 0x0001f006; - MCHBAR32(0x4230 + (channel << 10)) = 0x0028a004; - MCHBAR32(0x4200 + (channel << 10)) = + MCHBAR32(0x4220 + channel * 0x400) = 0x0001f006; + MCHBAR32(0x4230 + channel * 0x400) = 0x0028a004; + MCHBAR32(0x4200 + channel * 0x400) = 0x00060000 | (slotrank << 24); - MCHBAR32(0x4210 + (channel << 10)) = 0x00000244; + MCHBAR32(0x4210 + channel * 0x400) = 0x00000244; /* DRAM command WR */ - MCHBAR32(0x4224 + (channel << 10)) = 0x0001f201; - MCHBAR32(0x4234 + (channel << 10)) = 0x08281064; - MCHBAR32(0x4204 + (channel << 10)) = + MCHBAR32(0x4224 + channel * 0x400) = 0x0001f201; + MCHBAR32(0x4234 + channel * 0x400) = 0x08281064; + MCHBAR32(0x4204 + channel * 0x400) = 0x00000000 | (slotrank << 24); - MCHBAR32(0x4214 + (channel << 10)) = 0x00000242; + MCHBAR32(0x4214 + channel * 0x400) = 0x00000242; /* DRAM command RD */ - MCHBAR32(0x4228 + (channel << 10)) = 0x0001f105; - MCHBAR32(0x4238 + (channel << 10)) = 0x04281064; - MCHBAR32(0x4208 + (channel << 10)) = + MCHBAR32(0x4228 + channel * 0x400) = 0x0001f105; + MCHBAR32(0x4238 + channel * 0x400) = 0x04281064; + MCHBAR32(0x4208 + channel * 0x400) = 0x00000000 | (slotrank << 24); - MCHBAR32(0x4218 + (channel << 10)) = 0x00000242; + MCHBAR32(0x4218 + channel * 0x400) = 0x00000242; /* DRAM command PRE */ - MCHBAR32(0x422c + (channel << 10)) = 0x0001f002; - MCHBAR32(0x423c + (channel << 10)) = 0x00280c01; - MCHBAR32(0x420c + (channel << 10)) = + MCHBAR32(0x422c + channel * 0x400) = 0x0001f002; + MCHBAR32(0x423c + channel * 0x400) = 0x00280c01; + MCHBAR32(0x420c + channel * 0x400) = 0x00060400 | (slotrank << 24); - MCHBAR32(0x421c + (channel << 10)) = 0x00000240; + MCHBAR32(0x421c + channel * 0x400) = 0x00000240; // execute command queue - MCHBAR32(0x4284 + (channel << 10)) = RUN_QUEUE_4284(4); + MCHBAR32(0x4284 + channel * 0x400) = RUN_QUEUE_4284(4); wait_428c(channel); FOR_ALL_LANES - if (MCHBAR32(0x4340 + (channel << 10) + 4 * lane)) { + if (MCHBAR32(0x4340 + channel * 0x400 + lane * 4)) { printk(BIOS_EMERG, "Mini channel test failed (2): %d, %d, %d\n", channel, slotrank, lane); return MAKE_ERR; @@ -3035,10 +3032,10 @@ {0x00028bfa, 0x53fe4b49, 0x19ed5483} }; FOR_ALL_POPULATED_CHANNELS { - MCHBAR32(0x4020 + 0x400 * channel) &= ~0x10000000; - MCHBAR32(0x4034 + 0x400 * channel) = seeds[channel][0]; - MCHBAR32(0x403c + 0x400 * channel) = seeds[channel][1]; - MCHBAR32(0x4038 + 0x400 * channel) = seeds[channel][2]; + MCHBAR32(0x4020 + channel * 0x400) &= ~0x10000000; + MCHBAR32(0x4034 + channel * 0x400) = seeds[channel][0]; + MCHBAR32(0x403c + channel * 0x400) = seeds[channel][1]; + MCHBAR32(0x4038 + channel * 0x400) = seeds[channel][2]; } } @@ -3060,7 +3057,7 @@ FOR_ALL_POPULATED_CHANNELS { // Always drive command bus - MCHBAR32_OR(0x4004 + 0x400 * channel, 0x20000000); + MCHBAR32_OR(0x4004 + channel * 0x400, 0x20000000); } udelay(1); @@ -3096,7 +3093,7 @@ dram_odt_stretch(ctrl, channel); - MCHBAR32(0x4008 + (channel << 10)) = + MCHBAR32(0x4008 + channel * 0x400) = 0x0a000000 | (b20 << 20) | ((ctrl->ref_card_offset[channel] + 2) << 16) | b4_8_12; } @@ -3106,9 +3103,9 @@ { int channel; FOR_ALL_POPULATED_CHANNELS { - MCHBAR32(0x42a0 + 0x400 * channel) = + MCHBAR32(0x42a0 + channel * 0x400) = 0x00001000 | ctrl->rankmap[channel]; - MCHBAR32_AND(0x4004 + 0x400 * channel, ~0x20000000); + MCHBAR32_AND(0x4004 + channel * 0x400, ~0x20000000); } } @@ -3130,7 +3127,7 @@ MCHBAR32(0x4cd4) = 0x00000046; FOR_ALL_CHANNELS - MCHBAR32_AND_OR(0x400c + 0x400 * channel, 0xFFFFCFFF, 0x1000); + MCHBAR32_AND_OR(0x400c + channel * 0x400, 0xFFFFCFFF, 0x1000); if (is_mobile) /* APD - DLL Off, 64 DCLKs until idle, decision per rank */ @@ -3169,7 +3166,7 @@ MCHBAR32_AND(MEM_TRML_INTERRUPT, ~0x1f); FOR_ALL_CHANNELS - MCHBAR32_AND_OR(TC_RFP_C0 + 0x400 * channel, ~0x30000, 1 << 16); + MCHBAR32_AND_OR(TC_RFP_C0 + channel * 0x400, ~0x30000, 1 << 16); MCHBAR32_OR(0x5030, 1); MCHBAR32_OR(0x5030, 0x80); @@ -3183,7 +3180,7 @@ r32 = MCHBAR32(0x5064); if (r32 & 0x20000) t1_cycles += (r32 & 0xfff); - t1_cycles += MCHBAR32(channel * 0x400 + 0x42a4) & 0xfff; + t1_cycles += MCHBAR32(0x42a4 + channel * 0x400) & 0xfff; t1_ns = t1_cycles * ctrl->tCK / 256 + 544; if (!(r32 & 0x20000)) t1_ns += 500; @@ -3211,7 +3208,7 @@ int channel, slotrank, lane; FOR_ALL_POPULATED_CHANNELS - MCHBAR32(0x4004 + 0x400 * channel) = + MCHBAR32(0x4004 + channel * 0x400) = ctrl->tRRD | (ctrl->tRTP << 4) | (ctrl->tCKE << 8) @@ -3227,15 +3224,15 @@ } FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - MCHBAR32(0x4080 + 0x400 * channel + 4 * lane) = 0; + MCHBAR32(0x4080 + channel * 0x400 + lane * 4) = 0; } FOR_ALL_POPULATED_CHANNELS - MCHBAR32_OR(0x4008 + 0x400 * channel, 0x8000000); + MCHBAR32_OR(0x4008 + channel * 0x400, 0x8000000); FOR_ALL_POPULATED_CHANNELS { udelay (1); - MCHBAR32_OR(0x4020 + 0x400 * channel, 0x200000); + MCHBAR32_OR(0x4020 + channel * 0x400, 0x200000); } printram("CPE\n"); @@ -3267,7 +3264,7 @@ // Set valid rank CKE reg = 0; reg = (reg & ~0xf) | ctrl->rankmap[channel]; - addr = 0x400 * channel + 0x42a0; + addr = 0x42a0 + channel * 0x400; MCHBAR32(addr) = reg; // Wait 10ns for ranks to settle @@ -3288,7 +3285,7 @@ MCHBAR32(0x3000) = 0; FOR_ALL_CHANNELS { - MCHBAR32_AND(channel * 0x100 + 0xe3c, ~0x3f000000); + MCHBAR32_AND(0xe3c + channel * 0x100, ~0x3f000000); udelay(2); } diff --git a/src/northbridge/intel/sandybridge/raminit_ivy.c b/src/northbridge/intel/sandybridge/raminit_ivy.c index 5c1a58a..7542a37 100644 --- a/src/northbridge/intel/sandybridge/raminit_ivy.c +++ b/src/northbridge/intel/sandybridge/raminit_ivy.c @@ -590,12 +590,12 @@ // IO clock FOR_ALL_CHANNELS { - MCHBAR32(0xc00 + 0x100 * channel) = ctrl->rankmap[channel]; + MCHBAR32(0xc00 + channel * 0x100) = ctrl->rankmap[channel]; } // IO command FOR_ALL_CHANNELS { - MCHBAR32(0x3200 + 0x100 * channel) = ctrl->rankmap[channel]; + MCHBAR32(0x3200 + channel * 0x100) = ctrl->rankmap[channel]; } // IO control diff --git a/src/northbridge/intel/sandybridge/raminit_sandy.c b/src/northbridge/intel/sandybridge/raminit_sandy.c index 9fa6c7b..1191754 100644 --- a/src/northbridge/intel/sandybridge/raminit_sandy.c +++ b/src/northbridge/intel/sandybridge/raminit_sandy.c @@ -361,12 +361,12 @@ // IO clock FOR_ALL_CHANNELS { - MCHBAR32(0xc00 + 0x100 * channel) = ctrl->rankmap[channel]; + MCHBAR32(0xc00 + channel * 0x100) = ctrl->rankmap[channel]; } // IO command FOR_ALL_CHANNELS { - MCHBAR32(0x3200 + 0x100 * channel) = ctrl->rankmap[channel]; + MCHBAR32(0x3200 + channel * 0x100) = ctrl->rankmap[channel]; } // IO control -- To view, visit https://review.coreboot.org/c/coreboot/+/38206 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9772832c60089b35889df7298e20a2bd02b35b00 Gerrit-Change-Number: 38206 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: doc/tutorial/part1.md: Add information for yum- & pacman-based distro
by Patrik Tesarik (Code Review) 09 Jan '20

09 Jan '20

Hello Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/38225 to look at the new patch set (#2). Change subject: doc/tutorial/part1.md: Add information for yum- & pacman-based distro ...................................................................... doc/tutorial/part1.md: Add information for yum- & pacman-based distro * Additional information on non-debian cli tools * Improve Spellings and descriptions to the best of my knowledge Adding info about needed tools in other distribution's package managers was requested at the coreboot beginner's workshop at 36C3. Change-Id: Ifff3c8354b4bec9f195f075eb6b2f377195fc237 Signed-off-by: Patrik Tesarik <mail(a)patrik-tesarik.de> --- M Documentation/tutorial/part1.md 1 file changed, 26 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/38225/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/38225 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifff3c8354b4bec9f195f075eb6b2f377195fc237 Gerrit-Change-Number: 38225 Gerrit-PatchSet: 2 Gerrit-Owner: Patrik Tesarik Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrik Tesarik Gerrit-CC: Marcello Sylvester Bauer <sylv(a)sylv.io> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/tigerlake: Update GPIO config
by Furquan Shaikh (Code Review) 09 Jan '20

09 Jan '20

1 0

Change in coreboot[master]: soc/intel/tigerlake: Update GPIO config
by Furquan Shaikh (Code Review) 09 Jan '20

09 Jan '20

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37427 ) Change subject: soc/intel/tigerlake: Update GPIO config ...................................................................... Patch Set 16: (3 comments) https://review.coreboot.org/c/coreboot/+/37427/16/src/soc/intel/tigerlake/a… File src/soc/intel/tigerlake/acpi/gpio.asl: https://review.coreboot.org/c/coreboot/+/37427/16/src/soc/intel/tigerlake/a… PS16, Line 20: Device (GPIO) So, I was looking at the latest version of pinctrl-tigerlake.c driver and one thing that I noticed was that it uses uid for each community e.g. https://github.com/torvalds/linux/blob/master/drivers/pinctrl/intel/pinctrl… This means that the way we have exported GPIO device on CNL and SKL/KBL will not work for TGL. Instead each community will have to be described as its own device with a different UID. Something like this should work: Device (GCM0) { » Name (_HID, "INT34C5") » Name (_UID, 0) » Name (_DDN, "GPIO Controller Community 0") » Name (RBUF, ResourceTemplate() » { » » Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM0) » » Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) » » » { GPIO_IRQ14 } » }) » Method (_CRS, 0, NotSerialized) » { » » CreateDWordField (^RBUF, ^COM0._BAS, BAS0) » » BAS0 = ^^PCRB (PID_GPIOCOM0) » » Return (^RBUF) » } » Method (_STA) » { » » Return (0xF) » } } Device (GCM1) { » Name (_HID, "INT34C5") » Name (_UID, 1) » Name (_DDN, "GPIO Controller Community 1") » Name (RBUF, ResourceTemplate() » { » » Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM1) » » Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) » » » { GPIO_IRQ14 } » }) » Method (_CRS, 0, NotSerialized) » { » » CreateDWordField (^RBUF, ^COM1._BAS, BAS1) » » BAS1 = ^^PCRB (PID_GPIOCOM1) » » Return (^RBUF) » } » Method (_STA) » { » » Return (0xF) » } } Device (GCM4) { » Name (_HID, "INT34C5") » Name (_UID, 4) » Name (_DDN, "GPIO Controller Community 4") » Name (RBUF, ResourceTemplate() » { » » Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM4) » » Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) » » » { GPIO_IRQ14 } » }) » Method (_CRS, 0, NotSerialized) » { » » CreateDWordField (^RBUF, ^COM4._BAS, BAS4) » » BAS4 = ^^PCRB (PID_GPIOCOM4) » » Return (^RBUF) » } » Method (_STA) » { » » Return (0xF) » } } Device (GCM5) { » Name (_HID, "INT34C5") » Name (_UID, 5) » Name (_DDN, "GPIO Controller Community 5") » Name (RBUF, ResourceTemplate() » { » » Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM5) » » Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) » » » { GPIO_IRQ14 } » }) » Method (_CRS, 0, NotSerialized) » { » » CreateDWordField (^RBUF, ^COM5._BAS, BAS5) » » BAS5 = ^^PCRB (PID_GPIOCOM5) » » Return (^RBUF) » } » Method (_STA) » { » » Return (0xF) » } } https://review.coreboot.org/c/coreboot/+/37427/16/src/soc/intel/tigerlake/g… File src/soc/intel/tigerlake/gpio.c: https://review.coreboot.org/c/coreboot/+/37427/16/src/soc/intel/tigerlake/g… PS16, Line 197: { PMC_GPP_G, GPP_G }, > I dont see these groups in EDS.SO i would guess for this version of silicon its not possible. […] Ack https://review.coreboot.org/c/coreboot/+/37427/16/src/soc/intel/tigerlake/i… File src/soc/intel/tigerlake/include/soc/gpio.h: https://review.coreboot.org/c/coreboot/+/37427/16/src/soc/intel/tigerlake/i… PS16, Line 22: CROS_GPIO_DEVICE_NAME This will have to be provided for each community device as per the comment on gpio.asl file. -- To view, visit https://review.coreboot.org/c/coreboot/+/37427 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I585100375feee39b5a9105bdf6d9f5ca3a5bb2fa Gerrit-Change-Number: 37427 Gerrit-PatchSet: 16 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Venkata Krishna Nimmagadda Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 09 Jan 2020 12:33:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shaunak Saha <shaunak.saha(a)intel.com> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/tglrvp: Add initial mainboard code
by Wonkyu Kim (Code Review) 09 Jan '20

09 Jan '20

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37868 ) Change subject: mb/intel/tglrvp: Add initial mainboard code ...................................................................... Patch Set 14: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/37868 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I86ada611de1cf28a1b872eea35cf41c0dc1c57f1 Gerrit-Change-Number: 37868 Gerrit-PatchSet: 14 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 09 Jan 2020 10:24:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: util/inteltool: Add GPIO dumping capabilites for Ice Lake U systems
by Mimoja (Code Review) 09 Jan '20

09 Jan '20

Mimoja has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38175 ) Change subject: util/inteltool: Add GPIO dumping capabilites for Ice Lake U systems ...................................................................... Patch Set 9: Can we give this a bit of momentum? I think we should make a decision if the spec and my testing are enought QA for us.. I could add an "GPIO Dumping on this PCH was not verified by two independent sources. Be carefull" disclaimer or somthings alike. But tbh I dont think that is necessary ;) -- To view, visit https://review.coreboot.org/c/coreboot/+/38175 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib40f1dbae57169678e92ea9ad0df60ff91b5b22c Gerrit-Change-Number: 38175 Gerrit-PatchSet: 9 Gerrit-Owner: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jeremy Soller <jeremy(a)system76.com> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Thu, 09 Jan 2020 09:38:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/{cnl,icl,tgl}: Move northbridge.asl into common/block/acpi
by Subrata Banik (Code Review) 09 Jan '20

09 Jan '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38155 ) Change subject: soc/intel/{cnl,icl,tgl}: Move northbridge.asl into common/block/acpi ...................................................................... soc/intel/{cnl,icl,tgl}: Move northbridge.asl into common/block/acpi This patch creates a common instance of northbridge.asl inside intel common code (soc/intel/common/block/acpi/acpi) and ask cnl & icl soc code to refer northbridge.asl from common code block. TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify Device(MCHC) presence after booting to OS. Change-Id: Ib9af844bcbbcce3f4b0ac7aada43d43e4171e08b Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/mainboard/google/dragonegg/dsdt.asl M src/mainboard/google/drallion/dsdt.asl M src/mainboard/google/hatch/dsdt.asl M src/mainboard/google/sarien/dsdt.asl M src/mainboard/intel/cannonlake_rvp/dsdt.asl M src/mainboard/intel/coffeelake_rvp/dsdt.asl M src/mainboard/intel/icelake_rvp/dsdt.asl M src/mainboard/intel/jasperlake_rvp/dsdt.asl D src/soc/intel/cannonlake/acpi/northbridge.asl R src/soc/intel/common/block/acpi/acpi/northbridge.asl D src/soc/intel/tigerlake/acpi/northbridge.asl 11 files changed, 9 insertions(+), 656 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/38155/1 diff --git a/src/mainboard/google/dragonegg/dsdt.asl b/src/mainboard/google/dragonegg/dsdt.asl index 24814da..f84b0b5 100644 --- a/src/mainboard/google/dragonegg/dsdt.asl +++ b/src/mainboard/google/dragonegg/dsdt.asl @@ -37,7 +37,7 @@ Scope (\_SB) { Device (PCI0) { - #include <soc/intel/icelake/acpi/northbridge.asl> + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> #include <soc/intel/icelake/acpi/southbridge.asl> } } diff --git a/src/mainboard/google/drallion/dsdt.asl b/src/mainboard/google/drallion/dsdt.asl index 78c6c16..ee63d6e 100644 --- a/src/mainboard/google/drallion/dsdt.asl +++ b/src/mainboard/google/drallion/dsdt.asl @@ -36,7 +36,7 @@ Scope (\_SB) { Device (PCI0) { - #include <soc/intel/cannonlake/acpi/northbridge.asl> + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> #include <soc/intel/cannonlake/acpi/southbridge.asl> } /* Per board variant mainboard hooks. */ diff --git a/src/mainboard/google/hatch/dsdt.asl b/src/mainboard/google/hatch/dsdt.asl index 1a0ff68..16a8a66 100644 --- a/src/mainboard/google/hatch/dsdt.asl +++ b/src/mainboard/google/hatch/dsdt.asl @@ -37,7 +37,7 @@ Scope (\_SB) { Device (PCI0) { - #include <soc/intel/cannonlake/acpi/northbridge.asl> + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> #include <soc/intel/cannonlake/acpi/southbridge.asl> } } diff --git a/src/mainboard/google/sarien/dsdt.asl b/src/mainboard/google/sarien/dsdt.asl index a809b75..c32470e 100644 --- a/src/mainboard/google/sarien/dsdt.asl +++ b/src/mainboard/google/sarien/dsdt.asl @@ -36,7 +36,7 @@ Scope (\_SB) { Device (PCI0) { - #include <soc/intel/cannonlake/acpi/northbridge.asl> + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> #include <soc/intel/cannonlake/acpi/southbridge.asl> } /* Per board variant mainboard hooks. */ diff --git a/src/mainboard/intel/cannonlake_rvp/dsdt.asl b/src/mainboard/intel/cannonlake_rvp/dsdt.asl index 26f1565..c6070dd 100644 --- a/src/mainboard/intel/cannonlake_rvp/dsdt.asl +++ b/src/mainboard/intel/cannonlake_rvp/dsdt.asl @@ -33,7 +33,7 @@ Scope (\_SB) { Device (PCI0) { - #include <soc/intel/cannonlake/acpi/northbridge.asl> + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> #include <soc/intel/cannonlake/acpi/southbridge.asl> } } diff --git a/src/mainboard/intel/coffeelake_rvp/dsdt.asl b/src/mainboard/intel/coffeelake_rvp/dsdt.asl index 58a10d9..316fe55 100644 --- a/src/mainboard/intel/coffeelake_rvp/dsdt.asl +++ b/src/mainboard/intel/coffeelake_rvp/dsdt.asl @@ -33,7 +33,7 @@ Scope (\_SB) { Device (PCI0) { - #include <soc/intel/cannonlake/acpi/northbridge.asl> + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> #include <soc/intel/cannonlake/acpi/southbridge.asl> } } diff --git a/src/mainboard/intel/icelake_rvp/dsdt.asl b/src/mainboard/intel/icelake_rvp/dsdt.asl index 2eab610..5d730ba 100644 --- a/src/mainboard/intel/icelake_rvp/dsdt.asl +++ b/src/mainboard/intel/icelake_rvp/dsdt.asl @@ -37,7 +37,7 @@ Scope (\_SB) { Device (PCI0) { - #include <soc/intel/icelake/acpi/northbridge.asl> + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> #include <soc/intel/icelake/acpi/southbridge.asl> } } diff --git a/src/mainboard/intel/jasperlake_rvp/dsdt.asl b/src/mainboard/intel/jasperlake_rvp/dsdt.asl index 6e11944..559e1e3 100644 --- a/src/mainboard/intel/jasperlake_rvp/dsdt.asl +++ b/src/mainboard/intel/jasperlake_rvp/dsdt.asl @@ -38,7 +38,7 @@ Scope (\_SB) { Device (PCI0) { - #include <soc/intel/tigerlake/acpi/northbridge.asl> + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> #include <soc/intel/tigerlake/acpi/southbridge.asl> } } diff --git a/src/soc/intel/cannonlake/acpi/northbridge.asl b/src/soc/intel/cannonlake/acpi/northbridge.asl deleted file mode 100644 index ead5c02..0000000 --- a/src/soc/intel/cannonlake/acpi/northbridge.asl +++ /dev/null @@ -1,324 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2017-2020 Intel Corp. - * (Written by Bora Guvendik <bora.guvendik(a)intel.com> for Intel Corp.) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <soc/iomap.h> - -#define BASE_32GB 0x800000000 -#define SIZE_16GB 0x400000000 - -Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID -Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID -Name (_SEG, Zero) // _SEG: PCI Segment -Name (_UID, Zero) // _UID: Unique ID - -Device (MCHC) -{ - Name (_ADR, 0x00000000) - - OperationRegion (MCHP, PCI_Config, 0x00, 0x100) - Field (MCHP, DWordAcc, NoLock, Preserve) - { - Offset(0x40), /* EPBAR (0:0:0:40) */ - EPEN, 1, /* Enable */ - , 11, - EPBR, 20, /* EPBAR [31:12] */ - - Offset(0x48), /* MCHBAR (0:0:0:48) */ - MHEN, 1, /* Enable */ - , 14, - MHBR, 17, /* MCHBAR [31:15] */ - - Offset(0x60), /* PCIEXBAR (0:0:0:60) */ - PXEN, 1, /* Enable */ - PXSZ, 2, /* PCI Express Size */ - , 23, - PXBR, 6, /* PCI Express BAR [31:26] */ - - Offset(0x68), /* DMIBAR (0:0:0:68) */ - DIEN, 1, /* Enable */ - , 11, - DIBR, 20, /* DMIBAR [31:12] */ - - Offset (0xa0), - TOM, 64, /* Top of Used Memory */ - TUUD, 64, /* Top of Upper Used Memory */ - - Offset (0xbc), /* Top of Low Used Memory */ - TLUD, 32, - } -} - -Method (_CRS, 0, Serialized) -{ - Name (MCRS, ResourceTemplate () - { - /* Bus Numbers */ - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100) - - /* IO Region 0 */ - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, - EntireRange, - 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8) - - /* PCI Config Space */ - Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) - - /* IO Region 1 */ - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, - EntireRange, - 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300) - - /* VGA memory (0xa0000-0xbffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, - 0x00020000) - - /* OPROM reserved (0xc0000-0xc3fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xc4000-0xc7fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xc8000-0xcbfff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xcc000-0xcffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xd0000-0xd3fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xd4000-0xd7fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xd8000-0xdbfff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xdc000-0xdffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, - 0x00004000) - - /* BIOS Extension (0xe0000-0xe3fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, - 0x00004000) - - /* BIOS Extension (0xe4000-0xe7fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, - 0x00004000) - - /* BIOS Extension (0xe8000-0xebfff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, - 0x00004000) - - /* BIOS Extension (0xec000-0xeffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000ec000, 0x000effff, 0x00000000, - 0x00004000) - - /* System BIOS (0xf0000-0xfffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, - 0x00010000) - - /* PCI Memory Region (TLUD - 0xdfffffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - NonCacheable, ReadWrite, - 0x00000000, 0x00000000, 0xdfffffff, 0x00000000, - 0xE0000000,,, PM01) - - /* PCI Memory Region (TUUD - (TUUD + ABOVE_4G_MMIO_SIZE)) */ - QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - NonCacheable, ReadWrite, - 0x00000000, 0x10000, 0x1ffff, 0x00000000, - 0x10000,,, PM02) - - /* PCH reserved resource (0xfc800000-0xfe7fffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, PCH_PRESERVED_BASE_ADDRESS, 0xfe7fffff, - 0x00000000, PCH_PRESERVED_BASE_SIZE) - - /* TPM Area (0xfed40000-0xfed47fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0xfed40000, 0xfed47fff, 0x00000000, - 0x00008000) - }) - - /* Find PCI resource area in MCRS */ - CreateDwordField (MCRS, PM01._MIN, PMIN) - CreateDwordField (MCRS, PM01._MAX, PMAX) - CreateDwordField (MCRS, PM01._LEN, PLEN) - - /* - * Fix up PCI memory region - * Start with Top of Lower Usable DRAM - */ - Store (\_SB.PCI0.MCHC.TLUD, PMIN) - Add (Subtract (PMAX, PMIN), 1, PLEN) - - /* Patch PM02 range based on Memory Size */ - CreateQwordField (MCRS, PM02._MIN, MMIN) - CreateQwordField (MCRS, PM02._MAX, MMAX) - CreateQwordField (MCRS, PM02._LEN, MLEN) - - Store (\_SB.PCI0.MCHC.TUUD, Local0) - - If (LLessEqual (Local0, BASE_32GB)) { - Store (BASE_32GB, MMIN) - Store (SIZE_16GB, MLEN) - } Else { - Store (0, MMIN) - Store (0, MLEN) - } - Subtract (Add (MMIN, MLEN), 1, MMAX) - - Return (MCRS) -} - -/* Get MCH BAR */ -Method (GMHB, 0, Serialized) -{ - ShiftLeft (\_SB.PCI0.MCHC.MHBR, 15, Local0) - Return (Local0) -} - -/* Get EP BAR */ -Method (GEPB, 0, Serialized) -{ - ShiftLeft (\_SB.PCI0.MCHC.EPBR, 12, Local0) - Return (Local0) -} - -/* Get PCIe BAR */ -Method (GPCB, 0, Serialized) -{ - ShiftLeft (\_SB.PCI0.MCHC.PXBR, 26, Local0) - Return (Local0) -} - -/* Get PCIe Length */ -Method (GPCL, 0, Serialized) -{ - ShiftRight (0x10000000, \_SB.PCI0.MCHC.PXSZ, Local0) - Return (Local0) -} - -/* Get DMI BAR */ -Method (GDMB, 0, Serialized) -{ - ShiftLeft (\_SB.PCI0.MCHC.DIBR, 12, Local0) - Return (Local0) -} - -/* PCI Device Resource Consumption */ -Device (PDRC) -{ - Name (_HID, EISAID ("PNP0C02")) - Name (_UID, 1) - - Method (_CRS, 0, Serialized) - { - Name (BUF0, ResourceTemplate () - { - /* MCH BAR _BAS will be updated in _CRS below according to - * B0:D0:F0:Reg.48h - */ - Memory32Fixed (ReadWrite, 0, 0x08000, MCHB) - - /* DMI BAR _BAS will be updated in _CRS below according to - * B0:D0:F0:Reg.68h - */ - Memory32Fixed (ReadWrite, 0, 0x01000, DMIB) - - /* EP BAR _BAS will be updated in _CRS below according to - * B0:D0:F0:Reg.40h - */ - Memory32Fixed (ReadWrite, 0, 0x01000, EGPB) - - /* PCI Express BAR _BAS and _LEN will be updated in - * _CRS below according to B0:D0:F0:Reg.60h - */ - Memory32Fixed (ReadWrite, 0, 0, PCIX) - - /* VTD engine memory range. */ - Memory32Fixed (ReadOnly, VTD_BASE_ADDRESS, VTD_BASE_SIZE) - - /* FLASH range */ - Memory32Fixed (ReadOnly, 0, CONFIG_ROM_SIZE, FIOH) - - /* Local APIC range(0xFEE0_0000 to 0xFEEF_FFFF) */ - Memory32Fixed (ReadOnly, 0xFEE00000, 0x100000) - - /* HPET address decode range */ - Memory32Fixed (ReadWrite, HPET_BASE_ADDRESS, 0x400) - }) - - CreateDwordField (BUF0, MCHB._BAS, MBR0) - Store (\_SB.PCI0.GMHB (), MBR0) - - CreateDwordField (BUF0, DMIB._BAS, DBR0) - Store (\_SB.PCI0.GDMB (), DBR0) - - CreateDwordField (BUF0, EGPB._BAS, EBR0) - Store (\_SB.PCI0.GEPB (), EBR0) - - CreateDwordField (BUF0, PCIX._BAS, XBR0) - Store (\_SB.PCI0.GPCB (), XBR0) - - CreateDwordField (BUF0, PCIX._LEN, XSZ0) - Store (\_SB.PCI0.GPCL (), XSZ0) - - CreateDwordField (BUF0, FIOH._BAS, FBR0) - Subtract(0x100000000, CONFIG_ROM_SIZE, FBR0) - - Return (BUF0) - } -} diff --git a/src/soc/intel/icelake/acpi/northbridge.asl b/src/soc/intel/common/block/acpi/acpi/northbridge.asl similarity index 99% rename from src/soc/intel/icelake/acpi/northbridge.asl rename to src/soc/intel/common/block/acpi/acpi/northbridge.asl index 6842021..2372e79 100644 --- a/src/soc/intel/icelake/acpi/northbridge.asl +++ b/src/soc/intel/common/block/acpi/acpi/northbridge.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018-2020 Intel Corp. + * Copyright (C) 2020 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/acpi/northbridge.asl b/src/soc/intel/tigerlake/acpi/northbridge.asl deleted file mode 100644 index 149839d..0000000 --- a/src/soc/intel/tigerlake/acpi/northbridge.asl +++ /dev/null @@ -1,323 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2019-2020 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <soc/iomap.h> - -#define BASE_32GB 0x800000000 -#define SIZE_16GB 0x400000000 - -Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID -Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID -Name (_SEG, Zero) // _SEG: PCI Segment -Name (_UID, Zero) // _UID: Unique ID - -Device (MCHC) -{ - Name (_ADR, 0x00000000) - - OperationRegion (MCHP, PCI_Config, 0x00, 0x100) - Field (MCHP, DWordAcc, NoLock, Preserve) - { - Offset(0x40), /* EPBAR (0:0:0:40) */ - EPEN, 1, /* Enable */ - , 11, - EPBR, 20, /* EPBAR [31:12] */ - - Offset(0x48), /* MCHBAR (0:0:0:48) */ - MHEN, 1, /* Enable */ - , 14, - MHBR, 17, /* MCHBAR [31:15] */ - - Offset(0x60), /* PCIEXBAR (0:0:0:60) */ - PXEN, 1, /* Enable */ - PXSZ, 2, /* PCI Express Size */ - , 23, - PXBR, 6, /* PCI Express BAR [31:26] */ - - Offset(0x68), /* DMIBAR (0:0:0:68) */ - DIEN, 1, /* Enable */ - , 11, - DIBR, 20, /* DMIBAR [31:12] */ - - Offset (0xa0), - TOM, 64, /* Top of Used Memory */ - TUUD, 64, /* Top of Upper Used Memory */ - - Offset (0xbc), /* Top of Low Used Memory */ - TLUD, 32, - } -} - -Method (_CRS, 0, Serialized) -{ - Name (MCRS, ResourceTemplate () - { - /* Bus Numbers */ - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100) - - /* IO Region 0 */ - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, - EntireRange, - 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8) - - /* PCI Config Space */ - Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) - - /* IO Region 1 */ - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, - EntireRange, - 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300) - - /* VGA memory (0xa0000-0xbffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, - 0x00020000) - - /* OPROM reserved (0xc0000-0xc3fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xc4000-0xc7fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xc8000-0xcbfff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xcc000-0xcffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xd0000-0xd3fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xd4000-0xd7fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xd8000-0xdbfff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xdc000-0xdffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, - 0x00004000) - - /* BIOS Extension (0xe0000-0xe3fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, - 0x00004000) - - /* BIOS Extension (0xe4000-0xe7fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, - 0x00004000) - - /* BIOS Extension (0xe8000-0xebfff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, - 0x00004000) - - /* BIOS Extension (0xec000-0xeffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000ec000, 0x000effff, 0x00000000, - 0x00004000) - - /* System BIOS (0xf0000-0xfffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, - 0x00010000) - - /* PCI Memory Region (TLUD - 0xdfffffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - NonCacheable, ReadWrite, - 0x00000000, 0x00000000, 0xdfffffff, 0x00000000, - 0xE0000000,,, PM01) - - /* PCI Memory Region (TUUD - (TUUD + ABOVE_4G_MMIO_SIZE)) */ - QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - NonCacheable, ReadWrite, - 0x00000000, 0x10000, 0x1ffff, 0x00000000, - 0x10000,,, PM02) - - /* PCH reserved resource (0xfc800000-0xfe7fffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, PCH_PRESERVED_BASE_ADDRESS, 0xfe7fffff, - 0x00000000, PCH_PRESERVED_BASE_SIZE) - - /* TPM Area (0xfed40000-0xfed47fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0xfed40000, 0xfed47fff, 0x00000000, - 0x00008000) - }) - - /* Find PCI resource area in MCRS */ - CreateDwordField (MCRS, PM01._MIN, PMIN) - CreateDwordField (MCRS, PM01._MAX, PMAX) - CreateDwordField (MCRS, PM01._LEN, PLEN) - - /* - * Fix up PCI memory region - * Start with Top of Lower Usable DRAM - */ - Store (\_SB.PCI0.MCHC.TLUD, PMIN) - Add (Subtract (PMAX, PMIN), 1, PLEN) - - /* Patch PM02 range based on Memory Size */ - CreateQwordField (MCRS, PM02._MIN, MMIN) - CreateQwordField (MCRS, PM02._MAX, MMAX) - CreateQwordField (MCRS, PM02._LEN, MLEN) - - Store (\_SB.PCI0.MCHC.TUUD, Local0) - - If (LLessEqual (Local0, BASE_32GB)) { - Store (BASE_32GB, MMIN) - Store (SIZE_16GB, MLEN) - } Else { - Store (0, MMIN) - Store (0, MLEN) - } - Subtract (Add (MMIN, MLEN), 1, MMAX) - - Return (MCRS) -} - -/* Get MCH BAR */ -Method (GMHB, 0, Serialized) -{ - ShiftLeft (\_SB.PCI0.MCHC.MHBR, 15, Local0) - Return (Local0) -} - -/* Get EP BAR */ -Method (GEPB, 0, Serialized) -{ - ShiftLeft (\_SB.PCI0.MCHC.EPBR, 12, Local0) - Return (Local0) -} - -/* Get PCIe BAR */ -Method (GPCB, 0, Serialized) -{ - ShiftLeft (\_SB.PCI0.MCHC.PXBR, 26, Local0) - Return (Local0) -} - -/* Get PCIe Length */ -Method (GPCL, 0, Serialized) -{ - ShiftRight (0x10000000, \_SB.PCI0.MCHC.PXSZ, Local0) - Return (Local0) -} - -/* Get DMI BAR */ -Method (GDMB, 0, Serialized) -{ - ShiftLeft (\_SB.PCI0.MCHC.DIBR, 12, Local0) - Return (Local0) -} - -/* PCI Device Resource Consumption */ -Device (PDRC) -{ - Name (_HID, EISAID ("PNP0C02")) - Name (_UID, 1) - - Method (_CRS, 0, Serialized) - { - Name (BUF0, ResourceTemplate () - { - /* MCH BAR _BAS will be updated in _CRS below according to - * B0:D0:F0:Reg.48h - */ - Memory32Fixed (ReadWrite, 0, 0x08000, MCHB) - - /* DMI BAR _BAS will be updated in _CRS below according to - * B0:D0:F0:Reg.68h - */ - Memory32Fixed (ReadWrite, 0, 0x01000, DMIB) - - /* EP BAR _BAS will be updated in _CRS below according to - * B0:D0:F0:Reg.40h - */ - Memory32Fixed (ReadWrite, 0, 0x01000, EGPB) - - /* PCI Express BAR _BAS and _LEN will be updated in - * _CRS below according to B0:D0:F0:Reg.60h - */ - Memory32Fixed (ReadWrite, 0, 0, PCIX) - - /* VTD engine memory range. */ - Memory32Fixed (ReadOnly, VTD_BASE_ADDRESS, VTD_BASE_SIZE) - - /* FLASH range */ - Memory32Fixed (ReadOnly, 0, CONFIG_ROM_SIZE, FIOH) - - /* Local APIC range(0xFEE0_0000 to 0xFEEF_FFFF) */ - Memory32Fixed (ReadOnly, 0xFEE00000, 0x100000) - - /* HPET address decode range */ - Memory32Fixed (ReadWrite, HPET_BASE_ADDRESS, 0x400) - }) - - CreateDwordField (BUF0, MCHB._BAS, MBR0) - Store (\_SB.PCI0.GMHB (), MBR0) - - CreateDwordField (BUF0, DMIB._BAS, DBR0) - Store (\_SB.PCI0.GDMB (), DBR0) - - CreateDwordField (BUF0, EGPB._BAS, EBR0) - Store (\_SB.PCI0.GEPB (), EBR0) - - CreateDwordField (BUF0, PCIX._BAS, XBR0) - Store (\_SB.PCI0.GPCB (), XBR0) - - CreateDwordField (BUF0, PCIX._LEN, XSZ0) - Store (\_SB.PCI0.GPCL (), XSZ0) - - CreateDwordField (BUF0, FIOH._BAS, FBR0) - Subtract(0x100000000, CONFIG_ROM_SIZE, FBR0) - - Return (BUF0) - } -} -- To view, visit https://review.coreboot.org/c/coreboot/+/38155 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9af844bcbbcce3f4b0ac7aada43d43e4171e08b Gerrit-Change-Number: 38155 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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coreboot-gerrit January 2020