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Change in coreboot[master]: amd/agesa/state_machine: Add BeforeInitLate hooks
by Michał Żygowski (Code Review) 09 Jan '20

09 Jan '20

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37998 ) Change subject: amd/agesa/state_machine: Add BeforeInitLate hooks ...................................................................... amd/agesa/state_machine: Add BeforeInitLate hooks Add missing BeforeInitLate hooks in order to bring back certain options that were lost on postcar migration. This will also allow to disable CDIT again that caused AmdInitLate error on 00730F01. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I1226e9c0c8a92920f2569ec0f85d0be0adcc9e30 --- M src/drivers/amd/agesa/state_machine.c M src/northbridge/amd/agesa/family14/state_machine.c M src/northbridge/amd/agesa/family15tn/state_machine.c M src/northbridge/amd/agesa/family16kb/state_machine.c M src/northbridge/amd/agesa/state_machine.h M src/northbridge/amd/pi/00730F01/state_machine.c 6 files changed, 22 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/37998/1 diff --git a/src/drivers/amd/agesa/state_machine.c b/src/drivers/amd/agesa/state_machine.c index 482b615..1678f84 100644 --- a/src/drivers/amd/agesa/state_machine.c +++ b/src/drivers/amd/agesa/state_machine.c @@ -223,6 +223,8 @@ case AMD_INIT_LATE: { AMD_LATE_PARAMS *param = (void *)StdHeader; + platform_BeforeInitLate(cb, param); + board_BeforeInitLate(cb, param); status = module_dispatch(func, StdHeader); platform_AfterInitLate(cb, param); completion_InitLate(cb, param); @@ -364,6 +366,8 @@ board_BeforeInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) { } void __weak board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *Mid) { } +void __weak +board_BeforeInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late) { } AGESA_STATUS __weak fchs3earlyrestore(AMD_CONFIG_PARAMS *StdHeader) diff --git a/src/northbridge/amd/agesa/family14/state_machine.c b/src/northbridge/amd/agesa/family14/state_machine.c index 91a8f70..175056c 100644 --- a/src/northbridge/amd/agesa/family14/state_machine.c +++ b/src/northbridge/amd/agesa/family14/state_machine.c @@ -104,6 +104,10 @@ amd_initcpuio(); } +void platform_BeforeInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late) +{ +} + void platform_AfterInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late) { sb_Late_Post(); diff --git a/src/northbridge/amd/agesa/family15tn/state_machine.c b/src/northbridge/amd/agesa/family15tn/state_machine.c index 473edfc..dafb64c 100644 --- a/src/northbridge/amd/agesa/family15tn/state_machine.c +++ b/src/northbridge/amd/agesa/family15tn/state_machine.c @@ -70,6 +70,10 @@ amd_initcpuio(); } +void platform_BeforeInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late) +{ +} + void platform_AfterInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late) { } diff --git a/src/northbridge/amd/agesa/family16kb/state_machine.c b/src/northbridge/amd/agesa/family16kb/state_machine.c index fea097f..7794f2d 100644 --- a/src/northbridge/amd/agesa/family16kb/state_machine.c +++ b/src/northbridge/amd/agesa/family16kb/state_machine.c @@ -77,6 +77,10 @@ amd_initcpuio(); } +void platform_BeforeInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late) +{ +} + void platform_AfterInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late) { } diff --git a/src/northbridge/amd/agesa/state_machine.h b/src/northbridge/amd/agesa/state_machine.h index c4a3054..6e86f53 100644 --- a/src/northbridge/amd/agesa/state_machine.h +++ b/src/northbridge/amd/agesa/state_machine.h @@ -84,6 +84,8 @@ void platform_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *Mid); void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *Mid); +void platform_BeforeInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late); +void board_BeforeInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late); void platform_AfterInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late); void completion_InitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late); diff --git a/src/northbridge/amd/pi/00730F01/state_machine.c b/src/northbridge/amd/pi/00730F01/state_machine.c index b567f38..7e5ca5b 100644 --- a/src/northbridge/amd/pi/00730F01/state_machine.c +++ b/src/northbridge/amd/pi/00730F01/state_machine.c @@ -58,11 +58,13 @@ amd_initcpuio(); } -void platform_AfterInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late) +void platform_BeforeInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late) { } - +void platform_AfterInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late) +{ +} void platform_BeforeInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume) { -- To view, visit https://review.coreboot.org/c/coreboot/+/37998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1226e9c0c8a92920f2569ec0f85d0be0adcc9e30 Gerrit-Change-Number: 37998 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: AGESA,binaryPI boards: Declare some IRQ tables static
by Kyösti Mälkki (Code Review) 09 Jan '20

09 Jan '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38261 ) Change subject: AGESA,binaryPI boards: Declare some IRQ tables static ...................................................................... AGESA,binaryPI boards: Declare some IRQ tables static Change-Id: Ib45c6372df6068ab041a055dad8bacf597717ba2 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/amd/bettong/mainboard.c M src/mainboard/amd/gardenia/mainboard.c M src/mainboard/amd/lamar/mainboard.c M src/mainboard/amd/padmelon/mainboard.c M src/mainboard/asus/am1i-a/mainboard.c M src/mainboard/bap/ode_e20XX/mainboard.c M src/mainboard/biostar/am1ml/mainboard.c M src/mainboard/gizmosphere/gizmo2/mainboard.c M src/mainboard/google/kahlee/mainboard.c 9 files changed, 18 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/38261/1 diff --git a/src/mainboard/amd/bettong/mainboard.c b/src/mainboard/amd/bettong/mainboard.c index 5b93751..8e2ecfd 100644 --- a/src/mainboard/amd/bettong/mainboard.c +++ b/src/mainboard/amd/bettong/mainboard.c @@ -28,7 +28,7 @@ * These values are used by the PCI configuration space, * MP Tables. TODO: Make ACPI use these values too. */ -const u8 mainboard_picr_data[] = { +static const u8 mainboard_picr_data[] = { [0x00] = 0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F, [0x08] = 0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, [0x10] = 0x1F,0x1F,0x1F,0x03,0x1F,0x1F,0x1F,0x1F, @@ -47,7 +47,7 @@ [0x78] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, }; -const u8 mainboard_intr_data[] = { +static const u8 mainboard_intr_data[] = { [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x1F,0x1F,0x10, diff --git a/src/mainboard/amd/gardenia/mainboard.c b/src/mainboard/amd/gardenia/mainboard.c index 3a4090c..26c80c0 100644 --- a/src/mainboard/amd/gardenia/mainboard.c +++ b/src/mainboard/amd/gardenia/mainboard.c @@ -32,7 +32,7 @@ * These values are used by the PCI configuration space, * MP Tables. TODO: Make ACPI use these values too. */ -const u8 mainboard_picr_data[] = { +static const u8 mainboard_picr_data[] = { [0x00] = 0x03, 0x04, 0x05, 0x07, 0x0B, 0x0A, 0x1F, 0x1F, [0x08] = 0xFA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, [0x10] = 0x1F, 0x1F, 0x1F, 0x03, 0x1F, 0x1F, 0x1F, 0x1F, @@ -51,7 +51,7 @@ [0x78] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, }; -const u8 mainboard_intr_data[] = { +static const u8 mainboard_intr_data[] = { [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, [0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x1F, 0x1F, 0x10, diff --git a/src/mainboard/amd/lamar/mainboard.c b/src/mainboard/amd/lamar/mainboard.c index 2f716d0..264c603 100644 --- a/src/mainboard/amd/lamar/mainboard.c +++ b/src/mainboard/amd/lamar/mainboard.c @@ -35,7 +35,7 @@ * These values are used by the PCI configuration space, * MP Tables. TODO: Make ACPI use these values too. */ -const u8 mainboard_picr_data[] = { +static const u8 mainboard_picr_data[] = { /* INTA# - INTH# */ [0x00] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B, /* Misc-nil,0,1,2, INT from Serial irq */ @@ -63,7 +63,7 @@ [0x80] = 0x0C,0x1F, }; -const u8 mainboard_intr_data[] = { +static const u8 mainboard_intr_data[] = { /* INTA# - INTH# */ [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* Misc-nil,0,1,2, INT from Serial irq */ diff --git a/src/mainboard/amd/padmelon/mainboard.c b/src/mainboard/amd/padmelon/mainboard.c index e106b4a..c8eef29 100644 --- a/src/mainboard/amd/padmelon/mainboard.c +++ b/src/mainboard/amd/padmelon/mainboard.c @@ -34,7 +34,7 @@ * These values are used by the PCI configuration space, * MP Tables. */ -const u8 mainboard_picr_data[] = { +static const u8 mainboard_picr_data[] = { [0x00] = 0x03, 0x04, 0x05, 0x07, 0x0B, 0x0A, 0x1F, 0x1F, [0x08] = 0xFA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, [0x10] = 0x1F, 0x1F, 0x1F, 0x03, 0x1F, 0x1F, 0x1F, 0x1F, @@ -53,7 +53,7 @@ [0x78] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, }; -const u8 mainboard_intr_data[] = { +static const u8 mainboard_intr_data[] = { [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, [0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x1F, 0x1F, 0x10, diff --git a/src/mainboard/asus/am1i-a/mainboard.c b/src/mainboard/asus/am1i-a/mainboard.c index bd6d3a3..ecf4006 100644 --- a/src/mainboard/asus/am1i-a/mainboard.c +++ b/src/mainboard/asus/am1i-a/mainboard.c @@ -25,7 +25,7 @@ #include <southbridge/amd/common/amd_pci_util.h> #include <northbridge/amd/agesa/family16kb/pci_devs.h> -const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = { +static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = { /* INTA# - INTH# */ [0x00] = 0x03,0x04,0x05,0x07,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */ @@ -40,7 +40,7 @@ [0x40] = 0x1F, 0x07 }; -const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = { +static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = { /* INTA# - INTH# */ [0x00] = 0x10,0x11,0x12,0x13,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */ diff --git a/src/mainboard/bap/ode_e20XX/mainboard.c b/src/mainboard/bap/ode_e20XX/mainboard.c index 6bd9445..2fcc1d6 100644 --- a/src/mainboard/bap/ode_e20XX/mainboard.c +++ b/src/mainboard/bap/ode_e20XX/mainboard.c @@ -34,7 +34,7 @@ * These values are used by the PCI configuration space, * MP Tables. TODO: Make ACPI use these values too. */ -const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = { +static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = { /* INTA# - INTH# */ [0x00] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B, /* Misc-nil,0,1,2, INT from Serial irq */ @@ -49,7 +49,7 @@ [0x41] = 0x0F, }; -const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = { +static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = { /* INTA# - INTH# */ [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* Misc-nil,0,1,2, INT from Serial irq */ diff --git a/src/mainboard/biostar/am1ml/mainboard.c b/src/mainboard/biostar/am1ml/mainboard.c index 4db720e..9d218d8 100644 --- a/src/mainboard/biostar/am1ml/mainboard.c +++ b/src/mainboard/biostar/am1ml/mainboard.c @@ -23,7 +23,7 @@ #include <southbridge/amd/common/amd_pci_util.h> #include <northbridge/amd/agesa/family16kb/pci_devs.h> -const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = { +static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = { /* INTA# - INTH# */ [0x00] = 0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */ @@ -38,7 +38,7 @@ [0x40] = 0x04, 0x04 }; -const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = { +static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = { /* INTA# - INTH# */ [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* Misc-nil,0,1,2, INT from Serial irq */ diff --git a/src/mainboard/gizmosphere/gizmo2/mainboard.c b/src/mainboard/gizmosphere/gizmo2/mainboard.c index f856df9..a6c1a6d 100644 --- a/src/mainboard/gizmosphere/gizmo2/mainboard.c +++ b/src/mainboard/gizmosphere/gizmo2/mainboard.c @@ -33,7 +33,7 @@ * These values are used by the PCI configuration space, * MP Tables. TODO: Make ACPI use these values too. */ -const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = { +static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = { /* INTA# - INTH# */ [0x00] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B, /* Misc-nil,0,1,2, INT from Serial irq */ @@ -48,7 +48,7 @@ [0x41] = 0x0F, }; -const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = { +static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = { /* INTA# - INTH# */ [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* Misc-nil,0,1,2, INT from Serial irq */ diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c index 0173064..42a82d4 100644 --- a/src/mainboard/google/kahlee/mainboard.c +++ b/src/mainboard/google/kahlee/mainboard.c @@ -45,7 +45,7 @@ * MP Tables. TODO: Make ACPI use these values too. */ -const u8 mainboard_picr_data[] = { +static const u8 mainboard_picr_data[] = { [0x00] = 0x03, 0x04, 0x05, 0x07, 0x0B, 0x1F, 0x1F, 0x1F, [0x08] = 0xFA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, [0x10] = 0x09, 0x1F, 0x1F, 0x03, 0x1F, 0x1F, 0x1F, 0x03, @@ -64,7 +64,7 @@ [0x78] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, }; -const u8 mainboard_intr_data[] = { +static const u8 mainboard_intr_data[] = { [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x1F, 0x16, 0x17, [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, [0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x1F, 0x1F, 0x10, -- To view, visit https://review.coreboot.org/c/coreboot/+/38261 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib45c6372df6068ab041a055dad8bacf597717ba2 Gerrit-Change-Number: 38261 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: drivers/pc80/rtc: Separate {get|set}_option() support
by Kyösti Mälkki (Code Review) 09 Jan '20

09 Jan '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38193 ) Change subject: drivers/pc80/rtc: Separate {get|set}_option() support ...................................................................... drivers/pc80/rtc: Separate {get|set}_option() support Change-Id: Ib23fcd89bf4efef9072fcaea1d8699145c1f2983 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/drivers/pc80/rtc/Makefile.inc M src/drivers/pc80/rtc/mc146818rtc.c A src/drivers/pc80/rtc/option.c M src/include/pc80/mc146818rtc.h 4 files changed, 242 insertions(+), 218 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/38193/1 diff --git a/src/drivers/pc80/rtc/Makefile.inc b/src/drivers/pc80/rtc/Makefile.inc index eb0ff6f..a958044 100644 --- a/src/drivers/pc80/rtc/Makefile.inc +++ b/src/drivers/pc80/rtc/Makefile.inc @@ -9,6 +9,9 @@ all-$(CONFIG_CMOS_POST) += post.c +all-$(CONFIG_USE_OPTION_TABLE) += option.c +smm-$(CONFIG_USE_OPTION_TABLE) += option.c + ifeq ($(CONFIG_USE_OPTION_TABLE),y) cbfs-files-$(CONFIG_HAVE_CMOS_DEFAULT) += cmos.default cmos.default-file = $(CONFIG_CMOS_DEFAULT_FILE):nvramtool diff --git a/src/drivers/pc80/rtc/mc146818rtc.c b/src/drivers/pc80/rtc/mc146818rtc.c index 74b326a..fe6900f 100644 --- a/src/drivers/pc80/rtc/mc146818rtc.c +++ b/src/drivers/pc80/rtc/mc146818rtc.c @@ -54,7 +54,7 @@ rtc_set(&time); } -static int cmos_checksum_valid(int range_start, int range_end, int cks_loc) +int cmos_checksum_valid(int range_start, int range_end, int cks_loc) { int i; u16 sum, old_sum; @@ -70,7 +70,7 @@ return sum == old_sum; } -static void cmos_set_checksum(int range_start, int range_end, int cks_loc) +void cmos_set_checksum(int range_start, int range_end, int cks_loc) { int i; u16 sum; @@ -195,222 +195,6 @@ __cmos_init(invalid); } -/* - * This routine returns the value of the requested bits. - * input bit = bit count from the beginning of the cmos image - * length = number of bits to include in the value - * ret = a character pointer to where the value is to be returned - * returns CB_SUCCESS = successful, cb_err code if an error occurred - */ -static enum cb_err get_cmos_value(unsigned long bit, unsigned long length, - void *vret) -{ - unsigned char *ret; - unsigned long byte, byte_bit; - unsigned long i; - unsigned char uchar; - - /* - * The table is checked when it is built to ensure all - * values are valid. - */ - ret = vret; - byte = bit / 8; /* find the byte where the data starts */ - byte_bit = bit % 8; /* find the bit in the byte where the data starts */ - if (length < 9) { /* one byte or less */ - uchar = cmos_read(byte); /* load the byte */ - uchar >>= byte_bit; /* shift the bits to byte align */ - /* clear unspecified bits */ - ret[0] = uchar & ((1 << length) - 1); - } else { /* more than one byte so transfer the whole bytes */ - for (i = 0; length; i++, length -= 8, byte++) { - /* load the byte */ - ret[i] = cmos_read(byte); - } - } - return CB_SUCCESS; -} - -static enum cb_err locate_cmos_layout(struct region_device *rdev) -{ - uint32_t cbfs_type = CBFS_COMPONENT_CMOS_LAYOUT; - MAYBE_STATIC_BSS struct cbfsf fh = {}; - - /* - * In case VBOOT is enabled and this function is called from SMM, - * we have multiple CMOS layout files and to locate them we'd need to - * include VBOOT into SMM... - * - * Support only one CMOS layout in the 'COREBOOT' region for now. - */ - if (!region_device_sz(&(fh.data))) { - if (cbfs_locate_file_in_region(&fh, "COREBOOT", "cmos_layout.bin", - &cbfs_type)) { - printk(BIOS_ERR, "RTC: cmos_layout.bin could not be found. " - "Options are disabled\n"); - return CB_CMOS_LAYOUT_NOT_FOUND; - } - } - - cbfs_file_data(rdev, &fh); - - return CB_SUCCESS; -} - -enum cb_err get_option(void *dest, const char *name) -{ - struct cmos_option_table *ct; - struct region_device rdev; - struct cmos_entries *ce; - size_t namelen; - int found = 0; - - if (!CONFIG(USE_OPTION_TABLE)) - return CB_CMOS_OTABLE_DISABLED; - - /* Figure out how long name is */ - namelen = strnlen(name, CMOS_MAX_NAME_LENGTH); - - if (locate_cmos_layout(&rdev) != CB_SUCCESS) { - return CB_CMOS_LAYOUT_NOT_FOUND; - } - ct = rdev_mmap_full(&rdev); - if (!ct) { - printk(BIOS_ERR, "RTC: cmos_layout.bin could not be mapped. " - "Options are disabled\n"); - - return CB_CMOS_LAYOUT_NOT_FOUND; - } - - /* find the requested entry record */ - ce = (struct cmos_entries *)((unsigned char *)ct + ct->header_length); - for (; ce->tag == LB_TAG_OPTION; - ce = (struct cmos_entries *)((unsigned char *)ce + ce->size)) { - if (memcmp(ce->name, name, namelen) == 0) { - found = 1; - break; - } - } - if (!found) { - printk(BIOS_DEBUG, "No CMOS option '%s'.\n", name); - rdev_munmap(&rdev, ct); - return CB_CMOS_OPTION_NOT_FOUND; - } - - if (!cmos_checksum_valid(LB_CKS_RANGE_START, LB_CKS_RANGE_END, LB_CKS_LOC)) { - rdev_munmap(&rdev, ct); - return CB_CMOS_CHECKSUM_INVALID; - } - if (get_cmos_value(ce->bit, ce->length, dest) != CB_SUCCESS) { - rdev_munmap(&rdev, ct); - return CB_CMOS_ACCESS_ERROR; - } - rdev_munmap(&rdev, ct); - return CB_SUCCESS; -} - -static enum cb_err set_cmos_value(unsigned long bit, unsigned long length, - void *vret) -{ - unsigned char *ret; - unsigned long byte, byte_bit; - unsigned long i; - unsigned char uchar, mask; - unsigned int chksum_update_needed = 0; - - ret = vret; - byte = bit / 8; /* find the byte where the data starts */ - byte_bit = bit % 8; /* find the bit where the data starts */ - if (length <= 8) { /* one byte or less */ - mask = (1 << length) - 1; - mask <<= byte_bit; - - uchar = cmos_read(byte); - uchar &= ~mask; - uchar |= (ret[0] << byte_bit); - cmos_write(uchar, byte); - if (byte >= LB_CKS_RANGE_START && byte <= LB_CKS_RANGE_END) - chksum_update_needed = 1; - } else { /* more that one byte so transfer the whole bytes */ - if (byte_bit || length % 8) - return CB_ERR_ARG; - - for (i = 0; length; i++, length -= 8, byte++) { - cmos_write(ret[i], byte); - if (byte >= LB_CKS_RANGE_START && - byte <= LB_CKS_RANGE_END) - chksum_update_needed = 1; - } - } - - if (chksum_update_needed) { - cmos_set_checksum(LB_CKS_RANGE_START, LB_CKS_RANGE_END, - LB_CKS_LOC); - } - return CB_SUCCESS; -} - -enum cb_err set_option(const char *name, void *value) -{ - struct cmos_option_table *ct; - struct region_device rdev; - struct cmos_entries *ce; - unsigned long length; - size_t namelen; - int found = 0; - - if (!CONFIG(USE_OPTION_TABLE)) - return CB_CMOS_OTABLE_DISABLED; - - /* Figure out how long name is */ - namelen = strnlen(name, CMOS_MAX_NAME_LENGTH); - - if (locate_cmos_layout(&rdev) != CB_SUCCESS) { - return CB_CMOS_LAYOUT_NOT_FOUND; - } - ct = rdev_mmap_full(&rdev); - if (!ct) { - printk(BIOS_ERR, "RTC: cmos_layout.bin could not be mapped. " - "Options are disabled\n"); - - return CB_CMOS_LAYOUT_NOT_FOUND; - } - - /* find the requested entry record */ - ce = (struct cmos_entries *)((unsigned char *)ct + ct->header_length); - for (; ce->tag == LB_TAG_OPTION; - ce = (struct cmos_entries *)((unsigned char *)ce + ce->size)) { - if (memcmp(ce->name, name, namelen) == 0) { - found = 1; - break; - } - } - if (!found) { - printk(BIOS_DEBUG, "WARNING: No CMOS option '%s'.\n", name); - rdev_munmap(&rdev, ct); - return CB_CMOS_OPTION_NOT_FOUND; - } - - length = ce->length; - if (ce->config == 's') { - length = MAX(strlen((const char *)value) * 8, ce->length - 8); - /* make sure the string is null terminated */ - if (set_cmos_value(ce->bit + ce->length - 8, 8, &(u8[]){0}) - != CB_SUCCESS) { - rdev_munmap(&rdev, ct); - return CB_CMOS_ACCESS_ERROR; - } - } - - if (set_cmos_value(ce->bit, length, value) != CB_SUCCESS) { - rdev_munmap(&rdev, ct); - return CB_CMOS_ACCESS_ERROR; - } - - rdev_munmap(&rdev, ct); - return CB_SUCCESS; -} - /* Upon return the caller is guaranteed 244 microseconds to complete any * RTC operations. wait_uip may be called a single time prior to multiple * accesses, but sequences requiring more time should call wait_uip again. diff --git a/src/drivers/pc80/rtc/option.c b/src/drivers/pc80/rtc/option.c new file mode 100644 index 0000000..65f75ef --- /dev/null +++ b/src/drivers/pc80/rtc/option.c @@ -0,0 +1,235 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <string.h> +#include <cbfs.h> +#include <option.h> +#include <pc80/mc146818rtc.h> +#include <types.h> + +/* option_table.h is autogenerated */ +#include "option_table.h" + +/* Don't warn for checking >= LB_CKS_RANGE_START even though it may be 0. */ +#pragma GCC diagnostic ignored "-Wtype-limits" + +/* + * This routine returns the value of the requested bits. + * input bit = bit count from the beginning of the cmos image + * length = number of bits to include in the value + * ret = a character pointer to where the value is to be returned + * returns CB_SUCCESS = successful, cb_err code if an error occurred + */ +static enum cb_err get_cmos_value(unsigned long bit, unsigned long length, + void *vret) +{ + unsigned char *ret; + unsigned long byte, byte_bit; + unsigned long i; + unsigned char uchar; + + /* + * The table is checked when it is built to ensure all + * values are valid. + */ + ret = vret; + byte = bit / 8; /* find the byte where the data starts */ + byte_bit = bit % 8; /* find the bit in the byte where the data starts */ + if (length < 9) { /* one byte or less */ + uchar = cmos_read(byte); /* load the byte */ + uchar >>= byte_bit; /* shift the bits to byte align */ + /* clear unspecified bits */ + ret[0] = uchar & ((1 << length) - 1); + } else { /* more than one byte so transfer the whole bytes */ + for (i = 0; length; i++, length -= 8, byte++) { + /* load the byte */ + ret[i] = cmos_read(byte); + } + } + return CB_SUCCESS; +} + +static enum cb_err locate_cmos_layout(struct region_device *rdev) +{ + uint32_t cbfs_type = CBFS_COMPONENT_CMOS_LAYOUT; + MAYBE_STATIC_BSS struct cbfsf fh = {}; + + /* + * In case VBOOT is enabled and this function is called from SMM, + * we have multiple CMOS layout files and to locate them we'd need to + * include VBOOT into SMM... + * + * Support only one CMOS layout in the 'COREBOOT' region for now. + */ + if (!region_device_sz(&(fh.data))) { + if (cbfs_locate_file_in_region(&fh, "COREBOOT", "cmos_layout.bin", + &cbfs_type)) { + printk(BIOS_ERR, "RTC: cmos_layout.bin could not be found. " + "Options are disabled\n"); + return CB_CMOS_LAYOUT_NOT_FOUND; + } + } + + cbfs_file_data(rdev, &fh); + + return CB_SUCCESS; +} + +enum cb_err get_option(void *dest, const char *name) +{ + struct cmos_option_table *ct; + struct region_device rdev; + struct cmos_entries *ce; + size_t namelen; + int found = 0; + + /* Figure out how long name is */ + namelen = strnlen(name, CMOS_MAX_NAME_LENGTH); + + if (locate_cmos_layout(&rdev) != CB_SUCCESS) { + return CB_CMOS_LAYOUT_NOT_FOUND; + } + ct = rdev_mmap_full(&rdev); + if (!ct) { + printk(BIOS_ERR, "RTC: cmos_layout.bin could not be mapped. " + "Options are disabled\n"); + + return CB_CMOS_LAYOUT_NOT_FOUND; + } + + /* find the requested entry record */ + ce = (struct cmos_entries *)((unsigned char *)ct + ct->header_length); + for (; ce->tag == LB_TAG_OPTION; + ce = (struct cmos_entries *)((unsigned char *)ce + ce->size)) { + if (memcmp(ce->name, name, namelen) == 0) { + found = 1; + break; + } + } + if (!found) { + printk(BIOS_DEBUG, "No CMOS option '%s'.\n", name); + rdev_munmap(&rdev, ct); + return CB_CMOS_OPTION_NOT_FOUND; + } + + if (!cmos_checksum_valid(LB_CKS_RANGE_START, LB_CKS_RANGE_END, LB_CKS_LOC)) { + rdev_munmap(&rdev, ct); + return CB_CMOS_CHECKSUM_INVALID; + } + if (get_cmos_value(ce->bit, ce->length, dest) != CB_SUCCESS) { + rdev_munmap(&rdev, ct); + return CB_CMOS_ACCESS_ERROR; + } + rdev_munmap(&rdev, ct); + return CB_SUCCESS; +} + +static enum cb_err set_cmos_value(unsigned long bit, unsigned long length, + void *vret) +{ + unsigned char *ret; + unsigned long byte, byte_bit; + unsigned long i; + unsigned char uchar, mask; + unsigned int chksum_update_needed = 0; + + ret = vret; + byte = bit / 8; /* find the byte where the data starts */ + byte_bit = bit % 8; /* find the bit where the data starts */ + if (length <= 8) { /* one byte or less */ + mask = (1 << length) - 1; + mask <<= byte_bit; + + uchar = cmos_read(byte); + uchar &= ~mask; + uchar |= (ret[0] << byte_bit); + cmos_write(uchar, byte); + if (byte >= LB_CKS_RANGE_START && byte <= LB_CKS_RANGE_END) + chksum_update_needed = 1; + } else { /* more that one byte so transfer the whole bytes */ + if (byte_bit || length % 8) + return CB_ERR_ARG; + + for (i = 0; length; i++, length -= 8, byte++) { + cmos_write(ret[i], byte); + if (byte >= LB_CKS_RANGE_START && + byte <= LB_CKS_RANGE_END) + chksum_update_needed = 1; + } + } + + if (chksum_update_needed) { + cmos_set_checksum(LB_CKS_RANGE_START, LB_CKS_RANGE_END, + LB_CKS_LOC); + } + return CB_SUCCESS; +} + +enum cb_err set_option(const char *name, void *value) +{ + struct cmos_option_table *ct; + struct region_device rdev; + struct cmos_entries *ce; + unsigned long length; + size_t namelen; + int found = 0; + + /* Figure out how long name is */ + namelen = strnlen(name, CMOS_MAX_NAME_LENGTH); + + if (locate_cmos_layout(&rdev) != CB_SUCCESS) { + return CB_CMOS_LAYOUT_NOT_FOUND; + } + ct = rdev_mmap_full(&rdev); + if (!ct) { + printk(BIOS_ERR, "RTC: cmos_layout.bin could not be mapped. " + "Options are disabled\n"); + + return CB_CMOS_LAYOUT_NOT_FOUND; + } + + /* find the requested entry record */ + ce = (struct cmos_entries *)((unsigned char *)ct + ct->header_length); + for (; ce->tag == LB_TAG_OPTION; + ce = (struct cmos_entries *)((unsigned char *)ce + ce->size)) { + if (memcmp(ce->name, name, namelen) == 0) { + found = 1; + break; + } + } + if (!found) { + printk(BIOS_DEBUG, "WARNING: No CMOS option '%s'.\n", name); + rdev_munmap(&rdev, ct); + return CB_CMOS_OPTION_NOT_FOUND; + } + + length = ce->length; + if (ce->config == 's') { + length = MAX(strlen((const char *)value) * 8, ce->length - 8); + /* make sure the string is null terminated */ + if (set_cmos_value(ce->bit + ce->length - 8, 8, &(u8[]){0}) + != CB_SUCCESS) { + rdev_munmap(&rdev, ct); + return CB_CMOS_ACCESS_ERROR; + } + } + + if (set_cmos_value(ce->bit, length, value) != CB_SUCCESS) { + rdev_munmap(&rdev, ct); + return CB_CMOS_ACCESS_ERROR; + } + + rdev_munmap(&rdev, ct); + return CB_SUCCESS; +} diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h index 0f54e1e..26562d9 100644 --- a/src/include/pc80/mc146818rtc.h +++ b/src/include/pc80/mc146818rtc.h @@ -176,6 +176,8 @@ void cmos_init(bool invalid); void cmos_check_update_date(void); int cmos_error(void); +int cmos_checksum_valid(int range_start, int range_end, int cks_loc); +void cmos_set_checksum(int range_start, int range_end, int cks_loc); #if CONFIG(CMOS_POST) #if CONFIG(USE_OPTION_TABLE) -- To view, visit https://review.coreboot.org/c/coreboot/+/38193 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib23fcd89bf4efef9072fcaea1d8699145c1f2983 Gerrit-Change-Number: 38193 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 14

Change in coreboot[master]: drivers/pc80/rtc: Separate {get|set}_option() prototypes
by Kyösti Mälkki (Code Review) 09 Jan '20

09 Jan '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38192 ) Change subject: drivers/pc80/rtc: Separate {get|set}_option() prototypes ...................................................................... drivers/pc80/rtc: Separate {get|set}_option() prototypes Change-Id: Iad7b03dc985550da903d56b3deb5bd736013f8f1 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/hyperthreading/intel_sibling.c M src/drivers/pc80/rtc/mc146818rtc.c M src/ec/kontron/it8516e/ec.c M src/ec/lenovo/h8/h8.c M src/ec/lenovo/pmh7/pmh7.c M src/include/option.h M src/include/pc80/mc146818rtc.h M src/mainboard/asus/am1i-a/BiosCallOuts.c M src/mainboard/getac/p470/early_init.c M src/mainboard/ibase/mb899/superio_hwm.c M src/mainboard/kontron/986lcd-m/early_init.c M src/mainboard/kontron/986lcd-m/mainboard.c M src/mainboard/kontron/ktqm77/mainboard.c M src/mainboard/lenovo/x60/smihandler.c M src/mainboard/roda/rk886ex/early_init.c M src/northbridge/intel/gm45/igd.c M src/northbridge/intel/i945/early_init.c M src/northbridge/intel/i945/gma.c M src/northbridge/intel/nehalem/raminit.c M src/northbridge/intel/pineview/early_init.c M src/northbridge/intel/sandybridge/early_init.c M src/northbridge/intel/x4x/early_init.c M src/soc/intel/broadwell/lpc.c M src/soc/intel/broadwell/smihandler.c M src/soc/intel/common/block/pmc/pmclib.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/bd82x6x/sata.c M src/southbridge/intel/common/smihandler.c M src/southbridge/intel/i82801dx/lpc.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801ix/sata.c M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/i82801jx/sata.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/ibexpeak/sata.c M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/smihandler.c M src/superio/ite/it8720f/superio.c M src/superio/nuvoton/nct5572d/superio.c M src/superio/winbond/w83627ehg/superio.c M src/superio/winbond/w83627hf/superio.c M src/superio/winbond/w83667hg-a/superio.c 43 files changed, 45 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/38192/1 diff --git a/src/cpu/intel/hyperthreading/intel_sibling.c b/src/cpu/intel/hyperthreading/intel_sibling.c index f5bcc87..f602ccd 100644 --- a/src/cpu/intel/hyperthreading/intel_sibling.c +++ b/src/cpu/intel/hyperthreading/intel_sibling.c @@ -15,7 +15,7 @@ #include <cpu/x86/lapic.h> #include <cpu/intel/hyperthreading.h> #include <device/device.h> -#include <pc80/mc146818rtc.h> +#include <option.h> #include <smp/spinlock.h> #if CONFIG(PARALLEL_CPU_INIT) diff --git a/src/drivers/pc80/rtc/mc146818rtc.c b/src/drivers/pc80/rtc/mc146818rtc.c index c8ba568..74b326a 100644 --- a/src/drivers/pc80/rtc/mc146818rtc.c +++ b/src/drivers/pc80/rtc/mc146818rtc.c @@ -17,6 +17,7 @@ #include <fallback.h> #include <version.h> #include <console/console.h> +#include <option.h> #include <pc80/mc146818rtc.h> #include <rtc.h> #include <string.h> diff --git a/src/ec/kontron/it8516e/ec.c b/src/ec/kontron/it8516e/ec.c index c0042fc..ca695b3 100644 --- a/src/ec/kontron/it8516e/ec.c +++ b/src/ec/kontron/it8516e/ec.c @@ -17,7 +17,7 @@ #include <device/device.h> #include <device/pnp.h> #include <ec/acpi/ec.h> -#include <pc80/mc146818rtc.h> +#include <option.h> #include "ec.h" #include "chip.h" diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c index 93a771c..73657bc 100644 --- a/src/ec/lenovo/h8/h8.c +++ b/src/ec/lenovo/h8/h8.c @@ -20,7 +20,7 @@ #include <ec/acpi/ec.h> #include <string.h> #include <smbios.h> -#include <pc80/mc146818rtc.h> +#include <option.h> #include <pc80/keyboard.h> #include <types.h> diff --git a/src/ec/lenovo/pmh7/pmh7.c b/src/ec/lenovo/pmh7/pmh7.c index 9dd668f..42e5238 100644 --- a/src/ec/lenovo/pmh7/pmh7.c +++ b/src/ec/lenovo/pmh7/pmh7.c @@ -17,7 +17,7 @@ #include <console/console.h> #include <device/device.h> #include <device/pnp.h> -#include <pc80/mc146818rtc.h> +#include <option.h> #include <delay.h> #include <types.h> diff --git a/src/include/option.h b/src/include/option.h index 7afedac..4bd5dee 100644 --- a/src/include/option.h +++ b/src/include/option.h @@ -24,7 +24,10 @@ * without a battery-backed CMOS (e.g. some laptops). */ #if CONFIG(USE_OPTION_TABLE) -#include <pc80/mc146818rtc.h> + +enum cb_err set_option(const char *name, void *val); +enum cb_err get_option(void *dest, const char *name); + #else static inline enum cb_err get_option(void *dest, const char *name) { diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h index 94d5ef5..0f54e1e 100644 --- a/src/include/pc80/mc146818rtc.h +++ b/src/include/pc80/mc146818rtc.h @@ -177,9 +177,6 @@ void cmos_check_update_date(void); int cmos_error(void); -enum cb_err set_option(const char *name, void *val); -enum cb_err get_option(void *dest, const char *name); - #if CONFIG(CMOS_POST) #if CONFIG(USE_OPTION_TABLE) # include "option_table.h" diff --git a/src/mainboard/asus/am1i-a/BiosCallOuts.c b/src/mainboard/asus/am1i-a/BiosCallOuts.c index ce54741..a61a722 100644 --- a/src/mainboard/asus/am1i-a/BiosCallOuts.c +++ b/src/mainboard/asus/am1i-a/BiosCallOuts.c @@ -22,7 +22,7 @@ #include <northbridge/amd/agesa/state_machine.h> #include <FchPlatform.h> #include <stdlib.h> -#include <pc80/mc146818rtc.h> +#include <option.h> #include <types.h> const BIOS_CALLOUT_STRUCT BiosCallouts[] = diff --git a/src/mainboard/getac/p470/early_init.c b/src/mainboard/getac/p470/early_init.c index 0581f80..f4f974a 100644 --- a/src/mainboard/getac/p470/early_init.c +++ b/src/mainboard/getac/p470/early_init.c @@ -20,7 +20,7 @@ #include <delay.h> #include <device/pnp_ops.h> #include <device/pci_ops.h> -#include <pc80/mc146818rtc.h> +#include <option.h> #include <console/console.h> #include <northbridge/intel/i945/i945.h> #include <southbridge/intel/i82801gx/i82801gx.h> diff --git a/src/mainboard/ibase/mb899/superio_hwm.c b/src/mainboard/ibase/mb899/superio_hwm.c index 175c9a0..f57a06d 100644 --- a/src/mainboard/ibase/mb899/superio_hwm.c +++ b/src/mainboard/ibase/mb899/superio_hwm.c @@ -17,7 +17,7 @@ #include <types.h> #include <console/console.h> #include <device/device.h> -#include <pc80/mc146818rtc.h> +#include <option.h> #include <superio/hwm5_conf.h> #include <superio/nuvoton/common/hwm.h> diff --git a/src/mainboard/kontron/986lcd-m/early_init.c b/src/mainboard/kontron/986lcd-m/early_init.c index 995a346..827f792 100644 --- a/src/mainboard/kontron/986lcd-m/early_init.c +++ b/src/mainboard/kontron/986lcd-m/early_init.c @@ -17,7 +17,7 @@ #include <device/pci_ops.h> #include <device/pnp_ops.h> #include <device/pnp_def.h> -#include <pc80/mc146818rtc.h> +#include <option.h> #include <northbridge/intel/i945/i945.h> #include <southbridge/intel/i82801gx/i82801gx.h> #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/kontron/986lcd-m/mainboard.c b/src/mainboard/kontron/986lcd-m/mainboard.c index cc2e32b..30368e8 100644 --- a/src/mainboard/kontron/986lcd-m/mainboard.c +++ b/src/mainboard/kontron/986lcd-m/mainboard.c @@ -18,7 +18,7 @@ #include <device/device.h> #include <console/console.h> #include <drivers/intel/gma/int15.h> -#include <pc80/mc146818rtc.h> +#include <option.h> #include <superio/hwm5_conf.h> #include <superio/nuvoton/common/hwm.h> diff --git a/src/mainboard/kontron/ktqm77/mainboard.c b/src/mainboard/kontron/ktqm77/mainboard.c index 50a7b6b..2af5eb2 100644 --- a/src/mainboard/kontron/ktqm77/mainboard.c +++ b/src/mainboard/kontron/ktqm77/mainboard.c @@ -22,7 +22,7 @@ #if CONFIG(VGA_ROM_RUN) #include <x86emu/x86emu.h> #endif -#include <pc80/mc146818rtc.h> +#include <option.h> #include <arch/interrupt.h> #include <southbridge/intel/bd82x6x/pch.h> diff --git a/src/mainboard/lenovo/x60/smihandler.c b/src/mainboard/lenovo/x60/smihandler.c index 7aacc45..d5c92e5 100644 --- a/src/mainboard/lenovo/x60/smihandler.c +++ b/src/mainboard/lenovo/x60/smihandler.c @@ -21,7 +21,7 @@ #include <southbridge/intel/i82801gx/nvs.h> #include <southbridge/intel/common/pmutil.h> #include <ec/acpi/ec.h> -#include <pc80/mc146818rtc.h> +#include <option.h> #include <ec/lenovo/h8/h8.h> #include <delay.h> #include "dock.h" diff --git a/src/mainboard/roda/rk886ex/early_init.c b/src/mainboard/roda/rk886ex/early_init.c index efecb0d..b0d08f4 100644 --- a/src/mainboard/roda/rk886ex/early_init.c +++ b/src/mainboard/roda/rk886ex/early_init.c @@ -21,7 +21,7 @@ #include <device/pnp_ops.h> #include <device/pci_ops.h> #include <device/pci_def.h> -#include <pc80/mc146818rtc.h> +#include <option.h> #include <northbridge/intel/i945/i945.h> #include <southbridge/intel/i82801gx/i82801gx.h> #include <superio/smsc/lpc47n227/lpc47n227.h> diff --git a/src/northbridge/intel/gm45/igd.c b/src/northbridge/intel/gm45/igd.c index b1ce1be..cfd067e 100644 --- a/src/northbridge/intel/gm45/igd.c +++ b/src/northbridge/intel/gm45/igd.c @@ -19,7 +19,7 @@ #include <device/pci_ops.h> #include <device/pci_def.h> #include <console/console.h> -#include <pc80/mc146818rtc.h> +#include <option.h> #include "gm45.h" diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 6e650eb..1deca3e 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -21,7 +21,7 @@ #include <device/pci_def.h> #include <cbmem.h> #include <romstage_handoff.h> -#include <pc80/mc146818rtc.h> +#include <option.h> #include <types.h> #include "i945.h" diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index d08b77d..98e30e7 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -22,7 +22,7 @@ #include <device/pci.h> #include <device/pci_ops.h> #include <device/pci_ids.h> -#include <pc80/mc146818rtc.h> +#include <option.h> #include <edid.h> #include <drivers/intel/gma/edid.h> #include <drivers/intel/gma/i915.h> diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index 215e9b8..7735522 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -24,7 +24,7 @@ #include <cbmem.h> #include <cf9_reset.h> #include <ip_checksum.h> -#include <pc80/mc146818rtc.h> +#include <option.h> #include <device/pci_def.h> #include <device/device.h> #include <halt.h> diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c index b5c5ee0..c3cd380 100644 --- a/src/northbridge/intel/pineview/early_init.c +++ b/src/northbridge/intel/pineview/early_init.c @@ -20,7 +20,7 @@ #include <device/pci.h> #include <northbridge/intel/pineview/pineview.h> #include <northbridge/intel/pineview/chip.h> -#include <pc80/mc146818rtc.h> +#include <option.h> #include <types.h> #define LPC PCI_DEV(0, 0x1f, 0) diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index 95fc52d..74ae4f5 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -21,7 +21,7 @@ #include <device/device.h> #include <device/pci_ops.h> #include <device/pci_def.h> -#include <pc80/mc146818rtc.h> +#include <option.h> #include <romstage_handoff.h> #include <types.h> diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c index c9d44fc..3520b88 100644 --- a/src/northbridge/intel/x4x/early_init.c +++ b/src/northbridge/intel/x4x/early_init.c @@ -22,7 +22,7 @@ #else #include <southbridge/intel/i82801jx/i82801jx.h> /* DEFAULT_PMBASE */ #endif -#include <pc80/mc146818rtc.h> +#include <option.h> #include "x4x.h" #include <console/console.h> #include <romstage_handoff.h> diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index 007b56b..e86b5bd 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -18,7 +18,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <pc80/mc146818rtc.h> +#include <option.h> #include <pc80/isa-dma.h> #include <pc80/i8259.h> #include <arch/io.h> diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c index c2843a7..5b04f79 100644 --- a/src/soc/intel/broadwell/smihandler.c +++ b/src/soc/intel/broadwell/smihandler.c @@ -27,7 +27,7 @@ #include <spi-generic.h> #include <elog.h> #include <halt.h> -#include <pc80/mc146818rtc.h> +#include <option.h> #include <soc/lpc.h> #include <soc/nvs.h> #include <soc/pci_devs.h> diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index 82b391b..d022666 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -21,7 +21,7 @@ #include <intelblocks/pmclib.h> #include <intelblocks/gpio.h> #include <intelblocks/tco.h> -#include <pc80/mc146818rtc.h> +#include <option.h> #include <soc/pm.h> #include <stdint.h> #include <string.h> diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index ef66ca5..01576a6 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -20,7 +20,7 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <device/pci_def.h> -#include <pc80/mc146818rtc.h> +#include <option.h> #include <pc80/isa-dma.h> #include <pc80/i8259.h> #include <arch/io.h> diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index 3ec065f..f5243f6 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -20,7 +20,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <pc80/mc146818rtc.h> +#include <option.h> #include <acpi/sata.h> #include <types.h> diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index 7f376fd..9fba12f 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -25,7 +25,7 @@ #include <cpu/intel/em64t101_save_state.h> #include <elog.h> #include <halt.h> -#include <pc80/mc146818rtc.h> +#include <option.h> #include <southbridge/intel/common/pmbase.h> #include <smmstore.h> diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index a46f5a3..0e2aead 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c @@ -22,6 +22,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> +#include <option.h> #include <pc80/mc146818rtc.h> #include <pc80/isa-dma.h> #include <arch/io.h> diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 0330af0..779d319 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -18,6 +18,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <option.h> #include <pc80/mc146818rtc.h> #include <pc80/isa-dma.h> #include <pc80/i8259.h> diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index d541730..bac48c2 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -19,6 +19,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <option.h> #include <pc80/mc146818rtc.h> #include <pc80/isa-dma.h> #include <pc80/i8259.h> diff --git a/src/southbridge/intel/i82801ix/sata.c b/src/southbridge/intel/i82801ix/sata.c index fcf4045..546acdf 100644 --- a/src/southbridge/intel/i82801ix/sata.c +++ b/src/southbridge/intel/i82801ix/sata.c @@ -22,7 +22,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <pc80/mc146818rtc.h> +#include <option.h> #include <types.h> #include "chip.h" diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index a594452..91b1bde 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -19,6 +19,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <option.h> #include <pc80/mc146818rtc.h> #include <pc80/isa-dma.h> #include <pc80/i8259.h> diff --git a/src/southbridge/intel/i82801jx/sata.c b/src/southbridge/intel/i82801jx/sata.c index e6e08a3..ce8ae47 100644 --- a/src/southbridge/intel/i82801jx/sata.c +++ b/src/southbridge/intel/i82801jx/sata.c @@ -22,7 +22,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <pc80/mc146818rtc.h> +#include <option.h> #include <types.h> #include "chip.h" diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 324438e..851f4f5 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -19,6 +19,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <option.h> #include <pc80/mc146818rtc.h> #include <pc80/isa-dma.h> #include <pc80/i8259.h> diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c index 2d9412a..04e0564 100644 --- a/src/southbridge/intel/ibexpeak/sata.c +++ b/src/southbridge/intel/ibexpeak/sata.c @@ -21,7 +21,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <pc80/mc146818rtc.h> +#include <option.h> #include <acpi/sata.h> #include <types.h> diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 62d8aa6..4b39829 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -20,7 +20,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include <pc80/mc146818rtc.h> +#include <option.h> #include <pc80/isa-dma.h> #include <pc80/i8259.h> #include <arch/io.h> diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index 61f86fb..72c3447 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -25,7 +25,7 @@ #include <cpu/intel/em64t101_save_state.h> #include <elog.h> #include <halt.h> -#include <pc80/mc146818rtc.h> +#include <option.h> #include <southbridge/intel/common/finalize.h> #include <northbridge/intel/haswell/haswell.h> #include <cpu/intel/haswell/haswell.h> diff --git a/src/superio/ite/it8720f/superio.c b/src/superio/ite/it8720f/superio.c index 48bbfb2..b5198e7 100644 --- a/src/superio/ite/it8720f/superio.c +++ b/src/superio/ite/it8720f/superio.c @@ -18,7 +18,7 @@ #include <device/device.h> #include <device/pnp.h> #include <pc80/keyboard.h> -#include <pc80/mc146818rtc.h> +#include <option.h> #include <superio/ite/common/env_ctrl.h> #include <superio/conf_mode.h> #include <types.h> diff --git a/src/superio/nuvoton/nct5572d/superio.c b/src/superio/nuvoton/nct5572d/superio.c index 76c983a..163d6b9 100644 --- a/src/superio/nuvoton/nct5572d/superio.c +++ b/src/superio/nuvoton/nct5572d/superio.c @@ -20,7 +20,7 @@ #include <device/device.h> #include <device/pnp.h> #include <pc80/keyboard.h> -#include <pc80/mc146818rtc.h> +#include <option.h> #include <arch/acpi.h> #include <superio/conf_mode.h> diff --git a/src/superio/winbond/w83627ehg/superio.c b/src/superio/winbond/w83627ehg/superio.c index da50173..35fca01 100644 --- a/src/superio/winbond/w83627ehg/superio.c +++ b/src/superio/winbond/w83627ehg/superio.c @@ -23,7 +23,7 @@ #include <superio/hwm5_conf.h> #include <console/console.h> #include <pc80/keyboard.h> -#include <pc80/mc146818rtc.h> +#include <option.h> #include "w83627ehg.h" diff --git a/src/superio/winbond/w83627hf/superio.c b/src/superio/winbond/w83627hf/superio.c index a4d734f..4d76052 100644 --- a/src/superio/winbond/w83627hf/superio.c +++ b/src/superio/winbond/w83627hf/superio.c @@ -23,7 +23,7 @@ #include <superio/hwm5_conf.h> #include <console/console.h> #include <pc80/keyboard.h> -#include <pc80/mc146818rtc.h> +#include <option.h> #include "w83627hf.h" diff --git a/src/superio/winbond/w83667hg-a/superio.c b/src/superio/winbond/w83667hg-a/superio.c index 69ab91b..d0f4eef 100644 --- a/src/superio/winbond/w83667hg-a/superio.c +++ b/src/superio/winbond/w83667hg-a/superio.c @@ -20,7 +20,7 @@ #include <device/device.h> #include <device/pnp.h> #include <pc80/keyboard.h> -#include <pc80/mc146818rtc.h> +#include <option.h> #include <arch/acpi.h> #include <superio/conf_mode.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/38192 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad7b03dc985550da903d56b3deb5bd736013f8f1 Gerrit-Change-Number: 38192 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 7

Change in coreboot[master]: drivers/pc80/rtc: Remove duplicate cmos_chksum_valid()
by Kyösti Mälkki (Code Review) 09 Jan '20

09 Jan '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38194 ) Change subject: drivers/pc80/rtc: Remove duplicate cmos_chksum_valid() ...................................................................... drivers/pc80/rtc: Remove duplicate cmos_chksum_valid() This moves reference to LB_CKS_xxx to a file that is only built with USE_OPTION_TABLE and where option_table.h is always generated. Change-Id: I5a4b86921876c24cd1d310b674119b960c3d2fd6 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/drivers/pc80/rtc/mc146818rtc.c M src/drivers/pc80/rtc/mc146818rtc_boot.c M src/drivers/pc80/rtc/option.c M src/include/option.h 4 files changed, 9 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/38194/1 diff --git a/src/drivers/pc80/rtc/mc146818rtc.c b/src/drivers/pc80/rtc/mc146818rtc.c index fe6900f..d6a6279 100644 --- a/src/drivers/pc80/rtc/mc146818rtc.c +++ b/src/drivers/pc80/rtc/mc146818rtc.c @@ -26,18 +26,6 @@ #include <security/vboot/vbnv_layout.h> #include <types.h> -/* There's no way around this include guard. option_table.h is autogenerated */ -#if CONFIG(USE_OPTION_TABLE) -#include "option_table.h" -#else -#define LB_CKS_RANGE_START 0 -#define LB_CKS_RANGE_END 0 -#define LB_CKS_LOC 0 -#endif - -/* Don't warn for checking >= LB_CKS_RANGE_START even though it may be 0. */ -#pragma GCC diagnostic ignored "-Wtype-limits" - static void cmos_reset_date(void) { /* Now setup a default date equals to the build date */ @@ -154,8 +142,7 @@ if (CONFIG(USE_OPTION_TABLE)) { /* See if there is a LB CMOS checksum error */ - checksum_invalid = !cmos_checksum_valid(LB_CKS_RANGE_START, - LB_CKS_RANGE_END, LB_CKS_LOC); + checksum_invalid = !cmos_lb_cks_valid(); if (checksum_invalid) printk(BIOS_DEBUG, "RTC: coreboot checksum invalid\n"); diff --git a/src/drivers/pc80/rtc/mc146818rtc_boot.c b/src/drivers/pc80/rtc/mc146818rtc_boot.c index 307b1cf..89b2be3 100644 --- a/src/drivers/pc80/rtc/mc146818rtc_boot.c +++ b/src/drivers/pc80/rtc/mc146818rtc_boot.c @@ -17,30 +17,9 @@ #include <pc80/mc146818rtc.h> #include <fallback.h> -#if CONFIG(USE_OPTION_TABLE) -#include <option_table.h> - -static int cmos_chksum_valid(void) -{ - unsigned char addr; - u16 sum, old_sum; - - sum = 0; - /* Compute the cmos checksum */ - for (addr = LB_CKS_RANGE_START; addr <= LB_CKS_RANGE_END; addr++) - sum += cmos_read(addr); - - /* Read the stored checksum */ - old_sum = cmos_read(LB_CKS_LOC) << 8; - old_sum |= cmos_read(LB_CKS_LOC + 1); - - return sum == old_sum; -} - void sanitize_cmos(void) { - if (cmos_error() || !cmos_chksum_valid() || - CONFIG(STATIC_OPTION_TABLE)) { + if (cmos_error() || !cmos_lb_cks_valid() || CONFIG(STATIC_OPTION_TABLE)) { size_t length = 128; const unsigned char *cmos_default = cbfs_boot_map_with_leak("cmos.default", @@ -54,7 +33,6 @@ } } } -#endif #if CONFIG_MAX_REBOOT_CNT > 15 #error "CONFIG_MAX_REBOOT_CNT too high" @@ -84,7 +62,7 @@ { unsigned char byte; - if (cmos_error() || (CONFIG(USE_OPTION_TABLE) && !cmos_chksum_valid())) { + if (cmos_error() || (CONFIG(USE_OPTION_TABLE) && !cmos_lb_cks_valid())) { /* Invalid CMOS checksum detected! * Force fallback boot... */ diff --git a/src/drivers/pc80/rtc/option.c b/src/drivers/pc80/rtc/option.c index 65f75ef..0f4e553 100644 --- a/src/drivers/pc80/rtc/option.c +++ b/src/drivers/pc80/rtc/option.c @@ -233,3 +233,8 @@ rdev_munmap(&rdev, ct); return CB_SUCCESS; } + +int cmos_lb_cks_valid(void) +{ + return cmos_checksum_valid(LB_CKS_RANGE_START, LB_CKS_RANGE_END, LB_CKS_LOC); +} diff --git a/src/include/option.h b/src/include/option.h index 4bd5dee..e3736c9 100644 --- a/src/include/option.h +++ b/src/include/option.h @@ -17,6 +17,7 @@ #include <types.h> void sanitize_cmos(void); +int cmos_lb_cks_valid(void); /* * FIXME: get_option() needs to be abstracted better so that other non-volatile -- To view, visit https://review.coreboot.org/c/coreboot/+/38194 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a4b86921876c24cd1d310b674119b960c3d2fd6 Gerrit-Change-Number: 38194 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: Update Kconfig
by Subrata Banik (Code Review) 09 Jan '20

09 Jan '20

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37426 ) Change subject: soc/intel/tigerlake: Update Kconfig ...................................................................... soc/intel/tigerlake: Update Kconfig Update Kconfig: - use CAR NEM mode for tigerlake only as NEM Enhanced is under debug - update GSPI, RP max device #s according to PCH EDS#576591 vol1 rev1.2 - update UART M/N setting according to new PCH baseclock BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Change-Id: I04020d55f1063d521b15f8d0dabbd6f1dabf577c Signed-off-by: Wonkyu Kim <wonkyu.kim(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37426 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/tigerlake/Kconfig 1 file changed, 17 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Subrata Banik: Looks good to me, approved Wonkyu Kim: Looks good to me, approved diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index be4e26c..f1ae8a8 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -4,12 +4,15 @@ config SOC_INTEL_TIGERLAKE bool select SOC_INTEL_TIGERLAKE_BASE + #TODO - Enable INTEL_CAR_NEM_ENHANCED + select INTEL_CAR_NEM help Intel Tigerlake support config SOC_INTEL_JASPERLAKE bool select SOC_INTEL_TIGERLAKE_BASE + select INTEL_CAR_NEM_ENHANCED help Intel Jasperlake support @@ -61,7 +64,6 @@ select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_RESET select SOC_INTEL_COMMON_BLOCK_CAR - select INTEL_CAR_NEM_ENHANCED select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS select TSC_MONOTONIC_TIMER @@ -97,8 +99,8 @@ config IFD_CHIPSET string - default "tgl" if SOC_INTEL_TIGERLAKE default "jsl" if SOC_INTEL_JASPERLAKE + default "tgl" if SOC_INTEL_TIGERLAKE config IED_REGION_SIZE hex @@ -110,7 +112,8 @@ config MAX_ROOT_PORTS int - default 16 + default 16 if SOC_INTEL_JASPERLAKE + default 12 if SOC_INTEL_TIGERLAKE config SMM_TSEG_SIZE hex @@ -144,7 +147,8 @@ config SOC_INTEL_COMMON_BLOCK_GSPI_MAX int - default 3 + default 3 if SOC_INTEL_JASPERLAKE + default 4 if SOC_INTEL_TIGERLAKE config SOC_INTEL_I2C_DEV_MAX int @@ -160,13 +164,18 @@ depends on INTEL_LPSS_UART_FOR_CONSOLE # Clock divider parameters for 115200 baud rate +# Baudrate = (UART source clcok * M) /(N *16) +# TGL UART source clock: 120MHz +# JSL UART source clock: 100MHz config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL hex - default 0x30 + default 0x30 if SOC_INTEL_JASPERLAKE + default 0x25a if SOC_INTEL_TIGERLAKE config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL hex - default 0xc35 + default 0xc35 if SOC_INTEL_JASPERLAKE + default 0x7fff if SOC_INTEL_TIGERLAKE config CHROMEOS select CHROMEOS_RAMOOPS_DYNAMIC @@ -189,13 +198,13 @@ config FSP_HEADER_PATH string "Location of FSP headers" - default "src/vendorcode/intel/fsp/fsp2_0/tigerlake/" if SOC_INTEL_TIGERLAKE default "src/vendorcode/intel/fsp/fsp2_0/jasperlake/" if SOC_INTEL_JASPERLAKE + default "src/vendorcode/intel/fsp/fsp2_0/tigerlake/" if SOC_INTEL_TIGERLAKE config FSP_FD_PATH string depends on FSP_USE_REPO - default "3rdparty/fsp/TigerLakeFspBinPkg/Fsp.fd" if SOC_INTEL_TIGERLAKE default "3rdparty/fsp/JasperLakeFspBinPkg/Fsp.fd" if SOC_INTEL_JASPERLAKE + default "3rdparty/fsp/TigerLakeFspBinPkg/Fsp.fd" if SOC_INTEL_TIGERLAKE endif -- To view, visit https://review.coreboot.org/c/coreboot/+/37426 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I04020d55f1063d521b15f8d0dabbd6f1dabf577c Gerrit-Change-Number: 37426 Gerrit-PatchSet: 17 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Venkata Krishna Nimmagadda Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/tigerlake: Update Kconfig
by Subrata Banik (Code Review) 09 Jan '20

09 Jan '20

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37426 ) Change subject: soc/intel/tigerlake: Update Kconfig ...................................................................... Patch Set 16: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/37426 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I04020d55f1063d521b15f8d0dabbd6f1dabf577c Gerrit-Change-Number: 37426 Gerrit-PatchSet: 16 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Venkata Krishna Nimmagadda Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Thu, 09 Jan 2020 14:35:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: doc/tutorial/part1.md: Add information for yum- & pacman-based distro
by Patrik Tesarik (Code Review) 09 Jan '20

09 Jan '20

Hello Patrick Rudolph, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/38225 to look at the new patch set (#4). Change subject: doc/tutorial/part1.md: Add information for yum- & pacman-based distro ...................................................................... doc/tutorial/part1.md: Add information for yum- & pacman-based distro * Additional information on non-debian cli tools * Improve Spellings and descriptions to the best of my knowledge Adding info about needed tools in other distribution's package managers was requested at the coreboot beginner's workshop at 36C3. Change-Id: Ifff3c8354b4bec9f195f075eb6b2f377195fc237 Signed-off-by: Patrik Tesarik <mail(a)patrik-tesarik.de> --- D 3rdparty/amd_blobs M Documentation/tutorial/part1.md 2 files changed, 23 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/38225/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/38225 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifff3c8354b4bec9f195f075eb6b2f377195fc237 Gerrit-Change-Number: 38225 Gerrit-PatchSet: 4 Gerrit-Owner: Patrik Tesarik Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrik Tesarik Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marcello Sylvester Bauer <sylv(a)sylv.io> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: doc/tutorial/part1.md: Add information for yum- & pacman-based distro
by Patrik Tesarik (Code Review) 09 Jan '20

09 Jan '20

Hello Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/38225 to look at the new patch set (#3). Change subject: doc/tutorial/part1.md: Add information for yum- & pacman-based distro ...................................................................... doc/tutorial/part1.md: Add information for yum- & pacman-based distro * Additional information on non-debian cli tools * Improve Spellings and descriptions to the best of my knowledge Adding info about needed tools in other distribution's package managers was requested at the coreboot beginner's workshop at 36C3. Change-Id: Ifff3c8354b4bec9f195f075eb6b2f377195fc237 Signed-off-by: Patrik Tesarik <mail(a)patrik-tesarik.de> --- D 3rdparty/amd_blobs M Documentation/tutorial/part1.md 2 files changed, 24 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/38225/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/38225 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifff3c8354b4bec9f195f075eb6b2f377195fc237 Gerrit-Change-Number: 38225 Gerrit-PatchSet: 3 Gerrit-Owner: Patrik Tesarik Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrik Tesarik Gerrit-CC: Marcello Sylvester Bauer <sylv(a)sylv.io> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/intel/tglrvp: Add initial mainboard code
by Subrata Banik (Code Review) 09 Jan '20

09 Jan '20

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37868 ) Change subject: mb/intel/tglrvp: Add initial mainboard code ...................................................................... Patch Set 14: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/37868 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I86ada611de1cf28a1b872eea35cf41c0dc1c57f1 Gerrit-Change-Number: 37868 Gerrit-PatchSet: 14 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 09 Jan 2020 14:26:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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