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Change in coreboot[master]: nb/intel/i945,x4x,pineview: Remove wrapper spd_read_byte()
by Kyösti Mälkki (Code Review) 09 Jan '20

09 Jan '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38213 ) Change subject: nb/intel/i945,x4x,pineview: Remove wrapper spd_read_byte() ...................................................................... nb/intel/i945,x4x,pineview: Remove wrapper spd_read_byte() Change-Id: Ic9554ad2813ee70d0da16857d534aab5e17d808f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/northbridge/intel/i945/raminit.c M src/northbridge/intel/pineview/raminit.c M src/northbridge/intel/x4x/raminit.c 3 files changed, 4 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/38213/1 diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 7096774..f0ea142 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -62,11 +62,6 @@ } -static inline int spd_read_byte(unsigned int device, unsigned int address) -{ - return smbus_read_byte(device, address); -} - static __attribute__((noinline)) void do_ram_command(u32 command) { u32 reg32; @@ -365,7 +360,7 @@ if (!sdram_capabilities_dual_channel() && (i >> 1)) continue; - if (spd_read_byte(device, SPD_MEMORY_TYPE) != + if (smbus_read_byte(device, SPD_MEMORY_TYPE) != SPD_MEMORY_TYPE_SDRAM_DDR2) { printk(BIOS_DEBUG, "DDR II Channel %d Socket %d: N/A\n", (i >> 1), (i & 1)); @@ -386,7 +381,7 @@ printk(BIOS_DEBUG, "i2c block operation failed," " trying smbus byte operation.\n"); for (j = 0; j < 64; j++) - raw_spd[j] = spd_read_byte(device, j); + raw_spd[j] = smbus_read_byte(device, j); if (CONFIG(DEBUG_RAM_SETUP)) hexdump(raw_spd, 64); } diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index 720bd64..a9e2c3e 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -103,11 +103,6 @@ __asm__ __volatile__("": : :"memory"); } -static inline int spd_read_byte(unsigned int device, unsigned int address) -{ - return smbus_read_byte(device, address); -} - static int decode_spd(struct dimminfo *d, int i) { d->type = 0; diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index 8013af9..df2d31e 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -39,11 +39,6 @@ #define MRC_CACHE_VERSION 0 -static inline int spd_read_byte(unsigned int device, unsigned int address) -{ - return smbus_read_byte(device, address); -} - static u16 ddr2_get_crc(u8 device, u8 len) { u8 raw_spd[128] = {}; @@ -514,7 +509,7 @@ s->dimms[i].card_type = RAW_CARD_UNPOPULATED; continue; } - switch (spd_read_byte(s->spd_map[i], SPD_MEMORY_TYPE)) { + switch (smbus_read_byte(s->spd_map[i], SPD_MEMORY_TYPE)) { case DDR2SPD: dram_type_mask &= 1 << DDR2; s->spd_type = DDR2; @@ -535,7 +530,7 @@ printk(BIOS_DEBUG, "i2c block operation failed," " trying smbus byte operation.\n"); for (j = 0; j < 128; j++) - raw_spd[j] = spd_read_byte(device, j); + raw_spd[j] = smbus_read_byte(device, j); } if (s->spd_type == DDR2){ -- To view, visit https://review.coreboot.org/c/coreboot/+/38213 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9554ad2813ee70d0da16857d534aab5e17d808f Gerrit-Change-Number: 38213 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

2 5

Change in coreboot[master]: sb/intel/common: Add SMBUS register read-modify-write
by Kyösti Mälkki (Code Review) 09 Jan '20

09 Jan '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38151 ) Change subject: sb/intel/common: Add SMBUS register read-modify-write ...................................................................... sb/intel/common: Add SMBUS register read-modify-write Change-Id: Ibe967d02fd05f4a8f643a5c5b17885701946d1c7 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/southbridge/intel/common/smbus.c 1 file changed, 13 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/38151/1 diff --git a/src/southbridge/intel/common/smbus.c b/src/southbridge/intel/common/smbus.c index 00ff1dd..262de79 100644 --- a/src/southbridge/intel/common/smbus.c +++ b/src/southbridge/intel/common/smbus.c @@ -82,6 +82,15 @@ return inb(base + reg); } +static void host_update(unsigned int base, u8 reg, u8 mask, u8 or) +{ + u8 value; + value = host_inb(base, reg); + value &= mask; + value |= or; + host_outb(base, reg, value); +} + static int host_completed(u8 status) { if (status & SMBHSTSTS_HOST_BUSY) @@ -129,7 +138,7 @@ SMBUS_WAIT_UNTIL_READY_TIMEOUT); /* Clear any lingering errors, so the transaction will run. */ - host_outb(smbus_base, SMBHSTSTAT, host_inb(smbus_base, SMBHSTSTAT)); + host_update(smbus_base, SMBHSTSTAT, 0xff, 0); /* Set up transaction */ /* Disable interrupts */ @@ -147,7 +156,7 @@ u8 status; /* Start the command. */ - host_outb(smbus_base, SMBHSTCTL, host_inb(smbus_base, SMBHSTCTL) | SMBHSTCNT_START); + host_update(smbus_base, SMBHSTCTL, 0xff, SMBHSTCNT_START); /* Poll for it to start. */ do { @@ -298,9 +307,8 @@ /* Indicate that next byte is the last one. */ if (sw_drives_nak && (bytes + 1 >= max_bytes)) { - host_outb(smbus_base, SMBHSTCTL, - host_inb(smbus_base, SMBHSTCTL) | - SMBHSTCNT_LAST_BYTE); + host_update(smbus_base, SMBHSTCTL, + 0xff, SMBHSTCNT_LAST_BYTE); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/38151 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe967d02fd05f4a8f643a5c5b17885701946d1c7 Gerrit-Change-Number: 38151 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

3 7

Change in coreboot[master]: sb/intel/common: Replace inb/outb()
by Kyösti Mälkki (Code Review) 09 Jan '20

09 Jan '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38150 ) Change subject: sb/intel/common: Replace inb/outb() ...................................................................... sb/intel/common: Replace inb/outb() At least since ICH10 SMBUS controller implements register bank access via both IO and MMIO, we may want to change for the latter. Change-Id: I67fcbc7b6f6be61c93bc608e556a577ef9e52325 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/southbridge/intel/common/smbus.c 1 file changed, 41 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/38150/1 diff --git a/src/southbridge/intel/common/smbus.c b/src/southbridge/intel/common/smbus.c index 9546258..00ff1dd 100644 --- a/src/southbridge/intel/common/smbus.c +++ b/src/southbridge/intel/common/smbus.c @@ -72,6 +72,16 @@ inb(0x80); } +static void host_outb(unsigned int base, u8 reg, u8 value) +{ + outb(value, base + reg); +} + +static u8 host_inb(unsigned int base, u8 reg) +{ + return inb(base + reg); +} + static int host_completed(u8 status) { if (status & SMBHSTSTS_HOST_BUSY) @@ -111,7 +121,7 @@ do { smbus_delay(); - host_busy = inb(smbus_base + SMBHSTSTAT) & SMBHSTSTS_HOST_BUSY; + host_busy = host_inb(smbus_base, SMBHSTSTAT) & SMBHSTSTS_HOST_BUSY; } while (--loops && host_busy); if (loops == 0) @@ -119,14 +129,14 @@ SMBUS_WAIT_UNTIL_READY_TIMEOUT); /* Clear any lingering errors, so the transaction will run. */ - outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT); + host_outb(smbus_base, SMBHSTSTAT, host_inb(smbus_base, SMBHSTSTAT)); /* Set up transaction */ /* Disable interrupts */ - outb(ctrl, (smbus_base + SMBHSTCTL)); + host_outb(smbus_base, SMBHSTCTL, ctrl); /* Set the device I'm talking to. */ - outb(xmitadd, smbus_base + SMBXMITADD); + host_outb(smbus_base, SMBXMITADD, xmitadd); return 0; } @@ -137,8 +147,7 @@ u8 status; /* Start the command. */ - outb((inb(smbus_base + SMBHSTCTL) | SMBHSTCNT_START), - smbus_base + SMBHSTCTL); + host_outb(smbus_base, SMBHSTCTL, host_inb(smbus_base, SMBHSTCTL) | SMBHSTCNT_START); /* Poll for it to start. */ do { @@ -147,7 +156,7 @@ /* If we poll too slow, we could miss HOST_BUSY flag * set and detect INTR or x_ERR flags instead here. */ - status = inb(smbus_base + SMBHSTSTAT); + status = host_inb(smbus_base, SMBHSTSTAT); status &= ~(SMBHSTSTS_SMBALERT_STS | SMBHSTSTS_INUSE_STS); } while (--loops && status == 0); @@ -165,7 +174,7 @@ do { smbus_delay(); - status = inb(smbus_base + SMBHSTSTAT); + status = host_inb(smbus_base, SMBHSTSTAT); } while (--loops && !host_completed(status)); if (loops == 0) @@ -187,11 +196,11 @@ return ret; /* Set the command/address... */ - outb(address, smbus_base + SMBHSTCMD); + host_outb(smbus_base, SMBHSTCMD, address); /* Clear the data bytes... */ - outb(0, smbus_base + SMBHSTDAT0); - outb(0, smbus_base + SMBHSTDAT1); + host_outb(smbus_base, SMBHSTDAT0, 0); + host_outb(smbus_base, SMBHSTDAT1, 0); /* Start the command */ ret = execute_command(smbus_base); @@ -204,9 +213,9 @@ return ret; /* Read results of transaction */ - word = inb(smbus_base + SMBHSTDAT0); + word = host_inb(smbus_base, SMBHSTDAT0); if (ctrl == I801_WORD_DATA) - word |= inb(smbus_base + SMBHSTDAT1) << 8; + word |= host_inb(smbus_base, SMBHSTDAT1) << 8; return word; } @@ -222,12 +231,12 @@ return ret; /* Set the command/address... */ - outb(address, smbus_base + SMBHSTCMD); + host_outb(smbus_base, SMBHSTCMD, address); /* Set the data bytes... */ - outb(data & 0xff, smbus_base + SMBHSTDAT0); + host_outb(smbus_base, SMBHSTDAT0, data & 0xff); if (ctrl == I801_WORD_DATA) - outb(data >> 8, smbus_base + SMBHSTDAT1); + host_outb(smbus_base, SMBHSTDAT1, data >> 8); /* Start the command */ ret = execute_command(smbus_base); @@ -256,16 +265,16 @@ * was really updated with the transaction. */ if (!sw_drives_nak) { if (is_write_cmd) - outb(max_bytes, smbus_base + SMBHSTDAT0); + host_outb(smbus_base, SMBHSTDAT0, max_bytes); else - outb(0, smbus_base + SMBHSTDAT0); + host_outb(smbus_base, SMBHSTDAT0, 0); } /* Send first byte from buffer, bytes_sent increments after * hardware acknowledges it. */ if (is_write_cmd) - outb(*buf++, smbus_base + SMBBLKDAT); + host_outb(smbus_base, SMBBLKDAT, *buf++); /* Start the command */ ret = execute_command(smbus_base); @@ -274,24 +283,24 @@ /* Poll for transaction completion */ do { - status = inb(smbus_base + SMBHSTSTAT); + status = host_inb(smbus_base, SMBHSTSTAT); if (status & SMBHSTSTS_BYTE_DONE) { /* Byte done */ if (is_write_cmd) { bytes++; if (bytes < max_bytes) - outb(*buf++, smbus_base + SMBBLKDAT); + host_outb(smbus_base, SMBBLKDAT, *buf++); } else { if (bytes < max_bytes) - *buf++ = inb(smbus_base + SMBBLKDAT); + *buf++ = host_inb(smbus_base, SMBBLKDAT); bytes++; /* Indicate that next byte is the last one. */ if (sw_drives_nak && (bytes + 1 >= max_bytes)) { - outb(inb(smbus_base + SMBHSTCTL) - | SMBHSTCNT_LAST_BYTE, - smbus_base + SMBHSTCTL); + host_outb(smbus_base, SMBHSTCTL, + host_inb(smbus_base, SMBHSTCTL) | + SMBHSTCNT_LAST_BYTE); } } @@ -300,7 +309,7 @@ * and clears HOST_BUSY flag once the byte count * has been reached or LAST_BYTE was set. */ - outb(SMBHSTSTS_BYTE_DONE, smbus_base + SMBHSTSTAT); + host_outb(smbus_base, SMBHSTSTAT, SMBHSTSTS_BYTE_DONE); } } while (--loops && !host_completed(status)); @@ -354,7 +363,7 @@ return ret; /* Set the command/address... */ - outb(cmd, smbus_base + SMBHSTCMD); + host_outb(smbus_base, SMBHSTCMD, cmd); /* Execute block transaction. */ ret = block_cmd_loop(smbus_base, buf, max_bytes, BLOCK_READ); @@ -362,7 +371,7 @@ return ret; /* Post-check we received complete message. */ - slave_bytes = inb(smbus_base + SMBHSTDAT0); + slave_bytes = host_inb(smbus_base, SMBHSTDAT0); if (ret < slave_bytes) return SMBUS_ERROR; @@ -383,7 +392,7 @@ return ret; /* Set the command/address... */ - outb(cmd, smbus_base + SMBHSTCMD); + host_outb(smbus_base, SMBHSTCMD, cmd); /* Execute block transaction. */ ret = block_cmd_loop(smbus_base, (u8 *)buf, bytes, BLOCK_WRITE); @@ -425,7 +434,7 @@ return ret; /* device offset */ - outb(offset, smbus_base + SMBHSTDAT1); + host_outb(smbus_base, SMBHSTDAT1, offset); /* Execute block transaction. */ ret = block_cmd_loop(smbus_base, buf, bytes, BLOCK_READ | BLOCK_I2C); @@ -468,8 +477,8 @@ */ cmd = *buf++; bytes--; - outb(cmd, smbus_base + SMBHSTCMD); - outb(cmd, smbus_base + SMBHSTDAT1); + host_outb(smbus_base, SMBHSTCMD, cmd); + host_outb(smbus_base, SMBHSTDAT1, cmd); /* Execute block transaction. */ ret = block_cmd_loop(smbus_base, buf, bytes, BLOCK_WRITE); -- To view, visit https://review.coreboot.org/c/coreboot/+/38150 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67fcbc7b6f6be61c93bc608e556a577ef9e52325 Gerrit-Change-Number: 38150 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: soc/intel/common: Drop old forked version of SMBUS support
by Kyösti Mälkki (Code Review) 09 Jan '20

09 Jan '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38149 ) Change subject: soc/intel/common: Drop old forked version of SMBUS support ...................................................................... soc/intel/common: Drop old forked version of SMBUS support Change-Id: Idbff410991db9592a58b9cc0ae7ee8c45d750b13 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/common/block/smbus/smbus.c M src/soc/intel/common/block/smbus/smbuslib.c M src/soc/intel/common/block/smbus/smbuslib.h M src/soc/intel/common/pch/Kconfig 4 files changed, 4 insertions(+), 165 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/38149/1 diff --git a/src/soc/intel/common/block/smbus/smbus.c b/src/soc/intel/common/block/smbus/smbus.c index f22bacd..95def11 100644 --- a/src/soc/intel/common/block/smbus/smbus.c +++ b/src/soc/intel/common/block/smbus/smbus.c @@ -20,6 +20,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <soc/smbus.h> +#include <southbridge/intel/common/smbus.h> #include "smbuslib.h" static int lsmbus_read_byte(struct device *dev, u8 address) diff --git a/src/soc/intel/common/block/smbus/smbuslib.c b/src/soc/intel/common/block/smbus/smbuslib.c index 0004ba7..126adee 100644 --- a/src/soc/intel/common/block/smbus/smbuslib.c +++ b/src/soc/intel/common/block/smbus/smbuslib.c @@ -13,171 +13,12 @@ * GNU General Public License for more details. */ -#include <arch/io.h> #include <console/console.h> -#include <device/smbus_def.h> #include <spd_bin.h> +#include <southbridge/intel/common/smbus.h> #include <string.h> -#include <timer.h> #include "smbuslib.h" -static int smbus_wait_till_ready(u16 smbus_base) -{ - struct stopwatch sw; - unsigned char byte; - - stopwatch_init_msecs_expire(&sw, SMBUS_TIMEOUT); - do { - byte = inb(smbus_base + SMBHSTSTAT); - if (!(byte & 1)) - return 0; - } while (!stopwatch_expired(&sw)); - return -1; -} - -static int smbus_wait_till_done(u16 smbus_base) -{ - struct stopwatch sw; - unsigned char byte; - - stopwatch_init_msecs_expire(&sw, SMBUS_TIMEOUT); - do { - byte = inb(smbus_base + SMBHSTSTAT); - if (!((byte & 1) || (byte & ~((1 << 6) | (1 << 0))) == 0)) - return 0; - } while (!stopwatch_expired(&sw)); - return -1; -} - -int do_smbus_read_byte(unsigned int smbus_base, u8 device, unsigned int address) -{ - unsigned char global_status_register; - unsigned char byte; - - if (smbus_wait_till_ready(smbus_base) < 0) - return SMBUS_WAIT_UNTIL_READY_TIMEOUT; - - /* Setup transaction */ - /* Disable interrupts */ - outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL); - /* Set the device I'm talking to */ - outb(((device & 0x7f) << 1) | 1, smbus_base + SMBXMITADD); - /* Set the command/address... */ - outb(address & 0xff, smbus_base + SMBHSTCMD); - /* Set up for a byte data read */ - outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x2 << 2), - (smbus_base + SMBHSTCTL)); - /* Clear any lingering errors, so the transaction will run */ - outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT); - - /* Clear the data byte... */ - outb(0, smbus_base + SMBHSTDAT0); - - /* Start the command */ - outb((inb(smbus_base + SMBHSTCTL) | 0x40), - smbus_base + SMBHSTCTL); - - /* Poll for transaction completion */ - if (smbus_wait_till_done(smbus_base) < 0) - return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; - - global_status_register = inb(smbus_base + SMBHSTSTAT); - - /* Ignore the "In Use" status... */ - global_status_register &= ~(3 << 5); - - /* Read results of transaction */ - byte = inb(smbus_base + SMBHSTDAT0); - if (global_status_register != (1 << 1)) - return SMBUS_ERROR; - - return byte; -} - -int do_smbus_write_byte(unsigned int smbus_base, u8 device, unsigned int address, - unsigned int data) -{ - unsigned char global_status_register; - - if (smbus_wait_till_ready(smbus_base) < 0) - return SMBUS_WAIT_UNTIL_READY_TIMEOUT; - - /* Setup transaction */ - /* Disable interrupts */ - outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL); - /* Set the device I'm talking to */ - outb(((device & 0x7f) << 1) & ~0x01, smbus_base + SMBXMITADD); - /* Set the command/address... */ - outb(address & 0xff, smbus_base + SMBHSTCMD); - /* Set up for a byte data read */ - outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x2 << 2), - (smbus_base + SMBHSTCTL)); - /* Clear any lingering errors, so the transaction will run */ - outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT); - - /* Clear the data byte... */ - outb(data, smbus_base + SMBHSTDAT0); - - /* Start the command */ - outb((inb(smbus_base + SMBHSTCTL) | 0x40), - smbus_base + SMBHSTCTL); - - /* Poll for transaction completion */ - if (smbus_wait_till_done(smbus_base) < 0) - return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; - - global_status_register = inb(smbus_base + SMBHSTSTAT); - - /* Ignore the "In Use" status... */ - global_status_register &= ~(3 << 5); - - /* Read results of transaction */ - if (global_status_register != (1 << 1)) - return SMBUS_ERROR; - - return 0; -} - -int do_smbus_read_word(unsigned int smbus_base, u8 device, unsigned int address) -{ - unsigned char global_status_register; - unsigned short data; - - if (smbus_wait_till_ready(smbus_base) < 0) - return SMBUS_WAIT_UNTIL_READY_TIMEOUT; - - /* Set up transaction */ - /* Disable interrupts */ - outb(inb(smbus_base + SMBHSTCTL) & ~1, smbus_base + SMBHSTCTL); - /* Set the device I'm talking to */ - outb(((device & 0x7f) << 1) | 1, smbus_base + SMBXMITADD); - /* Set the command/address... */ - outb(address & 0xff, smbus_base + SMBHSTCMD); - /* Set up for a word data read */ - outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x3 << 2), - (smbus_base + SMBHSTCTL)); - /* Clear any lingering errors, so the transaction will run */ - outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT); - - /* Start the command */ - outb((inb(smbus_base + SMBHSTCTL) | 0x40), - smbus_base + SMBHSTCTL); - - /* Poll for transaction completion */ - if (smbus_wait_till_done(smbus_base) < 0) - return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; - - global_status_register = inb(smbus_base + SMBHSTSTAT); - /* Ignore the "In Use" status... */ - if ((global_status_register & ~(3 << 5)) != (1 << 1)) - return SMBUS_ERROR; - - /* Read results of transaction */ - data = inw(smbus_base + SMBHSTDAT0); - - return data; -} - static void update_spd_len(struct spd_block *blk) { u8 i, j = 0; diff --git a/src/soc/intel/common/block/smbus/smbuslib.h b/src/soc/intel/common/block/smbus/smbuslib.h index 45902a0..adc2d30 100644 --- a/src/soc/intel/common/block/smbus/smbuslib.h +++ b/src/soc/intel/common/block/smbus/smbuslib.h @@ -20,6 +20,7 @@ /* SMBus IO Base Address */ #define SMBUS_IO_BASE 0xefa0 + /* PCI Configuration Space : SMBus */ #define HOSTC 0x40 #define HST_EN (1 << 0) @@ -32,9 +33,4 @@ #define SMBUS_TIMEOUT 15 /* 15ms */ -int do_smbus_read_byte(unsigned int smbus_base, u8 device, unsigned int address); -int do_smbus_write_byte(unsigned int smbus_base, u8 device, unsigned int address, - unsigned int data); -int do_smbus_read_word(unsigned int smbus_base, u8 device, unsigned int address); - #endif /* SOC_INTEL_COMMON_BLOCK_SMBUS__LIB_H */ diff --git a/src/soc/intel/common/pch/Kconfig b/src/soc/intel/common/pch/Kconfig index 993593d..7f662fc 100644 --- a/src/soc/intel/common/pch/Kconfig +++ b/src/soc/intel/common/pch/Kconfig @@ -44,5 +44,6 @@ select SOC_INTEL_COMMON_BLOCK_XDCI select SOC_INTEL_COMMON_BLOCK_XHCI select SOC_INTEL_COMMON_PCH_LOCKDOWN + select SOUTHBRIDGE_INTEL_COMMON_SMBUS endif -- To view, visit https://review.coreboot.org/c/coreboot/+/38149 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idbff410991db9592a58b9cc0ae7ee8c45d750b13 Gerrit-Change-Number: 38149 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: soc/intel/broadwell: Drop old forked version of SMBUS support
by Kyösti Mälkki (Code Review) 09 Jan '20

09 Jan '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38142 ) Change subject: soc/intel/broadwell: Drop old forked version of SMBUS support ...................................................................... soc/intel/broadwell: Drop old forked version of SMBUS support Change-Id: Icbd54b5671ea2a94aea5db4642698ef679540625 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/broadwell/Kconfig M src/soc/intel/broadwell/Makefile.inc M src/soc/intel/broadwell/include/soc/romstage.h M src/soc/intel/broadwell/include/soc/smbus.h M src/soc/intel/broadwell/romstage/smbus.c M src/soc/intel/broadwell/smbus.c D src/soc/intel/broadwell/smbus_common.c 7 files changed, 2 insertions(+), 162 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/38142/1 diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index f01777f..20219d3 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -20,6 +20,7 @@ select HAVE_SMI_HANDLER select SOUTHBRIDGE_INTEL_COMMON_RESET select SOUTHBRIDGE_INTEL_COMMON_RTC + select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 select HAVE_USBDEBUG select IOAPIC diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index 03aa3fb..be854b2 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -53,8 +53,6 @@ ramstage-y += sata.c ramstage-y += serialio.c ramstage-y += smbus.c -ramstage-y += smbus_common.c -romstage-y += smbus_common.c ramstage-y += smi.c smm-y += smihandler.c ramstage-y += smmrelocate.c diff --git a/src/soc/intel/broadwell/include/soc/romstage.h b/src/soc/intel/broadwell/include/soc/romstage.h index 7d0270f..4631652 100644 --- a/src/soc/intel/broadwell/include/soc/romstage.h +++ b/src/soc/intel/broadwell/include/soc/romstage.h @@ -43,6 +43,5 @@ void intel_early_me_status(void); void enable_smbus(void); -int smbus_read_byte(unsigned int device, unsigned int address); #endif diff --git a/src/soc/intel/broadwell/include/soc/smbus.h b/src/soc/intel/broadwell/include/soc/smbus.h index 4d9d3e1..40aaf43 100644 --- a/src/soc/intel/broadwell/include/soc/smbus.h +++ b/src/soc/intel/broadwell/include/soc/smbus.h @@ -40,9 +40,4 @@ #define SMBUS_TIMEOUT (10 * 1000 * 100) #define SMBUS_SLAVE_ADDR 0x24 -int do_smbus_read_byte(unsigned int smbus_base, unsigned int device, - unsigned int address); -int do_smbus_write_byte(unsigned int smbus_base, unsigned int device, - unsigned int address, unsigned int data); - #endif diff --git a/src/soc/intel/broadwell/romstage/smbus.c b/src/soc/intel/broadwell/romstage/smbus.c index 48ba684..dd5d030 100644 --- a/src/soc/intel/broadwell/romstage/smbus.c +++ b/src/soc/intel/broadwell/romstage/smbus.c @@ -40,8 +40,3 @@ { reg_script_run_on_dev(PCH_DEV_SMBUS, smbus_init_script); } - -int smbus_read_byte(unsigned int device, unsigned int address) -{ - return do_smbus_read_byte(SMBUS_BASE_ADDRESS, device, address); -} diff --git a/src/soc/intel/broadwell/smbus.c b/src/soc/intel/broadwell/smbus.c index 68d3983..35fbc24 100644 --- a/src/soc/intel/broadwell/smbus.c +++ b/src/soc/intel/broadwell/smbus.c @@ -24,6 +24,7 @@ #include <soc/iomap.h> #include <soc/ramstage.h> #include <soc/smbus.h> +#include <southbridge/intel/common/smbus.h> static void pch_smbus_init(struct device *dev) { diff --git a/src/soc/intel/broadwell/smbus_common.c b/src/soc/intel/broadwell/smbus_common.c deleted file mode 100644 index 99ed55b..0000000 --- a/src/soc/intel/broadwell/smbus_common.c +++ /dev/null @@ -1,149 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 Yinghai Lu <yinghailu(a)gmail.com> - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <console/console.h> -#include <device/device.h> -#include <device/path.h> -#include <device/smbus_def.h> -#include <device/pci.h> -#include <soc/ramstage.h> -#include <soc/smbus.h> - -static void smbus_delay(void) -{ - inb(0x80); -} - -static int smbus_wait_until_ready(u16 smbus_base) -{ - unsigned int loops = SMBUS_TIMEOUT; - unsigned char byte; - do { - smbus_delay(); - if (--loops == 0) - break; - byte = inb(smbus_base + SMBHSTSTAT); - } while (byte & 1); - return loops ? 0 : -1; -} - -static int smbus_wait_until_done(u16 smbus_base) -{ - unsigned int loops = SMBUS_TIMEOUT; - unsigned char byte; - do { - smbus_delay(); - if (--loops == 0) - break; - byte = inb(smbus_base + SMBHSTSTAT); - } while ((byte & 1) || (byte & ~((1 << 6) | (1 << 0))) == 0); - return loops ? 0 : -1; -} - -int do_smbus_read_byte(unsigned int smbus_base, unsigned int device, - unsigned int address) -{ - unsigned char global_status_register; - unsigned char byte; - - if (smbus_wait_until_ready(smbus_base) < 0) - return SMBUS_WAIT_UNTIL_READY_TIMEOUT; - - /* Setup transaction */ - /* Disable interrupts */ - outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL); - /* Set the device I'm talking to */ - outb(((device & 0x7f) << 1) | 1, smbus_base + SMBXMITADD); - /* Set the command/address... */ - outb(address & 0xff, smbus_base + SMBHSTCMD); - /* Set up for a byte data read */ - outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x2 << 2), - (smbus_base + SMBHSTCTL)); - /* Clear any lingering errors, so the transaction will run */ - outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT); - - /* Clear the data byte... */ - outb(0, smbus_base + SMBHSTDAT0); - - /* Start the command */ - outb((inb(smbus_base + SMBHSTCTL) | 0x40), - smbus_base + SMBHSTCTL); - - /* Poll for transaction completion */ - if (smbus_wait_until_done(smbus_base) < 0) - return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; - - global_status_register = inb(smbus_base + SMBHSTSTAT); - - /* Ignore the "In Use" status... */ - global_status_register &= ~(3 << 5); - - /* Read results of transaction */ - byte = inb(smbus_base + SMBHSTDAT0); - if (global_status_register != (1 << 1)) - return SMBUS_ERROR; - return byte; -} - -int do_smbus_write_byte(unsigned int smbus_base, unsigned int device, - unsigned int address, unsigned int data) -{ - unsigned char global_status_register; - - if (smbus_wait_until_ready(smbus_base) < 0) - return SMBUS_WAIT_UNTIL_READY_TIMEOUT; - - /* Setup transaction */ - /* Disable interrupts */ - outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL); - /* Set the device I'm talking to */ - outb(((device & 0x7f) << 1) & ~0x01, smbus_base + SMBXMITADD); - /* Set the command/address... */ - outb(address & 0xff, smbus_base + SMBHSTCMD); - /* Set up for a byte data read */ - outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x2 << 2), - (smbus_base + SMBHSTCTL)); - /* Clear any lingering errors, so the transaction will run */ - outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT); - - /* Clear the data byte... */ - outb(data, smbus_base + SMBHSTDAT0); - - /* Start the command */ - outb((inb(smbus_base + SMBHSTCTL) | 0x40), - smbus_base + SMBHSTCTL); - - /* Poll for transaction completion */ - if (smbus_wait_until_done(smbus_base) < 0) { - printk(BIOS_ERR, "SMBUS transaction timeout\n"); - return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; - } - - global_status_register = inb(smbus_base + SMBHSTSTAT); - - /* Ignore the "In Use" status... */ - global_status_register &= ~(3 << 5); - - /* Read results of transaction */ - if (global_status_register != (1 << 1)) { - printk(BIOS_ERR, "SMBUS transaction error\n"); - return SMBUS_ERROR; - } - - return 0; -} -- To view, visit https://review.coreboot.org/c/coreboot/+/38142 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icbd54b5671ea2a94aea5db4642698ef679540625 Gerrit-Change-Number: 38142 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: sb/intel/common: Add smbus_{read/write}_word() variants
by Kyösti Mälkki (Code Review) 09 Jan '20

09 Jan '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38141 ) Change subject: sb/intel/common: Add smbus_{read/write}_word() variants ...................................................................... sb/intel/common: Add smbus_{read/write}_word() variants Change-Id: I1a9432c901e7baa545d34c1d0f82212bf59f8e23 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/southbridge/intel/common/smbus.c M src/southbridge/intel/common/smbus.h 2 files changed, 43 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/38141/1 diff --git a/src/southbridge/intel/common/smbus.c b/src/southbridge/intel/common/smbus.c index db934a3..9546258 100644 --- a/src/southbridge/intel/common/smbus.c +++ b/src/southbridge/intel/common/smbus.c @@ -175,22 +175,23 @@ return cb_err_from_stat(status); } -int do_smbus_read_byte(unsigned int smbus_base, u8 device, +static int smbus_read_cmd(unsigned int smbus_base, u8 ctrl, u8 device, unsigned int address) { int ret; - u8 byte; + u16 word; /* Set up for a byte data read. */ - ret = setup_command(smbus_base, I801_BYTE_DATA, XMIT_READ(device)); + ret = setup_command(smbus_base, ctrl, XMIT_READ(device)); if (ret < 0) return ret; /* Set the command/address... */ outb(address, smbus_base + SMBHSTCMD); - /* Clear the data byte... */ + /* Clear the data bytes... */ outb(0, smbus_base + SMBHSTDAT0); + outb(0, smbus_base + SMBHSTDAT1); /* Start the command */ ret = execute_command(smbus_base); @@ -203,25 +204,30 @@ return ret; /* Read results of transaction */ - byte = inb(smbus_base + SMBHSTDAT0); - return byte; + word = inb(smbus_base + SMBHSTDAT0); + if (ctrl == I801_WORD_DATA) + word |= inb(smbus_base + SMBHSTDAT1) << 8; + + return word; } -int do_smbus_write_byte(unsigned int smbus_base, u8 device, +static int smbus_write_cmd(unsigned int smbus_base, u8 ctrl, u8 device, unsigned int address, unsigned int data) { int ret; /* Set up for a byte data write. */ - ret = setup_command(smbus_base, I801_BYTE_DATA, XMIT_WRITE(device)); + ret = setup_command(smbus_base, ctrl, XMIT_WRITE(device)); if (ret < 0) return ret; /* Set the command/address... */ outb(address, smbus_base + SMBHSTCMD); - /* Set the data byte... */ - outb(data, smbus_base + SMBHSTDAT0); + /* Set the data bytes... */ + outb(data & 0xff, smbus_base + SMBHSTDAT0); + if (ctrl == I801_WORD_DATA) + outb(data >> 8, smbus_base + SMBHSTDAT1); /* Start the command */ ret = execute_command(smbus_base); @@ -313,6 +319,28 @@ return bytes; } +int do_smbus_read_byte(unsigned int smbus_base, u8 device, unsigned int address) +{ + return smbus_read_cmd(smbus_base, I801_BYTE_DATA, device, address); +} + +int do_smbus_read_word(unsigned int smbus_base, u8 device, unsigned int address) +{ + return smbus_read_cmd(smbus_base, I801_WORD_DATA, device, address); +} + +int do_smbus_write_byte(unsigned int smbus_base, u8 device, unsigned int address, + unsigned int data) +{ + return smbus_write_cmd(smbus_base, I801_BYTE_DATA, device, address, data); +} + +int do_smbus_write_word(unsigned int smbus_base, u8 device, unsigned int address, + unsigned int data) +{ + return smbus_write_cmd(smbus_base, I801_WORD_DATA, device, address, data); +} + int do_smbus_block_read(unsigned int smbus_base, u8 device, u8 cmd, unsigned int max_bytes, u8 *buf) { diff --git a/src/southbridge/intel/common/smbus.h b/src/southbridge/intel/common/smbus.h index 4875581..c70a3ee 100644 --- a/src/southbridge/intel/common/smbus.h +++ b/src/southbridge/intel/common/smbus.h @@ -36,6 +36,11 @@ unsigned int address); int do_smbus_write_byte(unsigned int smbus_base, u8 device, unsigned int address, unsigned int data); +int do_smbus_read_word(unsigned int smbus_base, u8 device, + unsigned int address); +int do_smbus_write_word(unsigned int smbus_base, u8 device, + unsigned int address, unsigned int data); + int do_smbus_block_read(unsigned int smbus_base, u8 device, u8 cmd, unsigned int max_bytes, u8 *buf); int do_smbus_block_write(unsigned int smbus_base, u8 device, -- To view, visit https://review.coreboot.org/c/coreboot/+/38141 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1a9432c901e7baa545d34c1d0f82212bf59f8e23 Gerrit-Change-Number: 38141 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: soc/intel/common: Remove extra call layer
by Kyösti Mälkki (Code Review) 09 Jan '20

09 Jan '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38122 ) Change subject: soc/intel/common: Remove extra call layer ...................................................................... soc/intel/common: Remove extra call layer Change-Id: I6987eb58b593e1f2bc6adf91be61bf7b5382440d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/common/block/smbus/smbuslib.c 1 file changed, 4 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/38122/1 diff --git a/src/soc/intel/common/block/smbus/smbuslib.c b/src/soc/intel/common/block/smbus/smbuslib.c index 0680ce2..6ea77ba 100644 --- a/src/soc/intel/common/block/smbus/smbuslib.c +++ b/src/soc/intel/common/block/smbus/smbuslib.c @@ -178,21 +178,6 @@ return data; } -static u16 smbus_read_word(u8 addr, u8 offset) -{ - return do_smbus_read_word(SMBUS_IO_BASE, addr, offset); -} - -static u8 smbus_read_byte(u8 addr, u8 offset) -{ - return do_smbus_read_byte(SMBUS_IO_BASE, addr, offset); -} - -static u8 smbus_write_byte(u8 addr, u8 offset, u8 value) -{ - return do_smbus_write_byte(SMBUS_IO_BASE, addr, offset, value); -} - static void update_spd_len(struct spd_block *blk) { u8 i, j = 0; @@ -218,9 +203,9 @@ for (i = 0; i < SPD_PAGE_LEN; i += step) { if (CONFIG(SPD_READ_BY_WORD)) ((u16*)spd)[i / sizeof(uint16_t)] = - smbus_read_word(addr, i); + do_smbus_read_word(SMBUS_IO_BASE, addr, i); else - spd[i] = smbus_read_byte(addr, i); + spd[i] = do_smbus_read_byte(SMBUS_IO_BASE, addr, i); } } @@ -239,10 +224,10 @@ if (spd[SPD_DRAM_TYPE] == SPD_DRAM_DDR4 && CONFIG_DIMM_SPD_SIZE > SPD_PAGE_LEN) { /* Switch to page 1 */ - smbus_write_byte(SPD_PAGE_1, 0, 0); + do_smbus_write_byte(SMBUS_IO_BASE, SPD_PAGE_1, 0, 0); smbus_read_spd(spd + SPD_PAGE_LEN, addr); /* Restore to page 0 */ - smbus_write_byte(SPD_PAGE_0, 0, 0); + do_smbus_write_byte(SMBUS_IO_BASE, SPD_PAGE_0, 0, 0); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/38122 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6987eb58b593e1f2bc6adf91be61bf7b5382440d Gerrit-Change-Number: 38122 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: [WIP] lib/spd_bim,soc/intel/common: Move get_spd_smbus()
by Kyösti Mälkki (Code Review) 09 Jan '20

09 Jan '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38121 ) Change subject: [WIP] lib/spd_bim,soc/intel/common: Move get_spd_smbus() ...................................................................... [WIP] lib/spd_bim,soc/intel/common: Move get_spd_smbus() Only smbuslib.c and spd_bin.c share the same prototypes for SMBUS functions. Therefore, get_spd_smbus() currently only works with soc/intel/.../smbuslib.c and can be implemented there locally. This allows removal of <device/early_smbus.h>. Change-Id: Ic2d9d83ede6388a01d40c6e4768f6bb6bf899c00 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- D src/include/device/early_smbus.h M src/lib/spd_bin.c M src/soc/intel/common/block/smbus/smbuslib.c 3 files changed, 73 insertions(+), 128 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/38121/1 diff --git a/src/include/device/early_smbus.h b/src/include/device/early_smbus.h deleted file mode 100644 index 015be67..0000000 --- a/src/include/device/early_smbus.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/** - * @file device/early_smbus.h - * - * This file defines a common API for accessing the SMBus during early - * initialization. It defines the prototypes for common SMBus functions. The - * actual implementations are hardware-dependent. - * - * The first parameter of all SMBus functions take a u32 value smbus_dev which - * represents some information on how to access the device, and is - * implementation defined. Usually, it just contains the IO base for the smbus. - * To get this argument @ref smbus_get_device() can be used. - * - * The header only defines the prototypes. Several steps are needed to use - * these: - * - * 1. Include this header - * @code{.c} - * #include <device/early_smbus.h> - * @endcode - * - * 2. Implement early_smbus.c for the hardware, or find a compatible - * implementation. - * - * 3. Link against the file that implements these functions. In the Makefile.inc - * of the chipset, add: - * @code - * romstage-y += ./path/to/early_smbus.c - * @endcode - */ - -#ifndef DEVICE_EARLY_SMBUS_H -#define DEVICE_EARLY_SMBUS_H - -#include <stdint.h> - -u16 smbus_read_word(u8 addr, u8 offset); -u8 smbus_read_byte(u8 addr, u8 offset); -u8 smbus_write_byte(u8 addr, u8 offset, u8 value); - -#endif /* DEVICE_EARLY_SMBUS_H */ diff --git a/src/lib/spd_bin.c b/src/lib/spd_bin.c index b022200..9e625b5 100644 --- a/src/lib/spd_bin.c +++ b/src/lib/spd_bin.c @@ -17,11 +17,8 @@ #include <console/console.h> #include <spd_bin.h> #include <string.h> -#include <device/early_smbus.h> #include <device/dram/ddr3.h> -static u8 spd_data[CONFIG_DIMM_MAX * CONFIG_DIMM_SPD_SIZE]; - void dump_spd_info(struct spd_block *blk) { u8 i; @@ -189,20 +186,6 @@ } } -static void update_spd_len(struct spd_block *blk) -{ - u8 i, j = 0; - for (i = 0 ; i < CONFIG_DIMM_MAX; i++) - if (blk->spd_array[i] != NULL) - j |= blk->spd_array[i][SPD_DRAM_TYPE]; - - /* If spd used is DDR4, then its length is 512 byte. */ - if (j == SPD_DRAM_DDR4) - blk->len = SPD_PAGE_LEN_DDR4; - else - blk->len = SPD_PAGE_LEN; -} - int get_spd_cbfs_rdev(struct region_device *spd_rdev, u8 spd_index) { struct cbfsf fh; @@ -216,57 +199,6 @@ CONFIG_DIMM_SPD_SIZE); } -static void smbus_read_spd(u8 *spd, u8 addr) -{ - u16 i; - u8 step = 1; - - if (CONFIG(SPD_READ_BY_WORD)) - step = sizeof(uint16_t); - - for (i = 0; i < SPD_PAGE_LEN; i += step) { - if (CONFIG(SPD_READ_BY_WORD)) - ((u16*)spd)[i / sizeof(uint16_t)] = - smbus_read_word(addr, i); - else - spd[i] = smbus_read_byte(addr, i); - } -} - -static void get_spd(u8 *spd, u8 addr) -{ - if (smbus_read_byte(addr, 0) == 0xff) { - printk(BIOS_INFO, "No memory dimm at address %02X\n", - addr << 1); - /* Make sure spd is zeroed if dimm doesn't exist. */ - memset(spd, 0, CONFIG_DIMM_SPD_SIZE); - return; - } - smbus_read_spd(spd, addr); - - /* Check if module is DDR4, DDR4 spd is 512 byte. */ - if (spd[SPD_DRAM_TYPE] == SPD_DRAM_DDR4 && - CONFIG_DIMM_SPD_SIZE > SPD_PAGE_LEN) { - /* Switch to page 1 */ - smbus_write_byte(SPD_PAGE_1, 0, 0); - smbus_read_spd(spd + SPD_PAGE_LEN, addr); - /* Restore to page 0 */ - smbus_write_byte(SPD_PAGE_0, 0, 0); - } -} - -void get_spd_smbus(struct spd_block *blk) -{ - u8 i; - for (i = 0 ; i < CONFIG_DIMM_MAX; i++) { - get_spd(&spd_data[i * CONFIG_DIMM_SPD_SIZE], - blk->addr_map[i]); - blk->spd_array[i] = &spd_data[i * CONFIG_DIMM_SPD_SIZE]; - } - - update_spd_len(blk); -} - #if CONFIG_DIMM_SPD_SIZE == 128 int read_ddr3_spd_from_cbfs(u8 *buf, int idx) { diff --git a/src/soc/intel/common/block/smbus/smbuslib.c b/src/soc/intel/common/block/smbus/smbuslib.c index e2df730..0680ce2 100644 --- a/src/soc/intel/common/block/smbus/smbuslib.c +++ b/src/soc/intel/common/block/smbus/smbuslib.c @@ -14,8 +14,10 @@ */ #include <arch/io.h> -#include <device/early_smbus.h> +#include <console/console.h> #include <device/smbus_def.h> +#include <spd_bin.h> +#include <string.h> #include <timer.h> #include "smbuslib.h" @@ -176,17 +178,84 @@ return data; } -u16 smbus_read_word(u8 addr, u8 offset) +static u16 smbus_read_word(u8 addr, u8 offset) { return do_smbus_read_word(SMBUS_IO_BASE, addr, offset); } -u8 smbus_read_byte(u8 addr, u8 offset) +static u8 smbus_read_byte(u8 addr, u8 offset) { return do_smbus_read_byte(SMBUS_IO_BASE, addr, offset); } -u8 smbus_write_byte(u8 addr, u8 offset, u8 value) +static u8 smbus_write_byte(u8 addr, u8 offset, u8 value) { return do_smbus_write_byte(SMBUS_IO_BASE, addr, offset, value); } + +static void update_spd_len(struct spd_block *blk) +{ + u8 i, j = 0; + for (i = 0 ; i < CONFIG_DIMM_MAX; i++) + if (blk->spd_array[i] != NULL) + j |= blk->spd_array[i][SPD_DRAM_TYPE]; + + /* If spd used is DDR4, then its length is 512 byte. */ + if (j == SPD_DRAM_DDR4) + blk->len = SPD_PAGE_LEN_DDR4; + else + blk->len = SPD_PAGE_LEN; +} + +static void smbus_read_spd(u8 *spd, u8 addr) +{ + u16 i; + u8 step = 1; + + if (CONFIG(SPD_READ_BY_WORD)) + step = sizeof(uint16_t); + + for (i = 0; i < SPD_PAGE_LEN; i += step) { + if (CONFIG(SPD_READ_BY_WORD)) + ((u16*)spd)[i / sizeof(uint16_t)] = + smbus_read_word(addr, i); + else + spd[i] = smbus_read_byte(addr, i); + } +} + +static void get_spd(u8 *spd, u8 addr) +{ + if (smbus_read_byte(addr, 0) == 0xff) { + printk(BIOS_INFO, "No memory dimm at address %02X\n", + addr << 1); + /* Make sure spd is zeroed if dimm doesn't exist. */ + memset(spd, 0, CONFIG_DIMM_SPD_SIZE); + return; + } + smbus_read_spd(spd, addr); + + /* Check if module is DDR4, DDR4 spd is 512 byte. */ + if (spd[SPD_DRAM_TYPE] == SPD_DRAM_DDR4 && + CONFIG_DIMM_SPD_SIZE > SPD_PAGE_LEN) { + /* Switch to page 1 */ + smbus_write_byte(SPD_PAGE_1, 0, 0); + smbus_read_spd(spd + SPD_PAGE_LEN, addr); + /* Restore to page 0 */ + smbus_write_byte(SPD_PAGE_0, 0, 0); + } +} + +static u8 spd_data[CONFIG_DIMM_MAX * CONFIG_DIMM_SPD_SIZE]; + +void get_spd_smbus(struct spd_block *blk) +{ + u8 i; + for (i = 0 ; i < CONFIG_DIMM_MAX; i++) { + get_spd(&spd_data[i * CONFIG_DIMM_SPD_SIZE], + blk->addr_map[i]); + blk->spd_array[i] = &spd_data[i * CONFIG_DIMM_SPD_SIZE]; + } + + update_spd_len(blk); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/38121 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2d9d83ede6388a01d40c6e4768f6bb6bf899c00 Gerrit-Change-Number: 38121 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common: Sync early SMBUS prototypes
by Kyösti Mälkki (Code Review) 09 Jan '20

09 Jan '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38120 ) Change subject: soc/intel/common: Sync early SMBUS prototypes ...................................................................... soc/intel/common: Sync early SMBUS prototypes Change-Id: I6b4b5ffd552b9eb4467689c8df85905a1c199bb0 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/common/block/smbus/smbus.c M src/soc/intel/common/block/smbus/smbuslib.c M src/soc/intel/common/block/smbus/smbuslib.h 3 files changed, 15 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/38120/1 diff --git a/src/soc/intel/common/block/smbus/smbus.c b/src/soc/intel/common/block/smbus/smbus.c index 6be2a5e..f22bacd 100644 --- a/src/soc/intel/common/block/smbus/smbus.c +++ b/src/soc/intel/common/block/smbus/smbus.c @@ -30,7 +30,7 @@ device = dev->path.i2c.device; pbus = get_pbus_smbus(dev); res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4); - return smbus_read8(res->base, device, address); + return do_smbus_read_byte(res->base, device, address); } static int lsmbus_write_byte(struct device *dev, u8 address, u8 data) @@ -42,7 +42,7 @@ device = dev->path.i2c.device; pbus = get_pbus_smbus(dev); res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4); - return smbus_write8(res->base, device, address, data); + return do_smbus_write_byte(res->base, device, address, data); } static struct smbus_bus_operations lops_smbus_bus = { diff --git a/src/soc/intel/common/block/smbus/smbuslib.c b/src/soc/intel/common/block/smbus/smbuslib.c index a8c2dad..e2df730 100644 --- a/src/soc/intel/common/block/smbus/smbuslib.c +++ b/src/soc/intel/common/block/smbus/smbuslib.c @@ -47,8 +47,7 @@ return -1; } -int smbus_read8(unsigned int smbus_base, unsigned int device, - unsigned int address) +int do_smbus_read_byte(unsigned int smbus_base, u8 device, unsigned int address) { unsigned char global_status_register; unsigned char byte; @@ -93,8 +92,8 @@ return byte; } -int smbus_write8(unsigned int smbus_base, unsigned int device, - unsigned int address, unsigned int data) +int do_smbus_write_byte(unsigned int smbus_base, u8 device, unsigned int address, + unsigned int data) { unsigned char global_status_register; @@ -137,8 +136,7 @@ return 0; } -int smbus_read16(unsigned int smbus_base, unsigned int device, - unsigned int address) +int do_smbus_read_word(unsigned int smbus_base, u8 device, unsigned int address) { unsigned char global_status_register; unsigned short data; @@ -180,15 +178,15 @@ u16 smbus_read_word(u8 addr, u8 offset) { - return smbus_read16(SMBUS_IO_BASE, addr, offset); + return do_smbus_read_word(SMBUS_IO_BASE, addr, offset); } u8 smbus_read_byte(u8 addr, u8 offset) { - return smbus_read8(SMBUS_IO_BASE, addr, offset); + return do_smbus_read_byte(SMBUS_IO_BASE, addr, offset); } u8 smbus_write_byte(u8 addr, u8 offset, u8 value) { - return smbus_write8(SMBUS_IO_BASE, addr, offset, value); + return do_smbus_write_byte(SMBUS_IO_BASE, addr, offset, value); } diff --git a/src/soc/intel/common/block/smbus/smbuslib.h b/src/soc/intel/common/block/smbus/smbuslib.h index 05dafe9..45902a0 100644 --- a/src/soc/intel/common/block/smbus/smbuslib.h +++ b/src/soc/intel/common/block/smbus/smbuslib.h @@ -16,6 +16,8 @@ #ifndef SOC_INTEL_COMMON_BLOCK_SMBUS__LIB_H #define SOC_INTEL_COMMON_BLOCK_SMBUS__LIB_H +#include <stdint.h> + /* SMBus IO Base Address */ #define SMBUS_IO_BASE 0xefa0 /* PCI Configuration Space : SMBus */ @@ -30,11 +32,9 @@ #define SMBUS_TIMEOUT 15 /* 15ms */ -int smbus_read8(unsigned int smbus_base, unsigned int device, - unsigned int address); -int smbus_write8(unsigned int smbus_base, unsigned int device, - unsigned int address, unsigned int data); -int smbus_read16(unsigned int smbus_base, unsigned int device, - unsigned int address); +int do_smbus_read_byte(unsigned int smbus_base, u8 device, unsigned int address); +int do_smbus_write_byte(unsigned int smbus_base, u8 device, unsigned int address, + unsigned int data); +int do_smbus_read_word(unsigned int smbus_base, u8 device, unsigned int address); #endif /* SOC_INTEL_COMMON_BLOCK_SMBUS__LIB_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/38120 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b4b5ffd552b9eb4467689c8df85905a1c199bb0 Gerrit-Change-Number: 38120 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/amd/pi/00730F01/state_machine: Add lost options
by Michał Żygowski (Code Review) 09 Jan '20

09 Jan '20

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37999 ) Change subject: nb/amd/pi/00730F01/state_machine: Add lost options ...................................................................... nb/amd/pi/00730F01/state_machine: Add lost options Add back options that were lost on postcar migration back. Some of them seem to be required for IOMMU initialization. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Ie9cc772d7fcbefded8bab88f9960fef663dc7217 --- M src/northbridge/amd/pi/00730F01/state_machine.c 1 file changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/37999/1 diff --git a/src/northbridge/amd/pi/00730F01/state_machine.c b/src/northbridge/amd/pi/00730F01/state_machine.c index 7e5ca5b..b0bf951 100644 --- a/src/northbridge/amd/pi/00730F01/state_machine.c +++ b/src/northbridge/amd/pi/00730F01/state_machine.c @@ -17,6 +17,7 @@ #include "AGESA.h" #include <cbmem.h> +#include <device/device.h> #include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/agesa_helper.h> @@ -26,10 +27,14 @@ void platform_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *Early) { + Early->GnbConfig.PsppPolicy = PsppDisabled; } void platform_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) { + Post->MemConfig.UmaMode = CONFIG(GFXUMA) ? UMA_AUTO : UMA_NONE; + Post->MemConfig.UmaSize = 0; + Post->MemConfig.BottomIo = (UINT16)(CONFIG_BOTTOMIO_POSITION >> 24); } void platform_AfterInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) @@ -56,10 +61,29 @@ void platform_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *Mid) { amd_initcpuio(); + + /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ + Mid->GnbMidConfiguration.iGpuVgaMode = 0; + Mid->GnbMidConfiguration.GnbIoapicAddress = 0xFEC20000; } void platform_BeforeInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late) { + struct device *iommu_dev = pcidev_on_root(0, 2); + + if(iommu_dev && iommu_dev->enabled) { + /* According to AGESA headers these must be set to sane values + * when IOMMU build config is enabled otherwise AGESA will skip + * it during IOMMU init and IVRS generation. + */ + Late->GnbLateConfiguration.GnbIoapicId = CONFIG_MAX_CPUS + 1; + Late->GnbLateConfiguration.FchIoapicId = CONFIG_MAX_CPUS; + } + + /* Code for creating CDIT requires hop count table. If it is not + * present AGESA_ERROR is returned, which confuses users. CDIT is not + * written to the ACPI tables anyway. */ + Late->PlatformConfig.UserOptionCdit = 0; } void platform_AfterInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late) -- To view, visit https://review.coreboot.org/c/coreboot/+/37999 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9cc772d7fcbefded8bab88f9960fef663dc7217 Gerrit-Change-Number: 37999 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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