Change in coreboot[master]: soc/intel/{cnl,icl,tgl}: Move northbridge.asl into common/block/acpi
Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38155 )
Change subject: soc/intel/{cnl,icl,tgl}: Move northbridge.asl into common/block/acpi ......................................................................
soc/intel/{cnl,icl,tgl}: Move northbridge.asl into common/block/acpi
This patch creates a common instance of northbridge.asl inside intel common code (soc/intel/common/block/acpi/acpi) and ask cnl & icl soc code to refer northbridge.asl from common code block.
TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify Device(MCHC) presence after booting to OS.
Change-Id: Ib9af844bcbbcce3f4b0ac7aada43d43e4171e08b Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/google/dragonegg/dsdt.asl M src/mainboard/google/drallion/dsdt.asl M src/mainboard/google/hatch/dsdt.asl M src/mainboard/google/sarien/dsdt.asl M src/mainboard/intel/cannonlake_rvp/dsdt.asl M src/mainboard/intel/coffeelake_rvp/dsdt.asl M src/mainboard/intel/icelake_rvp/dsdt.asl M src/mainboard/intel/jasperlake_rvp/dsdt.asl D src/soc/intel/cannonlake/acpi/northbridge.asl R src/soc/intel/common/block/acpi/acpi/northbridge.asl D src/soc/intel/tigerlake/acpi/northbridge.asl 11 files changed, 9 insertions(+), 656 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/38155/1
diff --git a/src/mainboard/google/dragonegg/dsdt.asl b/src/mainboard/google/dragonegg/dsdt.asl index 24814da..f84b0b5 100644 --- a/src/mainboard/google/dragonegg/dsdt.asl +++ b/src/mainboard/google/dragonegg/dsdt.asl @@ -37,7 +37,7 @@ Scope (_SB) { Device (PCI0) { - #include <soc/intel/icelake/acpi/northbridge.asl> + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> #include <soc/intel/icelake/acpi/southbridge.asl> } } diff --git a/src/mainboard/google/drallion/dsdt.asl b/src/mainboard/google/drallion/dsdt.asl index 78c6c16..ee63d6e 100644 --- a/src/mainboard/google/drallion/dsdt.asl +++ b/src/mainboard/google/drallion/dsdt.asl @@ -36,7 +36,7 @@ Scope (_SB) { Device (PCI0) { - #include <soc/intel/cannonlake/acpi/northbridge.asl> + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> #include <soc/intel/cannonlake/acpi/southbridge.asl> } /* Per board variant mainboard hooks. */ diff --git a/src/mainboard/google/hatch/dsdt.asl b/src/mainboard/google/hatch/dsdt.asl index 1a0ff68..16a8a66 100644 --- a/src/mainboard/google/hatch/dsdt.asl +++ b/src/mainboard/google/hatch/dsdt.asl @@ -37,7 +37,7 @@ Scope (_SB) { Device (PCI0) { - #include <soc/intel/cannonlake/acpi/northbridge.asl> + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> #include <soc/intel/cannonlake/acpi/southbridge.asl> } } diff --git a/src/mainboard/google/sarien/dsdt.asl b/src/mainboard/google/sarien/dsdt.asl index a809b75..c32470e 100644 --- a/src/mainboard/google/sarien/dsdt.asl +++ b/src/mainboard/google/sarien/dsdt.asl @@ -36,7 +36,7 @@ Scope (_SB) { Device (PCI0) { - #include <soc/intel/cannonlake/acpi/northbridge.asl> + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> #include <soc/intel/cannonlake/acpi/southbridge.asl> } /* Per board variant mainboard hooks. */ diff --git a/src/mainboard/intel/cannonlake_rvp/dsdt.asl b/src/mainboard/intel/cannonlake_rvp/dsdt.asl index 26f1565..c6070dd 100644 --- a/src/mainboard/intel/cannonlake_rvp/dsdt.asl +++ b/src/mainboard/intel/cannonlake_rvp/dsdt.asl @@ -33,7 +33,7 @@ Scope (_SB) { Device (PCI0) { - #include <soc/intel/cannonlake/acpi/northbridge.asl> + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> #include <soc/intel/cannonlake/acpi/southbridge.asl> } } diff --git a/src/mainboard/intel/coffeelake_rvp/dsdt.asl b/src/mainboard/intel/coffeelake_rvp/dsdt.asl index 58a10d9..316fe55 100644 --- a/src/mainboard/intel/coffeelake_rvp/dsdt.asl +++ b/src/mainboard/intel/coffeelake_rvp/dsdt.asl @@ -33,7 +33,7 @@ Scope (_SB) { Device (PCI0) { - #include <soc/intel/cannonlake/acpi/northbridge.asl> + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> #include <soc/intel/cannonlake/acpi/southbridge.asl> } } diff --git a/src/mainboard/intel/icelake_rvp/dsdt.asl b/src/mainboard/intel/icelake_rvp/dsdt.asl index 2eab610..5d730ba 100644 --- a/src/mainboard/intel/icelake_rvp/dsdt.asl +++ b/src/mainboard/intel/icelake_rvp/dsdt.asl @@ -37,7 +37,7 @@ Scope (_SB) { Device (PCI0) { - #include <soc/intel/icelake/acpi/northbridge.asl> + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> #include <soc/intel/icelake/acpi/southbridge.asl> } } diff --git a/src/mainboard/intel/jasperlake_rvp/dsdt.asl b/src/mainboard/intel/jasperlake_rvp/dsdt.asl index 6e11944..559e1e3 100644 --- a/src/mainboard/intel/jasperlake_rvp/dsdt.asl +++ b/src/mainboard/intel/jasperlake_rvp/dsdt.asl @@ -38,7 +38,7 @@ Scope (_SB) { Device (PCI0) { - #include <soc/intel/tigerlake/acpi/northbridge.asl> + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> #include <soc/intel/tigerlake/acpi/southbridge.asl> } } diff --git a/src/soc/intel/cannonlake/acpi/northbridge.asl b/src/soc/intel/cannonlake/acpi/northbridge.asl deleted file mode 100644 index ead5c02..0000000 --- a/src/soc/intel/cannonlake/acpi/northbridge.asl +++ /dev/null @@ -1,324 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2017-2020 Intel Corp. - * (Written by Bora Guvendik bora.guvendik@intel.com for Intel Corp.) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <soc/iomap.h> - -#define BASE_32GB 0x800000000 -#define SIZE_16GB 0x400000000 - -Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID -Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID -Name (_SEG, Zero) // _SEG: PCI Segment -Name (_UID, Zero) // _UID: Unique ID - -Device (MCHC) -{ - Name (_ADR, 0x00000000) - - OperationRegion (MCHP, PCI_Config, 0x00, 0x100) - Field (MCHP, DWordAcc, NoLock, Preserve) - { - Offset(0x40), /* EPBAR (0:0:0:40) */ - EPEN, 1, /* Enable */ - , 11, - EPBR, 20, /* EPBAR [31:12] */ - - Offset(0x48), /* MCHBAR (0:0:0:48) */ - MHEN, 1, /* Enable */ - , 14, - MHBR, 17, /* MCHBAR [31:15] */ - - Offset(0x60), /* PCIEXBAR (0:0:0:60) */ - PXEN, 1, /* Enable */ - PXSZ, 2, /* PCI Express Size */ - , 23, - PXBR, 6, /* PCI Express BAR [31:26] */ - - Offset(0x68), /* DMIBAR (0:0:0:68) */ - DIEN, 1, /* Enable */ - , 11, - DIBR, 20, /* DMIBAR [31:12] */ - - Offset (0xa0), - TOM, 64, /* Top of Used Memory */ - TUUD, 64, /* Top of Upper Used Memory */ - - Offset (0xbc), /* Top of Low Used Memory */ - TLUD, 32, - } -} - -Method (_CRS, 0, Serialized) -{ - Name (MCRS, ResourceTemplate () - { - /* Bus Numbers */ - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100) - - /* IO Region 0 */ - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, - EntireRange, - 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8) - - /* PCI Config Space */ - Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) - - /* IO Region 1 */ - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, - EntireRange, - 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300) - - /* VGA memory (0xa0000-0xbffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, - 0x00020000) - - /* OPROM reserved (0xc0000-0xc3fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xc4000-0xc7fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xc8000-0xcbfff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xcc000-0xcffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xd0000-0xd3fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xd4000-0xd7fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xd8000-0xdbfff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xdc000-0xdffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, - 0x00004000) - - /* BIOS Extension (0xe0000-0xe3fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, - 0x00004000) - - /* BIOS Extension (0xe4000-0xe7fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, - 0x00004000) - - /* BIOS Extension (0xe8000-0xebfff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, - 0x00004000) - - /* BIOS Extension (0xec000-0xeffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000ec000, 0x000effff, 0x00000000, - 0x00004000) - - /* System BIOS (0xf0000-0xfffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, - 0x00010000) - - /* PCI Memory Region (TLUD - 0xdfffffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - NonCacheable, ReadWrite, - 0x00000000, 0x00000000, 0xdfffffff, 0x00000000, - 0xE0000000,,, PM01) - - /* PCI Memory Region (TUUD - (TUUD + ABOVE_4G_MMIO_SIZE)) */ - QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - NonCacheable, ReadWrite, - 0x00000000, 0x10000, 0x1ffff, 0x00000000, - 0x10000,,, PM02) - - /* PCH reserved resource (0xfc800000-0xfe7fffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, PCH_PRESERVED_BASE_ADDRESS, 0xfe7fffff, - 0x00000000, PCH_PRESERVED_BASE_SIZE) - - /* TPM Area (0xfed40000-0xfed47fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0xfed40000, 0xfed47fff, 0x00000000, - 0x00008000) - }) - - /* Find PCI resource area in MCRS */ - CreateDwordField (MCRS, PM01._MIN, PMIN) - CreateDwordField (MCRS, PM01._MAX, PMAX) - CreateDwordField (MCRS, PM01._LEN, PLEN) - - /* - * Fix up PCI memory region - * Start with Top of Lower Usable DRAM - */ - Store (_SB.PCI0.MCHC.TLUD, PMIN) - Add (Subtract (PMAX, PMIN), 1, PLEN) - - /* Patch PM02 range based on Memory Size */ - CreateQwordField (MCRS, PM02._MIN, MMIN) - CreateQwordField (MCRS, PM02._MAX, MMAX) - CreateQwordField (MCRS, PM02._LEN, MLEN) - - Store (_SB.PCI0.MCHC.TUUD, Local0) - - If (LLessEqual (Local0, BASE_32GB)) { - Store (BASE_32GB, MMIN) - Store (SIZE_16GB, MLEN) - } Else { - Store (0, MMIN) - Store (0, MLEN) - } - Subtract (Add (MMIN, MLEN), 1, MMAX) - - Return (MCRS) -} - -/* Get MCH BAR */ -Method (GMHB, 0, Serialized) -{ - ShiftLeft (_SB.PCI0.MCHC.MHBR, 15, Local0) - Return (Local0) -} - -/* Get EP BAR */ -Method (GEPB, 0, Serialized) -{ - ShiftLeft (_SB.PCI0.MCHC.EPBR, 12, Local0) - Return (Local0) -} - -/* Get PCIe BAR */ -Method (GPCB, 0, Serialized) -{ - ShiftLeft (_SB.PCI0.MCHC.PXBR, 26, Local0) - Return (Local0) -} - -/* Get PCIe Length */ -Method (GPCL, 0, Serialized) -{ - ShiftRight (0x10000000, _SB.PCI0.MCHC.PXSZ, Local0) - Return (Local0) -} - -/* Get DMI BAR */ -Method (GDMB, 0, Serialized) -{ - ShiftLeft (_SB.PCI0.MCHC.DIBR, 12, Local0) - Return (Local0) -} - -/* PCI Device Resource Consumption */ -Device (PDRC) -{ - Name (_HID, EISAID ("PNP0C02")) - Name (_UID, 1) - - Method (_CRS, 0, Serialized) - { - Name (BUF0, ResourceTemplate () - { - /* MCH BAR _BAS will be updated in _CRS below according to - * B0:D0:F0:Reg.48h - */ - Memory32Fixed (ReadWrite, 0, 0x08000, MCHB) - - /* DMI BAR _BAS will be updated in _CRS below according to - * B0:D0:F0:Reg.68h - */ - Memory32Fixed (ReadWrite, 0, 0x01000, DMIB) - - /* EP BAR _BAS will be updated in _CRS below according to - * B0:D0:F0:Reg.40h - */ - Memory32Fixed (ReadWrite, 0, 0x01000, EGPB) - - /* PCI Express BAR _BAS and _LEN will be updated in - * _CRS below according to B0:D0:F0:Reg.60h - */ - Memory32Fixed (ReadWrite, 0, 0, PCIX) - - /* VTD engine memory range. */ - Memory32Fixed (ReadOnly, VTD_BASE_ADDRESS, VTD_BASE_SIZE) - - /* FLASH range */ - Memory32Fixed (ReadOnly, 0, CONFIG_ROM_SIZE, FIOH) - - /* Local APIC range(0xFEE0_0000 to 0xFEEF_FFFF) */ - Memory32Fixed (ReadOnly, 0xFEE00000, 0x100000) - - /* HPET address decode range */ - Memory32Fixed (ReadWrite, HPET_BASE_ADDRESS, 0x400) - }) - - CreateDwordField (BUF0, MCHB._BAS, MBR0) - Store (_SB.PCI0.GMHB (), MBR0) - - CreateDwordField (BUF0, DMIB._BAS, DBR0) - Store (_SB.PCI0.GDMB (), DBR0) - - CreateDwordField (BUF0, EGPB._BAS, EBR0) - Store (_SB.PCI0.GEPB (), EBR0) - - CreateDwordField (BUF0, PCIX._BAS, XBR0) - Store (_SB.PCI0.GPCB (), XBR0) - - CreateDwordField (BUF0, PCIX._LEN, XSZ0) - Store (_SB.PCI0.GPCL (), XSZ0) - - CreateDwordField (BUF0, FIOH._BAS, FBR0) - Subtract(0x100000000, CONFIG_ROM_SIZE, FBR0) - - Return (BUF0) - } -} diff --git a/src/soc/intel/icelake/acpi/northbridge.asl b/src/soc/intel/common/block/acpi/acpi/northbridge.asl similarity index 99% rename from src/soc/intel/icelake/acpi/northbridge.asl rename to src/soc/intel/common/block/acpi/acpi/northbridge.asl index 6842021..2372e79 100644 --- a/src/soc/intel/icelake/acpi/northbridge.asl +++ b/src/soc/intel/common/block/acpi/acpi/northbridge.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018-2020 Intel Corp. + * Copyright (C) 2020 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/acpi/northbridge.asl b/src/soc/intel/tigerlake/acpi/northbridge.asl deleted file mode 100644 index 149839d..0000000 --- a/src/soc/intel/tigerlake/acpi/northbridge.asl +++ /dev/null @@ -1,323 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2019-2020 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <soc/iomap.h> - -#define BASE_32GB 0x800000000 -#define SIZE_16GB 0x400000000 - -Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID -Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID -Name (_SEG, Zero) // _SEG: PCI Segment -Name (_UID, Zero) // _UID: Unique ID - -Device (MCHC) -{ - Name (_ADR, 0x00000000) - - OperationRegion (MCHP, PCI_Config, 0x00, 0x100) - Field (MCHP, DWordAcc, NoLock, Preserve) - { - Offset(0x40), /* EPBAR (0:0:0:40) */ - EPEN, 1, /* Enable */ - , 11, - EPBR, 20, /* EPBAR [31:12] */ - - Offset(0x48), /* MCHBAR (0:0:0:48) */ - MHEN, 1, /* Enable */ - , 14, - MHBR, 17, /* MCHBAR [31:15] */ - - Offset(0x60), /* PCIEXBAR (0:0:0:60) */ - PXEN, 1, /* Enable */ - PXSZ, 2, /* PCI Express Size */ - , 23, - PXBR, 6, /* PCI Express BAR [31:26] */ - - Offset(0x68), /* DMIBAR (0:0:0:68) */ - DIEN, 1, /* Enable */ - , 11, - DIBR, 20, /* DMIBAR [31:12] */ - - Offset (0xa0), - TOM, 64, /* Top of Used Memory */ - TUUD, 64, /* Top of Upper Used Memory */ - - Offset (0xbc), /* Top of Low Used Memory */ - TLUD, 32, - } -} - -Method (_CRS, 0, Serialized) -{ - Name (MCRS, ResourceTemplate () - { - /* Bus Numbers */ - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100) - - /* IO Region 0 */ - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, - EntireRange, - 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8) - - /* PCI Config Space */ - Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) - - /* IO Region 1 */ - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, - EntireRange, - 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300) - - /* VGA memory (0xa0000-0xbffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, - 0x00020000) - - /* OPROM reserved (0xc0000-0xc3fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xc4000-0xc7fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xc8000-0xcbfff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xcc000-0xcffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xd0000-0xd3fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xd4000-0xd7fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xd8000-0xdbfff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xdc000-0xdffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, - 0x00004000) - - /* BIOS Extension (0xe0000-0xe3fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, - 0x00004000) - - /* BIOS Extension (0xe4000-0xe7fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, - 0x00004000) - - /* BIOS Extension (0xe8000-0xebfff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, - 0x00004000) - - /* BIOS Extension (0xec000-0xeffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000ec000, 0x000effff, 0x00000000, - 0x00004000) - - /* System BIOS (0xf0000-0xfffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, - 0x00010000) - - /* PCI Memory Region (TLUD - 0xdfffffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - NonCacheable, ReadWrite, - 0x00000000, 0x00000000, 0xdfffffff, 0x00000000, - 0xE0000000,,, PM01) - - /* PCI Memory Region (TUUD - (TUUD + ABOVE_4G_MMIO_SIZE)) */ - QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - NonCacheable, ReadWrite, - 0x00000000, 0x10000, 0x1ffff, 0x00000000, - 0x10000,,, PM02) - - /* PCH reserved resource (0xfc800000-0xfe7fffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, PCH_PRESERVED_BASE_ADDRESS, 0xfe7fffff, - 0x00000000, PCH_PRESERVED_BASE_SIZE) - - /* TPM Area (0xfed40000-0xfed47fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0xfed40000, 0xfed47fff, 0x00000000, - 0x00008000) - }) - - /* Find PCI resource area in MCRS */ - CreateDwordField (MCRS, PM01._MIN, PMIN) - CreateDwordField (MCRS, PM01._MAX, PMAX) - CreateDwordField (MCRS, PM01._LEN, PLEN) - - /* - * Fix up PCI memory region - * Start with Top of Lower Usable DRAM - */ - Store (_SB.PCI0.MCHC.TLUD, PMIN) - Add (Subtract (PMAX, PMIN), 1, PLEN) - - /* Patch PM02 range based on Memory Size */ - CreateQwordField (MCRS, PM02._MIN, MMIN) - CreateQwordField (MCRS, PM02._MAX, MMAX) - CreateQwordField (MCRS, PM02._LEN, MLEN) - - Store (_SB.PCI0.MCHC.TUUD, Local0) - - If (LLessEqual (Local0, BASE_32GB)) { - Store (BASE_32GB, MMIN) - Store (SIZE_16GB, MLEN) - } Else { - Store (0, MMIN) - Store (0, MLEN) - } - Subtract (Add (MMIN, MLEN), 1, MMAX) - - Return (MCRS) -} - -/* Get MCH BAR */ -Method (GMHB, 0, Serialized) -{ - ShiftLeft (_SB.PCI0.MCHC.MHBR, 15, Local0) - Return (Local0) -} - -/* Get EP BAR */ -Method (GEPB, 0, Serialized) -{ - ShiftLeft (_SB.PCI0.MCHC.EPBR, 12, Local0) - Return (Local0) -} - -/* Get PCIe BAR */ -Method (GPCB, 0, Serialized) -{ - ShiftLeft (_SB.PCI0.MCHC.PXBR, 26, Local0) - Return (Local0) -} - -/* Get PCIe Length */ -Method (GPCL, 0, Serialized) -{ - ShiftRight (0x10000000, _SB.PCI0.MCHC.PXSZ, Local0) - Return (Local0) -} - -/* Get DMI BAR */ -Method (GDMB, 0, Serialized) -{ - ShiftLeft (_SB.PCI0.MCHC.DIBR, 12, Local0) - Return (Local0) -} - -/* PCI Device Resource Consumption */ -Device (PDRC) -{ - Name (_HID, EISAID ("PNP0C02")) - Name (_UID, 1) - - Method (_CRS, 0, Serialized) - { - Name (BUF0, ResourceTemplate () - { - /* MCH BAR _BAS will be updated in _CRS below according to - * B0:D0:F0:Reg.48h - */ - Memory32Fixed (ReadWrite, 0, 0x08000, MCHB) - - /* DMI BAR _BAS will be updated in _CRS below according to - * B0:D0:F0:Reg.68h - */ - Memory32Fixed (ReadWrite, 0, 0x01000, DMIB) - - /* EP BAR _BAS will be updated in _CRS below according to - * B0:D0:F0:Reg.40h - */ - Memory32Fixed (ReadWrite, 0, 0x01000, EGPB) - - /* PCI Express BAR _BAS and _LEN will be updated in - * _CRS below according to B0:D0:F0:Reg.60h - */ - Memory32Fixed (ReadWrite, 0, 0, PCIX) - - /* VTD engine memory range. */ - Memory32Fixed (ReadOnly, VTD_BASE_ADDRESS, VTD_BASE_SIZE) - - /* FLASH range */ - Memory32Fixed (ReadOnly, 0, CONFIG_ROM_SIZE, FIOH) - - /* Local APIC range(0xFEE0_0000 to 0xFEEF_FFFF) */ - Memory32Fixed (ReadOnly, 0xFEE00000, 0x100000) - - /* HPET address decode range */ - Memory32Fixed (ReadWrite, HPET_BASE_ADDRESS, 0x400) - }) - - CreateDwordField (BUF0, MCHB._BAS, MBR0) - Store (_SB.PCI0.GMHB (), MBR0) - - CreateDwordField (BUF0, DMIB._BAS, DBR0) - Store (_SB.PCI0.GDMB (), DBR0) - - CreateDwordField (BUF0, EGPB._BAS, EBR0) - Store (_SB.PCI0.GEPB (), EBR0) - - CreateDwordField (BUF0, PCIX._BAS, XBR0) - Store (_SB.PCI0.GPCB (), XBR0) - - CreateDwordField (BUF0, PCIX._LEN, XSZ0) - Store (_SB.PCI0.GPCL (), XSZ0) - - CreateDwordField (BUF0, FIOH._BAS, FBR0) - Subtract(0x100000000, CONFIG_ROM_SIZE, FBR0) - - Return (BUF0) - } -}
Subrata Banik has removed Name of user not set #1000227 from this change. ( https://review.coreboot.org/c/coreboot/+/38155 )
Change subject: soc/intel/{cnl,icl,tgl}: Move northbridge.asl into common/block/acpi ......................................................................
Removed reviewer null.
Hello Patrick Rudolph, Angel Pons, Arthur Heymans, Aamir Bohra, Wonkyu Kim, Maulik V Vaghela, V Sowmya, build bot (Jenkins), Patrick Georgi, Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38155
to look at the new patch set (#2).
Change subject: soc/intel/{cnl,icl,tgl}: Move northbridge.asl into common/block/acpi ......................................................................
soc/intel/{cnl,icl,tgl}: Move northbridge.asl into common/block/acpi
This patch creates a common instance of northbridge.asl inside intel common code (soc/intel/common/block/acpi/acpi) and ask cnl & icl soc code to refer northbridge.asl from common code block.
TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify Device(MCHC) presence after booting to OS.
Change-Id: Ib9af844bcbbcce3f4b0ac7aada43d43e4171e08b Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/google/dragonegg/dsdt.asl M src/mainboard/google/drallion/dsdt.asl M src/mainboard/google/hatch/dsdt.asl M src/mainboard/google/sarien/dsdt.asl M src/mainboard/intel/cannonlake_rvp/dsdt.asl M src/mainboard/intel/coffeelake_rvp/dsdt.asl M src/mainboard/intel/icelake_rvp/dsdt.asl M src/mainboard/intel/jasperlake_rvp/dsdt.asl D src/soc/intel/cannonlake/acpi/northbridge.asl R src/soc/intel/common/block/acpi/acpi/northbridge.asl D src/soc/intel/tigerlake/acpi/northbridge.asl 11 files changed, 9 insertions(+), 656 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/38155/2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38155 )
Change subject: soc/intel/{cnl,icl,tgl}: Move northbridge.asl into common/block/acpi ......................................................................
Patch Set 2: Code-Review+1
(1 comment)
A build test with `BUILD_TIMELESS` might be a good test.
https://review.coreboot.org/c/coreboot/+/38155/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38155/2//COMMIT_MSG@10 PS2, Line 10: ask ask*s*
*changes* might be better though
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38155 )
Change subject: soc/intel/{cnl,icl,tgl}: Move northbridge.asl into common/block/acpi ......................................................................
Patch Set 2:
(1 comment)
Patch Set 2: Code-Review+1
(1 comment)
A build test with `BUILD_TIMELESS` might be a good test.
Can you please help me to understand how to use BUILD_TIMELESS? I could see lots of patches use BUILD_TIMELESS=1 for testing.
I have tested 3 impacted platform as mentioned.
https://review.coreboot.org/c/coreboot/+/38155/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38155/2//COMMIT_MSG@10 PS2, Line 10: ask
ask*s* […]
Done
Hello Patrick Rudolph, Angel Pons, Arthur Heymans, Aamir Bohra, Wonkyu Kim, Maulik V Vaghela, Paul Menzel, V Sowmya, build bot (Jenkins), Patrick Georgi, Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38155
to look at the new patch set (#3).
Change subject: soc/intel/{cnl,icl,tgl}: Move northbridge.asl into common/block/acpi ......................................................................
soc/intel/{cnl,icl,tgl}: Move northbridge.asl into common/block/acpi
This patch creates a common instance of northbridge.asl inside intel common code (soc/intel/common/block/acpi/acpi) and changes cnl,icl & tgl soc code to refer northbridge.asl from common code block.
TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify Device(MCHC) presence after booting to OS.
Change-Id: Ib9af844bcbbcce3f4b0ac7aada43d43e4171e08b Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/google/dragonegg/dsdt.asl M src/mainboard/google/drallion/dsdt.asl M src/mainboard/google/hatch/dsdt.asl M src/mainboard/google/sarien/dsdt.asl M src/mainboard/intel/cannonlake_rvp/dsdt.asl M src/mainboard/intel/coffeelake_rvp/dsdt.asl M src/mainboard/intel/icelake_rvp/dsdt.asl M src/mainboard/intel/jasperlake_rvp/dsdt.asl D src/soc/intel/cannonlake/acpi/northbridge.asl R src/soc/intel/common/block/acpi/acpi/northbridge.asl D src/soc/intel/tigerlake/acpi/northbridge.asl 11 files changed, 9 insertions(+), 656 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/38155/3
Lance Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38155 )
Change subject: soc/intel/{cnl,icl,tgl}: Move northbridge.asl into common/block/acpi ......................................................................
Patch Set 3: Code-Review+1
Maybe we can take the chance to change that to ASL2.0 for easier understanding.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38155 )
Change subject: soc/intel/{cnl,icl,tgl}: Move northbridge.asl into common/block/acpi ......................................................................
Patch Set 3:
Patch Set 3: Code-Review+1
Maybe we can take the chance to change that to ASL2.0 for easier understanding.
Agree ASL 2.0 would be next thing and may be TGL should be good starting point. I have raised this request for IA coreboot team to pick that. will follow it up. Its also another pending AR from Arthur
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38155 )
Change subject: soc/intel/{cnl,icl,tgl}: Move northbridge.asl into common/block/acpi ......................................................................
Patch Set 3: Code-Review+1
Pratikkumar V Prajapati has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38155 )
Change subject: soc/intel/{cnl,icl,tgl}: Move northbridge.asl into common/block/acpi ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38155/5/src/mainboard/google/dragon... File src/mainboard/google/dragonegg/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/38155/5/src/mainboard/google/dragon... PS5, Line 40: #include <soc/intel/common/block/acpi/acpi/northbridge.asl> use '#if CONFIG(CONFIG_SOC_INTEL_COMMON) ... ' ? same for other places where you are including commmon asl?
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38155 )
Change subject: soc/intel/{cnl,icl,tgl}: Move northbridge.asl into common/block/acpi ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38155/5/src/mainboard/google/dragon... File src/mainboard/google/dragonegg/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/38155/5/src/mainboard/google/dragon... PS5, Line 40: #include <soc/intel/common/block/acpi/acpi/northbridge.asl>
use '#if CONFIG(CONFIG_SOC_INTEL_COMMON) ... […]
Incase of #if case then should't we also have to use something for #else ? But in this case there is no scope of anything in else part, because we wish to refer northbrodge.asl from common code. isn't it like been done above line for cpu.asl
// CPU #include <cpu/intel/common/acpi/cpu.asl>
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38155 )
Change subject: soc/intel/{cnl,icl,tgl}: Move northbridge.asl into common/block/acpi ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38155/5/src/mainboard/google/dragon... File src/mainboard/google/dragonegg/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/38155/5/src/mainboard/google/dragon... PS5, Line 40: #include <soc/intel/common/block/acpi/acpi/northbridge.asl>
Incase of #if case then should't we also have to use something for #else ? But in this case there is […]
I think main purpose of this patch is using common file to reduce duplicated asl file in each soc folder. Sp if we use compile condition, we need to keep duplicated asl file even if we use common asl file.
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38155 )
Change subject: soc/intel/{cnl,icl,tgl}: Move northbridge.asl into common/block/acpi ......................................................................
Patch Set 5: Code-Review+2
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38155 )
Change subject: soc/intel/{cnl,icl,tgl}: Move northbridge.asl into common/block/acpi ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38155/5/src/mainboard/google/dragon... File src/mainboard/google/dragonegg/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/38155/5/src/mainboard/google/dragon... PS5, Line 40: #include <soc/intel/common/block/acpi/acpi/northbridge.asl>
I think main purpose of this patch is using common file to reduce duplicated asl file in each soc fo […]
yes echo
Pratikkumar V Prajapati has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38155 )
Change subject: soc/intel/{cnl,icl,tgl}: Move northbridge.asl into common/block/acpi ......................................................................
Patch Set 6: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/38155/5/src/mainboard/google/dragon... File src/mainboard/google/dragonegg/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/38155/5/src/mainboard/google/dragon... PS5, Line 40: #include <soc/intel/common/block/acpi/acpi/northbridge.asl>
yes echo
yeah, that should be fine with the implicit declaration that these SOCs are only supported using the common block model.
Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38155 )
Change subject: soc/intel/{cnl,icl,tgl}: Move northbridge.asl into common/block/acpi ......................................................................
soc/intel/{cnl,icl,tgl}: Move northbridge.asl into common/block/acpi
This patch creates a common instance of northbridge.asl inside intel common code (soc/intel/common/block/acpi/acpi) and changes cnl,icl & tgl soc code to refer northbridge.asl from common code block.
TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify Device(MCHC) presence after booting to OS.
Change-Id: Ib9af844bcbbcce3f4b0ac7aada43d43e4171e08b Signed-off-by: Subrata Banik subrata.banik@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/38155 Reviewed-by: Pratikkumar V Prajapati pratikkumar.v.prajapati@intel.com Reviewed-by: Wonkyu Kim wonkyu.kim@intel.com Reviewed-by: Lance Zhao lance.zhao@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/dragonegg/dsdt.asl M src/mainboard/google/drallion/dsdt.asl M src/mainboard/google/hatch/dsdt.asl M src/mainboard/google/sarien/dsdt.asl M src/mainboard/intel/cannonlake_rvp/dsdt.asl M src/mainboard/intel/coffeelake_rvp/dsdt.asl M src/mainboard/intel/icelake_rvp/dsdt.asl M src/mainboard/intel/jasperlake_rvp/dsdt.asl D src/soc/intel/cannonlake/acpi/northbridge.asl R src/soc/intel/common/block/acpi/acpi/northbridge.asl D src/soc/intel/tigerlake/acpi/northbridge.asl 11 files changed, 9 insertions(+), 656 deletions(-)
Approvals: build bot (Jenkins): Verified Pratikkumar V Prajapati: Looks good to me, approved Lance Zhao: Looks good to me, but someone else must approve Wonkyu Kim: Looks good to me, approved
diff --git a/src/mainboard/google/dragonegg/dsdt.asl b/src/mainboard/google/dragonegg/dsdt.asl index 24814da..f84b0b5 100644 --- a/src/mainboard/google/dragonegg/dsdt.asl +++ b/src/mainboard/google/dragonegg/dsdt.asl @@ -37,7 +37,7 @@ Scope (_SB) { Device (PCI0) { - #include <soc/intel/icelake/acpi/northbridge.asl> + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> #include <soc/intel/icelake/acpi/southbridge.asl> } } diff --git a/src/mainboard/google/drallion/dsdt.asl b/src/mainboard/google/drallion/dsdt.asl index 78c6c16..ee63d6e 100644 --- a/src/mainboard/google/drallion/dsdt.asl +++ b/src/mainboard/google/drallion/dsdt.asl @@ -36,7 +36,7 @@ Scope (_SB) { Device (PCI0) { - #include <soc/intel/cannonlake/acpi/northbridge.asl> + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> #include <soc/intel/cannonlake/acpi/southbridge.asl> } /* Per board variant mainboard hooks. */ diff --git a/src/mainboard/google/hatch/dsdt.asl b/src/mainboard/google/hatch/dsdt.asl index 1a0ff68..16a8a66 100644 --- a/src/mainboard/google/hatch/dsdt.asl +++ b/src/mainboard/google/hatch/dsdt.asl @@ -37,7 +37,7 @@ Scope (_SB) { Device (PCI0) { - #include <soc/intel/cannonlake/acpi/northbridge.asl> + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> #include <soc/intel/cannonlake/acpi/southbridge.asl> } } diff --git a/src/mainboard/google/sarien/dsdt.asl b/src/mainboard/google/sarien/dsdt.asl index a809b75..c32470e 100644 --- a/src/mainboard/google/sarien/dsdt.asl +++ b/src/mainboard/google/sarien/dsdt.asl @@ -36,7 +36,7 @@ Scope (_SB) { Device (PCI0) { - #include <soc/intel/cannonlake/acpi/northbridge.asl> + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> #include <soc/intel/cannonlake/acpi/southbridge.asl> } /* Per board variant mainboard hooks. */ diff --git a/src/mainboard/intel/cannonlake_rvp/dsdt.asl b/src/mainboard/intel/cannonlake_rvp/dsdt.asl index 26f1565..c6070dd 100644 --- a/src/mainboard/intel/cannonlake_rvp/dsdt.asl +++ b/src/mainboard/intel/cannonlake_rvp/dsdt.asl @@ -33,7 +33,7 @@ Scope (_SB) { Device (PCI0) { - #include <soc/intel/cannonlake/acpi/northbridge.asl> + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> #include <soc/intel/cannonlake/acpi/southbridge.asl> } } diff --git a/src/mainboard/intel/coffeelake_rvp/dsdt.asl b/src/mainboard/intel/coffeelake_rvp/dsdt.asl index 58a10d9..316fe55 100644 --- a/src/mainboard/intel/coffeelake_rvp/dsdt.asl +++ b/src/mainboard/intel/coffeelake_rvp/dsdt.asl @@ -33,7 +33,7 @@ Scope (_SB) { Device (PCI0) { - #include <soc/intel/cannonlake/acpi/northbridge.asl> + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> #include <soc/intel/cannonlake/acpi/southbridge.asl> } } diff --git a/src/mainboard/intel/icelake_rvp/dsdt.asl b/src/mainboard/intel/icelake_rvp/dsdt.asl index 2eab610..5d730ba 100644 --- a/src/mainboard/intel/icelake_rvp/dsdt.asl +++ b/src/mainboard/intel/icelake_rvp/dsdt.asl @@ -37,7 +37,7 @@ Scope (_SB) { Device (PCI0) { - #include <soc/intel/icelake/acpi/northbridge.asl> + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> #include <soc/intel/icelake/acpi/southbridge.asl> } } diff --git a/src/mainboard/intel/jasperlake_rvp/dsdt.asl b/src/mainboard/intel/jasperlake_rvp/dsdt.asl index 6e11944..559e1e3 100644 --- a/src/mainboard/intel/jasperlake_rvp/dsdt.asl +++ b/src/mainboard/intel/jasperlake_rvp/dsdt.asl @@ -38,7 +38,7 @@ Scope (_SB) { Device (PCI0) { - #include <soc/intel/tigerlake/acpi/northbridge.asl> + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> #include <soc/intel/tigerlake/acpi/southbridge.asl> } } diff --git a/src/soc/intel/cannonlake/acpi/northbridge.asl b/src/soc/intel/cannonlake/acpi/northbridge.asl deleted file mode 100644 index ead5c02..0000000 --- a/src/soc/intel/cannonlake/acpi/northbridge.asl +++ /dev/null @@ -1,324 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2017-2020 Intel Corp. - * (Written by Bora Guvendik bora.guvendik@intel.com for Intel Corp.) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <soc/iomap.h> - -#define BASE_32GB 0x800000000 -#define SIZE_16GB 0x400000000 - -Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID -Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID -Name (_SEG, Zero) // _SEG: PCI Segment -Name (_UID, Zero) // _UID: Unique ID - -Device (MCHC) -{ - Name (_ADR, 0x00000000) - - OperationRegion (MCHP, PCI_Config, 0x00, 0x100) - Field (MCHP, DWordAcc, NoLock, Preserve) - { - Offset(0x40), /* EPBAR (0:0:0:40) */ - EPEN, 1, /* Enable */ - , 11, - EPBR, 20, /* EPBAR [31:12] */ - - Offset(0x48), /* MCHBAR (0:0:0:48) */ - MHEN, 1, /* Enable */ - , 14, - MHBR, 17, /* MCHBAR [31:15] */ - - Offset(0x60), /* PCIEXBAR (0:0:0:60) */ - PXEN, 1, /* Enable */ - PXSZ, 2, /* PCI Express Size */ - , 23, - PXBR, 6, /* PCI Express BAR [31:26] */ - - Offset(0x68), /* DMIBAR (0:0:0:68) */ - DIEN, 1, /* Enable */ - , 11, - DIBR, 20, /* DMIBAR [31:12] */ - - Offset (0xa0), - TOM, 64, /* Top of Used Memory */ - TUUD, 64, /* Top of Upper Used Memory */ - - Offset (0xbc), /* Top of Low Used Memory */ - TLUD, 32, - } -} - -Method (_CRS, 0, Serialized) -{ - Name (MCRS, ResourceTemplate () - { - /* Bus Numbers */ - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100) - - /* IO Region 0 */ - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, - EntireRange, - 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8) - - /* PCI Config Space */ - Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) - - /* IO Region 1 */ - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, - EntireRange, - 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300) - - /* VGA memory (0xa0000-0xbffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, - 0x00020000) - - /* OPROM reserved (0xc0000-0xc3fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xc4000-0xc7fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xc8000-0xcbfff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xcc000-0xcffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xd0000-0xd3fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xd4000-0xd7fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xd8000-0xdbfff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xdc000-0xdffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, - 0x00004000) - - /* BIOS Extension (0xe0000-0xe3fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, - 0x00004000) - - /* BIOS Extension (0xe4000-0xe7fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, - 0x00004000) - - /* BIOS Extension (0xe8000-0xebfff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, - 0x00004000) - - /* BIOS Extension (0xec000-0xeffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000ec000, 0x000effff, 0x00000000, - 0x00004000) - - /* System BIOS (0xf0000-0xfffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, - 0x00010000) - - /* PCI Memory Region (TLUD - 0xdfffffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - NonCacheable, ReadWrite, - 0x00000000, 0x00000000, 0xdfffffff, 0x00000000, - 0xE0000000,,, PM01) - - /* PCI Memory Region (TUUD - (TUUD + ABOVE_4G_MMIO_SIZE)) */ - QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - NonCacheable, ReadWrite, - 0x00000000, 0x10000, 0x1ffff, 0x00000000, - 0x10000,,, PM02) - - /* PCH reserved resource (0xfc800000-0xfe7fffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, PCH_PRESERVED_BASE_ADDRESS, 0xfe7fffff, - 0x00000000, PCH_PRESERVED_BASE_SIZE) - - /* TPM Area (0xfed40000-0xfed47fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0xfed40000, 0xfed47fff, 0x00000000, - 0x00008000) - }) - - /* Find PCI resource area in MCRS */ - CreateDwordField (MCRS, PM01._MIN, PMIN) - CreateDwordField (MCRS, PM01._MAX, PMAX) - CreateDwordField (MCRS, PM01._LEN, PLEN) - - /* - * Fix up PCI memory region - * Start with Top of Lower Usable DRAM - */ - Store (_SB.PCI0.MCHC.TLUD, PMIN) - Add (Subtract (PMAX, PMIN), 1, PLEN) - - /* Patch PM02 range based on Memory Size */ - CreateQwordField (MCRS, PM02._MIN, MMIN) - CreateQwordField (MCRS, PM02._MAX, MMAX) - CreateQwordField (MCRS, PM02._LEN, MLEN) - - Store (_SB.PCI0.MCHC.TUUD, Local0) - - If (LLessEqual (Local0, BASE_32GB)) { - Store (BASE_32GB, MMIN) - Store (SIZE_16GB, MLEN) - } Else { - Store (0, MMIN) - Store (0, MLEN) - } - Subtract (Add (MMIN, MLEN), 1, MMAX) - - Return (MCRS) -} - -/* Get MCH BAR */ -Method (GMHB, 0, Serialized) -{ - ShiftLeft (_SB.PCI0.MCHC.MHBR, 15, Local0) - Return (Local0) -} - -/* Get EP BAR */ -Method (GEPB, 0, Serialized) -{ - ShiftLeft (_SB.PCI0.MCHC.EPBR, 12, Local0) - Return (Local0) -} - -/* Get PCIe BAR */ -Method (GPCB, 0, Serialized) -{ - ShiftLeft (_SB.PCI0.MCHC.PXBR, 26, Local0) - Return (Local0) -} - -/* Get PCIe Length */ -Method (GPCL, 0, Serialized) -{ - ShiftRight (0x10000000, _SB.PCI0.MCHC.PXSZ, Local0) - Return (Local0) -} - -/* Get DMI BAR */ -Method (GDMB, 0, Serialized) -{ - ShiftLeft (_SB.PCI0.MCHC.DIBR, 12, Local0) - Return (Local0) -} - -/* PCI Device Resource Consumption */ -Device (PDRC) -{ - Name (_HID, EISAID ("PNP0C02")) - Name (_UID, 1) - - Method (_CRS, 0, Serialized) - { - Name (BUF0, ResourceTemplate () - { - /* MCH BAR _BAS will be updated in _CRS below according to - * B0:D0:F0:Reg.48h - */ - Memory32Fixed (ReadWrite, 0, 0x08000, MCHB) - - /* DMI BAR _BAS will be updated in _CRS below according to - * B0:D0:F0:Reg.68h - */ - Memory32Fixed (ReadWrite, 0, 0x01000, DMIB) - - /* EP BAR _BAS will be updated in _CRS below according to - * B0:D0:F0:Reg.40h - */ - Memory32Fixed (ReadWrite, 0, 0x01000, EGPB) - - /* PCI Express BAR _BAS and _LEN will be updated in - * _CRS below according to B0:D0:F0:Reg.60h - */ - Memory32Fixed (ReadWrite, 0, 0, PCIX) - - /* VTD engine memory range. */ - Memory32Fixed (ReadOnly, VTD_BASE_ADDRESS, VTD_BASE_SIZE) - - /* FLASH range */ - Memory32Fixed (ReadOnly, 0, CONFIG_ROM_SIZE, FIOH) - - /* Local APIC range(0xFEE0_0000 to 0xFEEF_FFFF) */ - Memory32Fixed (ReadOnly, 0xFEE00000, 0x100000) - - /* HPET address decode range */ - Memory32Fixed (ReadWrite, HPET_BASE_ADDRESS, 0x400) - }) - - CreateDwordField (BUF0, MCHB._BAS, MBR0) - Store (_SB.PCI0.GMHB (), MBR0) - - CreateDwordField (BUF0, DMIB._BAS, DBR0) - Store (_SB.PCI0.GDMB (), DBR0) - - CreateDwordField (BUF0, EGPB._BAS, EBR0) - Store (_SB.PCI0.GEPB (), EBR0) - - CreateDwordField (BUF0, PCIX._BAS, XBR0) - Store (_SB.PCI0.GPCB (), XBR0) - - CreateDwordField (BUF0, PCIX._LEN, XSZ0) - Store (_SB.PCI0.GPCL (), XSZ0) - - CreateDwordField (BUF0, FIOH._BAS, FBR0) - Subtract(0x100000000, CONFIG_ROM_SIZE, FBR0) - - Return (BUF0) - } -} diff --git a/src/soc/intel/icelake/acpi/northbridge.asl b/src/soc/intel/common/block/acpi/acpi/northbridge.asl similarity index 99% rename from src/soc/intel/icelake/acpi/northbridge.asl rename to src/soc/intel/common/block/acpi/acpi/northbridge.asl index 6842021..2372e79 100644 --- a/src/soc/intel/icelake/acpi/northbridge.asl +++ b/src/soc/intel/common/block/acpi/acpi/northbridge.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018-2020 Intel Corp. + * Copyright (C) 2020 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/tigerlake/acpi/northbridge.asl b/src/soc/intel/tigerlake/acpi/northbridge.asl deleted file mode 100644 index 149839d..0000000 --- a/src/soc/intel/tigerlake/acpi/northbridge.asl +++ /dev/null @@ -1,323 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2019-2020 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <soc/iomap.h> - -#define BASE_32GB 0x800000000 -#define SIZE_16GB 0x400000000 - -Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID -Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID -Name (_SEG, Zero) // _SEG: PCI Segment -Name (_UID, Zero) // _UID: Unique ID - -Device (MCHC) -{ - Name (_ADR, 0x00000000) - - OperationRegion (MCHP, PCI_Config, 0x00, 0x100) - Field (MCHP, DWordAcc, NoLock, Preserve) - { - Offset(0x40), /* EPBAR (0:0:0:40) */ - EPEN, 1, /* Enable */ - , 11, - EPBR, 20, /* EPBAR [31:12] */ - - Offset(0x48), /* MCHBAR (0:0:0:48) */ - MHEN, 1, /* Enable */ - , 14, - MHBR, 17, /* MCHBAR [31:15] */ - - Offset(0x60), /* PCIEXBAR (0:0:0:60) */ - PXEN, 1, /* Enable */ - PXSZ, 2, /* PCI Express Size */ - , 23, - PXBR, 6, /* PCI Express BAR [31:26] */ - - Offset(0x68), /* DMIBAR (0:0:0:68) */ - DIEN, 1, /* Enable */ - , 11, - DIBR, 20, /* DMIBAR [31:12] */ - - Offset (0xa0), - TOM, 64, /* Top of Used Memory */ - TUUD, 64, /* Top of Upper Used Memory */ - - Offset (0xbc), /* Top of Low Used Memory */ - TLUD, 32, - } -} - -Method (_CRS, 0, Serialized) -{ - Name (MCRS, ResourceTemplate () - { - /* Bus Numbers */ - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100) - - /* IO Region 0 */ - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, - EntireRange, - 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8) - - /* PCI Config Space */ - Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) - - /* IO Region 1 */ - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, - EntireRange, - 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300) - - /* VGA memory (0xa0000-0xbffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, - 0x00020000) - - /* OPROM reserved (0xc0000-0xc3fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xc4000-0xc7fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xc8000-0xcbfff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xcc000-0xcffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xd0000-0xd3fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xd4000-0xd7fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xd8000-0xdbfff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xdc000-0xdffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, - 0x00004000) - - /* BIOS Extension (0xe0000-0xe3fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, - 0x00004000) - - /* BIOS Extension (0xe4000-0xe7fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, - 0x00004000) - - /* BIOS Extension (0xe8000-0xebfff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, - 0x00004000) - - /* BIOS Extension (0xec000-0xeffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000ec000, 0x000effff, 0x00000000, - 0x00004000) - - /* System BIOS (0xf0000-0xfffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, - 0x00010000) - - /* PCI Memory Region (TLUD - 0xdfffffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - NonCacheable, ReadWrite, - 0x00000000, 0x00000000, 0xdfffffff, 0x00000000, - 0xE0000000,,, PM01) - - /* PCI Memory Region (TUUD - (TUUD + ABOVE_4G_MMIO_SIZE)) */ - QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - NonCacheable, ReadWrite, - 0x00000000, 0x10000, 0x1ffff, 0x00000000, - 0x10000,,, PM02) - - /* PCH reserved resource (0xfc800000-0xfe7fffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, PCH_PRESERVED_BASE_ADDRESS, 0xfe7fffff, - 0x00000000, PCH_PRESERVED_BASE_SIZE) - - /* TPM Area (0xfed40000-0xfed47fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0xfed40000, 0xfed47fff, 0x00000000, - 0x00008000) - }) - - /* Find PCI resource area in MCRS */ - CreateDwordField (MCRS, PM01._MIN, PMIN) - CreateDwordField (MCRS, PM01._MAX, PMAX) - CreateDwordField (MCRS, PM01._LEN, PLEN) - - /* - * Fix up PCI memory region - * Start with Top of Lower Usable DRAM - */ - Store (_SB.PCI0.MCHC.TLUD, PMIN) - Add (Subtract (PMAX, PMIN), 1, PLEN) - - /* Patch PM02 range based on Memory Size */ - CreateQwordField (MCRS, PM02._MIN, MMIN) - CreateQwordField (MCRS, PM02._MAX, MMAX) - CreateQwordField (MCRS, PM02._LEN, MLEN) - - Store (_SB.PCI0.MCHC.TUUD, Local0) - - If (LLessEqual (Local0, BASE_32GB)) { - Store (BASE_32GB, MMIN) - Store (SIZE_16GB, MLEN) - } Else { - Store (0, MMIN) - Store (0, MLEN) - } - Subtract (Add (MMIN, MLEN), 1, MMAX) - - Return (MCRS) -} - -/* Get MCH BAR */ -Method (GMHB, 0, Serialized) -{ - ShiftLeft (_SB.PCI0.MCHC.MHBR, 15, Local0) - Return (Local0) -} - -/* Get EP BAR */ -Method (GEPB, 0, Serialized) -{ - ShiftLeft (_SB.PCI0.MCHC.EPBR, 12, Local0) - Return (Local0) -} - -/* Get PCIe BAR */ -Method (GPCB, 0, Serialized) -{ - ShiftLeft (_SB.PCI0.MCHC.PXBR, 26, Local0) - Return (Local0) -} - -/* Get PCIe Length */ -Method (GPCL, 0, Serialized) -{ - ShiftRight (0x10000000, _SB.PCI0.MCHC.PXSZ, Local0) - Return (Local0) -} - -/* Get DMI BAR */ -Method (GDMB, 0, Serialized) -{ - ShiftLeft (_SB.PCI0.MCHC.DIBR, 12, Local0) - Return (Local0) -} - -/* PCI Device Resource Consumption */ -Device (PDRC) -{ - Name (_HID, EISAID ("PNP0C02")) - Name (_UID, 1) - - Method (_CRS, 0, Serialized) - { - Name (BUF0, ResourceTemplate () - { - /* MCH BAR _BAS will be updated in _CRS below according to - * B0:D0:F0:Reg.48h - */ - Memory32Fixed (ReadWrite, 0, 0x08000, MCHB) - - /* DMI BAR _BAS will be updated in _CRS below according to - * B0:D0:F0:Reg.68h - */ - Memory32Fixed (ReadWrite, 0, 0x01000, DMIB) - - /* EP BAR _BAS will be updated in _CRS below according to - * B0:D0:F0:Reg.40h - */ - Memory32Fixed (ReadWrite, 0, 0x01000, EGPB) - - /* PCI Express BAR _BAS and _LEN will be updated in - * _CRS below according to B0:D0:F0:Reg.60h - */ - Memory32Fixed (ReadWrite, 0, 0, PCIX) - - /* VTD engine memory range. */ - Memory32Fixed (ReadOnly, VTD_BASE_ADDRESS, VTD_BASE_SIZE) - - /* FLASH range */ - Memory32Fixed (ReadOnly, 0, CONFIG_ROM_SIZE, FIOH) - - /* Local APIC range(0xFEE0_0000 to 0xFEEF_FFFF) */ - Memory32Fixed (ReadOnly, 0xFEE00000, 0x100000) - - /* HPET address decode range */ - Memory32Fixed (ReadWrite, HPET_BASE_ADDRESS, 0x400) - }) - - CreateDwordField (BUF0, MCHB._BAS, MBR0) - Store (_SB.PCI0.GMHB (), MBR0) - - CreateDwordField (BUF0, DMIB._BAS, DBR0) - Store (_SB.PCI0.GDMB (), DBR0) - - CreateDwordField (BUF0, EGPB._BAS, EBR0) - Store (_SB.PCI0.GEPB (), EBR0) - - CreateDwordField (BUF0, PCIX._BAS, XBR0) - Store (_SB.PCI0.GPCB (), XBR0) - - CreateDwordField (BUF0, PCIX._LEN, XSZ0) - Store (_SB.PCI0.GPCL (), XSZ0) - - CreateDwordField (BUF0, FIOH._BAS, FBR0) - Subtract(0x100000000, CONFIG_ROM_SIZE, FBR0) - - Return (BUF0) - } -}
-
Lance Zhao (Code Review) -
Paul Menzel (Code Review)
-
Pratikkumar V Prajapati (Code Review)
-
Subrata Banik (Code Review)
-
Wonkyu Kim (Code Review)