January 2020 - coreboot-gerrit

Change in coreboot[master]: soc/intel/tigerlake: Update Kconfig
by Wonkyu Kim (Code Review) Jan. 7, 2020

Jan. 7, 2020

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37426 ) Change subject: soc/intel/tigerlake: Update Kconfig ...................................................................... Patch Set 14: Code-Review+1 (3 comments) https://review.coreboot.org/c/coreboot/+/37426/11//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/37426/11//COMMIT_MSG@13 PS11, Line 13: PCH baseclock > Can you please email me the details of the document? Sure. We're checking internally for external reference document. We'll send document once we found it. https://review.coreboot.org/c/coreboot/+/37426/8/src/soc/intel/tigerlake/Kc… File src/soc/intel/tigerlake/Kconfig: https://review.coreboot.org/c/coreboot/+/37426/8/src/soc/intel/tigerlake/Kc… PS8, Line 169: 0x7FFF > That makes sense. […] Ack https://review.coreboot.org/c/coreboot/+/37426/13/src/soc/intel/tigerlake/K… File src/soc/intel/tigerlake/Kconfig: https://review.coreboot.org/c/coreboot/+/37426/13/src/soc/intel/tigerlake/K… PS13, Line 199: > nit: extra blank line not required. Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/37426 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I04020d55f1063d521b15f8d0dabbd6f1dabf577c Gerrit-Change-Number: 37426 Gerrit-PatchSet: 14 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Venkata Krishna Nimmagadda Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Tue, 07 Jan 2020 17:49:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Wonkyu Kim <wonkyu.kim(a)intel.com> Comment-In-Reply-To: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Update Kconfig
by Wonkyu Kim (Code Review) Jan. 7, 2020

Jan. 7, 2020

Wonkyu Kim has uploaded a new patch set (#14) to the change originally created by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/37426 ) Change subject: soc/intel/tigerlake: Update Kconfig ...................................................................... soc/intel/tigerlake: Update Kconfig Update Kconfig: - use CAR NEM mode for tigerlake only as NEM Enhanced is under debug - update GSPI, RP max device #s according to PCH EDS#576591 vol1 rev1.2 - update UART M/N setting according to new PCH baseclock BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Change-Id: I04020d55f1063d521b15f8d0dabbd6f1dabf577c Signed-off-by: Wonkyu Kim <wonkyu.kim(a)intel.com> --- M src/soc/intel/tigerlake/Kconfig 1 file changed, 16 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/37426/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/37426 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I04020d55f1063d521b15f8d0dabbd6f1dabf577c Gerrit-Change-Number: 37426 Gerrit-PatchSet: 14 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Venkata Krishna Nimmagadda Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/intel/gma/vbt: Clean up includes
by HAOUAS Elyes (Code Review) Jan. 7, 2020

Jan. 7, 2020

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37848 ) Change subject: drivers/intel/gma/vbt: Clean up includes ...................................................................... drivers/intel/gma/vbt: Clean up includes Change-Id: I831b30c6e5b8c4e13b190aafd0ce22152ac64b46 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/drivers/intel/gma/vbt.c 1 file changed, 4 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/37848/1 diff --git a/src/drivers/intel/gma/vbt.c b/src/drivers/intel/gma/vbt.c index 603044a..711a34d 100644 --- a/src/drivers/intel/gma/vbt.c +++ b/src/drivers/intel/gma/vbt.c @@ -12,11 +12,12 @@ * GNU General Public License for more details. */ -#include <device/pci_ops.h> #include <device/device.h> -#include <string.h> -#include <device/pci.h> +#include <device/pci_ops.h> +#include <device/pci_def.h> +#include <device/pci_rom.h> #include <drivers/intel/gma/opregion.h> +#include <string.h> #include "i915.h" #include "intel_bios.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/37848 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I831b30c6e5b8c4e13b190aafd0ce22152ac64b46 Gerrit-Change-Number: 37848 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: [test] nb/i945: Write CxWL1REOST
by HAOUAS Elyes (Code Review) Jan. 7, 2020

Jan. 7, 2020

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37448 ) Change subject: [test] nb/i945: Write CxWL1REOST ...................................................................... [test] nb/i945: Write CxWL1REOST Got the error: "Could not find rising edge" if channel 0 is not populated. Change-Id: I6c17c18171e258a70e153009e953ce898ad3baa9 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/rcven.c 1 file changed, 68 insertions(+), 47 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/37448/1 diff --git a/src/northbridge/intel/i945/rcven.c b/src/northbridge/intel/i945/rcven.c index 5a90807..1faf71e 100644 --- a/src/northbridge/intel/i945/rcven.c +++ b/src/northbridge/intel/i945/rcven.c @@ -21,11 +21,14 @@ /** * sample the strobes signal */ -static u32 sample_strobes(int channel_offset, struct sys_info *sysinfo) +static u32 sample_strobes(int dimm, struct sys_info *sysinfo) { u32 reg32, addr; int i; + int channel_offset = 0; + if (dimm >> 1) + channel_offset = 0x80; MCHBAR32(C0DRC1 + channel_offset) |= (1 << 6); MCHBAR32(C0DRC1 + channel_offset) &= ~(1 << 6); @@ -60,10 +63,13 @@ * This function sets receive enable coarse and medium timing parameters */ -static void set_receive_enable(int channel_offset, u8 medium, u8 coarse) +static void set_receive_enable(int dimm, u8 medium, u8 coarse) { u32 reg32; + int channel_offset = 0; + if (dimm >> 1) + channel_offset = 0x80; printk(BIOS_SPEW, " set_receive_enable() medium=0x%x, coarse=0x%x\n", medium, coarse); reg32 = MCHBAR32(C0DRT1 + channel_offset); @@ -97,8 +103,13 @@ } -static int normalize(int channel_offset, u8 *mediumcoarse, u8 *fine) +static int normalize(int dimm, u8 *mediumcoarse, u8 *fine) { + int channel_offset = 0; + + if (dimm >> 1) + channel_offset = 0x80; + printk(BIOS_SPEW, " normalize()\n"); if (*fine < 0x80) @@ -112,19 +123,23 @@ return -1; } - set_receive_enable(channel_offset, *mediumcoarse & 3, + set_receive_enable(dimm, *mediumcoarse & 3, *mediumcoarse >> 2); - MCHBAR8(C0WL0REOST + channel_offset) = *fine; + MCHBAR8(C0WL0REOST + (dimm >> 1) + channel_offset) = *fine; return 0; } -static int find_preamble(int channel_offset, u8 *mediumcoarse, +static int find_preamble(int dimm, u8 *mediumcoarse, struct sys_info *sysinfo) { /* find start of the data phase */ u32 reg32; + int channel_offset = 0; + + if (dimm >> 1) + channel_offset = 0x80; printk(BIOS_SPEW, " find_preamble()\n"); @@ -135,10 +150,10 @@ } *mediumcoarse -= 4; - set_receive_enable(channel_offset, *mediumcoarse & 3, + set_receive_enable(dimm, *mediumcoarse & 3, *mediumcoarse >> 2); - reg32 = sample_strobes(channel_offset, sysinfo); + reg32 = sample_strobes(dimm, sysinfo); } while (reg32 & (1 << 19)); @@ -154,8 +169,13 @@ * add a quarter clock to the current receive enable settings */ -static int add_quarter_clock(int channel_offset, u8 *mediumcoarse, u8 *fine) +static int add_quarter_clock(int dimm, u8 *mediumcoarse, u8 *fine) { + int channel_offset = 0; + + if (dimm >> 1) + channel_offset = 0x80; + printk(BIOS_SPEW, " add_quarter_clock() mediumcoarse=%02x fine=%02x\n", *mediumcoarse, *fine); if (*fine >= 0x80) { @@ -167,31 +187,34 @@ return -1; } - set_receive_enable(channel_offset, *mediumcoarse & 3, + set_receive_enable(dimm, *mediumcoarse & 3, *mediumcoarse >> 2); } else { *fine += 0x80; } - MCHBAR8(C0WL0REOST + channel_offset) = *fine; + MCHBAR8(C0WL0REOST + (dimm >> 1) + channel_offset) = *fine; return 0; } -static int find_strobes_low(int channel_offset, u8 *mediumcoarse, u8 *fine, +static int find_strobes_low(int dimm, u8 *mediumcoarse, u8 *fine, struct sys_info *sysinfo) { u32 rcvenmt; + int channel_offset = 0; + if (dimm >> 1) + channel_offset = 0x80; printk(BIOS_SPEW, " find_strobes_low()\n"); for (;;) { - MCHBAR8(C0WL0REOST + channel_offset) = *fine; + MCHBAR8(C0WL0REOST + (dimm >> 1) + channel_offset) = *fine; - set_receive_enable(channel_offset, *mediumcoarse & 3, + set_receive_enable(dimm, *mediumcoarse & 3, *mediumcoarse >> 2); - rcvenmt = sample_strobes(channel_offset, sysinfo); + rcvenmt = sample_strobes(dimm, sysinfo); if (((rcvenmt & (1 << 18)) != 0)) return 0; @@ -212,22 +235,26 @@ return 0; } -static int find_strobes_edge(int channel_offset, u8 *mediumcoarse, u8 *fine, +static int find_strobes_edge(int dimm, u8 *mediumcoarse, u8 *fine, struct sys_info *sysinfo) { int counter; u32 rcvenmt; + int channel_offset = 0; + + if (dimm >> 1) + channel_offset = 0x80; printk(BIOS_SPEW, " find_strobes_edge()\n"); counter = 8; - set_receive_enable(channel_offset, *mediumcoarse & 3, + set_receive_enable(dimm, *mediumcoarse & 3, *mediumcoarse >> 2); for (;;) { - MCHBAR8(C0WL0REOST + channel_offset) = *fine; - rcvenmt = sample_strobes(channel_offset, sysinfo); + MCHBAR8(C0WL0REOST + (dimm >> 1) + channel_offset) = *fine; + rcvenmt = sample_strobes(dimm, sysinfo); if ((rcvenmt & (1 << 19)) == 0) { counter = 8; @@ -249,7 +276,7 @@ *fine = 0; *mediumcoarse += 2; if (*mediumcoarse <= 0x40) { - set_receive_enable(channel_offset, *mediumcoarse & 3, + set_receive_enable(dimm, *mediumcoarse & 3, *mediumcoarse >> 2); continue; } @@ -261,57 +288,55 @@ *fine -= 7; if (*fine >= 0xf9) { *mediumcoarse -= 2; - set_receive_enable(channel_offset, *mediumcoarse & 3, + set_receive_enable(dimm, *mediumcoarse & 3, *mediumcoarse >> 2); } *fine &= ~(1 << 3); - MCHBAR8(C0WL0REOST + channel_offset) = *fine; + MCHBAR8(C0WL0REOST + (dimm >> 1) + channel_offset) = *fine; return 0; } -/** - * Here we use a trick. The RCVEN channel 0 registers are all at an - * offset of 0x80 to the channel 0 registers. We don't want to waste - * a lot of if ()s so let's just pass 0 or 0x80 for the channel offset. - */ - -static int receive_enable_autoconfig(int channel_offset, +static int receive_enable_autoconfig(int dimm, struct sys_info *sysinfo) { + int channel_offset; u8 mediumcoarse; u8 fine; + if (dimm >> 1) /* Channel 1 */ + channel_offset = 0x80; + printk(BIOS_SPEW, "receive_enable_autoconfig() for channel %d\n", - channel_offset ? 1 : 0); + dimm >> 1); /* Set initial values */ mediumcoarse = (sysinfo->cas << 2) | 3; fine = 0; - if (find_strobes_low(channel_offset, &mediumcoarse, &fine, sysinfo)) + if (find_strobes_low(dimm, &mediumcoarse, &fine, sysinfo)) return -1; - if (find_strobes_edge(channel_offset, &mediumcoarse, &fine, sysinfo)) + if (find_strobes_edge(dimm, &mediumcoarse, &fine, sysinfo)) return -1; - if (add_quarter_clock(channel_offset, &mediumcoarse, &fine)) + if (add_quarter_clock(dimm, &mediumcoarse, &fine)) return -1; - if (find_preamble(channel_offset, &mediumcoarse, sysinfo)) + if (find_preamble(dimm, &mediumcoarse, sysinfo)) return -1; - if (add_quarter_clock(channel_offset, &mediumcoarse, &fine)) + if (add_quarter_clock(dimm, &mediumcoarse, &fine)) return -1; - if (normalize(channel_offset, &mediumcoarse, &fine)) + if (normalize(dimm, &mediumcoarse, &fine)) return -1; /* This is a debug check to see if the rcven code is fully working. * It can be removed when the output message is not printed anymore */ - if (MCHBAR8(C0WL0REOST + channel_offset) == 0) + if (MCHBAR8(C0WL0REOST + (dimm >> 1) + channel_offset) == 0) printk(BIOS_DEBUG, "Weird. No C%sWL0REOST\n", channel_offset?"1":"0"); return 0; @@ -319,15 +344,11 @@ void receive_enable_adjust(struct sys_info *sysinfo) { - /* Is channel 0 populated? */ - if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED - || sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED) - if (receive_enable_autoconfig(0, sysinfo)) - return; + int i; - /* Is channel 1 populated? */ - if (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED - || sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED) - if (receive_enable_autoconfig(0x80, sysinfo)) - return; + for (i = 0; i < (2 * DIMM_SOCKETS); i++) { + if (sysinfo->dimm[i] != SYSINFO_DIMM_NOT_POPULATED) + if (receive_enable_autoconfig(i, sysinfo)) + return; + } } -- To view, visit https://review.coreboot.org/c/coreboot/+/37448 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6c17c18171e258a70e153009e953ce898ad3baa9 Gerrit-Change-Number: 37448 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/x86/smm: Don't redefine LAPIC_ID
by HAOUAS Elyes (Code Review) Jan. 7, 2020

Jan. 7, 2020

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37173 ) Change subject: cpu/x86/smm: Don't redefine LAPIC_ID ...................................................................... cpu/x86/smm: Don't redefine LAPIC_ID Use already defined LAPIC_ID in <cpu/x86/lapic_def.h>. Change-Id: Iaf7da1ea0df58020fe53f2a3482b0f535265b03f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/x86/smm/smihandler.c M src/cpu/x86/smm/smmrelocate.S 2 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/37173/1 diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c index 20417d1..9710142 100644 --- a/src/cpu/x86/smm/smihandler.c +++ b/src/cpu/x86/smm/smihandler.c @@ -15,6 +15,7 @@ #include <arch/io.h> #include <console/console.h> #include <cpu/x86/cache.h> +#include <cpu/x86/lapic_def.h> #include <cpu/x86/smm.h> #include <cpu/x86/smi_deprecated.h> #include <cpu/amd/amd64_save_state.h> @@ -78,10 +79,9 @@ ); } -#define LAPIC_ID 0xfee00020 static __always_inline unsigned long nodeid(void) { - return (*((volatile unsigned long *)(LAPIC_ID)) >> 24); + return (*((volatile unsigned long *)(LOCAL_APIC_ADDR | LAPIC_ID)) >> 24); } void io_trap_handler(int smif) diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S index f64b365..1ee7b59 100644 --- a/src/cpu/x86/smm/smmrelocate.S +++ b/src/cpu/x86/smm/smmrelocate.S @@ -31,7 +31,7 @@ #error "Only use this file with ASEG." #endif /* CONFIG_SMM_ASEG */ -#define LAPIC_ID 0xfee00020 +#include <cpu/x86/lapic_def.h> .global smm_relocation_start .global smm_relocation_end @@ -113,7 +113,7 @@ smm_relocate: /* Get this CPU's LAPIC ID */ - movl $LAPIC_ID, %esi + movl $(LOCAL_APIC_ADDR | LAPIC_ID), %esi ADDR32(movl) (%esi), %ecx shr $24, %ecx -- To view, visit https://review.coreboot.org/c/coreboot/+/37173 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf7da1ea0df58020fe53f2a3482b0f535265b03f Gerrit-Change-Number: 37173 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mainboard: Remove unused 'include <x86emu/x86emu.h>
by HAOUAS Elyes (Code Review) Jan. 7, 2020

Jan. 7, 2020

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38119 ) Change subject: mainboard: Remove unused 'include <x86emu/x86emu.h> ...................................................................... mainboard: Remove unused 'include <x86emu/x86emu.h> Change-Id: I98908f07708206ca59a95139de938e5e6b743ec1 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/google/link/mainboard.c M src/mainboard/google/rambi/mainboard.c M src/mainboard/kontron/ktqm77/mainboard.c 3 files changed, 0 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/38119/1 diff --git a/src/mainboard/google/link/mainboard.c b/src/mainboard/google/link/mainboard.c index 5a812e8..751306d 100644 --- a/src/mainboard/google/link/mainboard.c +++ b/src/mainboard/google/link/mainboard.c @@ -18,9 +18,6 @@ #include <device/device.h> #include <device/pci_ops.h> #include <console/console.h> -#if CONFIG(VGA_ROM_RUN) -#include <x86emu/x86emu.h> -#endif #include <arch/acpi.h> #include <arch/io.h> #include <arch/interrupt.h> diff --git a/src/mainboard/google/rambi/mainboard.c b/src/mainboard/google/rambi/mainboard.c index d4e38d0..fa7889e 100644 --- a/src/mainboard/google/rambi/mainboard.c +++ b/src/mainboard/google/rambi/mainboard.c @@ -17,9 +17,6 @@ #include <types.h> #include <device/device.h> #include <console/console.h> -#if CONFIG(VGA_ROM_RUN) -#include <x86emu/x86emu.h> -#endif #include <arch/acpi.h> #include <arch/interrupt.h> #include <smbios.h> diff --git a/src/mainboard/kontron/ktqm77/mainboard.c b/src/mainboard/kontron/ktqm77/mainboard.c index 50a7b6b..c1b3d17 100644 --- a/src/mainboard/kontron/ktqm77/mainboard.c +++ b/src/mainboard/kontron/ktqm77/mainboard.c @@ -19,9 +19,6 @@ #include <device/device.h> #include <device/pci_def.h> #include <console/console.h> -#if CONFIG(VGA_ROM_RUN) -#include <x86emu/x86emu.h> -#endif #include <pc80/mc146818rtc.h> #include <arch/interrupt.h> #include <southbridge/intel/bd82x6x/pch.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/38119 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I98908f07708206ca59a95139de938e5e6b743ec1 Gerrit-Change-Number: 38119 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: {device,drivers}: Add missing include <device/pci_rom.h>
by HAOUAS Elyes (Code Review) Jan. 7, 2020

Jan. 7, 2020

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37844 ) Change subject: {device,drivers}: Add missing include <device/pci_rom.h> ...................................................................... {device,drivers}: Add missing include <device/pci_rom.h> Change-Id: I1ab9d0d61099bff1a72d4b2eecc37201eaf9ef51 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/device/pci_device.c M src/device/pci_rom.c M src/drivers/intel/gma/opregion.c 3 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/37844/1 diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 36b7c82..2f85e1a 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -18,6 +18,7 @@ #include <arch/acpi.h> #include <device/pci_ops.h> +#include <device/pci_rom.h> #include <bootmode.h> #include <console/console.h> #include <stdlib.h> diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index 3676f9c..a405dff 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -17,6 +17,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> +#include <device/pci_rom.h> #include <string.h> #include <cbfs.h> #include <cbmem.h> diff --git a/src/drivers/intel/gma/opregion.c b/src/drivers/intel/gma/opregion.c index 56449d0..037821d 100644 --- a/src/drivers/intel/gma/opregion.c +++ b/src/drivers/intel/gma/opregion.c @@ -20,6 +20,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> +#include <device/pci_rom.h> #include <console/console.h> #include <cbmem.h> #include "intel_bios.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/37844 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ab9d0d61099bff1a72d4b2eecc37201eaf9ef51 Gerrit-Change-Number: 37844 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: device/oprom/realmode: Add missing <device/device.h>
by HAOUAS Elyes (Code Review) Jan. 7, 2020

Jan. 7, 2020

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37845 ) Change subject: device/oprom/realmode: Add missing <device/device.h> ...................................................................... device/oprom/realmode: Add missing <device/device.h> Change-Id: I3b9de1972177cb6695aac1fecfa8bd835eb3d1d6 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/device/oprom/realmode/x86.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/37845/1 diff --git a/src/device/oprom/realmode/x86.c b/src/device/oprom/realmode/x86.c index 8ba0241..a39e038 100644 --- a/src/device/oprom/realmode/x86.c +++ b/src/device/oprom/realmode/x86.c @@ -17,6 +17,7 @@ #include <boot/coreboot_tables.h> #include <console/console.h> #include <delay.h> +#include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> #include <pc80/i8259.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/37845 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b9de1972177cb6695aac1fecfa8bd835eb3d1d6 Gerrit-Change-Number: 37845 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: nb/i945: Consolidate sdram_setup_processor_side()
by HAOUAS Elyes (Code Review) Jan. 7, 2020

Jan. 7, 2020

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33781 Change subject: nb/i945: Consolidate sdram_setup_processor_side() ...................................................................... nb/i945: Consolidate sdram_setup_processor_side() Change-Id: I9c5aae06ae8e3643253fe4a5b080448403f81ebc Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/raminit.c 1 file changed, 3 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/33781/1 diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 281e7b2..c994786 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -2695,13 +2695,11 @@ static void sdram_setup_processor_side(void) { - if (i945_silicon_revision() == 0) + if (i945_silicon_revision() == 0) { MCHBAR32(FSBPMC3) |= (1 << 2); - - MCHBAR8(0xb00) |= 1; - - if (i945_silicon_revision() == 0) MCHBAR32(SLPCTL) |= (1 << 8); + } + MCHBAR8(0xb00) |= 1; } /** -- To view, visit https://review.coreboot.org/c/coreboot/+/33781 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c5aae06ae8e3643253fe4a5b080448403f81ebc Gerrit-Change-Number: 33781 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/i945: Remove unneeded whitespaces
by HAOUAS Elyes (Code Review) Jan. 7, 2020

Jan. 7, 2020

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36467 ) Change subject: nb/i945: Remove unneeded whitespaces ...................................................................... nb/i945: Remove unneeded whitespaces Change-Id: Ib1cbb5d466666eff6006d1137525dd5fb0de8e18 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/raminit.c 1 file changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/36467/1 diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 7096774..27fdf00 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -816,9 +816,9 @@ const u8 *slew_group; /* Dual Channel needs different tables. */ if (dual_channel) - slew_group = dual_channel_slew_group_lookup; + slew_group = dual_channel_slew_group_lookup; else - slew_group = single_channel_slew_group_lookup; + slew_group = single_channel_slew_group_lookup; switch (slew_group[index]) { case DQ2030: return dq2030; @@ -957,7 +957,7 @@ printk(BIOS_DEBUG, "Programming Dual Channel RCOMP\n"); strength_multiplier = dual_channel_strength_multiplier; dual_channel = 1; - idx = 5 * sysinfo->dimm[0] + sysinfo->dimm[2]; + idx = 5 * sysinfo->dimm[0] + sysinfo->dimm[2]; } else { printk(BIOS_DEBUG, "Programming Single Channel RCOMP\n"); strength_multiplier = single_channel_strength_multiplier; @@ -1209,7 +1209,7 @@ if (sysinfo->interleaved) tolud = (cum0 + cum1) << 1; else - tolud = (cum1 ? cum1 : cum0) << 1; + tolud = (cum1 ? cum1 : cum0) << 1; /* The TOM register has a different format */ tom = tolud >> 3; @@ -1349,7 +1349,7 @@ reg32 |= (1 << 11); MCHBAR32(C0DRC1) = reg32; - /* Do we have to do this if we're in Single Channel Mode? */ + /* Do we have to do this if we're in Single Channel Mode? */ reg32 = MCHBAR32(C1DRC1); for (i = 4; i < 8; i++) { @@ -1706,7 +1706,7 @@ if (voltage == VOLTAGE_1_50) { second_vco = 1; - } else if ((i945_silicon_revision() > 0) && (freq == CRCLK_250MHz)) { + } else if ((i945_silicon_revision() > 0) && (freq == CRCLK_250MHz)) { u16 mem = sysinfo->memory_frequency; u16 fsb = sysinfo->fsb_frequency; @@ -2034,7 +2034,7 @@ u32 chan0 = 0, chan1 = 0; int chan0_dualsided, chan1_dualsided, chan0_populated, chan1_populated; - chan0_populated = (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED || + chan0_populated = (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED || sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED); chan1_populated = (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED || sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED); @@ -2514,7 +2514,7 @@ } #define RTT_ODT_NONE 0 -#define RTT_ODT_50_OHM ((1 << 9) | (1 << 5)) +#define RTT_ODT_50_OHM ((1 << 9) | (1 << 5)) #define RTT_ODT_75_OHM (1 << 5) #define RTT_ODT_150_OHM (1 << 9) -- To view, visit https://review.coreboot.org/c/coreboot/+/36467 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib1cbb5d466666eff6006d1137525dd5fb0de8e18 Gerrit-Change-Number: 36467 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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