coreboot-gerrit January 2020

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Change in coreboot[master]: mb/hp/*/devicetree.cb: Inherit the subsystemid
by Angel Pons (Code Review) 10 Jan '20

10 Jan '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38081 ) Change subject: mb/hp/*/devicetree.cb: Inherit the subsystemid ...................................................................... mb/hp/*/devicetree.cb: Inherit the subsystemid Since the same subsystemid is used for all the devices on the devicetree, factor it out via inheritance. While we are at it, tidy up all the now-empty device blocks. Change-Id: Iccd74fff9456e1204735a80ecc4f7685624cb78e Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/hp/2570p/devicetree.cb M src/mainboard/hp/2760p/devicetree.cb M src/mainboard/hp/8460p/devicetree.cb M src/mainboard/hp/8470p/devicetree.cb M src/mainboard/hp/8770w/devicetree.cb M src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb M src/mainboard/hp/folio_9470m/devicetree.cb M src/mainboard/hp/revolve_810_g1/devicetree.cb M src/mainboard/hp/z220_sff_workstation/devicetree.cb 9 files changed, 255 insertions(+), 593 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/38081/1 diff --git a/src/mainboard/hp/2570p/devicetree.cb b/src/mainboard/hp/2570p/devicetree.cb index c638676..abac787 100644 --- a/src/mainboard/hp/2570p/devicetree.cb +++ b/src/mainboard/hp/2570p/devicetree.cb @@ -43,6 +43,7 @@ end end device domain 0x0 on + subsystemid 0x103c 0x17df inherit chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "c2_latency" = "0x0065" register "docking_supported" = "0" @@ -61,54 +62,26 @@ register "superspeed_capable_ports" = "0x0000000f" register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" - device pci 14.0 on # USB 3.0 Controller - subsystemid 0x103c 0x17df - end - device pci 16.0 on # Management Engine Interface 1 - subsystemid 0x103c 0x17df - end - device pci 16.1 off # Management Engine Interface 2 - end - device pci 16.2 off # Management Engine IDE-R - end - device pci 16.3 off # Management Engine KT - end - device pci 19.0 on # Intel Gigabit Ethernet - subsystemid 0x103c 0x17df - end - device pci 1a.0 on # USB2 EHCI #2 - subsystemid 0x103c 0x17df - end - device pci 1b.0 on # High Definition Audio Audio controller - subsystemid 0x103c 0x17df - end - device pci 1c.0 on # PCIe Port #1 - subsystemid 0x103c 0x17df - end - device pci 1c.1 on # PCIe Port #2, ExpressCard - subsystemid 0x103c 0x17df - end - device pci 1c.2 on # PCIe Port #3, SD/MMC - subsystemid 0x103c 0x17df - end - device pci 1c.3 on # PCIe Port #4, WLAN - subsystemid 0x103c 0x17df - end - device pci 1c.4 off # PCIe Port #5 - end - device pci 1c.5 off # PCIe Port #6 - end - device pci 1c.6 off # PCIe Port #7 - end - device pci 1c.7 off # PCIe Port #8 - end - device pci 1d.0 on # USB2 EHCI #1 - subsystemid 0x103c 0x17df - end - device pci 1e.0 off # PCI bridge - end - device pci 1f.0 on # LPC bridge PCI-LPC bridge - subsystemid 0x103c 0x17df + + device pci 14.0 on end # USB 3.0 Controller + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 on end # Intel Gigabit Ethernet + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # High Definition Audio Audio controller + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 on end # PCIe Port #2, ExpressCard + device pci 1c.2 on end # PCIe Port #3, SD/MMC + device pci 1c.3 on end # PCIe Port #4, WLAN + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on # LPC bridge PCI-LPC bridge chip ec/hp/kbc1126 register "ec_data_port" = "0x62" register "ec_cmd_port" = "0x66" @@ -117,23 +90,13 @@ device pnp ff.1 off end end # kbc1126 end - device pci 1f.2 on # SATA Controller 1 - subsystemid 0x103c 0x17df - end - device pci 1f.3 off # SMBus - end - device pci 1f.5 off # SATA Controller 2 - end - device pci 1f.6 off # Thermal - end + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 off end # SMBus + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 off end # Thermal end - device pci 00.0 on # Host bridge Host bridge - subsystemid 0x103c 0x17df - end - device pci 01.0 off # PCIe Bridge for discrete graphics - end - device pci 02.0 on # Internal graphics VGA controller - subsystemid 0x103c 0x17df - end + device pci 00.0 on end # Host bridge Host bridge + device pci 01.0 off end # PCIe Bridge for discrete graphics + device pci 02.0 on end # Internal graphics VGA controller end end diff --git a/src/mainboard/hp/2760p/devicetree.cb b/src/mainboard/hp/2760p/devicetree.cb index 06124ed..f33d016 100644 --- a/src/mainboard/hp/2760p/devicetree.cb +++ b/src/mainboard/hp/2760p/devicetree.cb @@ -43,14 +43,11 @@ end end device domain 0x0 on - device pci 00.0 on # Host bridge Host bridge - subsystemid 0x103c 0x162a - end - device pci 01.0 off # PCIe Bridge for discrete graphics - end - device pci 02.0 on # Internal graphics VGA controller - subsystemid 0x103c 0x162a - end + subsystemid 0x103c 0x162a inherit + + device pci 00.0 on end # Host bridge Host bridge + device pci 01.0 off end # PCIe Bridge for discrete graphics + device pci 02.0 on end # Internal graphics VGA controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "c2_latency" = "0x0065" @@ -65,54 +62,27 @@ register "pcie_port_coalesce" = "1" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x21" - register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0" - device pci 16.0 on # Management Engine Interface 1 - subsystemid 0x103c 0x162a - end - device pci 16.1 off # Management Engine Interface 2 - end - device pci 16.2 off # Management Engine IDE-R - end - device pci 16.3 off # Management Engine KT - end - device pci 19.0 on # Intel Gigabit Ethernet - subsystemid 0x103c 0x162a - end - device pci 1a.0 on # USB2 EHCI #2 - subsystemid 0x103c 0x162a - end - device pci 1b.0 on # High Definition Audio Audio controller - subsystemid 0x103c 0x162a - end - device pci 1c.0 on # PCIe Port #1 - subsystemid 0x103c 0x162a - end - device pci 1c.1 on # PCIe Port #2, ExpressCard - subsystemid 0x103c 0x162a - end - device pci 1c.2 on # PCIe Port #3, SD/MMC - subsystemid 0x103c 0x162a - end - device pci 1c.3 on # WLAN - end - device pci 1c.4 off # PCIe Port #5 - end - device pci 1c.5 off # PCIe Port #6 - end - device pci 1c.6 on # PCIe Port #7, WWAN - end - device pci 1c.7 off # PCIe Port #8 - end - device pci 1d.0 on # USB2 EHCI #1 - subsystemid 0x103c 0x162a - end - device pci 1e.0 off # PCI bridge - end - device pci 1f.0 on # LPC bridge PCI-LPC bridge - subsystemid 0x103c 0x162a + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 on end # Intel Gigabit Ethernet + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # High Definition Audio Audio controller + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 on end # PCIe Port #2, ExpressCard + device pci 1c.2 on end # PCIe Port #3, SD/MMC + device pci 1c.3 on end # WLAN + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 on end # PCIe Port #7, WWAN + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on # LPC bridge PCI-LPC bridge chip ec/hp/kbc1126 register "ec_data_port" = "0x60" register "ec_cmd_port" = "0x64" @@ -121,15 +91,10 @@ device pnp ff.1 off end end # kbc1126 end - device pci 1f.2 on # SATA Controller 1 - subsystemid 0x103c 0x162a - end - device pci 1f.3 off # SMBus - end - device pci 1f.5 off # SATA Controller 2 - end - device pci 1f.6 off # Thermal - end + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 off end # SMBus + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 off end # Thermal end end end diff --git a/src/mainboard/hp/8460p/devicetree.cb b/src/mainboard/hp/8460p/devicetree.cb index 6852f02..972ee48 100644 --- a/src/mainboard/hp/8460p/devicetree.cb +++ b/src/mainboard/hp/8460p/devicetree.cb @@ -43,14 +43,12 @@ end end device domain 0x0 on - device pci 00.0 on # Host bridge - subsystemid 0x103c 0x161c - end - device pci 01.0 on # PCIe Bridge for discrete graphics - end - device pci 02.0 on # Internal graphics - subsystemid 0x103c 0x161c - end + subsystemid 0x103c 0x161c inherit + + device pci 00.0 on end # Host bridge + device pci 01.0 on end # PCIe Bridge for discrete graphics + device pci 02.0 on end # Internal graphics + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "c2_latency" = "0x0065" register "docking_supported" = "0" @@ -65,57 +63,27 @@ register "sata_interface_speed_support" = "0x3" # HDD(0), ODD(1), docking(3,5), eSATA(4) register "sata_port_map" = "0x3b" - register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0" - device pci 16.0 on # Management Engine Interface 1 - subsystemid 0x103c 0x161c - end - device pci 16.1 off # Management Engine Interface 2 - end - device pci 16.2 off # Management Engine IDE-R - end - device pci 16.3 on # Management Engine KT - subsystemid 0x103c 0x161c - end - device pci 19.0 on # Intel Gigabit Ethernet - subsystemid 0x103c 0x161c - end - device pci 1a.0 on # USB2 EHCI #2 - subsystemid 0x103c 0x161c - end - device pci 1b.0 on # High Definition Audio Audio controller - subsystemid 0x103c 0x161c - end - device pci 1c.0 on # PCIe Port #1 - subsystemid 0x103c 0x161c - end - device pci 1c.1 on # PCIe Port #2, ExpressCard - subsystemid 0x103c 0x161c - end - device pci 1c.2 on # PCIe Port #3, SD/MMC - subsystemid 0x103c 0x161c - end - device pci 1c.3 on # PCIe Port #4, WLAN - subsystemid 0x103c 0x161c - end - device pci 1c.4 off # PCIe Port #5 - end - device pci 1c.5 off # PCIe Port #6 - end - device pci 1c.6 on # PCIe Port #7, WWAN - end - device pci 1c.7 on # PCIe Port #8, NEC USB 3.0 Host Controller - subsystemid 0x103c 0x161c - end - device pci 1d.0 on # USB2 EHCI #1 - subsystemid 0x103c 0x161c - end - device pci 1e.0 off # PCI bridge - end - device pci 1f.0 on # LPC bridge PCI-LPC bridge - subsystemid 0x103c 0x161c + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 on end # Management Engine KT + device pci 19.0 on end # Intel Gigabit Ethernet + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # High Definition Audio Audio controller + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 on end # PCIe Port #2, ExpressCard + device pci 1c.2 on end # PCIe Port #3, SD/MMC + device pci 1c.3 on end # PCIe Port #4, WLAN + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 on end # PCIe Port #7, WWAN + device pci 1c.7 on end # PCIe Port #8, NEC USB 3.0 Host Controller + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on # LPC bridge PCI-LPC bridge chip ec/hp/kbc1126 register "ec_data_port" = "0x60" register "ec_cmd_port" = "0x64" @@ -140,15 +108,10 @@ device pnp 0c31.0 on end end end - device pci 1f.2 on # SATA Controller 1 - subsystemid 0x103c 0x161c - end - device pci 1f.3 off # SMBus - end - device pci 1f.5 off # SATA Controller 2 - end - device pci 1f.6 off # Thermal - end + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 off end # SMBus + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 off end # Thermal end end end diff --git a/src/mainboard/hp/8470p/devicetree.cb b/src/mainboard/hp/8470p/devicetree.cb index 3725b08..afb254f 100644 --- a/src/mainboard/hp/8470p/devicetree.cb +++ b/src/mainboard/hp/8470p/devicetree.cb @@ -43,14 +43,11 @@ end end device domain 0x0 on - device pci 00.0 on # Host bridge - subsystemid 0x103c 0x179b - end - device pci 01.0 on # PCIe Bridge for discrete graphics - end - device pci 02.0 on # Internal graphics VGA controller - subsystemid 0x103c 0x179b - end + subsystemid 0x103c 0x179b inherit + + device pci 00.0 on end # Host bridge + device pci 01.0 on end # PCIe Bridge for discrete graphics + device pci 02.0 on end # Internal graphics VGA controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "c2_latency" = "0x0065" @@ -69,59 +66,28 @@ register "superspeed_capable_ports" = "0x0000000f" register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" - register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0" - device pci 14.0 on # USB 3.0 Controller - subsystemid 0x103c 0x179b - end - device pci 16.0 on # Management Engine Interface 1 - subsystemid 0x103c 0x179b - end - device pci 16.1 off # Management Engine Interface 2 - end - device pci 16.2 off # Management Engine IDE-R - end - device pci 16.3 on # Management Engine KT - subsystemid 0x103c 0x179b - end - device pci 19.0 on # Intel Gigabit Ethernet - subsystemid 0x103c 0x179b - end - device pci 1a.0 on # USB2 EHCI #2 - subsystemid 0x103c 0x179b - end - device pci 1b.0 on # High Definition Audio Audio controller - subsystemid 0x103c 0x179b - end - device pci 1c.0 on # PCIe Port #1 - subsystemid 0x103c 0x179b - end - device pci 1c.1 on # PCIe Port #2, ExpressCard - subsystemid 0x103c 0x179b - end - device pci 1c.2 on # PCIe Port #3, SD/MMC - subsystemid 0x103c 0x179b - end - device pci 1c.3 on # PCIe Port #4, WLAN - subsystemid 0x103c 0x179b - end - device pci 1c.4 off # PCIe Port #5 - end - device pci 1c.5 off # PCIe Port #6 - end - device pci 1c.6 off # PCIe Port #7 - end - device pci 1c.7 off # PCIe Port #8 - end - device pci 1d.0 on # USB2 EHCI #1 - subsystemid 0x103c 0x179b - end - device pci 1e.0 off # PCI bridge - end - device pci 1f.0 on # LPC bridge PCI-LPC bridge - subsystemid 0x103c 0x179b + device pci 14.0 on end # USB 3.0 Controller + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 on end # Management Engine KT + device pci 19.0 on end # Intel Gigabit Ethernet + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # High Definition Audio Audio controller + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 on end # PCIe Port #2, ExpressCard + device pci 1c.2 on end # PCIe Port #3, SD/MMC + device pci 1c.3 on end # PCIe Port #4, WLAN + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on # LPC bridge PCI-LPC bridge chip ec/hp/kbc1126 register "ec_data_port" = "0x62" register "ec_cmd_port" = "0x66" @@ -142,15 +108,10 @@ end end #chip superio/smsc/lpc47n217 end - device pci 1f.2 on # SATA Controller 1 - subsystemid 0x103c 0x179b - end - device pci 1f.3 off # SMBus - end - device pci 1f.5 off # SATA Controller 2 - end - device pci 1f.6 off # Thermal - end + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 off end # SMBus + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 off end # Thermal end end end diff --git a/src/mainboard/hp/8770w/devicetree.cb b/src/mainboard/hp/8770w/devicetree.cb index 0a30de2..a9096c5 100644 --- a/src/mainboard/hp/8770w/devicetree.cb +++ b/src/mainboard/hp/8770w/devicetree.cb @@ -29,16 +29,14 @@ end end device domain 0x0 on - device pci 00.0 on # Host bridge - subsystemid 0x103c 0x176c + subsystemid 0x103c 0x176c inherit + + device pci 00.0 on end # Host bridge + device pci 01.0 on # PCIe Bridge for discrete graphics + device pci 00.0 on end # GPU + device pci 00.1 on end # HDMI Audio on GPU end - device pci 01.0 on # PCIe Bridge for discrete graphics - device pci 00.0 on end # GPU - device pci 00.1 on end # HDMI Audio on GPU - end - device pci 02.0 off # Internal graphics VGA controller - subsystemid 0x103c 0x176c - end + device pci 02.0 off end # Internal graphics VGA controller chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH register "c2_latency" = "0x0065" @@ -56,59 +54,28 @@ register "superspeed_capable_ports" = "0x0000000f" register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" - register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0" - device pci 14.0 on # USB 3.0 Controller - subsystemid 0x103c 0x176c - end - device pci 16.0 on # Management Engine Interface 1 - subsystemid 0x103c 0x176c - end - device pci 16.1 off # Management Engine Interface 2 - end - device pci 16.2 off # Management Engine IDE-R - end - device pci 16.3 off # Management Engine KT - end - device pci 19.0 on # Intel Gigabit Ethernet - subsystemid 0x103c 0x176c - end - device pci 1a.0 on # USB2 EHCI #2 - subsystemid 0x103c 0x176c - end - device pci 1b.0 on # High Definition Audio Audio controller - subsystemid 0x103c 0x176c - end - device pci 1c.0 on # PCIe Port #1 - subsystemid 0x103c 0x176c - end - device pci 1c.1 on # PCIe Port #2 - subsystemid 0x103c 0x176c - end - device pci 1c.2 on # Media Card and FireWire host controller - subsystemid 0x103c 0x176c - end - device pci 1c.3 on # Wireless LAN Adapter - subsystemid 0x103c 0x176c - end - device pci 1c.4 on # SATA Controller 2 for dock - subsystemid 0x103c 0x176c - end - device pci 1c.5 off # PCIe Port #6 - end - device pci 1c.6 off # PCIe Port #7 - end - device pci 1c.7 off # PCIe Port #8 - end - device pci 1d.0 on # USB2 EHCI #1 - subsystemid 0x103c 0x176c - end - device pci 1e.0 off # PCI bridge - end - device pci 1f.0 on # LPC bridge PCI-LPC bridge - subsystemid 0x103c 0x176c + device pci 14.0 on end # USB 3.0 Controller + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 on end # Intel Gigabit Ethernet + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # High Definition Audio Audio controller + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 on end # PCIe Port #2 + device pci 1c.2 on end # Media Card and FireWire host controller + device pci 1c.3 on end # Wireless LAN Adapter + device pci 1c.4 on end # SATA Controller 2 for dock + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on # LPC bridge PCI-LPC bridge chip ec/hp/kbc1126 register "ec_data_port" = "0x62" register "ec_cmd_port" = "0x66" @@ -129,15 +96,10 @@ end end #chip superio/smsc/lpc47n217 end - device pci 1f.2 on # SATA Controller 1 - subsystemid 0x103c 0x176c - end - device pci 1f.3 off # SMBus - end - device pci 1f.5 off # SATA Controller 2 - end - device pci 1f.6 off # Thermal - end + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 off end # SMBus + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 off end # Thermal end end end diff --git a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb index 1472f84..660e3b0 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb +++ b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb @@ -39,6 +39,8 @@ register "pci_mmio_size" = "2048" device domain 0x0 on + subsystemid 0x103c 0x1495 inherit + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "c2_latency" = "0x0065" register "docking_supported" = "0" @@ -50,53 +52,25 @@ register "sata_port_map" = "0xf" register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x0" - device pci 16.0 on # Management Engine Interface 1 - subsystemid 0x103c 0x1495 - end - device pci 16.1 off # Management Engine Interface 2 - end - device pci 16.2 off # Management Engine IDE-R - end - device pci 16.3 on # Management Engine KT - subsystemid 0x103c 0x1495 - end - device pci 19.0 on # Intel Gigabit Ethernet - subsystemid 0x103c 0x1495 - end - device pci 1a.0 on # USB2 EHCI #2 - subsystemid 0x103c 0x1495 - end - device pci 1b.0 on # High Definition Audio Audio controller - subsystemid 0x103c 0x1495 - end - device pci 1c.0 on # PCIe Port #1 - subsystemid 0x103c 0x1495 - end - device pci 1c.1 off # PCIe Port #2 - end - device pci 1c.2 off # PCIe Port #3 - end - device pci 1c.3 off # PCIe Port #4 - end - device pci 1c.4 on # PCIe Port #5 - subsystemid 0x103c 0x1495 - end - device pci 1c.5 off # PCIe Port #6 - end - device pci 1c.6 on # PCIe Port #7 - subsystemid 0x103c 0x1495 - end - device pci 1c.7 on # PCIe Port #8 - subsystemid 0x103c 0x1495 - end - device pci 1d.0 on # USB2 EHCI #1 - subsystemid 0x103c 0x1495 - end - device pci 1e.0 on # PCI bridge - subsystemid 0x103c 0x1495 - end - device pci 1f.0 on # LPC bridge PCI-LPC bridge - subsystemid 0x103c 0x1495 + + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 on end # Management Engine KT + device pci 19.0 on end # Intel Gigabit Ethernet + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # High Definition Audio Audio controller + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 on end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 on end # PCIe Port #7 + device pci 1c.7 on end # PCIe Port #8 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 on end # PCI bridge + device pci 1f.0 on # LPC bridge PCI-LPC bridge chip superio/nuvoton/npcd378 device pnp 2e.0 off end # Floppy device pnp 2e.1 on # Parallel port @@ -197,25 +171,13 @@ device pnp 4e.0 on end # TPM module end end - device pci 1f.2 on # SATA Controller 1 - subsystemid 0x103c 0x1495 - end - device pci 1f.3 on # SMBus - subsystemid 0x103c 0x1495 - end - device pci 1f.5 off # SATA Controller 2 - end - device pci 1f.6 off # Thermal - end + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 off end # Thermal end - device pci 00.0 on # Host bridge Host bridge - subsystemid 0x103c 0x1495 - end - device pci 01.0 on # PCIe Bridge for discrete graphics - subsystemid 0x103c 0x1495 - end - device pci 02.0 on # Internal graphics VGA controller - subsystemid 0x103c 0x1495 - end + device pci 00.0 on end # Host bridge Host bridge + device pci 01.0 on end # PCIe Bridge for discrete graphics + device pci 02.0 on end # Internal graphics VGA controller end end diff --git a/src/mainboard/hp/folio_9470m/devicetree.cb b/src/mainboard/hp/folio_9470m/devicetree.cb index cd610b6..7d0265d 100644 --- a/src/mainboard/hp/folio_9470m/devicetree.cb +++ b/src/mainboard/hp/folio_9470m/devicetree.cb @@ -43,6 +43,8 @@ end end device domain 0x0 on + subsystemid 0x103c 0x18df inherit + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "c2_latency" = "0x0065" register "docking_supported" = "0" @@ -61,54 +63,26 @@ register "superspeed_capable_ports" = "0x0000000f" register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" - device pci 14.0 on # USB 3.0 Controller - subsystemid 0x103c 0x18df - end - device pci 16.0 off # Management Engine Interface 1 - subsystemid 0x103c 0x18df - end - device pci 16.1 off # Management Engine Interface 2 - end - device pci 16.2 off # Management Engine IDE-R - end - device pci 16.3 off # Management Engine KT - subsystemid 0x103c 0x18df - end - device pci 19.0 on # Intel Gigabit Ethernet - subsystemid 0x103c 0x18df - end - device pci 1a.0 on # USB2 EHCI #2 - subsystemid 0x103c 0x18df - end - device pci 1b.0 on # High Definition Audio Audio controller - subsystemid 0x103c 0x18df - end - device pci 1c.0 on # PCIe Port #1 - subsystemid 0x103c 0x18df - end - device pci 1c.1 off # PCIe Port #2 - end - device pci 1c.2 on # PCIe Port #3 - subsystemid 0x103c 0x18df - end # SDHCI - device pci 1c.3 on # PCIe Port #4 - subsystemid 0x103c 0x18df - end # WLAN - device pci 1c.4 off # PCIe Port #5 - end - device pci 1c.5 off # PCIe Port #6 - end - device pci 1c.6 off # PCIe Port #7 - end - device pci 1c.7 off # PCIe Port #8 - end - device pci 1d.0 on # USB2 EHCI #1 - subsystemid 0x103c 0x18df - end - device pci 1e.0 off # PCI bridge - end - device pci 1f.0 on # LPC bridge PCI-LPC bridge - subsystemid 0x103c 0x18df + + device pci 14.0 on end # USB 3.0 Controller + device pci 16.0 off end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 on end # Intel Gigabit Ethernet + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # High Definition Audio Audio controller + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 on end # PCIe Port #3 SDHCI + device pci 1c.3 on end # PCIe Port #4 WLAN + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on # LPC bridge PCI-LPC bridge chip ec/hp/kbc1126 register "ec_data_port" = "0x62" register "ec_cmd_port" = "0x66" @@ -121,24 +95,13 @@ device pnp 0c31.0 on end end end - device pci 1f.2 on # SATA Controller 1 - subsystemid 0x103c 0x18df - end - device pci 1f.3 on # SMBus - subsystemid 0x103c 0x18df - end - device pci 1f.5 off # SATA Controller 2 - end - device pci 1f.6 off # Thermal - end + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 off end # Thermal end - device pci 00.0 on # Host bridge Host bridge - subsystemid 0x103c 0x18df - end - device pci 01.0 off # PCIe Bridge for discrete graphics - end - device pci 02.0 on # Internal graphics VGA controller - subsystemid 0x103c 0x18df - end + device pci 00.0 on end # Host bridge Host bridge + device pci 01.0 off end # PCIe Bridge for discrete graphics + device pci 02.0 on end # Internal graphics VGA controller end end diff --git a/src/mainboard/hp/revolve_810_g1/devicetree.cb b/src/mainboard/hp/revolve_810_g1/devicetree.cb index 32d04ea..4a08f42 100644 --- a/src/mainboard/hp/revolve_810_g1/devicetree.cb +++ b/src/mainboard/hp/revolve_810_g1/devicetree.cb @@ -43,6 +43,8 @@ end end device domain 0x0 on + subsystemid 0x103c 0x18f8 inherit + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "c2_latency" = "0x0065" register "docking_supported" = "0" @@ -61,54 +63,26 @@ register "superspeed_capable_ports" = "0x0000000f" register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" - device pci 14.0 on # USB 3.0 Controller - subsystemid 0x103c 0x18f8 - end - device pci 16.0 off # Management Engine Interface 1 - subsystemid 0x103c 0x18f8 - end - device pci 16.1 off # Management Engine Interface 2 - end - device pci 16.2 off # Management Engine IDE-R - end - device pci 16.3 off # Management Engine KT - subsystemid 0x103c 0x18f8 - end - device pci 19.0 on # Intel Gigabit Ethernet - subsystemid 0x8086 0x18f8 - end - device pci 1a.0 on # USB2 EHCI #2 - subsystemid 0x103c 0x18f8 - end - device pci 1b.0 on # High Definition Audio Audio controller - subsystemid 0x103c 0x18f8 - end - device pci 1c.0 on # PCIe Port #1 - subsystemid 0x103c 0x18f8 - end - device pci 1c.1 off # PCIe Port #2 - end - device pci 1c.2 on # PCIe Port #3 - subsystemid 0x103c 0x18f8 - end - device pci 1c.3 on # PCIe Port #4 - subsystemid 0x103c 0x18f8 - end - device pci 1c.4 off # PCIe Port #5 - end - device pci 1c.5 off # PCIe Port #6 - end - device pci 1c.6 off # PCIe Port #7 - end - device pci 1c.7 off # PCIe Port #8 - end - device pci 1d.0 on # USB2 EHCI #1 - subsystemid 0x103c 0x18f8 - end - device pci 1e.0 off # PCI bridge - end - device pci 1f.0 on # LPC bridge PCI-LPC bridge - subsystemid 0x103c 0x18f8 + + device pci 14.0 on end # USB 3.0 Controller + device pci 16.0 off end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 on end # Intel Gigabit Ethernet + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # High Definition Audio Audio controller + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 on end # PCIe Port #3 + device pci 1c.3 on end # PCIe Port #4 + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on # LPC bridge PCI-LPC bridge chip ec/hp/kbc1126 register "ec_data_port" = "0x62" register "ec_cmd_port" = "0x66" @@ -121,23 +95,13 @@ device pnp 0c31.0 on end end end - device pci 1f.2 on # SATA Controller 1 - subsystemid 0x103c 0x18f8 - end - device pci 1f.3 off # SMBus - end - device pci 1f.5 off # SATA Controller 2 - end - device pci 1f.6 off # Thermal - end + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 off end # SMBus + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 off end # Thermal end - device pci 00.0 on # Host bridge Host bridge - subsystemid 0x103c 0x18f8 - end - device pci 01.0 off # PCIe Bridge for discrete graphics - end - device pci 02.0 on # Internal graphics VGA controller - subsystemid 0x103c 0x18f8 - end + device pci 00.0 on end # Host bridge Host bridge + device pci 01.0 off end # PCIe Bridge for discrete graphics + device pci 02.0 on end # Internal graphics VGA controller end end diff --git a/src/mainboard/hp/z220_sff_workstation/devicetree.cb b/src/mainboard/hp/z220_sff_workstation/devicetree.cb index 5108db4..94d079a 100644 --- a/src/mainboard/hp/z220_sff_workstation/devicetree.cb +++ b/src/mainboard/hp/z220_sff_workstation/devicetree.cb @@ -39,6 +39,7 @@ register "pci_mmio_size" = "2048" device domain 0x0 on + subsystemid 0x103c 0x1791 inherit chip southbridge/intel/bd82x6x # Intel Series 7 PCH register "c2_latency" = "0x0065" register "docking_supported" = "0" @@ -50,56 +51,26 @@ register "sata_port_map" = "0xf" register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x2005" - device pci 14.0 on # xHCI - subsystemid 0x103c 0x1791 - end - device pci 16.0 on # Management Engine Interface 1 - subsystemid 0x103c 0x1791 - end - device pci 16.1 off # Management Engine Interface 2 - end - device pci 16.2 off # Management Engine IDE-R - end - device pci 16.3 on # Management Engine KT - subsystemid 0x103c 0x1791 - end - device pci 19.0 on # Intel Gigabit Ethernet - subsystemid 0x103c 0x1791 - end - device pci 1a.0 on # USB2 EHCI #2 - subsystemid 0x103c 0x1791 - end - device pci 1b.0 on # High Definition Audio Audio controller - subsystemid 0x103c 0x1791 - end - device pci 1c.0 on # PCIe Port #1 - subsystemid 0x103c 0x1791 - end - device pci 1c.1 off # PCIe Port #2 - end - device pci 1c.2 off # PCIe Port #3 - end - device pci 1c.3 off # PCIe Port #4 - end - device pci 1c.4 on # PCIe Port #5 - subsystemid 0x103c 0x1791 - end - device pci 1c.5 off # PCIe Port #6 - end - device pci 1c.6 on # PCIe Port #7 - subsystemid 0x103c 0x1791 - end - device pci 1c.7 on # PCIe Port #8 - subsystemid 0x103c 0x1791 - end - device pci 1d.0 on # USB2 EHCI #1 - subsystemid 0x103c 0x1791 - end - device pci 1e.0 on # PCI bridge - subsystemid 0x103c 0x1791 - end - device pci 1f.0 on # LPC bridge PCI-LPC bridge - subsystemid 0x103c 0x1791 + + device pci 14.0 on end # xHCI + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 on end # Management Engine KT + device pci 19.0 on end # Intel Gigabit Ethernet + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # High Definition Audio Audio controller + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 on end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 on end # PCIe Port #7 + device pci 1c.7 on end # PCIe Port #8 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 on end # PCI bridge + device pci 1f.0 on # LPC bridge PCI-LPC bridge chip superio/nuvoton/npcd378 device pnp 2e.0 off end # Floppy device pnp 2e.1 on # Parallel port @@ -200,25 +171,13 @@ device pnp 4e.0 on end # TPM module end end - device pci 1f.2 on # SATA Controller 1 - subsystemid 0x103c 0x1791 - end - device pci 1f.3 on # SMBus - subsystemid 0x103c 0x1791 - end - device pci 1f.5 off # SATA Controller 2 - end - device pci 1f.6 off # Thermal - end + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 off end # Thermal end - device pci 00.0 on # Host bridge Host bridge - subsystemid 0x103c 0x1791 - end - device pci 01.0 on # PCIe Bridge for discrete graphics - subsystemid 0x103c 0x1791 - end - device pci 02.0 on # Internal graphics VGA controller - subsystemid 0x103c 0x1791 - end + device pci 00.0 on end # Host bridge Host bridge + device pci 01.0 on end # PCIe Bridge for discrete graphics + device pci 02.0 on end # Internal graphics VGA controller end end -- To view, visit https://review.coreboot.org/c/coreboot/+/38081 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iccd74fff9456e1204735a80ecc4f7685624cb78e Gerrit-Change-Number: 38081 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 10

Change in coreboot[master]: vc/amd/agesa: Remove unused assignments
by Name of user not set (Code Review) 10 Jan '20

10 Jan '20

awokd(a)danwin1210.me has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36257 ) Change subject: vc/amd/agesa: Remove unused assignments ...................................................................... vc/amd/agesa: Remove unused assignments 'Status' is assigned a value three times before it is checked. Remove the first two assignments. Change-Id: Id7136d62b4dbd6dce877983467960373b3a7ac22 Signed-off-by: Joe Moore <awokd(a)danwin1210.me> Found-by: Coverity CID 1241809 --- M src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c M src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c M src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c M src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c 4 files changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/36257/1 diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c index fd7ab4e..d74949b 100644 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c +++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c @@ -472,13 +472,11 @@ if (ExtDisplayDeviceInfo == NULL) { //Run out of supported display device types AGESA_STATUS_UPDATE (AGESA_ERROR, ConnectorEnumInfo.Status); - Status = AGESA_ERROR; PcieConfigDisableEngine (ConnectorEnumInfo.Engine); } if ((Gfx->Gnb3dStereoPinIndex != 0) && (ConnectorEnumInfo.Engine->Type.Ddi.DdiData.HdpIndex == (Gfx->Gnb3dStereoPinIndex - 1))) { AGESA_STATUS_UPDATE (AGESA_ERROR, ConnectorEnumInfo.Status); - Status = AGESA_ERROR; PcieConfigDisableEngine (ConnectorEnumInfo.Engine); } diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c index 70aa595..440c5ff 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c @@ -474,13 +474,11 @@ if (ExtDisplayDeviceInfo == NULL) { //Run out of supported display device types AGESA_STATUS_UPDATE (AGESA_ERROR, ConnectorEnumInfo.Status); - Status = AGESA_ERROR; PcieConfigDisableEngine (ConnectorEnumInfo.Engine); } if ((Gfx->Gnb3dStereoPinIndex != 0) && (ConnectorEnumInfo.Engine->Type.Ddi.DdiData.HdpIndex == (Gfx->Gnb3dStereoPinIndex - 1))) { AGESA_STATUS_UPDATE (AGESA_ERROR, ConnectorEnumInfo.Status); - Status = AGESA_ERROR; PcieConfigDisableEngine (ConnectorEnumInfo.Engine); } diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c index f3af5e9..2d42063 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c @@ -488,13 +488,11 @@ if (ExtDisplayDeviceInfo == NULL) { //Run out of supported display device types AGESA_STATUS_UPDATE (AGESA_ERROR, ConnectorEnumInfo.Status); - Status = AGESA_ERROR; PcieConfigDisableEngine (ConnectorEnumInfo.Engine); } if ((Gfx->Gnb3dStereoPinIndex != 0) && (ConnectorEnumInfo.Engine->Type.Ddi.DdiData.HdpIndex == (Gfx->Gnb3dStereoPinIndex - 1))) { AGESA_STATUS_UPDATE (AGESA_ERROR, ConnectorEnumInfo.Status); - Status = AGESA_ERROR; PcieConfigDisableEngine (ConnectorEnumInfo.Engine); } diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c index c9c9166..2350122 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c @@ -488,13 +488,11 @@ if (ExtDisplayDeviceInfo == NULL) { //Run out of supported display device types AGESA_STATUS_UPDATE (AGESA_ERROR, ConnectorEnumInfo.Status); - Status = AGESA_ERROR; PcieConfigDisableEngine (ConnectorEnumInfo.Engine); } if ((Gfx->Gnb3dStereoPinIndex != 0) && (ConnectorEnumInfo.Engine->Type.Ddi.DdiData.HdpIndex == (Gfx->Gnb3dStereoPinIndex - 1))) { AGESA_STATUS_UPDATE (AGESA_ERROR, ConnectorEnumInfo.Status); - Status = AGESA_ERROR; PcieConfigDisableEngine (ConnectorEnumInfo.Engine); } -- To view, visit https://review.coreboot.org/c/coreboot/+/36257 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id7136d62b4dbd6dce877983467960373b3a7ac22 Gerrit-Change-Number: 36257 Gerrit-PatchSet: 1 Gerrit-Owner: awokd(a)danwin1210.me Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: soc/intel/{common,skl,cnl,icl,apl,tgl}: Make me_hfsts1 structure SoC ...
by Sridhar Siricilla (Code Review) 10 Jan '20

10 Jan '20

Sridhar Siricilla has uploaded a new patch set (#21) to the change originally created by Rizwan Qureshi. ( https://review.coreboot.org/c/coreboot/+/35546 ) Change subject: soc/intel/{common,skl,cnl,icl,apl,tgl}: Make me_hfsts1 structure SoC specific ...................................................................... soc/intel/{common,skl,cnl,icl,apl,tgl}: Make me_hfsts1 structure SoC specific Move me_hfsts1 structure from common code to SoC specific. TEST=Build and Boot hatch, soraka, tglrvp, bobba boards. TBD=iclrvp Change-Id: If7ea6043d7b5473d0c16e83d7b2d4b620c125652 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- M src/soc/intel/apollolake/cse.c A src/soc/intel/apollolake/include/soc/me.h M src/soc/intel/cannonlake/include/soc/me.h M src/soc/intel/cannonlake/me.c M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/cse.h M src/soc/intel/icelake/Makefile.inc A src/soc/intel/icelake/include/soc/me.h A src/soc/intel/icelake/me.c M src/soc/intel/skylake/include/soc/me.h M src/soc/intel/skylake/me.c M src/soc/intel/tigerlake/Makefile.inc A src/soc/intel/tigerlake/include/soc/me.h A src/soc/intel/tigerlake/me.c 14 files changed, 568 insertions(+), 51 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/35546/21 -- To view, visit https://review.coreboot.org/c/coreboot/+/35546 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7ea6043d7b5473d0c16e83d7b2d4b620c125652 Gerrit-Change-Number: 35546 Gerrit-PatchSet: 21 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <riz.pro(a)gmail.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/pcengines/apu1/bootblock.c: Add possibility to redirect output to ...
by Nico Huber (Code Review) 10 Jan '20

10 Jan '20

Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/29791 ) Change subject: mb/pcengines/apu1/bootblock.c: Add possibility to redirect output to COM2 ...................................................................... mb/pcengines/apu1/bootblock.c: Add possibility to redirect output to COM2 Enable COM2 port on SuperIO if UART index is 1. This change allows to use full RS232 COM1 port for different purposes when COM2 is selected as main port. TEST=flash coreboot with console on COM2 and observer output with UBS-TTL converter connected to COM2 header on PC Engines apu1 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I1e72c5a43a302658f86dafd863e5a67580eae3e4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/29791 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/pcengines/apu1/bootblock.c M src/mainboard/pcengines/apu1/romstage.c 2 files changed, 6 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved diff --git a/src/mainboard/pcengines/apu1/bootblock.c b/src/mainboard/pcengines/apu1/bootblock.c index 2d34cba..dc9f87d 100644 --- a/src/mainboard/pcengines/apu1/bootblock.c +++ b/src/mainboard/pcengines/apu1/bootblock.c @@ -17,9 +17,13 @@ #include <superio/nuvoton/nct5104d/nct5104d.h> #define SIO_PORT 0x2e -#define SERIAL_DEV PNP_DEV(SIO_PORT, NCT5104D_SP1) +#define SERIAL1_DEV PNP_DEV(SIO_PORT, NCT5104D_SP1) +#define SERIAL2_DEV PNP_DEV(SIO_PORT, NCT5104D_SP2) void bootblock_mainboard_early_init(void) { - nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + if (CONFIG_UART_FOR_CONSOLE == 1) + nuvoton_enable_serial(SERIAL2_DEV, CONFIG_TTYS0_BASE); + else if (CONFIG_UART_FOR_CONSOLE == 0) + nuvoton_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/pcengines/apu1/romstage.c b/src/mainboard/pcengines/apu1/romstage.c index 20a6318..df91b04 100644 --- a/src/mainboard/pcengines/apu1/romstage.c +++ b/src/mainboard/pcengines/apu1/romstage.c @@ -17,15 +17,10 @@ #include <amdblocks/acpimmio.h> #include <northbridge/amd/agesa/state_machine.h> -#include <superio/nuvoton/common/nuvoton.h> -#include <superio/nuvoton/nct5104d/nct5104d.h> #include "gpio_ftns.h" #include <SB800.h> #include <sb_cimx.h> -#define SIO_PORT 0x2e -#define SERIAL_DEV PNP_DEV(SIO_PORT, NCT5104D_SP1) - static void early_lpc_init(void) { u32 mmio_base; -- To view, visit https://review.coreboot.org/c/coreboot/+/29791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e72c5a43a302658f86dafd863e5a67580eae3e4 Gerrit-Change-Number: 29791 Gerrit-PatchSet: 5 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: [UNTESTED] nb/intel/sandybridge: Add a bunch of MCHBAR defines
by Angel Pons (Code Review) 10 Jan '20

10 Jan '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38036 ) Change subject: [UNTESTED] nb/intel/sandybridge: Add a bunch of MCHBAR defines ...................................................................... [UNTESTED] nb/intel/sandybridge: Add a bunch of MCHBAR defines Change-Id: I5e5fe56eaa90842dbbdd1bfbbcb7709237b4c486 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/early_init.c M src/northbridge/intel/sandybridge/finalize.c M src/northbridge/intel/sandybridge/northbridge.c M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/raminit_ivy.c M src/northbridge/intel/sandybridge/raminit_mrc.c M src/northbridge/intel/sandybridge/raminit_sandy.c M src/northbridge/intel/sandybridge/sandybridge.h 9 files changed, 841 insertions(+), 492 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/38036/1 diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index 4866558..dbb5784 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -36,9 +36,9 @@ /* setup BARs */ MCHBAR32(0x5404) = IOMMU_BASE1 >> 32; - MCHBAR32(0x5400) = IOMMU_BASE1 | 1; + MCHBAR32(VTD1_BASE) = IOMMU_BASE1 | 1; MCHBAR32(0x5414) = IOMMU_BASE2 >> 32; - MCHBAR32(0x5410) = IOMMU_BASE2 | 1; + MCHBAR32(VTD2_BASE) = IOMMU_BASE2 | 1; /* lock policies */ write32((void *)(IOMMU_BASE1 + 0xff0), 0x80000000); @@ -127,13 +127,13 @@ pci_write_config8(PCI_DEV(0, 2, 0), MSAC, reg8); /* Erratum workarounds */ - reg32 = MCHBAR32(0x5f00); + reg32 = MCHBAR32(SAPMCTL); reg32 |= (1 << 9)|(1 << 10); - MCHBAR32(0x5f00) = reg32; + MCHBAR32(SAPMCTL) = reg32; /* Enable SA Clock Gating */ - reg32 = MCHBAR32(0x5f00); - MCHBAR32(0x5f00) = reg32 | 1; + reg32 = MCHBAR32(SAPMCTL); + MCHBAR32(SAPMCTL) = reg32 | 1; /* GPU RC6 workaround for sighting 366252 */ reg32 = MCHBAR32(0x5d14); diff --git a/src/northbridge/intel/sandybridge/finalize.c b/src/northbridge/intel/sandybridge/finalize.c index e07c6c2..54028f8 100644 --- a/src/northbridge/intel/sandybridge/finalize.c +++ b/src/northbridge/intel/sandybridge/finalize.c @@ -34,8 +34,8 @@ pci_or_config32(PCI_DEV_SNB, TSEGMB, 1 << 0); pci_or_config32(PCI_DEV_SNB, TOLUD, 1 << 0); - MCHBAR32_OR(0x5500, 1 << 0); /* PAVP */ - MCHBAR32_OR(0x5f00, 1 << 31); /* SA PM */ + MCHBAR32_OR(MMIO_PAVP_CTL, 1 << 0); /* PAVP */ + MCHBAR32_OR(SAPMCTL, 1 << 31); /* SA PM */ MCHBAR32_OR(0x6020, 1 << 0); /* UMA GFX */ MCHBAR32_OR(0x63fc, 1 << 0); /* VTDTRK */ MCHBAR32_OR(0x6800, 1 << 31); @@ -43,7 +43,7 @@ MCHBAR32_OR(0x77fc, 1 << 0); /* Memory Controller Lockdown */ - MCHBAR8(0x50fc) = 0x8f; + MCHBAR8(MC_LOCK) = 0x8f; /* Read+write the following */ MCHBAR32(0x6030) = MCHBAR32(0x6030); diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 5ff123e..a9b1c25 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -391,15 +391,15 @@ northbridge_dmi_init(dev); - bridge_type = MCHBAR32(0x5f10); + bridge_type = MCHBAR32(SAPMTIMERS); bridge_type &= ~0xff; if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) { /* Enable Power Aware Interrupt Routing */ - u8 pair = MCHBAR8(0x5418); + u8 pair = MCHBAR8(PAIR_CTL); pair &= ~0xf; /* Clear 3:0 */ pair |= 0x4; /* Fixed Priority */ - MCHBAR8(0x5418) = pair; + MCHBAR8(PAIR_CTL) = pair; /* 30h for IvyBridge */ bridge_type |= 0x30; @@ -407,7 +407,7 @@ /* 20h for Sandybridge */ bridge_type |= 0x20; } - MCHBAR32(0x5f10) = bridge_type; + MCHBAR32(SAPMTIMERS) = bridge_type; /* Turn off unused devices. Has to be done before * setting BIOS_RESET_CPL. @@ -433,12 +433,12 @@ */ if (cpu_config_tdp_levels()) { msr_t msr = rdmsr(MSR_PKG_POWER_LIMIT); - MCHBAR32(0x59A0) = msr.lo; - MCHBAR32(0x59A4) = msr.hi; + MCHBAR32(MC_TURBO_PL1) = msr.lo; + MCHBAR32(MC_TURBO_PL2) = msr.hi; } /* Set here before graphics PM init */ - MCHBAR32(0x5500) = 0x00100001; + MCHBAR32(MMIO_PAVP_CTL) = 0x00100001; } void northbridge_write_smram(u8 smram) diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 0362330..9ac31f7 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -293,7 +293,7 @@ int err; u32 cpu; - MCHBAR32(0x5f00) |= 1; + MCHBAR32(SAPMCTL) |= 1; /* Wait for ME to be ready */ intel_early_me_init(); @@ -404,8 +404,8 @@ if (err) die("raminit failed"); - /* FIXME: should be hardware revision-dependent. */ - MCHBAR32(0x5024) = 0x00a030ce; + /* FIXME: should be hardware revision-dependent. Register seems to be only for IVB. */ + MCHBAR32(CHANNEL_HASH) = 0x00a030ce; set_scrambling_seed(&ctrl); diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 644c415..3bfd10d 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -73,10 +73,10 @@ static void toggle_io_reset(void) { /* toggle IO reset bit */ - u32 r32 = MCHBAR32(0x5030); - MCHBAR32(0x5030) = r32 | 0x20; + u32 r32 = MCHBAR32(MC_INIT_STATE_G); + MCHBAR32(MC_INIT_STATE_G) = r32 | 0x20; udelay(1); - MCHBAR32(0x5030) = r32 & ~0x20; + MCHBAR32(MC_INIT_STATE_G) = r32 & ~0x20; udelay(1); } @@ -179,15 +179,15 @@ FOR_ALL_CHANNELS { // enable xover clk reg = get_XOVER_CLK(ctrl->rankmap[channel]); - printram("XOVER CLK [%x] = %x\n", channel * 0x100 + 0xc14, + printram("XOVER CLK [%x] = %x\n", channel * 0x100 + GDCRCKPICODE_C0, reg); - MCHBAR32(channel * 0x100 + 0xc14) = reg; + MCHBAR32(channel * 0x100 + GDCRCKPICODE_C0) = reg; // enable xover ctl & xover cmd reg = get_XOVER_CMD(ctrl->rankmap[channel]); - printram("XOVER CMD [%x] = %x\n", 0x100 * channel + 0x320c, + printram("XOVER CMD [%x] = %x\n", 0x100 * channel + GDCRCMDPICODING_C0, reg); - MCHBAR32(0x100 * channel + 0x320c) = reg; + MCHBAR32(0x100 * channel + GDCRCMDPICODING_C0) = reg; } } @@ -202,14 +202,14 @@ if (IS_SANDY_CPU(cpu) && IS_SANDY_CPU_C(cpu)) { if (stretch == 2) stretch = 3; - addr = 0x401c + 0x400 * channel; + addr = SCHED_SECOND_CBIT_C0 + 0x400 * channel; MCHBAR32_AND_OR(addr, 0xffffc3ff, (stretch << 12) | (stretch << 10)); printk(RAM_DEBUG, "OTHP Workaround [%x] = %x\n", addr, MCHBAR32(addr)); } else { // OTHP - addr = 0x400c + 0x400 * channel; + addr = TC_OTHP_C0 + 0x400 * channel; MCHBAR32_AND_OR(addr, 0xfff0ffff, (stretch << 16) | (stretch << 18)); printk(RAM_DEBUG, "OTHP [%x] = %x\n", addr, MCHBAR32(addr)); @@ -245,7 +245,7 @@ MCHBAR32(TC_RAP_C0 + 0x400 * channel) = reg; // OTHP - addr = 0x400 * channel + 0x400c; + addr = 0x400 * channel + TC_OTHP_C0; reg = 0; reg |= ctrl->tXPDLL; reg |= (ctrl->tXP << 5); @@ -254,6 +254,7 @@ printram("OTHP [%x] = %x\n", addr, reg); MCHBAR32(addr) = reg; + /* FIXME: Register 0x4014 does not seem to exist. */ MCHBAR32(0x400 * channel + 0x4014) = 0; MCHBAR32_OR(addr, 0x00020000); @@ -288,7 +289,7 @@ reg = (reg & ~0xf0000000) | (val32 << 28); printram("SRFTP [%x] = %x\n", 0x400 * channel + 0x42a4, reg); - MCHBAR32(0x400 * channel + 0x42a4) = reg; + MCHBAR32(0x400 * channel + TC_SRFTP_C0) = reg; } } @@ -359,18 +360,18 @@ } if (ch0size >= ch1size) { - reg = MCHBAR32(0x5014); + reg = MCHBAR32(MAD_ZR); val = ch1size / 256; reg = (reg & ~0xff000000) | val << 24; reg = (reg & ~0xff0000) | (2 * val) << 16; - MCHBAR32(0x5014) = reg; + MCHBAR32(MAD_ZR) = reg; MCHBAR32(MAD_CHNL) = 0x24; } else { - reg = MCHBAR32(0x5014); + reg = MCHBAR32(MAD_ZR); val = ch0size / 256; reg = (reg & ~0xff000000) | val << 24; reg = (reg & ~0xff0000) | (2 * val) << 16; - MCHBAR32(0x5014) = reg; + MCHBAR32(MAD_ZR) = reg; MCHBAR32(MAD_CHNL) = 0x21; } } @@ -618,7 +619,7 @@ static void wait_428c(int channel) { while (1) { - if (MCHBAR32(0x428c + (channel << 10)) & 0x50) + if (MCHBAR32(IOSAV_STATUS_C0 + (channel << 10)) & 0x50) return; } } @@ -636,13 +637,14 @@ slotrank = (ctrl->rankmap[channel] & 1) ? 0 : 2; /* DRAM command ZQCS */ - MCHBAR32(0x4220 + 0x400 * channel) = 0x0f003; - MCHBAR32(0x4230 + 0x400 * channel) = 0x80c01; - MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x60000; - MCHBAR32(0x4210 + 0x400 * channel) = 0; + MCHBAR32(IOSAV_0_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x0f003; + MCHBAR32(IOSAV_0_SUBSEQ_CTL_C0 + 0x400 * channel) = 0x80c01; + MCHBAR32(IOSAV_0_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = + (slotrank << 24) | 0x60000; + MCHBAR32(IOSAV_0_ADDR_UPD_C0 + 0x400 * channel) = 0; // execute command queue - why is bit 22 set here?! - MCHBAR32(0x4284 + 0x400 * channel) = (1 << 22) | RUN_QUEUE_4284(1); + MCHBAR32(IOSAV_SEQ_CTL_C0 + 0x400 * channel) = (1 << 22) | RUN_QUEUE_4284(1); wait_428c(channel); } @@ -652,32 +654,32 @@ u32 reg; int channel; - while (!(MCHBAR32(0x5084) & 0x10000)); + while (!(MCHBAR32(RCOMP_TIMER) & 0x10000)); do { - reg = MCHBAR32(0x428c); + reg = MCHBAR32(IOSAV_STATUS_C0); } while ((reg & 0x14) == 0); // Set state of memory controller reg = 0x112; - MCHBAR32(0x5030) = reg; - MCHBAR32(0x4ea0) = 0; + MCHBAR32(MC_INIT_STATE_G) = reg; + MCHBAR32(MC_INIT_STATE) = 0; reg |= 2; //ddr reset - MCHBAR32(0x5030) = reg; + MCHBAR32(MC_INIT_STATE_G) = reg; // Assert dimm reset signal - MCHBAR32_AND(0x5030, ~0x2); + MCHBAR32_AND(MC_INIT_STATE_G, ~0x2); // Wait 200us udelay(200); // Deassert dimm reset signal - MCHBAR32_OR(0x5030, 2); + MCHBAR32_OR(MC_INIT_STATE_G, 2); // Wait 500us udelay(500); // Enable DCLK - MCHBAR32_OR(0x5030, 4); + MCHBAR32_OR(MC_INIT_STATE_G, 4); // XXX Wait 20ns udelay(1); @@ -685,13 +687,13 @@ FOR_ALL_CHANNELS { // Set valid rank CKE reg = ctrl->rankmap[channel]; - MCHBAR32(0x42a0 + 0x400 * channel) = reg; + MCHBAR32(MC_INIT_STATE_C0 + 0x400 * channel) = reg; // Wait 10ns for ranks to settle //udelay(0.01); reg = (reg & ~0xf0) | (ctrl->rankmap[channel] << 4); - MCHBAR32(0x42a0 + 0x400 * channel) = reg; + MCHBAR32(MC_INIT_STATE_C0 + 0x400 * channel) = reg; // Write reset using a NOP write_reset(ctrl); @@ -726,28 +728,28 @@ } /* DRAM command MRS */ - MCHBAR32(0x4220 + 0x400 * channel) = 0x0f000; - MCHBAR32(0x4230 + 0x400 * channel) = 0x41001; - MCHBAR32(0x4200 + 0x400 * channel) = + MCHBAR32(IOSAV_0_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x0f000; + MCHBAR32(IOSAV_0_SUBSEQ_CTL_C0 + 0x400 * channel) = 0x41001; + MCHBAR32(IOSAV_0_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = (slotrank << 24) | (reg << 20) | val | 0x60000; - MCHBAR32(0x4210 + 0x400 * channel) = 0; + MCHBAR32(IOSAV_0_ADDR_UPD_C0 + 0x400 * channel) = 0; /* DRAM command MRS */ - MCHBAR32(0x4224 + 0x400 * channel) = 0x1f000; - MCHBAR32(0x4234 + 0x400 * channel) = 0x41001; - MCHBAR32(0x4204 + 0x400 * channel) = + MCHBAR32(IOSAV_1_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f000; + MCHBAR32(IOSAV_1_SUBSEQ_CTL_C0 + 0x400 * channel) = 0x41001; + MCHBAR32(IOSAV_1_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = (slotrank << 24) | (reg << 20) | val | 0x60000; - MCHBAR32(0x4214 + 0x400 * channel) = 0; + MCHBAR32(IOSAV_1_ADDR_UPD_C0 + 0x400 * channel) = 0; /* DRAM command MRS */ - MCHBAR32(0x4228 + 0x400 * channel) = 0x0f000; - MCHBAR32(0x4238 + 0x400 * channel) = 0x1001 | (ctrl->tMOD << 16); - MCHBAR32(0x4208 + 0x400 * channel) = + MCHBAR32(IOSAV_2_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x0f000; + MCHBAR32(IOSAV_2_SUBSEQ_CTL_C0 + 0x400 * channel) = 0x1001 | (ctrl->tMOD << 16); + MCHBAR32(IOSAV_2_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = (slotrank << 24) | (reg << 20) | val | 0x60000; - MCHBAR32(0x4218 + 0x400 * channel) = 0; + MCHBAR32(IOSAV_2_ADDR_UPD_C0 + 0x400 * channel) = 0; // execute command queue - MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(3); + MCHBAR32(IOSAV_SEQ_CTL_C0 + 0x400 * channel) = RUN_QUEUE_4284(3); } static u32 make_mr0(ramctr_timing * ctrl, u8 rank) @@ -870,19 +872,19 @@ } /* DRAM command NOP */ - MCHBAR32(0x4e20) = 0x7; - MCHBAR32(0x4e30) = 0xf1001; - MCHBAR32(0x4e00) = 0x60002; - MCHBAR32(0x4e10) = 0; + MCHBAR32(IOSAV_0_SPECIAL_COMMAND_CTL) = 0x7; + MCHBAR32(IOSAV_0_SUBSEQ_CTL) = 0xf1001; + MCHBAR32(IOSAV_0_SPECIAL_COMMAND_ADDR) = 0x60002; + MCHBAR32(IOSAV_0_ADDR_UPD) = 0; /* DRAM command ZQCL */ - MCHBAR32(0x4e24) = 0x1f003; - MCHBAR32(0x4e34) = 0x1901001; - MCHBAR32(0x4e04) = 0x60400; - MCHBAR32(0x4e14) = 0x288; + MCHBAR32(IOSAV_0_SPECIAL_COMMAND_CTL) = 0x1f003; + MCHBAR32(IOSAV_0_SUBSEQ_CTL) = 0x1901001; + MCHBAR32(IOSAV_0_SPECIAL_COMMAND_ADDR) = 0x60400; + MCHBAR32(IOSAV_0_ADDR_UPD) = 0x288; // execute command queue on all channels? Why isn't bit 0 set here? - MCHBAR32(0x4e84) = 0x40004; + MCHBAR32(IOSAV_SEQ_CTL) = 0x40004; // Drain FOR_ALL_CHANNELS { @@ -891,10 +893,10 @@ } // Refresh enable - MCHBAR32_OR(0x5030, 8); + MCHBAR32_OR(MC_INIT_STATE_G, 8); FOR_ALL_POPULATED_CHANNELS { - MCHBAR32_AND(0x4020 + 0x400 * channel, ~0x200000); + MCHBAR32_AND(SCHED_CBIT_C0 + 0x400 * channel, ~0x200000); wait_428c(channel); @@ -904,14 +906,14 @@ wait_428c(channel); /* DRAM command ZQCS */ - MCHBAR32(0x4220 + 0x400 * channel) = 0x0f003; - MCHBAR32(0x4230 + 0x400 * channel) = 0x659001; - MCHBAR32(0x4200 + 0x400 * channel) = + MCHBAR32(IOSAV_0_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x0f003; + MCHBAR32(IOSAV_0_SUBSEQ_CTL_C0 + 0x400 * channel) = 0x659001; + MCHBAR32(IOSAV_0_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = (slotrank << 24) | 0x60000; - MCHBAR32(0x4210 + 0x400 * channel) = 0x3e0; + MCHBAR32(IOSAV_0_ADDR_UPD_C0 + 0x400 * channel) = 0x3e0; // execute command queue - MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(1); + MCHBAR32(IOSAV_SEQ_CTL_C0 + 0x400 * channel) = RUN_QUEUE_4284(1); // Drain wait_428c(channel); @@ -967,7 +969,7 @@ reg32 |= (slot320c[1] & 0x7f) << 18; reg32 |= (full_shift & 0x3f) | ((full_shift & 0x40) << 6); - MCHBAR32(0x320c + 0x100 * channel) = reg32; + MCHBAR32(GDCRCMDPICODING_C0 + 0x100 * channel) = reg32; /* enable CLK XOVER */ reg_c14 = get_XOVER_CLK(ctrl->rankmap[channel]); @@ -985,8 +987,8 @@ reg_c18 |= ((offset_val_c14 >> 6) & 1) << slotrank; } - MCHBAR32(0xc14 + channel * 0x100) = reg_c14; - MCHBAR32(0xc18 + channel * 0x100) = reg_c18; + MCHBAR32(GDCRCKPICODE_C0 + channel * 0x100) = reg_c14; + MCHBAR32(GDCRCKLOGICDELAY_C0 + channel * 0x100) = reg_c18; reg_io_latency = MCHBAR32(SC_IO_LATENCY_C0 + 0x400 * channel); reg_io_latency &= 0xffff0000; @@ -1064,7 +1066,7 @@ timC + shift) & 0x40) << 13)); } } - MCHBAR32(0x4024 + 0x400 * channel) = reg_4024; + MCHBAR32(SC_ROUNDT_LAT_C0 + 0x400 * channel) = reg_4024; MCHBAR32(SC_IO_LATENCY_C0 + 0x400 * channel) = reg_io_latency; } @@ -1076,32 +1078,35 @@ * write MR3 MPR enable * in this mode only RD and RDA are allowed * all reads return a predefined pattern */ - MCHBAR32(0x4220 + 0x400 * channel) = 0x1f000; - MCHBAR32(0x4230 + 0x400 * channel) = (0xc01 | (ctrl->tMOD << 16)); - MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x360004; - MCHBAR32(0x4210 + 0x400 * channel) = 0; + MCHBAR32(IOSAV_0_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f000; + MCHBAR32(IOSAV_0_SUBSEQ_CTL_C0 + 0x400 * channel) = (0xc01 | (ctrl->tMOD << 16)); + MCHBAR32(IOSAV_0_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = + (slotrank << 24) | 0x360004; + MCHBAR32(IOSAV_0_ADDR_UPD_C0 + 0x400 * channel) = 0; /* DRAM command RD */ - MCHBAR32(0x4224 + 0x400 * channel) = 0x1f105; - MCHBAR32(0x4234 + 0x400 * channel) = 0x4040c01; - MCHBAR32(0x4204 + 0x400 * channel) = (slotrank << 24); - MCHBAR32(0x4214 + 0x400 * channel) = 0; + MCHBAR32(IOSAV_1_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f105; + MCHBAR32(IOSAV_1_SUBSEQ_CTL_C0 + 0x400 * channel) = 0x4040c01; + MCHBAR32(IOSAV_1_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = (slotrank << 24); + MCHBAR32(IOSAV_1_ADDR_UPD_C0 + 0x400 * channel) = 0; /* DRAM command RD */ - MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105; - MCHBAR32(0x4238 + 0x400 * channel) = 0x100f | ((ctrl->CAS + 36) << 16); - MCHBAR32(0x4208 + 0x400 * channel) = (slotrank << 24) | 0x60000; - MCHBAR32(0x4218 + 0x400 * channel) = 0; + MCHBAR32(IOSAV_2_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f105; + MCHBAR32(IOSAV_2_SUBSEQ_CTL_C0 + 0x400 * channel) = 0x100f | ((ctrl->CAS + 36) << 16); + MCHBAR32(IOSAV_2_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = + (slotrank << 24) | 0x60000; + MCHBAR32(IOSAV_2_ADDR_UPD_C0 + 0x400 * channel) = 0; /* DRAM command MRS * write MR3 MPR disable */ - MCHBAR32(0x422c + 0x400 * channel) = 0x1f000; - MCHBAR32(0x423c + 0x400 * channel) = 0xc01 | (ctrl->tMOD << 16); - MCHBAR32(0x420c + 0x400 * channel) = (slotrank << 24) | 0x360000; - MCHBAR32(0x421c + 0x400 * channel) = 0; + MCHBAR32(IOSAV_3_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f000; + MCHBAR32(IOSAV_3_SUBSEQ_CTL_C0 + 0x400 * channel) = 0xc01 | (ctrl->tMOD << 16); + MCHBAR32(IOSAV_3_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = + (slotrank << 24) | 0x360000; + MCHBAR32(IOSAV_3_ADDR_UPD_C0 + 0x400 * channel) = 0; // execute command queue - MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(4); + MCHBAR32(IOSAV_SEQ_CTL_C0 + 0x400 * channel) = RUN_QUEUE_4284(4); wait_428c(channel); } @@ -1357,15 +1362,16 @@ wait_428c(channel); /* DRAM command PREA */ - MCHBAR32(0x4220 + 0x400 * channel) = 0x1f002; - MCHBAR32(0x4230 + 0x400 * channel) = 0xc01 | (ctrl->tRP << 16); - MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x60400; - MCHBAR32(0x4210 + 0x400 * channel) = 0; + MCHBAR32(IOSAV_0_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f002; + MCHBAR32(IOSAV_0_SUBSEQ_CTL_C0 + 0x400 * channel) = 0xc01 | (ctrl->tRP << 16); + MCHBAR32(IOSAV_0_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = + (slotrank << 24) | 0x60400; + MCHBAR32(IOSAV_0_ADDR_UPD_C0 + 0x400 * channel) = 0; // execute command queue - MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(1); + MCHBAR32(IOSAV_SEQ_CTL_C0 + 0x400 * channel) = RUN_QUEUE_4284(1); - MCHBAR32(0x3400) = (slotrank << 2) | 0x8001; + MCHBAR32(GDCRTRAININGMOD) = (slotrank << 2) | 0x8001; ctrl->timings[channel][slotrank].val_4028 = 4; ctrl->timings[channel][slotrank].val_4024 = 55; @@ -1433,7 +1439,7 @@ lane, ctrl->timings[channel][slotrank].lanes[lane].timA); - MCHBAR32(0x3400) = 0; + MCHBAR32(GDCRTRAININGMOD) = 0; toggle_io_reset(); } @@ -1442,7 +1448,7 @@ program_timings(ctrl, channel); } FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - MCHBAR32(0x4080 + 0x400 * channel + 4 * lane) = 0; + MCHBAR32(IOSAV_B0_BW_MASK_C0 + 0x400 * channel + 4 * lane) = 0; } return 0; } @@ -1452,73 +1458,77 @@ int lane; FOR_ALL_LANES { - MCHBAR32(0x4340 + 0x400 * channel + 4 * lane) = 0; - MCHBAR32(0x4140 + 0x400 * channel + 4 * lane); + MCHBAR32(IOSAV_B0_ERROR_COUNT_C0 + 0x400 * channel + 4 * lane) = 0; + MCHBAR32(IOSAV_B0_BW_SERROR_C_C0 + 0x400 * channel + 4 * lane); } wait_428c(channel); /* DRAM command ACT */ - MCHBAR32(0x4220 + 0x400 * channel) = 0x1f006; - MCHBAR32(0x4230 + 0x400 * channel) = + MCHBAR32(IOSAV_0_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f006; + MCHBAR32(IOSAV_0_SUBSEQ_CTL_C0 + 0x400 * channel) = (MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD) << 10) | 4 | (ctrl->tRCD << 16); - MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | (6 << 16); - MCHBAR32(0x4210 + 0x400 * channel) = 0x244; + MCHBAR32(IOSAV_0_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = + (slotrank << 24) | (6 << 16); + MCHBAR32(IOSAV_0_ADDR_UPD_C0 + 0x400 * channel) = 0x244; /* DRAM command NOP */ - MCHBAR32(0x4224 + 0x400 * channel) = 0x1f207; - MCHBAR32(0x4234 + 0x400 * channel) = 0x8041001; - MCHBAR32(0x4204 + 0x400 * channel) = (slotrank << 24) | 8; - MCHBAR32(0x4214 + 0x400 * channel) = 0x3e0; + MCHBAR32(IOSAV_1_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f207; + MCHBAR32(IOSAV_1_SUBSEQ_CTL_C0 + 0x400 * channel) = 0x8041001; + MCHBAR32(IOSAV_1_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = (slotrank << 24) | 8; + MCHBAR32(IOSAV_1_ADDR_UPD_C0 + 0x400 * channel) = 0x3e0; /* DRAM command WR */ - MCHBAR32(0x4228 + 0x400 * channel) = 0x1f201; - MCHBAR32(0x4238 + 0x400 * channel) = 0x80411f4; - MCHBAR32(0x4208 + 0x400 * channel) = slotrank << 24; - MCHBAR32(0x4218 + 0x400 * channel) = 0x242; + MCHBAR32(IOSAV_2_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f201; + MCHBAR32(IOSAV_2_SUBSEQ_CTL_C0 + 0x400 * channel) = 0x80411f4; + MCHBAR32(IOSAV_2_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = slotrank << 24; + MCHBAR32(IOSAV_2_ADDR_UPD_C0 + 0x400 * channel) = 0x242; /* DRAM command NOP */ - MCHBAR32(0x422c + 0x400 * channel) = 0x1f207; - MCHBAR32(0x423c + 0x400 * channel) = + MCHBAR32(IOSAV_3_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f207; + MCHBAR32(IOSAV_3_SUBSEQ_CTL_C0 + 0x400 * channel) = 0x8000c01 | ((ctrl->CWL + ctrl->tWTR + 5) << 16); - MCHBAR32(0x420c + 0x400 * channel) = (slotrank << 24) | 8; - MCHBAR32(0x421c + 0x400 * channel) = 0x3e0; + MCHBAR32(IOSAV_3_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = (slotrank << 24) | 8; + MCHBAR32(IOSAV_3_ADDR_UPD_C0 + 0x400 * channel) = 0x3e0; // execute command queue - MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(4); + MCHBAR32(IOSAV_SEQ_CTL_C0 + 0x400 * channel) = RUN_QUEUE_4284(4); wait_428c(channel); /* DRAM command PREA */ - MCHBAR32(0x4220 + 0x400 * channel) = 0x1f002; - MCHBAR32(0x4230 + 0x400 * channel) = 0xc01 | (ctrl->tRP << 16); - MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x60400; - MCHBAR32(0x4210 + 0x400 * channel) = 0x240; + MCHBAR32(IOSAV_0_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f002; + MCHBAR32(IOSAV_0_SUBSEQ_CTL_C0 + 0x400 * channel) = 0xc01 | (ctrl->tRP << 16); + MCHBAR32(IOSAV_0_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = + (slotrank << 24) | 0x60400; + MCHBAR32(IOSAV_0_ADDR_UPD_C0 + 0x400 * channel) = 0x240; /* DRAM command ACT */ - MCHBAR32(0x4224 + 0x400 * channel) = 0x1f006; - MCHBAR32(0x4234 + 0x400 * channel) = + MCHBAR32(IOSAV_1_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f006; + MCHBAR32(IOSAV_1_SUBSEQ_CTL_C0 + 0x400 * channel) = (MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1) << 10) | 8 | (ctrl->CAS << 16); - MCHBAR32(0x4204 + 0x400 * channel) = (slotrank << 24) | 0x60000; - MCHBAR32(0x4214 + 0x400 * channel) = 0x244; + MCHBAR32(IOSAV_1_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = + (slotrank << 24) | 0x60000; + MCHBAR32(IOSAV_1_ADDR_UPD_C0 + 0x400 * channel) = 0x244; /* DRAM command RD */ - MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105; - MCHBAR32(0x4238 + 0x400 * channel) = + MCHBAR32(IOSAV_2_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f105; + MCHBAR32(IOSAV_2_SUBSEQ_CTL_C0 + 0x400 * channel) = 0x40011f4 | (MAX(ctrl->tRTP, 8) << 16); - MCHBAR32(0x4208 + 0x400 * channel) = (slotrank << 24); - MCHBAR32(0x4218 + 0x400 * channel) = 0x242; + MCHBAR32(IOSAV_2_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = (slotrank << 24); + MCHBAR32(IOSAV_2_ADDR_UPD_C0 + 0x400 * channel) = 0x242; /* DRAM command PREA */ - MCHBAR32(0x422c + 0x400 * channel) = 0x1f002; - MCHBAR32(0x423c + 0x400 * channel) = 0xc01 | (ctrl->tRP << 16); - MCHBAR32(0x420c + 0x400 * channel) = (slotrank << 24) | 0x60400; - MCHBAR32(0x421c + 0x400 * channel) = 0x240; + MCHBAR32(IOSAV_3_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f002; + MCHBAR32(IOSAV_3_SUBSEQ_CTL_C0 + 0x400 * channel) = 0xc01 | (ctrl->tRP << 16); + MCHBAR32(IOSAV_3_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = + (slotrank << 24) | 0x60400; + MCHBAR32(IOSAV_3_ADDR_UPD_C0 + 0x400 * channel) = 0x240; // execute command queue - MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(4); + MCHBAR32(IOSAV_SEQ_CTL_C0 + 0x400 * channel) = RUN_QUEUE_4284(4); wait_428c(channel); } @@ -1550,13 +1560,14 @@ wait_428c(channel); /* DRAM command PREA */ - MCHBAR32(0x4220 + 0x400 * channel) = 0x1f002; - MCHBAR32(0x4230 + 0x400 * channel) = 0xc01 | (ctrl->tRP << 16); - MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x60400; - MCHBAR32(0x4210 + 0x400 * channel) = 0x240; + MCHBAR32(IOSAV_0_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f002; + MCHBAR32(IOSAV_0_SUBSEQ_CTL_C0 + 0x400 * channel) = 0xc01 | (ctrl->tRP << 16); + MCHBAR32(IOSAV_0_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = + (slotrank << 24) | 0x60400; + MCHBAR32(IOSAV_0_ADDR_UPD_C0 + 0x400 * channel) = 0x240; // execute command queue - MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(1); + MCHBAR32(IOSAV_SEQ_CTL_C0 + 0x400 * channel) = RUN_QUEUE_4284(1); for (timC = 0; timC <= MAX_TIMC; timC++) { FOR_ALL_LANES ctrl->timings[channel][slotrank].lanes[lane]. @@ -1567,7 +1578,7 @@ FOR_ALL_LANES { statistics[lane][timC] = - MCHBAR32(0x4340 + 4 * lane + 0x400 * channel); + MCHBAR32(IOSAV_B0_ERROR_COUNT_C0 + 4 * lane + 0x400 * channel); } } FOR_ALL_LANES { @@ -1656,39 +1667,39 @@ * write MR3 MPR enable * in this mode only RD and RDA are allowed * all reads return a predefined pattern */ - MCHBAR32(0x4220 + 0x400 * channel) = 0x1f000; - MCHBAR32(0x4230 + 0x400 * channel) = + MCHBAR32(IOSAV_0_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f000; + MCHBAR32(IOSAV_0_SUBSEQ_CTL_C0 + 0x400 * channel) = 0xc01 | (ctrl->tMOD << 16); - MCHBAR32(0x4200 + 0x400 * channel) = + MCHBAR32(IOSAV_0_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = (slotrank << 24) | 0x360004; - MCHBAR32(0x4210 + 0x400 * channel) = 0; + MCHBAR32(IOSAV_0_ADDR_UPD_C0 + 0x400 * channel) = 0; /* DRAM command RD */ - MCHBAR32(0x4224 + 0x400 * channel) = 0x1f105; - MCHBAR32(0x4234 + 0x400 * channel) = 0x4041003; - MCHBAR32(0x4204 + 0x400 * channel) = + MCHBAR32(IOSAV_1_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f105; + MCHBAR32(IOSAV_1_SUBSEQ_CTL_C0 + 0x400 * channel) = 0x4041003; + MCHBAR32(IOSAV_1_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = (slotrank << 24) | 0; - MCHBAR32(0x4214 + 0x400 * channel) = 0; + MCHBAR32(IOSAV_1_ADDR_UPD_C0 + 0x400 * channel) = 0; /* DRAM command RD */ - MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105; - MCHBAR32(0x4238 + 0x400 * channel) = + MCHBAR32(IOSAV_2_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f105; + MCHBAR32(IOSAV_2_SUBSEQ_CTL_C0 + 0x400 * channel) = 0x1001 | ((ctrl->CAS + 8) << 16); - MCHBAR32(0x4208 + 0x400 * channel) = + MCHBAR32(IOSAV_2_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = (slotrank << 24) | 0x60000; - MCHBAR32(0x4218 + 0x400 * channel) = 0; + MCHBAR32(IOSAV_2_ADDR_UPD_C0 + 0x400 * channel) = 0; /* DRAM command MRS * write MR3 MPR disable */ - MCHBAR32(0x422c + 0x400 * channel) = 0x1f000; - MCHBAR32(0x423c + 0x400 * channel) = + MCHBAR32(IOSAV_3_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f000; + MCHBAR32(IOSAV_3_SUBSEQ_CTL_C0 + 0x400 * channel) = 0xc01 | (ctrl->tMOD << 16); - MCHBAR32(0x420c + 0x400 * channel) = + MCHBAR32(IOSAV_3_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = (slotrank << 24) | 0x360000; - MCHBAR32(0x421c + 0x400 * channel) = 0; + MCHBAR32(IOSAV_3_ADDR_UPD_C0 + 0x400 * channel) = 0; // execute command queue - MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(4); + MCHBAR32(IOSAV_SEQ_CTL_C0 + 0x400 * channel) = RUN_QUEUE_4284(4); wait_428c(channel); } @@ -1708,39 +1719,39 @@ * write MR3 MPR enable * in this mode only RD and RDA are allowed * all reads return a predefined pattern */ - MCHBAR32(0x4220 + 0x400 * channel) = 0x1f000; - MCHBAR32(0x4230 + 0x400 * channel) = + MCHBAR32(IOSAV_0_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f000; + MCHBAR32(IOSAV_0_SUBSEQ_CTL_C0 + 0x400 * channel) = 0xc01 | (ctrl->tMOD << 16); - MCHBAR32(0x4200 + 0x400 * channel) = + MCHBAR32(IOSAV_0_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = (slotrank << 24) | 0x360004; - MCHBAR32(0x4210 + 0x400 * channel) = 0; + MCHBAR32(IOSAV_0_ADDR_UPD_C0 + 0x400 * channel) = 0; /* DRAM command RD */ - MCHBAR32(0x4224 + 0x400 * channel) = 0x1f105; - MCHBAR32(0x4234 + 0x400 * channel) = 0x4041003; - MCHBAR32(0x4204 + 0x400 * channel) = + MCHBAR32(IOSAV_1_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f105; + MCHBAR32(IOSAV_1_SUBSEQ_CTL_C0 + 0x400 * channel) = 0x4041003; + MCHBAR32(IOSAV_1_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = (slotrank << 24) | 0; - MCHBAR32(0x4214 + 0x400 * channel) = 0; + MCHBAR32(IOSAV_1_ADDR_UPD_C0 + 0x400 * channel) = 0; /* DRAM command RD */ - MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105; - MCHBAR32(0x4238 + 0x400 * channel) = + MCHBAR32(IOSAV_2_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f105; + MCHBAR32(IOSAV_2_SUBSEQ_CTL_C0 + 0x400 * channel) = 0x1001 | ((ctrl->CAS + 8) << 16); - MCHBAR32(0x4208 + 0x400 * channel) = + MCHBAR32(IOSAV_2_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = (slotrank << 24) | 0x60000; - MCHBAR32(0x4218 + 0x400 * channel) = 0; + MCHBAR32(IOSAV_2_ADDR_UPD_C0 + 0x400 * channel) = 0; /* DRAM command MRS * write MR3 MPR disable */ - MCHBAR32(0x422c + 0x400 * channel) = 0x1f000; - MCHBAR32(0x423c + 0x400 * channel) = + MCHBAR32(IOSAV_3_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f000; + MCHBAR32(IOSAV_3_SUBSEQ_CTL_C0 + 0x400 * channel) = 0xc01 | (ctrl->tMOD << 16); - MCHBAR32(0x420c + 0x400 * channel) = + MCHBAR32(IOSAV_3_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = (slotrank << 24) | 0x360000; - MCHBAR32(0x421c + 0x400 * channel) = 0; + MCHBAR32(IOSAV_3_ADDR_UPD_C0 + 0x400 * channel) = 0; // execute command queue - MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(4); + MCHBAR32(IOSAV_SEQ_CTL_C0 + 0x400 * channel) = RUN_QUEUE_4284(4); wait_428c(channel); } @@ -1755,21 +1766,21 @@ wait_428c(channel); /* DRAM command NOP */ - MCHBAR32(0x4220 + 0x400 * channel) = 0x1f207; - MCHBAR32(0x4230 + 0x400 * channel) = + MCHBAR32(IOSAV_0_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f207; + MCHBAR32(IOSAV_0_SUBSEQ_CTL_C0 + 0x400 * channel) = 0x8000c01 | ((ctrl->CWL + ctrl->tWLO) << 16); - MCHBAR32(0x4200 + 0x400 * channel) = 8 | (slotrank << 24); - MCHBAR32(0x4210 + 0x400 * channel) = 0; + MCHBAR32(IOSAV_0_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = 8 | (slotrank << 24); + MCHBAR32(IOSAV_0_ADDR_UPD_C0 + 0x400 * channel) = 0; /* DRAM command NOP */ - MCHBAR32(0x4224 + 0x400 * channel) = 0x1f107; - MCHBAR32(0x4234 + 0x400 * channel) = + MCHBAR32(IOSAV_1_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f107; + MCHBAR32(IOSAV_1_SUBSEQ_CTL_C0 + 0x400 * channel) = 0x4000c01 | ((ctrl->CAS + 38) << 16); - MCHBAR32(0x4204 + 0x400 * channel) = (slotrank << 24) | 4; - MCHBAR32(0x4214 + 0x400 * channel) = 0; + MCHBAR32(IOSAV_1_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = (slotrank << 24) | 4; + MCHBAR32(IOSAV_1_ADDR_UPD_C0 + 0x400 * channel) = 0; // execute command queue - MCHBAR32(0x400 * channel + 0x4284) = RUN_QUEUE_4284(2); + MCHBAR32(0x400 * channel + IOSAV_SEQ_CTL_C0) = RUN_QUEUE_4284(2); wait_428c(channel); @@ -1784,7 +1795,7 @@ int statistics[NUM_LANES][128]; int lane; - MCHBAR32(0x3400) = 0x108052 | (slotrank << 2); + MCHBAR32(GDCRTRAININGMOD) = 0x108052 | (slotrank << 2); for (timB = 0; timB < 128; timB++) { FOR_ALL_LANES { @@ -1853,72 +1864,77 @@ static void adjust_high_timB(ramctr_timing * ctrl) { int channel, slotrank, lane, old; - MCHBAR32(0x3400) = 0x200; + MCHBAR32(GDCRTRAININGMOD) = 0x200; FOR_ALL_POPULATED_CHANNELS { fill_pattern1(ctrl, channel); - MCHBAR32(0x4288 + (channel << 10)) = 1; + MCHBAR32(IOSAV_DATA_CTL_C0 + (channel << 10)) = 1; } FOR_ALL_POPULATED_CHANNELS FOR_ALL_POPULATED_RANKS { - MCHBAR32(0x4288 + 0x400 * channel) = 0x10001; + MCHBAR32(IOSAV_DATA_CTL_C0 + 0x400 * channel) = 0x10001; wait_428c(channel); /* DRAM command ACT */ - MCHBAR32(0x4220 + 0x400 * channel) = 0x1f006; - MCHBAR32(0x4230 + 0x400 * channel) = 0xc01 | (ctrl->tRCD << 16); - MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x60000; - MCHBAR32(0x4210 + 0x400 * channel) = 0; + MCHBAR32(IOSAV_0_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f006; + MCHBAR32(IOSAV_0_SUBSEQ_CTL_C0 + 0x400 * channel) = 0xc01 | (ctrl->tRCD << 16); + MCHBAR32(IOSAV_0_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = + (slotrank << 24) | 0x60000; + MCHBAR32(IOSAV_0_ADDR_UPD_C0 + 0x400 * channel) = 0; /* DRAM command NOP */ - MCHBAR32(0x4224 + 0x400 * channel) = 0x1f207; - MCHBAR32(0x4234 + 0x400 * channel) = 0x8040c01; - MCHBAR32(0x4204 + 0x400 * channel) = (slotrank << 24) | 0x8; - MCHBAR32(0x4214 + 0x400 * channel) = 0x3e0; + MCHBAR32(IOSAV_1_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f207; + MCHBAR32(IOSAV_1_SUBSEQ_CTL_C0 + 0x400 * channel) = 0x8040c01; + MCHBAR32(IOSAV_1_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = + (slotrank << 24) | 0x8; + MCHBAR32(IOSAV_1_ADDR_UPD_C0 + 0x400 * channel) = 0x3e0; /* DRAM command WR */ - MCHBAR32(0x4228 + 0x400 * channel) = 0x1f201; - MCHBAR32(0x4238 + 0x400 * channel) = 0x8041003; - MCHBAR32(0x4208 + 0x400 * channel) = (slotrank << 24); - MCHBAR32(0x4218 + 0x400 * channel) = 0x3e2; + MCHBAR32(IOSAV_2_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f201; + MCHBAR32(IOSAV_2_SUBSEQ_CTL_C0 + 0x400 * channel) = 0x8041003; + MCHBAR32(IOSAV_2_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = (slotrank << 24); + MCHBAR32(IOSAV_2_ADDR_UPD_C0 + 0x400 * channel) = 0x3e2; /* DRAM command NOP */ - MCHBAR32(0x422c + 0x400 * channel) = 0x1f207; - MCHBAR32(0x423c + 0x400 * channel) = + MCHBAR32(IOSAV_3_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f207; + MCHBAR32(IOSAV_3_SUBSEQ_CTL_C0 + 0x400 * channel) = 0x8000c01 | ((ctrl->CWL + ctrl->tWTR + 5) << 16); - MCHBAR32(0x420c + 0x400 * channel) = (slotrank << 24) | 0x8; - MCHBAR32(0x421c + 0x400 * channel) = 0x3e0; + MCHBAR32(IOSAV_3_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = + (slotrank << 24) | 0x8; + MCHBAR32(IOSAV_3_ADDR_UPD_C0 + 0x400 * channel) = 0x3e0; // execute command queue - MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(4); + MCHBAR32(IOSAV_SEQ_CTL_C0 + 0x400 * channel) = RUN_QUEUE_4284(4); wait_428c(channel); /* DRAM command PREA */ - MCHBAR32(0x4220 + 0x400 * channel) = 0x1f002; - MCHBAR32(0x4230 + 0x400 * channel) = + MCHBAR32(IOSAV_0_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f002; + MCHBAR32(IOSAV_0_SUBSEQ_CTL_C0 + 0x400 * channel) = 0xc01 | ((ctrl->tRP) << 16); - MCHBAR32(0x4200 + 0x400 * channel) = + MCHBAR32(IOSAV_0_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = (slotrank << 24) | 0x60400; - MCHBAR32(0x4210 + 0x400 * channel) = 0x240; + MCHBAR32(IOSAV_0_ADDR_UPD_C0 + 0x400 * channel) = 0x240; /* DRAM command ACT */ - MCHBAR32(0x4224 + 0x400 * channel) = 0x1f006; - MCHBAR32(0x4234 + 0x400 * channel) = + MCHBAR32(IOSAV_1_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f006; + MCHBAR32(IOSAV_1_SUBSEQ_CTL_C0 + 0x400 * channel) = 0xc01 | ((ctrl->tRCD) << 16); - MCHBAR32(0x4204 + 0x400 * channel) = (slotrank << 24) | 0x60000; - MCHBAR32(0x4214 + 0x400 * channel) = 0; + MCHBAR32(IOSAV_1_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = + (slotrank << 24) | 0x60000; + MCHBAR32(IOSAV_1_ADDR_UPD_C0 + 0x400 * channel) = 0; /* DRAM command RD */ - MCHBAR32(0x4228 + 0x400 * channel) = 0x3f105; - MCHBAR32(0x4238 + 0x400 * channel) = 0x4000c01 | ((ctrl->tRP + + MCHBAR32(IOSAV_2_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x3f105; + MCHBAR32(IOSAV_2_SUBSEQ_CTL_C0 + 0x400 * channel) = 0x4000c01 | ((ctrl->tRP + ctrl->timings[channel][slotrank].val_4024 + ctrl->timings[channel][slotrank].val_4028) << 16); - MCHBAR32(0x4208 + 0x400 * channel) = (slotrank << 24) | 0x60008; - MCHBAR32(0x4218 + 0x400 * channel) = 0; + MCHBAR32(IOSAV_2_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = + (slotrank << 24) | 0x60008; + MCHBAR32(IOSAV_2_ADDR_UPD_C0 + 0x400 * channel) = 0; // execute command queue - MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(3); + MCHBAR32(IOSAV_SEQ_CTL_C0 + 0x400 * channel) = RUN_QUEUE_4284(3); wait_428c(channel); FOR_ALL_LANES { @@ -1937,7 +1953,7 @@ timB); } } - MCHBAR32(0x3400) = 0; + MCHBAR32(GDCRTRAININGMOD) = 0; } static void write_op(ramctr_timing * ctrl, int channel) @@ -1950,13 +1966,14 @@ slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; /* DRAM command ACT */ - MCHBAR32(0x4220 + 0x400 * channel) = 0x0f003; - MCHBAR32(0x4230 + 0x400 * channel) = 0x41001; - MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x60000; - MCHBAR32(0x4210 + 0x400 * channel) = 0x3e0; + MCHBAR32(IOSAV_0_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x0f003; + MCHBAR32(IOSAV_0_SUBSEQ_CTL_C0 + 0x400 * channel) = 0x41001; + MCHBAR32(IOSAV_0_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = + (slotrank << 24) | 0x60000; + MCHBAR32(IOSAV_0_ADDR_UPD_C0 + 0x400 * channel) = 0x3e0; // execute command queue - MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(1); + MCHBAR32(IOSAV_SEQ_CTL_C0 + 0x400 * channel) = RUN_QUEUE_4284(1); wait_428c(channel); } @@ -1979,15 +1996,15 @@ int err; FOR_ALL_POPULATED_CHANNELS - MCHBAR32_OR(0x4008 + 0x400 * channel, 0x8000000); + MCHBAR32_OR(TC_RWP_C0 + 0x400 * channel, 0x8000000); FOR_ALL_POPULATED_CHANNELS { write_op(ctrl, channel); - MCHBAR32_OR(0x4020 + 0x400 * channel, 0x200000); + MCHBAR32_OR(SCHED_CBIT_C0 + 0x400 * channel, 0x200000); } /* refresh disable */ - MCHBAR32_AND(0x5030, ~8); + MCHBAR32_AND(MC_INIT_STATE_G, ~8); FOR_ALL_POPULATED_CHANNELS { write_op(ctrl, channel); } @@ -2000,7 +2017,7 @@ write_mrreg(ctrl, channel, slotrank, 1, make_mr1(ctrl, slotrank, channel) | 0x1080); - MCHBAR32(0x3400) = 0x108052; + MCHBAR32(GDCRTRAININGMOD) = 0x108052; toggle_io_reset(); @@ -2016,27 +2033,27 @@ write_mrreg(ctrl, channel, slotrank, 1, make_mr1(ctrl, slotrank, channel)); - MCHBAR32(0x3400) = 0; + MCHBAR32(GDCRTRAININGMOD) = 0; FOR_ALL_POPULATED_CHANNELS wait_428c(channel); /* refresh enable */ - MCHBAR32_OR(0x5030, 8); + MCHBAR32_OR(MC_INIT_STATE_G, 8); FOR_ALL_POPULATED_CHANNELS { - MCHBAR32_AND(0x4020 + 0x400 * channel, ~0x00200000); - MCHBAR32(0x428c + 0x400 * channel); + MCHBAR32_AND(SCHED_CBIT_C0 + 0x400 * channel, ~0x00200000); + MCHBAR32(IOSAV_STATUS_C0 + 0x400 * channel); wait_428c(channel); /* DRAM command ZQCS */ - MCHBAR32(0x4220 + 0x400 * channel) = 0x0f003; - MCHBAR32(0x4230 + 0x400 * channel) = 0x659001; - MCHBAR32(0x4200 + 0x400 * channel) = 0x60000; - MCHBAR32(0x4210 + 0x400 * channel) = 0x3e0; + MCHBAR32(IOSAV_0_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x0f003; + MCHBAR32(IOSAV_0_SUBSEQ_CTL_C0 + 0x400 * channel) = 0x659001; + MCHBAR32(IOSAV_0_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = 0x60000; + MCHBAR32(IOSAV_0_ADDR_UPD_C0 + 0x400 * channel) = 0x3e0; // execute command queue - MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(1); + MCHBAR32(IOSAV_SEQ_CTL_C0 + 0x400 * channel) = RUN_QUEUE_4284(1); wait_428c(channel); } @@ -2048,12 +2065,12 @@ printram("CPF\n"); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - MCHBAR32_AND(0x4080 + 0x400 * channel + 4 * lane, 0); + MCHBAR32_AND(IOSAV_B0_BW_MASK_C0 + 0x400 * channel + 4 * lane, 0); } FOR_ALL_POPULATED_CHANNELS { fill_pattern0(ctrl, channel, 0xaaaaaaaa, 0x55555555); - MCHBAR32(0x4288 + (channel << 10)) = 0; + MCHBAR32(IOSAV_DATA_CTL_C0 + (channel << 10)) = 0; } FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { @@ -2072,7 +2089,7 @@ program_timings(ctrl, channel); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - MCHBAR32_AND(0x4080 + 0x400 * channel + 4 * lane, 0); + MCHBAR32_AND(IOSAV_B0_BW_MASK_C0 + 0x400 * channel + 4 * lane, 0); } return 0; } @@ -2092,49 +2109,51 @@ } program_timings(ctrl, channel); FOR_ALL_LANES { - MCHBAR32(4 * lane + 0x4f40) = 0; + MCHBAR32(4 * lane + IOSAV_B0_ERROR_COUNT) = 0; } - MCHBAR32(0x4288 + 0x400 * channel) = 0x1f; + MCHBAR32(IOSAV_DATA_CTL_C0 + 0x400 * channel) = 0x1f; wait_428c(channel); /* DRAM command ACT */ - MCHBAR32(0x4220 + 0x400 * channel) = 0x1f006; - MCHBAR32(0x4230 + 0x400 * channel) = + MCHBAR32(IOSAV_0_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f006; + MCHBAR32(IOSAV_0_SUBSEQ_CTL_C0 + 0x400 * channel) = ((MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1)) << 10) | 8 | (ctrl->tRCD << 16); - MCHBAR32(0x4200 + 0x400 * channel) = + MCHBAR32(IOSAV_0_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = (slotrank << 24) | ctr | 0x60000; - MCHBAR32(0x4210 + 0x400 * channel) = 0x244; + MCHBAR32(IOSAV_0_ADDR_UPD_C0 + 0x400 * channel) = 0x244; /* DRAM command WR */ - MCHBAR32(0x4224 + 0x400 * channel) = 0x1f201; - MCHBAR32(0x4234 + 0x400 * channel) = + MCHBAR32(IOSAV_1_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f201; + MCHBAR32(IOSAV_1_SUBSEQ_CTL_C0 + 0x400 * channel) = 0x8001020 | ((ctrl->CWL + ctrl->tWTR + 8) << 16); - MCHBAR32(0x4204 + 0x400 * channel) = (slotrank << 24); - MCHBAR32(0x4244 + 0x400 * channel) = 0x389abcd; - MCHBAR32(0x4214 + 0x400 * channel) = 0x20e42; + MCHBAR32(IOSAV_1_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = (slotrank << 24); + MCHBAR32(IOSAV_1_ADDRESS_LFSR_C0 + 0x400 * channel) = 0x389abcd; + MCHBAR32(IOSAV_1_ADDR_UPD_C0 + 0x400 * channel) = 0x20e42; /* DRAM command RD */ - MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105; - MCHBAR32(0x4238 + 0x400 * channel) = + MCHBAR32(IOSAV_2_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f105; + MCHBAR32(IOSAV_2_SUBSEQ_CTL_C0 + 0x400 * channel) = 0x4001020 | (MAX(ctrl->tRTP, 8) << 16); - MCHBAR32(0x4208 + 0x400 * channel) = (slotrank << 24); - MCHBAR32(0x4248 + 0x400 * channel) = 0x389abcd; - MCHBAR32(0x4218 + 0x400 * channel) = 0x20e42; + MCHBAR32(IOSAV_2_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = (slotrank << 24); + MCHBAR32(IOSAV_2_ADDRESS_LFSR_C0 + 0x400 * channel) = 0x389abcd; + MCHBAR32(IOSAV_2_ADDR_UPD_C0 + 0x400 * channel) = 0x20e42; /* DRAM command PRE */ - MCHBAR32(0x422c + 0x400 * channel) = 0x1f002; - MCHBAR32(0x423c + 0x400 * channel) = 0xf1001; - MCHBAR32(0x420c + 0x400 * channel) = (slotrank << 24) | 0x60400; - MCHBAR32(0x421c + 0x400 * channel) = 0x240; + MCHBAR32(IOSAV_3_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f002; + MCHBAR32(IOSAV_3_SUBSEQ_CTL_C0 + 0x400 * channel) = 0xf1001; + MCHBAR32(IOSAV_3_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = + (slotrank << 24) | 0x60400; + MCHBAR32(IOSAV_3_ADDR_UPD_C0 + 0x400 * channel) = 0x240; // execute command queue - MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(4); + MCHBAR32(IOSAV_SEQ_CTL_C0 + 0x400 * channel) = RUN_QUEUE_4284(4); wait_428c(channel); FOR_ALL_LANES { - u32 r32 = MCHBAR32(0x4340 + 4 * lane + 0x400 * channel); + u32 r32 = + MCHBAR32(IOSAV_B0_ERROR_COUNT_C0 + 4 * lane + 0x400 * channel); if (r32 == 0) lanes_ok |= 1 << lane; @@ -2192,20 +2211,21 @@ slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; /* DRAM command ZQCS */ - MCHBAR32(0x4220 + 0x400 * channel) = 0x0f003; - MCHBAR32(0x4230 + 0x400 * channel) = 0x41001; - MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x60000; - MCHBAR32(0x4210 + 0x400 * channel) = 0x3e0; + MCHBAR32(IOSAV_0_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x0f003; + MCHBAR32(IOSAV_0_SUBSEQ_CTL_C0 + 0x400 * channel) = 0x41001; + MCHBAR32(IOSAV_0_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = + (slotrank << 24) | 0x60000; + MCHBAR32(IOSAV_0_ADDR_UPD_C0 + 0x400 * channel) = 0x3e0; // execute command queue - MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(1); + MCHBAR32(IOSAV_SEQ_CTL_C0 + 0x400 * channel) = RUN_QUEUE_4284(1); wait_428c(channel); - MCHBAR32_OR(0x4020 + 0x400 * channel, 0x200000); + MCHBAR32_OR(SCHED_CBIT_C0 + 0x400 * channel, 0x200000); } /* refresh disable */ - MCHBAR32_AND(0x5030, ~8); + MCHBAR32_AND(MC_INIT_STATE_G, ~8); FOR_ALL_POPULATED_CHANNELS { wait_428c(channel); @@ -2213,13 +2233,14 @@ slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; /* DRAM command ZQCS */ - MCHBAR32(0x4220 + 0x400 * channel) = 0x0f003; - MCHBAR32(0x4230 + 0x400 * channel) = 0x41001; - MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x60000; - MCHBAR32(0x4210 + 0x400 * channel) = 0x3e0; + MCHBAR32(IOSAV_0_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x0f003; + MCHBAR32(IOSAV_0_SUBSEQ_CTL_C0 + 0x400 * channel) = 0x41001; + MCHBAR32(IOSAV_0_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = + (slotrank << 24) | 0x60000; + MCHBAR32(IOSAV_0_ADDR_UPD_C0 + 0x400 * channel) = 0x3e0; // execute command queue - MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(1); + MCHBAR32(IOSAV_SEQ_CTL_C0 + 0x400 * channel) = RUN_QUEUE_4284(1); wait_428c(channel); } @@ -2251,7 +2272,7 @@ ctrl->cmd_stretch[channel] = cmd_stretch; - MCHBAR32(0x4004 + 0x400 * channel) = + MCHBAR32(TC_RAP_C0 + 0x400 * channel) = ctrl->tRRD | (ctrl->tRTP << 4) | (ctrl->tCKE << 8) @@ -2307,7 +2328,7 @@ FOR_ALL_POPULATED_CHANNELS { fill_pattern5(ctrl, channel, 0); - MCHBAR32(0x4288 + 0x400 * channel) = 0x1f; + MCHBAR32(IOSAV_DATA_CTL_C0 + 0x400 * channel) = 0x1f; } FOR_ALL_POPULATED_CHANNELS { @@ -2371,8 +2392,8 @@ program_timings(ctrl, channel); FOR_ALL_LANES { - MCHBAR32(0x4340 + 0x400 * channel + 4 * lane) = 0; - MCHBAR32(0x400 * channel + 4 * lane + 0x4140); + MCHBAR32(IOSAV_B0_ERROR_COUNT_C0 + 0x400 * channel + 4 * lane) = 0; + MCHBAR32(0x400 * channel + 4 * lane + IOSAV_B0_BW_SERROR_C_C0); } wait_428c(channel); @@ -2380,41 +2401,42 @@ * write MR3 MPR enable * in this mode only RD and RDA are allowed * all reads return a predefined pattern */ - MCHBAR32(0x4220 + 0x400 * channel) = 0x1f000; - MCHBAR32(0x4230 + 0x400 * channel) = 0xc01 | (ctrl->tMOD << 16); - MCHBAR32(0x4200 + 0x400 * channel) = + MCHBAR32(IOSAV_0_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f000; + MCHBAR32(IOSAV_0_SUBSEQ_CTL_C0 + 0x400 * channel) = 0xc01 | (ctrl->tMOD << 16); + MCHBAR32(IOSAV_0_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = (slotrank << 24) | 0x360004; - MCHBAR32(0x4210 + 0x400 * channel) = 0; + MCHBAR32(IOSAV_0_ADDR_UPD_C0 + 0x400 * channel) = 0; /* DRAM command RD */ - MCHBAR32(0x4224 + 0x400 * channel) = 0x1f105; - MCHBAR32(0x4234 + 0x400 * channel) = 0x40411f4; - MCHBAR32(0x4204 + 0x400 * channel) = slotrank << 24; - MCHBAR32(0x4214 + 0x400 * channel) = 0; + MCHBAR32(IOSAV_1_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f105; + MCHBAR32(IOSAV_1_SUBSEQ_CTL_C0 + 0x400 * channel) = 0x40411f4; + MCHBAR32(IOSAV_1_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = slotrank << 24; + MCHBAR32(IOSAV_1_ADDR_UPD_C0 + 0x400 * channel) = 0; /* DRAM command RD */ - MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105; - MCHBAR32(0x4238 + 0x400 * channel) = + MCHBAR32(IOSAV_2_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f105; + MCHBAR32(IOSAV_2_SUBSEQ_CTL_C0 + 0x400 * channel) = 0x1001 | ((ctrl->CAS + 8) << 16); - MCHBAR32(0x4208 + 0x400 * channel) = (slotrank << 24) | 0x60000; - MCHBAR32(0x4218 + 0x400 * channel) = 0; + MCHBAR32(IOSAV_2_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = + (slotrank << 24) | 0x60000; + MCHBAR32(IOSAV_2_ADDR_UPD_C0 + 0x400 * channel) = 0; /* DRAM command MRS * MR3 disable MPR */ - MCHBAR32(0x422c + 0x400 * channel) = 0x1f000; - MCHBAR32(0x423c + 0x400 * channel) = 0xc01 | (ctrl->tMOD << 16); - MCHBAR32(0x420c + 0x400 * channel) = + MCHBAR32(IOSAV_3_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f000; + MCHBAR32(IOSAV_3_SUBSEQ_CTL_C0 + 0x400 * channel) = 0xc01 | (ctrl->tMOD << 16); + MCHBAR32(IOSAV_3_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = (slotrank << 24) | 0x360000; - MCHBAR32(0x421c + 0x400 * channel) = 0; + MCHBAR32(IOSAV_3_ADDR_UPD_C0 + 0x400 * channel) = 0; // execute command queue - MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(4); + MCHBAR32(IOSAV_SEQ_CTL_C0 + 0x400 * channel) = RUN_QUEUE_4284(4); wait_428c(channel); FOR_ALL_LANES { statistics[lane][edge] = - MCHBAR32(0x4340 + 0x400 * channel + lane * 4); + MCHBAR32(IOSAV_B0_ERROR_COUNT_C0 + 0x400 * channel + lane * 4); } } FOR_ALL_LANES { @@ -2439,19 +2461,19 @@ int channel, slotrank, lane; int err; - MCHBAR32(0x3400) = 0; + MCHBAR32(GDCRTRAININGMOD) = 0; toggle_io_reset(); FOR_ALL_POPULATED_CHANNELS FOR_ALL_LANES { - MCHBAR32(4 * lane + 0x400 * channel + 0x4080) = 0; + MCHBAR32(4 * lane + 0x400 * channel + IOSAV_B0_BW_MASK_C0) = 0; } FOR_ALL_POPULATED_CHANNELS { fill_pattern0(ctrl, channel, 0, 0); - MCHBAR32(0x4288 + (channel << 10)) = 0; + MCHBAR32(IOSAV_DATA_CTL_C0 + (channel << 10)) = 0; FOR_ALL_LANES { - MCHBAR32(0x400 * channel + lane * 4 + 0x4140); + MCHBAR32(0x400 * channel + lane * 4 + IOSAV_B0_BW_SERROR_C_C0); } FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { @@ -2471,39 +2493,39 @@ * write MR3 MPR enable * in this mode only RD and RDA are allowed * all reads return a predefined pattern */ - MCHBAR32(0x4220 + 0x400 * channel) = 0x1f000; - MCHBAR32(0x4230 + 0x400 * channel) = + MCHBAR32(IOSAV_0_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f000; + MCHBAR32(IOSAV_0_SUBSEQ_CTL_C0 + 0x400 * channel) = 0xc01 | (ctrl->tMOD << 16); - MCHBAR32(0x4200 + 0x400 * channel) = + MCHBAR32(IOSAV_0_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = (slotrank << 24) | 0x360004; - MCHBAR32(0x4210 + 0x400 * channel) = 0; + MCHBAR32(IOSAV_0_ADDR_UPD_C0 + 0x400 * channel) = 0; /* DRAM command RD */ - MCHBAR32(0x4224 + 0x400 * channel) = 0x1f105; - MCHBAR32(0x4234 + 0x400 * channel) = 0x4041003; - MCHBAR32(0x4204 + 0x400 * channel) = + MCHBAR32(IOSAV_1_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f105; + MCHBAR32(IOSAV_1_SUBSEQ_CTL_C0 + 0x400 * channel) = 0x4041003; + MCHBAR32(IOSAV_1_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = (slotrank << 24) | 0; - MCHBAR32(0x4214 + 0x400 * channel) = 0; + MCHBAR32(IOSAV_1_ADDR_UPD_C0 + 0x400 * channel) = 0; /* DRAM command RD */ - MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105; - MCHBAR32(0x4238 + 0x400 * channel) = + MCHBAR32(IOSAV_2_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f105; + MCHBAR32(IOSAV_2_SUBSEQ_CTL_C0 + 0x400 * channel) = 0x1001 | ((ctrl->CAS + 8) << 16); - MCHBAR32(0x4208 + 0x400 * channel) = + MCHBAR32(IOSAV_2_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = (slotrank << 24) | 0x60000; - MCHBAR32(0x4218 + 0x400 * channel) = 0; + MCHBAR32(IOSAV_2_ADDR_UPD_C0 + 0x400 * channel) = 0; /* DRAM command MRS * MR3 disable MPR */ - MCHBAR32(0x422c + 0x400 * channel) = 0x1f000; - MCHBAR32(0x423c + 0x400 * channel) = + MCHBAR32(IOSAV_3_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f000; + MCHBAR32(IOSAV_3_SUBSEQ_CTL_C0 + 0x400 * channel) = 0xc01 | (ctrl->tMOD << 16); - MCHBAR32(0x420c + 0x400 * channel) = + MCHBAR32(IOSAV_3_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = (slotrank << 24) | 0x360000; - MCHBAR32(0x421c + 0x400 * channel) = 0; + MCHBAR32(IOSAV_3_ADDR_UPD_C0 + 0x400 * channel) = 0; // execute command queue - MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(4); + MCHBAR32(IOSAV_SEQ_CTL_C0 + 0x400 * channel) = RUN_QUEUE_4284(4); wait_428c(channel); } @@ -2527,39 +2549,39 @@ * write MR3 MPR enable * in this mode only RD and RDA are allowed * all reads return a predefined pattern */ - MCHBAR32(0x4220 + 0x400 * channel) = 0x1f000; - MCHBAR32(0x4230 + 0x400 * channel) = + MCHBAR32(IOSAV_0_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f000; + MCHBAR32(IOSAV_0_SUBSEQ_CTL_C0 + 0x400 * channel) = 0xc01 | (ctrl->tMOD << 16); - MCHBAR32(0x4200 + 0x400 * channel) = + MCHBAR32(IOSAV_0_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = (slotrank << 24) | 0x360004; - MCHBAR32(0x4210 + 0x400 * channel) = 0; + MCHBAR32(IOSAV_0_ADDR_UPD_C0 + 0x400 * channel) = 0; /* DRAM command RD */ - MCHBAR32(0x4224 + 0x400 * channel) = 0x1f105; - MCHBAR32(0x4234 + 0x400 * channel) = 0x4041003; - MCHBAR32(0x4204 + 0x400 * channel) = + MCHBAR32(IOSAV_1_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f105; + MCHBAR32(IOSAV_1_SUBSEQ_CTL_C0 + 0x400 * channel) = 0x4041003; + MCHBAR32(IOSAV_1_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = (slotrank << 24) | 0; - MCHBAR32(0x4214 + 0x400 * channel) = 0; + MCHBAR32(IOSAV_1_ADDR_UPD_C0 + 0x400 * channel) = 0; /* DRAM command RD */ - MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105; - MCHBAR32(0x4238 + 0x400 * channel) = + MCHBAR32(IOSAV_2_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f105; + MCHBAR32(IOSAV_2_SUBSEQ_CTL_C0 + 0x400 * channel) = 0x1001 | ((ctrl->CAS + 8) << 16); - MCHBAR32(0x4208 + 0x400 * channel) = + MCHBAR32(IOSAV_2_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = (slotrank << 24) | 0x60000; - MCHBAR32(0x4218 + 0x400 * channel) = 0; + MCHBAR32(IOSAV_2_ADDR_UPD_C0 + 0x400 * channel) = 0; /* DRAM command MRS * MR3 disable MPR */ - MCHBAR32(0x422c + 0x400 * channel) = 0x1f000; - MCHBAR32(0x423c + 0x400 * channel) = + MCHBAR32(IOSAV_3_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f000; + MCHBAR32(IOSAV_3_SUBSEQ_CTL_C0 + 0x400 * channel) = 0xc01 | (ctrl->tMOD << 16); - MCHBAR32(0x420c + 0x400 * channel) = + MCHBAR32(IOSAV_3_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = (slotrank << 24) | 0x360000; - MCHBAR32(0x421c + 0x400 * channel) = 0; + MCHBAR32(IOSAV_3_ADDR_UPD_C0 + 0x400 * channel) = 0; // execute command queue - MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(4); + MCHBAR32(IOSAV_SEQ_CTL_C0 + 0x400 * channel) = RUN_QUEUE_4284(4); wait_428c(channel); } @@ -2567,18 +2589,18 @@ /* XXX: check any measured value ? */ FOR_ALL_LANES { - MCHBAR32(0x4080 + 0x400 * channel + lane * 4) = - ~MCHBAR32(0x4040 + 0x400 * channel + lane * 4) + MCHBAR32(IOSAV_B0_BW_MASK_C0 + 0x400 * channel + lane * 4) = + ~MCHBAR32(IOSAV_B0_BW_SERROR_C0 + 0x400 * channel + lane * 4) & 0xff; } fill_pattern0(ctrl, channel, 0, 0xffffffff); - MCHBAR32(0x4288 + (channel << 10)) = 0; + MCHBAR32(IOSAV_DATA_CTL_C0 + (channel << 10)) = 0; } /* FIXME: under some conditions (older chipsets?) vendor BIOS sets both edges to the same value. */ - MCHBAR32(0x4eb0) = 0x300; - printram("discover falling edges:\n[%x] = %x\n", 0x4eb0, 0x300); + MCHBAR32(IOSAV_DC_MASK) = 0x300; + printram("discover falling edges:\n[%x] = %x\n", IOSAV_DC_MASK, 0x300); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { err = discover_edges_real(ctrl, channel, slotrank, @@ -2587,8 +2609,8 @@ return err; } - MCHBAR32(0x4eb0) = 0x200; - printram("discover rising edges:\n[%x] = %x\n", 0x4eb0, 0x200); + MCHBAR32(IOSAV_DC_MASK) = 0x200; + printram("discover rising edges:\n[%x] = %x\n", IOSAV_DC_MASK, 0x200); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { err = discover_edges_real(ctrl, channel, slotrank, @@ -2597,7 +2619,7 @@ return err; } - MCHBAR32(0x4eb0) = 0; + MCHBAR32(IOSAV_DC_MASK) = 0; FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { ctrl->timings[channel][slotrank].lanes[lane].falling = @@ -2611,7 +2633,7 @@ } FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - MCHBAR32(0x4080 + 0x400 * channel + 4 * lane) = 0; + MCHBAR32(IOSAV_B0_BW_MASK_C0 + 0x400 * channel + 4 * lane) = 0; } return 0; } @@ -2634,12 +2656,12 @@ } for (i = 0; i < 3; i++) { - MCHBAR32(0x3000 + 0x100 * channel) = reg3000b24[i] << 24; + MCHBAR32(GDCRTRAININGMOD_C0 + 0x100 * channel) = reg3000b24[i] << 24; printram("[%x] = 0x%08x\n", - 0x3000 + 0x100 * channel, reg3000b24[i] << 24); + GDCRTRAININGMOD_C0 + 0x100 * channel, reg3000b24[i] << 24); for (pat = 0; pat < NUM_PATTERNS; pat++) { fill_pattern5(ctrl, channel, pat); - MCHBAR32(0x4288 + 0x400 * channel) = 0x1f; + MCHBAR32(IOSAV_DATA_CTL_C0 + 0x400 * channel) = 0x1f; printram("using pattern %d\n", pat); for (edge = 0; edge <= MAX_EDGE_TIMING; edge++) { FOR_ALL_LANES { @@ -2651,57 +2673,62 @@ program_timings(ctrl, channel); FOR_ALL_LANES { - MCHBAR32(0x4340 + 0x400 * channel + + MCHBAR32(IOSAV_B0_ERROR_COUNT_C0 + 0x400 * channel + 4 * lane) = 0; MCHBAR32(0x400 * channel + - 4 * lane + 0x4140); + 4 * lane + IOSAV_B0_BW_SERROR_C_C0); } wait_428c(channel); /* DRAM command ACT */ - MCHBAR32(0x4220 + 0x400 * channel) = 0x1f006; - MCHBAR32(0x4230 + 0x400 * channel) = + MCHBAR32(IOSAV_0_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = + 0x1f006; + MCHBAR32(IOSAV_0_SUBSEQ_CTL_C0 + 0x400 * channel) = 0x4 | (ctrl->tRCD << 16) | (MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1) << 10); - MCHBAR32(0x4200 + 0x400 * channel) = + MCHBAR32(IOSAV_0_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = (slotrank << 24) | 0x60000; - MCHBAR32(0x4210 + 0x400 * channel) = 0x240; + MCHBAR32(IOSAV_0_ADDR_UPD_C0 + 0x400 * channel) = 0x240; /* DRAM command WR */ - MCHBAR32(0x4224 + 0x400 * channel) = 0x1f201; - MCHBAR32(0x4234 + 0x400 * channel) = 0x8005020 | + MCHBAR32(IOSAV_1_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = + 0x1f201; + MCHBAR32(IOSAV_1_SUBSEQ_CTL_C0 + 0x400 * channel) = 0x8005020 | ((ctrl->tWTR + ctrl->CWL + 8) << 16); - MCHBAR32(0x4204 + 0x400 * channel) = + MCHBAR32(IOSAV_1_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = slotrank << 24; - MCHBAR32(0x4214 + 0x400 * channel) = 0x242; + MCHBAR32(IOSAV_1_ADDR_UPD_C0 + 0x400 * channel) = 0x242; /* DRAM command RD */ - MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105; - MCHBAR32(0x4238 + 0x400 * channel) = + MCHBAR32(IOSAV_2_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = + 0x1f105; + MCHBAR32(IOSAV_2_SUBSEQ_CTL_C0 + 0x400 * channel) = 0x4005020 | (MAX(ctrl->tRTP, 8) << 16); - MCHBAR32(0x4208 + 0x400 * channel) = + MCHBAR32(IOSAV_2_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = slotrank << 24; - MCHBAR32(0x4218 + 0x400 * channel) = 0x242; + MCHBAR32(IOSAV_2_ADDR_UPD_C0 + 0x400 * channel) = 0x242; /* DRAM command PRE */ - MCHBAR32(0x422c + 0x400 * channel) = 0x1f002; - MCHBAR32(0x423c + 0x400 * channel) = + MCHBAR32(IOSAV_3_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = + 0x1f002; + MCHBAR32(IOSAV_3_SUBSEQ_CTL_C0 + 0x400 * channel) = 0xc01 | (ctrl->tRP << 16); - MCHBAR32(0x420c + 0x400 * channel) = + MCHBAR32(IOSAV_3_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = (slotrank << 24) | 0x60400; - MCHBAR32(0x421c + 0x400 * channel) = 0; + MCHBAR32(IOSAV_3_ADDR_UPD_C0 + 0x400 * channel) = 0; // execute command queue - MCHBAR32(0x4284 + 0x400 * channel) = + MCHBAR32(IOSAV_SEQ_CTL_C0 + 0x400 * channel) = RUN_QUEUE_4284(4); wait_428c(channel); FOR_ALL_LANES { - MCHBAR32(0x4340 + + MCHBAR32(IOSAV_B0_ERROR_COUNT_C0 + 0x400 * channel + lane * 4); } + /* FIXME: Register 0x436c does not seem to exist. */ raw_statistics[edge] = MCHBAR32(0x436c + 0x400 * channel); } @@ -2730,7 +2757,7 @@ } } - MCHBAR32(0x3000) = 0; + MCHBAR32(GDCRTRAININGMOD_C0) = 0; printram("CPA\n"); return 0; } @@ -2743,8 +2770,8 @@ int err; /* FIXME: under some conditions (older chipsets?) vendor BIOS sets both edges to the same value. */ - MCHBAR32(0x4eb0) = 0x300; - printram("discover falling edges write:\n[%x] = %x\n", 0x4eb0, 0x300); + MCHBAR32(IOSAV_DC_MASK) = 0x300; + printram("discover falling edges write:\n[%x] = %x\n", IOSAV_DC_MASK, 0x300); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { err = discover_edges_write_real(ctrl, channel, slotrank, @@ -2753,8 +2780,8 @@ return err; } - MCHBAR32(0x4eb0) = 0x200; - printram("discover rising edges write:\n[%x] = %x\n", 0x4eb0, 0x200); + MCHBAR32(IOSAV_DC_MASK) = 0x200; + printram("discover rising edges write:\n[%x] = %x\n", IOSAV_DC_MASK, 0x200); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { err = discover_edges_write_real(ctrl, channel, slotrank, @@ -2763,7 +2790,7 @@ return err; } - MCHBAR32(0x4eb0) = 0; + MCHBAR32(IOSAV_DC_MASK) = 0; FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { ctrl->timings[channel][slotrank].lanes[lane].falling = @@ -2776,7 +2803,7 @@ program_timings(ctrl, channel); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - MCHBAR32(0x4080 + 0x400 * channel + 4 * lane) = 0; + MCHBAR32(IOSAV_B0_BW_MASK_C0 + 0x400 * channel + 4 * lane) = 0; } return 0; } @@ -2785,36 +2812,37 @@ { wait_428c(channel); /* DRAM command ACT */ - MCHBAR32(0x4220 + 0x400 * channel) = 0x1f006; - MCHBAR32(0x4230 + 0x400 * channel) = + MCHBAR32(IOSAV_0_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f006; + MCHBAR32(IOSAV_0_SUBSEQ_CTL_C0 + 0x400 * channel) = (MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD) << 10) | (ctrl->tRCD << 16) | 4; - MCHBAR32(0x4200 + 0x400 * channel) = + MCHBAR32(IOSAV_0_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = (slotrank << 24) | 0x60000; - MCHBAR32(0x4210 + 0x400 * channel) = 0x244; + MCHBAR32(IOSAV_0_ADDR_UPD_C0 + 0x400 * channel) = 0x244; /* DRAM command WR */ - MCHBAR32(0x4224 + 0x400 * channel) = 0x1f201; - MCHBAR32(0x4234 + 0x400 * channel) = + MCHBAR32(IOSAV_1_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f201; + MCHBAR32(IOSAV_1_SUBSEQ_CTL_C0 + 0x400 * channel) = 0x80011e0 | ((ctrl->tWTR + ctrl->CWL + 8) << 16); - MCHBAR32(0x4204 + 0x400 * channel) = slotrank << 24; - MCHBAR32(0x4214 + 0x400 * channel) = 0x242; + MCHBAR32(IOSAV_1_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = slotrank << 24; + MCHBAR32(IOSAV_1_ADDR_UPD_C0 + 0x400 * channel) = 0x242; /* DRAM command RD */ - MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105; - MCHBAR32(0x4238 + 0x400 * channel) = + MCHBAR32(IOSAV_2_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f105; + MCHBAR32(IOSAV_2_SUBSEQ_CTL_C0 + 0x400 * channel) = 0x40011e0 | (MAX(ctrl->tRTP, 8) << 16); - MCHBAR32(0x4208 + 0x400 * channel) = slotrank << 24; - MCHBAR32(0x4218 + 0x400 * channel) = 0x242; + MCHBAR32(IOSAV_2_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = slotrank << 24; + MCHBAR32(IOSAV_2_ADDR_UPD_C0 + 0x400 * channel) = 0x242; /* DRAM command PRE */ - MCHBAR32(0x422c + 0x400 * channel) = 0x1f002; - MCHBAR32(0x423c + 0x400 * channel) = 0x1001 | (ctrl->tRP << 16); - MCHBAR32(0x420c + 0x400 * channel) = (slotrank << 24) | 0x60400; - MCHBAR32(0x421c + 0x400 * channel) = 0; + MCHBAR32(IOSAV_3_SPECIAL_COMMAND_CTL_C0 + 0x400 * channel) = 0x1f002; + MCHBAR32(IOSAV_3_SUBSEQ_CTL_C0 + 0x400 * channel) = 0x1001 | (ctrl->tRP << 16); + MCHBAR32(IOSAV_3_SPECIAL_COMMAND_ADDR_C0 + 0x400 * channel) = + (slotrank << 24) | 0x60400; + MCHBAR32(IOSAV_3_ADDR_UPD_C0 + 0x400 * channel) = 0; // execute command queue - MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(4); + MCHBAR32(IOSAV_SEQ_CTL_C0 + 0x400 * channel) = RUN_QUEUE_4284(4); wait_428c(channel); } @@ -2833,13 +2861,17 @@ upper[channel][slotrank][lane] = MAX_TIMC; } - MCHBAR32(0x4ea8) = 1; + /* + * Enable IOSAV_n_SPECIAL_COMMAND_ADDR optimization. + * FIXME: This must only be done on Ivy Bridge. + */ + MCHBAR32(MCMNTS_SPARE) = 1; printram("discover timC write:\n"); for (i = 0; i < 3; i++) FOR_ALL_POPULATED_CHANNELS { - MCHBAR32_AND_OR(0xe3c + (channel * 0x100), ~0x3f000000, - rege3c_b24[i] << 24); + MCHBAR32_AND_OR(GDCRCMDDEBUGMUXCFG_C0_S + (channel * 0x100), + ~0x3f000000, rege3c_b24[i] << 24); udelay(2); for (pat = 0; pat < NUM_PATTERNS; pat++) { FOR_ALL_POPULATED_RANKS { @@ -2851,7 +2883,7 @@ statistics[MAX_TIMC] = 1; fill_pattern5(ctrl, channel, pat); - MCHBAR32(0x4288 + 0x400 * channel) = + MCHBAR32(IOSAV_DATA_CTL_C0 + 0x400 * channel) = 0x1f; for (timC = 0; timC < MAX_TIMC; timC++) { FOR_ALL_LANES @@ -2860,6 +2892,7 @@ test_timC_write (ctrl, channel, slotrank); + /* FIXME: Register 0x436c may not exist. */ raw_statistics[timC] = MCHBAR32(0x436c + 0x400 * channel); } @@ -2895,11 +2928,15 @@ } FOR_ALL_CHANNELS { - MCHBAR32_AND((channel * 0x100) + 0xe3c, ~0x3f000000); + MCHBAR32_AND((channel * 0x100) + GDCRCMDDEBUGMUXCFG_C0_S, ~0x3f000000); udelay(2); } - MCHBAR32(0x4ea8) = 0; + /* + * Disable IOSAV_n_SPECIAL_COMMAND_ADDR optimization. + * FIXME: This must only be done on Ivy Bridge. + */ + MCHBAR32(MCMNTS_SPARE) = 0; printram("CPB\n"); @@ -2962,7 +2999,7 @@ slotrank = 0; FOR_ALL_POPULATED_CHANNELS - if (MCHBAR32(0x42a0 + (channel << 10)) & 0xa000) { + if (MCHBAR32(MC_INIT_STATE_C0 + (channel << 10)) & 0xa000) { printk(BIOS_EMERG, "Mini channel test failed (1): %d\n", channel); return MAKE_ERR; @@ -2970,52 +3007,52 @@ FOR_ALL_POPULATED_CHANNELS { fill_pattern0(ctrl, channel, 0x12345678, 0x98765432); - MCHBAR32(0x4288 + (channel << 10)) = 0; + MCHBAR32(IOSAV_DATA_CTL_C0 + (channel << 10)) = 0; } for (slotrank = 0; slotrank < 4; slotrank++) FOR_ALL_CHANNELS if (ctrl->rankmap[channel] & (1 << slotrank)) { FOR_ALL_LANES { - MCHBAR32(0x4f40 + 4 * lane) = 0; - MCHBAR32(0x4d40 + 4 * lane) = 0; + MCHBAR32(IOSAV_B0_ERROR_COUNT + 4 * lane) = 0; + MCHBAR32(IOSAV_B0_BW_SERROR_C + 4 * lane) = 0; } wait_428c(channel); /* DRAM command ACT */ - MCHBAR32(0x4220 + (channel << 10)) = 0x0001f006; - MCHBAR32(0x4230 + (channel << 10)) = 0x0028a004; - MCHBAR32(0x4200 + (channel << 10)) = + MCHBAR32(IOSAV_0_SPECIAL_COMMAND_CTL_C0 + (channel << 10)) = 0x0001f006; + MCHBAR32(IOSAV_0_SUBSEQ_CTL_C0 + (channel << 10)) = 0x0028a004; + MCHBAR32(IOSAV_0_SPECIAL_COMMAND_ADDR_C0 + (channel << 10)) = 0x00060000 | (slotrank << 24); - MCHBAR32(0x4210 + (channel << 10)) = 0x00000244; + MCHBAR32(IOSAV_0_ADDR_UPD_C0 + (channel << 10)) = 0x00000244; /* DRAM command WR */ - MCHBAR32(0x4224 + (channel << 10)) = 0x0001f201; - MCHBAR32(0x4234 + (channel << 10)) = 0x08281064; - MCHBAR32(0x4204 + (channel << 10)) = + MCHBAR32(IOSAV_1_SPECIAL_COMMAND_CTL_C0 + (channel << 10)) = 0x0001f201; + MCHBAR32(IOSAV_1_SUBSEQ_CTL_C0 + (channel << 10)) = 0x08281064; + MCHBAR32(IOSAV_1_SPECIAL_COMMAND_ADDR_C0 + (channel << 10)) = 0x00000000 | (slotrank << 24); - MCHBAR32(0x4214 + (channel << 10)) = 0x00000242; + MCHBAR32(IOSAV_1_ADDR_UPD_C0 + (channel << 10)) = 0x00000242; /* DRAM command RD */ - MCHBAR32(0x4228 + (channel << 10)) = 0x0001f105; - MCHBAR32(0x4238 + (channel << 10)) = 0x04281064; - MCHBAR32(0x4208 + (channel << 10)) = + MCHBAR32(IOSAV_2_SPECIAL_COMMAND_CTL_C0 + (channel << 10)) = 0x0001f105; + MCHBAR32(IOSAV_2_SUBSEQ_CTL_C0 + (channel << 10)) = 0x04281064; + MCHBAR32(IOSAV_2_SPECIAL_COMMAND_ADDR_C0 + (channel << 10)) = 0x00000000 | (slotrank << 24); - MCHBAR32(0x4218 + (channel << 10)) = 0x00000242; + MCHBAR32(IOSAV_2_ADDR_UPD_C0 + (channel << 10)) = 0x00000242; /* DRAM command PRE */ - MCHBAR32(0x422c + (channel << 10)) = 0x0001f002; - MCHBAR32(0x423c + (channel << 10)) = 0x00280c01; - MCHBAR32(0x420c + (channel << 10)) = + MCHBAR32(IOSAV_3_SPECIAL_COMMAND_CTL_C0 + (channel << 10)) = 0x0001f002; + MCHBAR32(IOSAV_3_SUBSEQ_CTL_C0 + (channel << 10)) = 0x00280c01; + MCHBAR32(IOSAV_3_SPECIAL_COMMAND_ADDR_C0 + (channel << 10)) = 0x00060400 | (slotrank << 24); - MCHBAR32(0x421c + (channel << 10)) = 0x00000240; + MCHBAR32(IOSAV_3_ADDR_UPD_C0 + (channel << 10)) = 0x00000240; // execute command queue - MCHBAR32(0x4284 + (channel << 10)) = RUN_QUEUE_4284(4); + MCHBAR32(IOSAV_SEQ_CTL_C0 + (channel << 10)) = RUN_QUEUE_4284(4); wait_428c(channel); FOR_ALL_LANES - if (MCHBAR32(0x4340 + (channel << 10) + 4 * lane)) { + if (MCHBAR32(IOSAV_B0_ERROR_COUNT_C0 + (channel << 10) + 4 * lane)) { printk(BIOS_EMERG, "Mini channel test failed (2): %d, %d, %d\n", channel, slotrank, lane); return MAKE_ERR; @@ -3035,10 +3072,10 @@ {0x00028bfa, 0x53fe4b49, 0x19ed5483} }; FOR_ALL_POPULATED_CHANNELS { - MCHBAR32(0x4020 + 0x400 * channel) &= ~0x10000000; - MCHBAR32(0x4034 + 0x400 * channel) = seeds[channel][0]; - MCHBAR32(0x403c + 0x400 * channel) = seeds[channel][1]; - MCHBAR32(0x4038 + 0x400 * channel) = seeds[channel][2]; + MCHBAR32(SCHED_CBIT_C0 + 0x400 * channel) &= ~0x10000000; + MCHBAR32(SCRAMBLING_SEED_1_C0 + 0x400 * channel) = seeds[channel][0]; + MCHBAR32(SCRAMBLING_SEED_2_HIGH_C0 + 0x400 * channel) = seeds[channel][1]; + MCHBAR32(SCRAMBLING_SEED_2_LOW_C0 + 0x400 * channel) = seeds[channel][2]; } } @@ -3048,9 +3085,9 @@ cpu = cpu_get_cpuid(); if (IS_SANDY_CPU(cpu) && (IS_SANDY_CPU_D0(cpu) || IS_SANDY_CPU_D1(cpu))) { - MCHBAR32(0x4f8c) = 0x141D1519; + MCHBAR32(SC_WDBWM) = 0x141D1519; } else { - MCHBAR32(0x4f8c) = 0x551D1519; + MCHBAR32(SC_WDBWM) = 0x551D1519; } } @@ -3060,7 +3097,7 @@ FOR_ALL_POPULATED_CHANNELS { // Always drive command bus - MCHBAR32_OR(0x4004 + 0x400 * channel, 0x20000000); + MCHBAR32_OR(TC_RAP_C0 + 0x400 * channel, 0x20000000); } udelay(1); @@ -3096,7 +3133,7 @@ dram_odt_stretch(ctrl, channel); - MCHBAR32(0x4008 + (channel << 10)) = + MCHBAR32(TC_RWP_C0 + (channel << 10)) = 0x0a000000 | (b20 << 20) | ((ctrl->ref_card_offset[channel] + 2) << 16) | b4_8_12; } @@ -3106,9 +3143,9 @@ { int channel; FOR_ALL_POPULATED_CHANNELS { - MCHBAR32(0x42a0 + 0x400 * channel) = + MCHBAR32(MC_INIT_STATE_C0 + 0x400 * channel) = 0x00001000 | ctrl->rankmap[channel]; - MCHBAR32_AND(0x4004 + 0x400 * channel, ~0x20000000); + MCHBAR32_AND(TC_RAP_C0 + 0x400 * channel, ~0x20000000); } } @@ -3127,10 +3164,11 @@ int t3_ns; u32 r32; - MCHBAR32(0x4cd4) = 0x00000046; + /* FIXME: This register only exists on IvyBridge. */ + MCHBAR32(WMM_READ_CONFIG) = 0x00000046; FOR_ALL_CHANNELS - MCHBAR32_AND_OR(0x400c + 0x400 * channel, 0xFFFFCFFF, 0x1000); + MCHBAR32_AND_OR(TC_OTHP_C0 + 0x400 * channel, 0xFFFFCFFF, 0x1000); if (is_mobile) /* APD - DLL Off, 64 DCLKs until idle, decision per rank */ @@ -3140,26 +3178,26 @@ MCHBAR32(PM_PDWN_CONFIG) = 0x00000340; FOR_ALL_CHANNELS - MCHBAR32(0x4380 + 0x400 * channel) = 0x00000aaa; + MCHBAR32(PM_TRML_M_CONFIG_C0 + 0x400 * channel) = 0x00000aaa; - MCHBAR32(0x4f88) = 0x5f7003ff; // OK - MCHBAR32(0x5064) = 0x00073000 | ctrl->reg_5064b0; // OK + MCHBAR32(PM_BW_LIMIT_CONFIG) = 0x5f7003ff; // OK + MCHBAR32(PM_DLL_CONFIG) = 0x00073000 | ctrl->reg_5064b0; // OK FOR_ALL_CHANNELS { switch (ctrl->rankmap[channel]) { /* Unpopulated channel. */ case 0: - MCHBAR32(0x4384 + channel * 0x400) = 0; + MCHBAR32(PM_CMD_PWR_C0 + channel * 0x400) = 0; break; /* Only single-ranked dimms. */ case 1: case 4: case 5: - MCHBAR32(0x4384 + channel * 0x400) = 0x373131; + MCHBAR32(PM_CMD_PWR_C0 + channel * 0x400) = 0x373131; break; /* Dual-ranked dimms present. */ default: - MCHBAR32(0x4384 + channel * 0x400) = 0x9b6ea1; + MCHBAR32(PM_CMD_PWR_C0 + channel * 0x400) = 0x9b6ea1; break; } } @@ -3171,16 +3209,18 @@ FOR_ALL_CHANNELS MCHBAR32_AND_OR(TC_RFP_C0 + 0x400 * channel, ~0x30000, 1 << 16); - MCHBAR32_OR(0x5030, 1); - MCHBAR32_OR(0x5030, 0x80); - MCHBAR32(0x5f18) = 0xfa; + MCHBAR32_OR(MC_INIT_STATE_G, 1); + MCHBAR32_OR(MC_INIT_STATE_G, 0x80); + + /* FIXME: BANDTIMERS_SNB is only applicable to Sandy Bridge! */ + MCHBAR32(BANDTIMERS_SNB) = 0xfa; /* Find a populated channel. */ FOR_ALL_POPULATED_CHANNELS break; - t1_cycles = (MCHBAR32(0x4290 + channel * 0x400) >> 8) & 0xff; - r32 = MCHBAR32(0x5064); + t1_cycles = (MCHBAR32(TC_ZQCAL_C0 + channel * 0x400) >> 8) & 0xff; + r32 = MCHBAR32(PM_DLL_CONFIG); if (r32 & 0x20000) t1_cycles += (r32 & 0xfff); t1_cycles += MCHBAR32(channel * 0x400 + 0x42a4) & 0xfff; @@ -3188,11 +3228,13 @@ if (!(r32 & 0x20000)) t1_ns += 500; - t2_ns = 10 * ((MCHBAR32(0x5f10) >> 8) & 0xfff); - if (MCHBAR32(0x5f00) & 8) + t2_ns = 10 * ((MCHBAR32(SAPMTIMERS) >> 8) & 0xfff); + + /* FIXME: SAPMTIMERS2_IVB and BANDTIMERS_IVB only exist on Ivy Bridge! */ + if (MCHBAR32(SAPMCTL) & 8) { - t3_ns = 10 * ((MCHBAR32(0x5f20) >> 8) & 0xfff); - t3_ns += 10 * (MCHBAR32(0x5f18) & 0xff); + t3_ns = 10 * ((MCHBAR32(BANDTIMERS_IVB) >> 8) & 0xfff); + t3_ns += 10 * (MCHBAR32(SAPMTIMERS2_IVB) & 0xff); } else { @@ -3211,7 +3253,7 @@ int channel, slotrank, lane; FOR_ALL_POPULATED_CHANNELS - MCHBAR32(0x4004 + 0x400 * channel) = + MCHBAR32(TC_RAP_C0 + 0x400 * channel) = ctrl->tRRD | (ctrl->tRTP << 4) | (ctrl->tCKE << 8) @@ -3227,21 +3269,21 @@ } FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - MCHBAR32(0x4080 + 0x400 * channel + 4 * lane) = 0; + MCHBAR32(IOSAV_B0_BW_MASK_C0 + 0x400 * channel + 4 * lane) = 0; } FOR_ALL_POPULATED_CHANNELS - MCHBAR32_OR(0x4008 + 0x400 * channel, 0x8000000); + MCHBAR32_OR(TC_RWP_C0 + 0x400 * channel, 0x8000000); FOR_ALL_POPULATED_CHANNELS { udelay (1); - MCHBAR32_OR(0x4020 + 0x400 * channel, 0x200000); + MCHBAR32_OR(SCHED_CBIT_C0 + 0x400 * channel, 0x200000); } printram("CPE\n"); - MCHBAR32(0x3400) = 0; - MCHBAR32(0x4eb0) = 0; + MCHBAR32(GDCRTRAININGMOD) = 0; + MCHBAR32(IOSAV_DC_MASK) = 0; printram("CP5b\n"); @@ -3251,14 +3293,14 @@ u32 reg, addr; - while (!(MCHBAR32(0x5084) & 0x10000)); + while (!(MCHBAR32(RCOMP_TIMER) & 0x10000)); do { - reg = MCHBAR32(0x428c); + reg = MCHBAR32(IOSAV_STATUS_C0); } while ((reg & 0x14) == 0); // Set state of memory controller - MCHBAR32(0x5030) = 0x116; - MCHBAR32(0x4ea0) = 0; + MCHBAR32(MC_INIT_STATE_G) = 0x116; + MCHBAR32(MC_INIT_STATE) = 0; // Wait 500us udelay(500); @@ -3267,7 +3309,7 @@ // Set valid rank CKE reg = 0; reg = (reg & ~0xf) | ctrl->rankmap[channel]; - addr = 0x400 * channel + 0x42a0; + addr = 0x400 * channel + MC_INIT_STATE_C0; MCHBAR32(addr) = reg; // Wait 10ns for ranks to settle @@ -3285,12 +3327,17 @@ printram("CP5c\n"); - MCHBAR32(0x3000) = 0; + MCHBAR32(GDCRTRAININGMOD_C0) = 0; FOR_ALL_CHANNELS { - MCHBAR32_AND(channel * 0x100 + 0xe3c, ~0x3f000000); + MCHBAR32_AND(channel * 0x100 + GDCRCMDDEBUGMUXCFG_C0_S, ~0x3f000000); udelay(2); } - MCHBAR32(0x4ea8) = 0; + /* + * Disable IOSAV_n_SPECIAL_COMMAND_ADDR optimization. + * FIXME: This must only be done on Ivy Bridge. Moreover, this instance seems to be + * spurious, because nothing else enabled this optimization before. + */ + MCHBAR32(MCMNTS_SPARE) = 0; } diff --git a/src/northbridge/intel/sandybridge/raminit_ivy.c b/src/northbridge/intel/sandybridge/raminit_ivy.c index 5c1a58a..a8d84d5 100644 --- a/src/northbridge/intel/sandybridge/raminit_ivy.c +++ b/src/northbridge/intel/sandybridge/raminit_ivy.c @@ -590,12 +590,12 @@ // IO clock FOR_ALL_CHANNELS { - MCHBAR32(0xc00 + 0x100 * channel) = ctrl->rankmap[channel]; + MCHBAR32(GDCRCLKRANKSUSED_C0 + 0x100 * channel) = ctrl->rankmap[channel]; } // IO command FOR_ALL_CHANNELS { - MCHBAR32(0x3200 + 0x100 * channel) = ctrl->rankmap[channel]; + MCHBAR32(GDCRCTLRANKSUSED_C0 + 0x100 * channel) = ctrl->rankmap[channel]; } // IO control @@ -607,27 +607,27 @@ printram("RCOMP..."); reg = 0; while (reg == 0) { - reg = MCHBAR32(0x5084) & 0x10000; + reg = MCHBAR32(RCOMP_TIMER) & 0x10000; } printram("done\n"); // Set comp2 comp2 = get_COMP2(ctrl->tCK, ctrl->base_freq); - MCHBAR32(0x3714) = comp2; + MCHBAR32(CRCOMPOFST2) = comp2; printram("COMP2 done\n"); // Set comp1 FOR_ALL_POPULATED_CHANNELS { - reg = MCHBAR32(0x1810 + channel * 0x100); //ch0 + reg = MCHBAR32(CRCOMPOFST1_C0 + channel * 0x100); //ch0 reg = (reg & ~0xe00) | (1 << 9); //odt reg = (reg & ~0xe00000) | (1 << 21); //clk drive up reg = (reg & ~0x38000000) | (1 << 27); //ctl drive up - MCHBAR32(0x1810 + channel * 0x100) = reg; + MCHBAR32(CRCOMPOFST1_C0 + channel * 0x100) = reg; } printram("COMP1 done\n"); printram("FORCE RCOMP and wait 20us..."); - MCHBAR32(0x5f08) |= 0x100; + MCHBAR32(M_COMP) |= 0x100; udelay(20); printram("done\n"); } @@ -656,7 +656,7 @@ } /* Set version register */ - MCHBAR32(0x5034) = 0xC04EB002; + MCHBAR32(MRC_REVISION) = 0xC04EB002; /* Enable crossover */ dram_xover(ctrl); @@ -665,16 +665,16 @@ dram_timing_regs(ctrl); /* Power mode preset */ - MCHBAR32(0x4e80) = 0x5500; + MCHBAR32(PM_THML_STAT) = 0x5500; /* Set scheduler parameters */ - MCHBAR32(0x4c20) = 0x10100005; + MCHBAR32(SCHED_CBIT) = 0x10100005; /* Set CPU specific register */ set_4f8c(); /* Clear IO reset bit */ - MCHBAR32(0x5030) &= ~0x20; + MCHBAR32(MC_INIT_STATE_G) &= ~0x20; /* Set MAD-DIMM registers */ dram_dimm_set_mapping(ctrl); diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index aa166c9..aa8ef5e 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -249,7 +249,7 @@ /* For reference print the System Agent version * after executing the UEFI PEI stage. */ - u32 version = MCHBAR32(0x5034); + u32 version = MCHBAR32(MRC_REVISION); printk(BIOS_DEBUG, "System Agent Version %d.%d.%d Build %d\n", version >> 24, (version >> 16) & 0xff, (version >> 8) & 0xff, version & 0xff); diff --git a/src/northbridge/intel/sandybridge/raminit_sandy.c b/src/northbridge/intel/sandybridge/raminit_sandy.c index 9fa6c7b..6b8bba7 100644 --- a/src/northbridge/intel/sandybridge/raminit_sandy.c +++ b/src/northbridge/intel/sandybridge/raminit_sandy.c @@ -361,12 +361,12 @@ // IO clock FOR_ALL_CHANNELS { - MCHBAR32(0xc00 + 0x100 * channel) = ctrl->rankmap[channel]; + MCHBAR32(GDCRCLKRANKSUSED_C0 + 0x100 * channel) = ctrl->rankmap[channel]; } // IO command FOR_ALL_CHANNELS { - MCHBAR32(0x3200 + 0x100 * channel) = ctrl->rankmap[channel]; + MCHBAR32(GDCRCTLRANKSUSED_C0 + 0x100 * channel) = ctrl->rankmap[channel]; } // IO control @@ -378,27 +378,27 @@ printram("RCOMP..."); reg = 0; while (reg == 0) { - reg = MCHBAR32(0x5084) & 0x10000; + reg = MCHBAR32(RCOMP_TIMER) & 0x10000; } printram("done\n"); // Set comp2 comp2 = get_COMP2(ctrl->tCK); - MCHBAR32(0x3714) = comp2; + MCHBAR32(CRCOMPOFST2) = comp2; printram("COMP2 done\n"); // Set comp1 FOR_ALL_POPULATED_CHANNELS { - reg = MCHBAR32(0x1810 + channel * 0x100); //ch0 + reg = MCHBAR32(CRCOMPOFST1_C0 + channel * 0x100); //ch0 reg = (reg & ~0xe00) | (1 << 9); //odt reg = (reg & ~0xe00000) | (1 << 21); //clk drive up reg = (reg & ~0x38000000) | (1 << 27); //ctl drive up - MCHBAR32(0x1810 + channel * 0x100) = reg; + MCHBAR32(CRCOMPOFST1_C0 + channel * 0x100) = reg; } printram("COMP1 done\n"); printram("FORCE RCOMP and wait 20us..."); - MCHBAR32(0x5f08) |= 0x100; + MCHBAR32(M_COMP) |= 0x100; udelay(20); printram("done\n"); } @@ -427,7 +427,7 @@ } /* Set version register */ - MCHBAR32(0x5034) = 0xC04EB002; + MCHBAR32(MRC_REVISION) = 0xC04EB002; /* Enable crossover */ dram_xover(ctrl); @@ -436,16 +436,16 @@ dram_timing_regs(ctrl); /* Power mode preset */ - MCHBAR32(0x4e80) = 0x5500; + MCHBAR32(PM_THML_STAT) = 0x5500; /* Set scheduler parameters */ - MCHBAR32(0x4c20) = 0x10100005; + MCHBAR32(SCHED_CBIT) = 0x10100005; /* Set CPU specific register */ set_4f8c(); /* Clear IO reset bit */ - MCHBAR32(0x5030) &= ~0x20; + MCHBAR32(MC_INIT_STATE_G) &= ~0x20; /* Set MAD-DIMM registers */ dram_dimm_set_mapping(ctrl); diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 52d4c5b..2b7e6d1 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -127,23 +127,325 @@ #define MCHBAR32_AND(x, and) (MCHBAR32(x) = (MCHBAR32(x) & (and))) #define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or)) +#define GDCRTRAININGRESULT1_C0_B0 0x0004 /* Results according to PI settings */ +#define GDCRTRAININGRESULT2_C0_B0 0x0008 +#define GDCRRXRANK0_C0_B0 0x0010 /* Time setting for Rx data byte */ +#define GDCRRXRANK1_C0_B0 0x0014 +#define GDCRRXRANK2_C0_B0 0x0018 +#define GDCRRXRANK3_C0_B0 0x001c +#define GDCRRXRANK0_C0_B0 0x0020 /* Time setting for Tx data byte */ +#define GDCRRXRANK1_C0_B0 0x0024 +#define GDCRRXRANK2_C0_B0 0x0028 +#define GDCRRXRANK3_C0_B0 0x002c + +#define GDCRCLKRANKSUSED_C0 0x0c00 /* Indicates which rank is populated */ +#define GDCRCLKCOMP_C0 0x0c04 /* RCOMP result register */ +#define GDCRCKPICODE_C0 0x0c14 /* PI coding for DDR CLK pins */ +#define GDCRCKLOGICDELAY_C0 0x0c18 /* Logic delay of 1 QCLK in CLK slice */ +#define GDDLLFUSE_C0 0x0c20 /* Used for fuse download to the DLLs */ +#define GDCRCLKDEBUGMUXCFG_C0 0x0c3c /* Debug MUX control */ + +#define GDCRCMDDEBUGMUXCFG_C0_S 0x0e3c /* Debug MUX control */ + +#define CRCOMPOFST1_C0 0x1810 /* DQ, CTL and CLK Offset values */ + +#define GDCRTRAININGMOD_C0 0x3000 /* Data training mode control register */ +#define GDCRTRAININGRESULT1_C0 0x3004 /* Training results according to PI settings */ +#define GDCRTRAININGRESULT2_C0 0x3008 + +#define GDCRRXRANK0_C0 0x3010 /* Time setting for Rx data byte */ +#define GDCRRXRANK1_C0 0x3014 +#define GDCRRXRANK2_C0 0x3018 +#define GDCRRXRANK3_C0 0x301c + +#define GDCRTXRANK0_C0 0x3020 /* Time setting for Tx data byte */ +#define GDCRTXRANK1_C0 0x3024 +#define GDCRTXRANK2_C0 0x3028 +#define GDCRTXRANK3_C0 0x302c + +#define GDCRCTLRANKSUSED_C0 0x3200 /* Indicates which rank is populated */ +#define GDCRCMDCOMP_C0 0x3204 /* COMP values register */ +#define GDCRCMDCTLCOMP_C0 0x320c /* COMP values register */ +#define GDCRCMDPICODING_C0 0x320c /* Command and control PI coding */ + +#define GDCRTRAININGMOD 0x3400 /* Data training mode control register */ +#define GDCRDATACOMP 0x340c /* COMP values register */ + +#define CRCOMPOFST2 0x3714 /* CMD DRV, SComp and Static Leg controls */ + +/* MC Channel 0 */ #define TC_DBP_C0 0x4000 /* Timing of DDR - bin parameters */ #define TC_RAP_C0 0x4004 /* Timing of DDR - regular access parameters */ +#define TC_RWP_C0 0x4008 /* Timing of DDR - read/write parameters */ +#define TC_OTHP_C0 0x400c /* Timing of DDR - other timing parameters */ +#define SCHED_SECOND_CBIT_C0 0x401c /* More chicken bits */ +#define SCHED_CBIT_C0 0x4020 /* Chicken bits in scheduler */ +#define SC_ROUNDT_LAT_C0 0x4024 /* Round-trip latency per rank */ #define SC_IO_LATENCY_C0 0x4028 /* IO Latency Configuration */ +#define SCRAMBLING_SEED_1_C0 0x4034 /* Scrambling seed 1 */ +#define SCRAMBLING_SEED_2_LOW_C0 0x4038 /* Scrambling seed 2 low */ +#define SCRAMBLING_SEED_2_HIGH_C0 0x403c /* Scrambling seed 2 high */ + +#define IOSAV_B0_BW_SERROR_C0 0x4040 /* IOSAV Bytelane 0 Bit-wise error */ +#define IOSAV_B1_BW_SERROR_C0 0x4044 +#define IOSAV_B2_BW_SERROR_C0 0x4048 +#define IOSAV_B3_BW_SERROR_C0 0x404c +#define IOSAV_B4_BW_SERROR_C0 0x4050 +#define IOSAV_B5_BW_SERROR_C0 0x4054 +#define IOSAV_B6_BW_SERROR_C0 0x4058 +#define IOSAV_B7_BW_SERROR_C0 0x405c +#define IOSAV_B8_BW_SERROR_C0 0x4060 + +#define IOSAV_B0_BW_MASK_C0 0x4080 /* IOSAV Bytelane 0 Bit-wise compare mask */ +#define IOSAV_B1_BW_MASK_C0 0x4084 +#define IOSAV_B2_BW_MASK_C0 0x4088 +#define IOSAV_B3_BW_MASK_C0 0x408c +#define IOSAV_B4_BW_MASK_C0 0x4090 +#define IOSAV_B5_BW_MASK_C0 0x4094 +#define IOSAV_B6_BW_MASK_C0 0x4098 +#define IOSAV_B7_BW_MASK_C0 0x409c +#define IOSAV_B8_BW_MASK_C0 0x40a0 + +/* + * Defines the number of transactions (non-VC1 RD CAS commands) between two priority ticks. + * Different counters for transactions that are issued on the ring agents (core or GT) and + * transactions issued in the SA. + */ +#define SC_PR_CNT_CONFIG_C0 0x40a8 +#define SC_PCIT_C0 0x40ac /* Page-close idle timer setup - 8 bits */ +#define PM_PDWN_CONFIG_C0 0x40b0 /* Power-down (CKE-off) operation config */ +#define ECC_INJECT_COUNT_C0 0x40b4 /* ECC error injection count */ +#define ECC_DFT_C0 0x40b8 /* ECC DFT features (ECC4ANA, error inject) */ + +#define SC_WR_ADD_DELAY_C0 0x40d0 /* Extra WR delay to overcome WR-flyby issue */ + +#define IOSAV_B0_BW_SERROR_C_C0 0x4140 /* IOSAV Bytelane 0 Bit-wise error */ +#define IOSAV_B1_BW_SERROR_C_C0 0x4144 /* IOSAV Bytelane 0 Bit-wise error */ +#define IOSAV_B2_BW_SERROR_C_C0 0x4148 /* IOSAV Bytelane 0 Bit-wise error */ +#define IOSAV_B3_BW_SERROR_C_C0 0x414c /* IOSAV Bytelane 0 Bit-wise error */ +#define IOSAV_B4_BW_SERROR_C_C0 0x4150 /* IOSAV Bytelane 0 Bit-wise error */ +#define IOSAV_B5_BW_SERROR_C_C0 0x4154 /* IOSAV Bytelane 0 Bit-wise error */ +#define IOSAV_B6_BW_SERROR_C_C0 0x4158 /* IOSAV Bytelane 0 Bit-wise error */ +#define IOSAV_B7_BW_SERROR_C_C0 0x415c /* IOSAV Bytelane 0 Bit-wise error */ +#define IOSAV_B8_BW_SERROR_C_C0 0x4160 /* IOSAV Bytelane 0 Bit-wise error */ + +#define IOSAV_0_SPECIAL_COMMAND_ADDR_C0 0x4200 /* Sub-sequence command address */ +#define IOSAV_1_SPECIAL_COMMAND_ADDR_C0 0x4204 +#define IOSAV_2_SPECIAL_COMMAND_ADDR_C0 0x4208 +#define IOSAV_3_SPECIAL_COMMAND_ADDR_C0 0x420c +#define IOSAV_0_ADDR_UPD_C0 0x4210 /* Address update after command execution */ +#define IOSAV_1_ADDR_UPD_C0 0x4214 +#define IOSAV_2_ADDR_UPD_C0 0x4218 +#define IOSAV_3_ADDR_UPD_C0 0x421c +#define IOSAV_0_SPECIAL_COMMAND_CTL_C0 0x4220 /* Command signals in sub-sequence command */ +#define IOSAV_1_SPECIAL_COMMAND_CTL_C0 0x4224 +#define IOSAV_2_SPECIAL_COMMAND_CTL_C0 0x4228 +#define IOSAV_3_SPECIAL_COMMAND_CTL_C0 0x422c +#define IOSAV_0_SUBSEQ_CTL_C0 0x4230 /* Sub-sequence command parameter control */ +#define IOSAV_1_SUBSEQ_CTL_C0 0x4234 +#define IOSAV_2_SUBSEQ_CTL_C0 0x4238 +#define IOSAV_3_SUBSEQ_CTL_C0 0x423c +#define IOSAV_0_ADDRESS_LFSR_C0 0x4240 /* 23-bit LFSR value of the sequence */ +#define IOSAV_1_ADDRESS_LFSR_C0 0x4244 +#define IOSAV_2_ADDRESS_LFSR_C0 0x4248 +#define IOSAV_3_ADDRESS_LFSR_C0 0x424c + +#define PM_THML_STAT_C0 0x4280 /* Thermal status of each rank */ +#define IOSAV_SEQ_CTL_C0 0x4284 /* IOSAV sequence level control */ +#define IOSAV_DATA_CTL_C0 0x4288 /* Data control in IOSAV mode */ +#define IOSAV_STATUS_C0 0x428c /* State of the IOSAV sequence machine */ +#define TC_ZQCAL_C0 0x4290 /* ZQCAL control register */ #define TC_RFP_C0 0x4294 /* Refresh Parameters */ #define TC_RFTP_C0 0x4298 /* Refresh Timing Parameters */ -#define PM_PDWN_CONFIG 0x4cb0 +#define TC_MR2_SHADOW_C0 0x429c /* MR2 shadow - copy of DDR configuration */ +#define MC_INIT_STATE_C0 0x42a0 /* IOSAV mode control */ +#define TC_SRFTP_C0 0x42a4 /* Self-refresh timing parameters */ +#define IOSAV_ERROR_C0 0x42ac /* Data vector count of the first error */ +#define IOSAV_DC_MASK_C0 0x42b0 /* IOSAV data check masking */ + +#define IOSAV_B0_ERROR_COUNT_C0 0x4340 /* Per-byte 16-bit error counter */ +#define IOSAV_B1_ERROR_COUNT_C0 0x4344 +#define IOSAV_B2_ERROR_COUNT_C0 0x4348 +#define IOSAV_B3_ERROR_COUNT_C0 0x434c +#define IOSAV_B4_ERROR_COUNT_C0 0x4350 +#define IOSAV_B5_ERROR_COUNT_C0 0x4354 +#define IOSAV_B6_ERROR_COUNT_C0 0x4358 +#define IOSAV_B7_ERROR_COUNT_C0 0x435c +#define IOSAV_B8_ERROR_COUNT_C0 0x4360 +#define IOSAV_G_ERROR_COUNT_C0 0x4364 /* Global 16-bit error counter */ + +#define PM_TRML_M_CONFIG_C0 0x4380 /* Thermal mode configuration */ +#define PM_CMD_PWR_C0 0x4384 /* Power contribution of commands */ +#define PM_BW_LIMIT_CONFIG_C0 0x4388 /* Bandwidth throttling on overtemperature */ +#define SC_WDBWM_C0 0x438c /* Watermarks and starvation counter config */ + +/* MC Channel Broadcast */ +#define TC_DBP 0x4c00 /* Timing of DDR - bin parameters */ +#define TC_RAP 0x4c04 /* Timing of DDR - regular access parameters */ +#define TC_RWP 0x4c08 /* Timing of DDR - read/write parameters */ +#define TC_OTHP 0x4c0c /* Timing of DDR - other timing parameters */ +#define SCHED_SECOND_CBIT 0x4c1c /* More chicken bits */ +#define SCHED_CBIT 0x4c20 /* Chicken bits in scheduler */ +#define SC_ROUNDT_LAT 0x4c24 /* Round-trip latency per rank */ +#define SC_IO_LATENCY 0x4c28 /* IO Latency Configuration */ +#define SCRAMBLING_SEED_1 0x4c34 /* Scrambling seed 1 */ +#define SCRAMBLING_SEED_2_LOW 0x4c38 /* Scrambling seed 2 low */ +#define SCRAMBLING_SEED_2_HIGH 0x4c3c /* Scrambling seed 2 high */ + +#define IOSAV_B0_BW_SERROR 0x4c40 /* IOSAV Bytelane 0 Bit-wise error */ +#define IOSAV_B1_BW_SERROR 0x4c44 +#define IOSAV_B2_BW_SERROR 0x4c48 +#define IOSAV_B3_BW_SERROR 0x4c4c +#define IOSAV_B4_BW_SERROR 0x4c50 +#define IOSAV_B5_BW_SERROR 0x4c54 +#define IOSAV_B6_BW_SERROR 0x4c58 +#define IOSAV_B7_BW_SERROR 0x4c5c +#define IOSAV_B8_BW_SERROR 0x4c60 + +#define IOSAV_B0_BW_MASK 0x4c80 /* IOSAV Bytelane 0 Bit-wise compare mask */ +#define IOSAV_B1_BW_MASK 0x4c84 +#define IOSAV_B2_BW_MASK 0x4c88 +#define IOSAV_B3_BW_MASK 0x4c8c +#define IOSAV_B4_BW_MASK 0x4c90 +#define IOSAV_B5_BW_MASK 0x4c94 +#define IOSAV_B6_BW_MASK 0x4c98 +#define IOSAV_B7_BW_MASK 0x4c9c +#define IOSAV_B8_BW_MASK 0x4ca0 + +/* + * Defines the number of transactions (non-VC1 RD CAS commands) between two priority ticks. + * Different counters for transactions that are issued on the ring agents (core or GT) and + * transactions issued in the SA. + */ +#define SC_PR_CNT_CONFIG 0x4ca8 +#define SC_PCIT 0x4cac /* Page-close idle timer setup - 8 bits */ +#define PM_PDWN_CONFIG 0x4cb0 /* Power-down (CKE-off) operation config */ +#define ECC_INJECT_COUNT 0x4cb4 /* ECC error injection count */ +#define ECC_DFT 0x4cb8 /* ECC DFT features (ECC4ANA, error inject) */ + +#define SC_WR_ADD_DELAY 0x4cd0 /* Extra WR delay to overcome WR-flyby issue */ + +/* Opportunistic reads configuration during write-major-mode (WMM) */ +#define WMM_READ_CONFIG 0x4cd4 /** WARNING: Only exists on IVB! */ + +#define IOSAV_B0_BW_SERROR_C 0x4d40 /* IOSAV Bytelane 0 Bit-wise error */ +#define IOSAV_B1_BW_SERROR_C 0x4d44 /* IOSAV Bytelane 0 Bit-wise error */ +#define IOSAV_B2_BW_SERROR_C 0x4d48 /* IOSAV Bytelane 0 Bit-wise error */ +#define IOSAV_B3_BW_SERROR_C 0x4d4c /* IOSAV Bytelane 0 Bit-wise error */ +#define IOSAV_B4_BW_SERROR_C 0x4d50 /* IOSAV Bytelane 0 Bit-wise error */ +#define IOSAV_B5_BW_SERROR_C 0x4d54 /* IOSAV Bytelane 0 Bit-wise error */ +#define IOSAV_B6_BW_SERROR_C 0x4d58 /* IOSAV Bytelane 0 Bit-wise error */ +#define IOSAV_B7_BW_SERROR_C 0x4d5c /* IOSAV Bytelane 0 Bit-wise error */ +#define IOSAV_B8_BW_SERROR_C 0x4d60 /* IOSAV Bytelane 0 Bit-wise error */ + +#define IOSAV_0_SPECIAL_COMMAND_ADDR 0x4e00 /* Sub-sequence command address */ +#define IOSAV_1_SPECIAL_COMMAND_ADDR 0x4e04 +#define IOSAV_2_SPECIAL_COMMAND_ADDR 0x4e08 +#define IOSAV_3_SPECIAL_COMMAND_ADDR 0x4e0c +#define IOSAV_0_ADDR_UPD 0x4e10 /* Address update after command execution */ +#define IOSAV_1_ADDR_UPD 0x4e14 +#define IOSAV_2_ADDR_UPD 0x4e18 +#define IOSAV_3_ADDR_UPD 0x4e1c +#define IOSAV_0_SPECIAL_COMMAND_CTL 0x4e20 /* Command signals in sub-sequence command */ +#define IOSAV_1_SPECIAL_COMMAND_CTL 0x4e24 +#define IOSAV_2_SPECIAL_COMMAND_CTL 0x4e28 +#define IOSAV_3_SPECIAL_COMMAND_CTL 0x4e2c +#define IOSAV_0_SUBSEQ_CTL 0x4e30 /* Sub-sequence command parameter control */ +#define IOSAV_1_SUBSEQ_CTL 0x4e34 +#define IOSAV_2_SUBSEQ_CTL 0x4e38 +#define IOSAV_3_SUBSEQ_CTL 0x4e3c +#define IOSAV_0_ADDRESS_LFSR 0x4e40 /* 23-bit LFSR value of the sequence */ +#define IOSAV_1_ADDRESS_LFSR 0x4e44 +#define IOSAV_2_ADDRESS_LFSR 0x4e48 +#define IOSAV_3_ADDRESS_LFSR 0x4e4c + +#define PM_THML_STAT 0x4e80 /* Thermal status of each rank */ +#define IOSAV_SEQ_CTL 0x4e84 /* IOSAV sequence level control */ +#define IOSAV_DATA_CTL 0x4e88 /* Data control in IOSAV mode */ +#define IOSAV_STATUS 0x4e8c /* State of the IOSAV sequence machine */ +#define TC_ZQCAL 0x4e90 /* ZQCAL control register */ +#define TC_RFP 0x4e94 /* Refresh Parameters */ +#define TC_RFTP 0x4e98 /* Refresh Timing Parameters */ +#define TC_MR2_SHADOW 0x4e9c /* MR2 shadow - copy of DDR configuration */ +#define MC_INIT_STATE 0x4ea0 /* IOSAV mode control */ +#define TC_SRFTP 0x4ea4 /* Self-refresh timing parameters */ + +/* + * Auxiliary register in mcmnts synthesis FUB (Functional Unit Block). Additionally, this + * register is also used to enable IOSAV_n_SPECIAL_COMMAND_ADDR optimization on Ivy Bridge. + */ +#define MCMNTS_SPARE 0x4ea8 /** WARNING: Reserved, use only on IVB! */ + +#define IOSAV_ERROR 0x4eac /* Data vector count of the first error */ +#define IOSAV_DC_MASK 0x4eb0 /* IOSAV data check masking */ + +#define IOSAV_B0_ERROR_COUNT 0x4f40 /* Per-byte 16-bit error counter */ +#define IOSAV_B1_ERROR_COUNT 0x4f44 +#define IOSAV_B2_ERROR_COUNT 0x4f48 +#define IOSAV_B3_ERROR_COUNT 0x4f4c +#define IOSAV_B4_ERROR_COUNT 0x4f50 +#define IOSAV_B5_ERROR_COUNT 0x4f54 +#define IOSAV_B6_ERROR_COUNT 0x4f58 +#define IOSAV_B7_ERROR_COUNT 0x4f5c +#define IOSAV_B8_ERROR_COUNT 0x4f60 +#define IOSAV_G_ERROR_COUNT 0x4f64 /* Global 16-bit error counter */ + +#define PM_TRML_M_CONFIG 0x4f80 /* Thermal mode configuration */ +#define PM_CMD_PWR 0x4f84 /* Power contribution of commands */ +#define PM_BW_LIMIT_CONFIG 0x4f88 /* Bandwidth throttling on overtemperature */ +#define SC_WDBWM 0x4f8c /* Watermarks and starvation counter config */ + #define MAD_CHNL 0x5000 /* Address Decoder Channel Configuration */ #define MAD_DIMM_CH0 0x5004 /* Address Decode Channel 0 */ #define MAD_DIMM_CH1 0x5008 /* Address Decode Channel 1 */ +#define MAD_DIMM_CH2 0x500c /* Address Decode Channel 2 (unused on SNB) */ +#define MAD_ZR 0x5014 /* Address Decode Zones */ +#define MCDECS_SPARE 0x5018 /* Spare register in mcdecs synthesis FUB */ +#define MCDECS_CBIT 0x501c /* Chicken bits in mcdecs synthesis FUB */ + +#define CHANNEL_HASH 0x5024 /** WARNING: Only exists on IVB! */ + +#define MC_INIT_STATE_G 0x5030 /* High-level behavior in IOSAV mode */ +#define MRC_REVISION 0x5034 /* MRC Revision */ +#define PM_DLL_CONFIG 0x5064 /* Memory Controller I/O DLL config */ +#define RCOMP_TIMER 0x5084 /* RCOMP evaluation timer register */ + +#define MC_LOCK 0x50fc /* Memory Controlller Lock register */ + +#define VTD1_BASE 0x5400 /* Base address for IGD */ +#define VTD2_BASE 0x5410 /* Base address for PEG, USB, SATA, etc. */ +#define PAIR_CTL 0x5418 /* Power Aware Interrupt Routing Control */ + +/* PAVP control register, undocumented. Different from PAVPC on PCI config space. */ +#define MMIO_PAVP_CTL 0x5500 /* Bit 0 locks PAVP settings */ + #define MEM_TRML_ESTIMATION_CONFIG 0x5880 #define MEM_TRML_THRESHOLDS_CONFIG 0x5888 #define MEM_TRML_INTERRUPT 0x58a8 + +#define MC_TURBO_PL1 0x59a0 /* Turbo Power Limit 1 parameters */ +#define MC_TURBO_PL2 0x59a4 /* Turbo Power Limit 2 parameters */ + #define MC_BIOS_REQ 0x5e00 #define MC_BIOS_DATA 0x5e04 +#define SSKPD_OK 0x5d10 /* 64-bit scratchpad register */ #define SSKPD 0x5d14 /* 16bit (scratchpad) */ #define BIOS_RESET_CPL 0x5da8 /* 8bit */ +/* PCODE will sample SAPM-related registers at the end of Phase 4. */ +#define MC_BIOS_REQ 0x5e00 /* Memory frequency request register */ +#define MC_BIOS_DATA 0x5e04 /* Miscellaneous information for BIOS */ +#define SAPMCTL 0x5f00 /* Bit 3 enables DDR EPG (C7i) on IVB */ +#define M_COMP 0x5f08 /* Memory COMP control */ +#define SAPMTIMERS 0x5f10 /* SAPM timers in 10ns (100 MHz) units */ + +/* WARNING: Only applies to Sandy Bridge! */ +#define BANDTIMERS_SNB 0x5f18 /* MPLL and PPLL time to do self-banding */ + +/** WARNING: Only applies to Ivy Bridge! */ +#define SAPMTIMERS2_IVB 0x5f18 /** Extra latency for DDRIO EPG exit (C7i) */ +#define BANDTIMERS_IVB 0x5f20 /** MPLL and PPLL time to do self-banding */ + /* * EPBAR - Egress Port Root Complex Register Block */ -- To view, visit https://review.coreboot.org/c/coreboot/+/38036 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e5fe56eaa90842dbbdd1bfbbcb7709237b4c486 Gerrit-Change-Number: 38036 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/facebook/monolith: Remove unused SDIO controller from devicetree
by Wim Vervoorn (Code Review) 10 Jan '20

10 Jan '20

Wim Vervoorn has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38129 ) Change subject: mb/facebook/monolith: Remove unused SDIO controller from devicetree ...................................................................... mb/facebook/monolith: Remove unused SDIO controller from devicetree The SDIO device is disabled so remove it from the devicetree. BUG=N/A TEST=build Change-Id: I6497f6134d8fc001bf4cb7e348ae00077aa34814 Signed-off-by: Wim Vervoorn <wvervoorn(a)eltan.com> --- M src/mainboard/facebook/monolith/devicetree.cb 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/38129/1 diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb index f715eb3..dbe36f0 100644 --- a/src/mainboard/facebook/monolith/devicetree.cb +++ b/src/mainboard/facebook/monolith/devicetree.cb @@ -232,7 +232,6 @@ device pci 1d.0 on end # PCI Express Port 9 x4 FPGA device pci 1e.0 on end # UART #0 device pci 1e.4 on end # eMMC - device pci 1e.5 off end # SDIO device pci 1f.0 on # LPC Interface chip drivers/pc80/tpm device pnp 0c31.0 on end -- To view, visit https://review.coreboot.org/c/coreboot/+/38129 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6497f6134d8fc001bf4cb7e348ae00077aa34814 Gerrit-Change-Number: 38129 Gerrit-PatchSet: 1 Gerrit-Owner: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/facebook/monolith: Enable HDA for HDMI output
by Wim Vervoorn (Code Review) 10 Jan '20

10 Jan '20

Wim Vervoorn has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38128 ) Change subject: mb/facebook/monolith: Enable HDA for HDMI output ...................................................................... mb/facebook/monolith: Enable HDA for HDMI output The HDA controller was disabed as there is not HDA codec in the system. Because of this there is no audio support if an HDMI monitor is connected. Enable Azalia and enable the HDA device in the device tree. BUG=N/A TEST=tested on facebook monolith Change-Id: I7be2c29151dc9d6c247c3332fb9adfb34449c703 Signed-off-by: Wim Vervoorn <wvervoorn(a)eltan.com> --- M src/mainboard/facebook/monolith/devicetree.cb 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/38128/1 diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb index b5e3191..f715eb3 100644 --- a/src/mainboard/facebook/monolith/devicetree.cb +++ b/src/mainboard/facebook/monolith/devicetree.cb @@ -28,7 +28,7 @@ register "dptf_enable" = "0" # FSP Configuration - register "EnableAzalia" = "0" + register "EnableAzalia" = "1" register "SmbusEnable" = "1" register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" @@ -240,6 +240,7 @@ end # LPC Bridge device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # HDA Controller for HDMI only device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI device pci 1f.6 on end # GbE -- To view, visit https://review.coreboot.org/c/coreboot/+/38128 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7be2c29151dc9d6c247c3332fb9adfb34449c703 Gerrit-Change-Number: 38128 Gerrit-PatchSet: 1 Gerrit-Owner: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: fsp1_1: Drop unused weak function
by Nico Huber (Code Review) 10 Jan '20

10 Jan '20

Hello Wim Vervoorn, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/38138 to review the following change. Change subject: fsp1_1: Drop unused weak function ...................................................................... fsp1_1: Drop unused weak function All FSP 1.1 platforms override the weak soc_load_logo(). Change-Id: Ib2eae166e02771311c50ea7e4f294790dfa2b99e Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/drivers/intel/fsp1_1/ramstage.c 1 file changed, 0 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/38138/1 diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c index 40e79cc..05a29cb 100644 --- a/src/drivers/intel/fsp1_1/ramstage.c +++ b/src/drivers/intel/fsp1_1/ramstage.c @@ -209,9 +209,3 @@ __weak void soc_silicon_init_params(SILICON_INIT_UPD *params) { } - -/* Load bmp and set FSP parameters, fsp_load_logo can be used */ -__weak const struct cbmem_entry *soc_load_logo(SILICON_INIT_UPD *params) -{ - return NULL; -} -- To view, visit https://review.coreboot.org/c/coreboot/+/38138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2eae166e02771311c50ea7e4f294790dfa2b99e Gerrit-Change-Number: 38138 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP] vc/amd/agesa/f16kb/Proc/GNB: Fix out-of-bounds read
by Name of user not set (Code Review) 10 Jan '20

10 Jan '20

awokd(a)danwin1210.me has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38056 ) Change subject: [WIP] vc/amd/agesa/f16kb/Proc/GNB: Fix out-of-bounds read ...................................................................... [WIP] vc/amd/agesa/f16kb/Proc/GNB: Fix out-of-bounds read Incorrect values read from a different memory region will cause incorrect computations. VceFlags array size should be 4 based on similar code in f15 branch, and because f16kb/Proc/GNB/Modules/GnbInitKB/GnbF1TableKB.c only loads 4 values for VceFlags in DefaultPpF1ArrayKB. Leaving it at 5 creates Coverity CID 1241878. Change-Id: I0242c0634e66616018e6df04ac6f1505b82a630f Signed-off-by: Joe Moore <awokd(a)danwin1210.me> Found-by: Coverity CID 1241878 --- M src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbF1Table.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/38056/1 diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbF1Table.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbF1Table.h index add5509..90df07c 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbF1Table.h +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbF1Table.h @@ -66,7 +66,7 @@ UINT32 PP_FUSE_ARRAY_V2_fld11; UINT32 PP_FUSE_ARRAY_V2_fld12; BOOLEAN PP_FUSE_ARRAY_V2_fld13; - UINT8 VceFlags[5]; ///< VCE Flags + UINT8 VceFlags[4]; ///< VCE Flags UINT8 VceMclk; ///< MCLK for VCE UINT8 PP_FUSE_ARRAY_V2_fld16[4]; UINT8 EclkDid[5]; ///< Eclk DID -- To view, visit https://review.coreboot.org/c/coreboot/+/38056 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0242c0634e66616018e6df04ac6f1505b82a630f Gerrit-Change-Number: 38056 Gerrit-PatchSet: 1 Gerrit-Owner: awokd(a)danwin1210.me Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/facebook/monolith: Add UNIFIED_MRC_CACHE region in fmd file
by Wim Vervoorn (Code Review) 10 Jan '20

10 Jan '20

Wim Vervoorn has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38130 ) Change subject: mb/facebook/monolith: Add UNIFIED_MRC_CACHE region in fmd file ...................................................................... mb/facebook/monolith: Add UNIFIED_MRC_CACHE region in fmd file The RW_MRC_CACHE was not included in a UNIFIED_MRC_CACHE region which is expected by some parts of the code. Add the UNIFIED_MRC_CACHE and include the RW_MRC_CACHE in this region. BUG=N/A TEST=tested on facebook monolith Change-Id: I1654ca210dc2a8e976d698fd8330641da23e8380 Signed-off-by: Wim Vervoorn <wvervoorn(a)eltan.com> --- M src/mainboard/facebook/monolith/vboot-ro.fmd M src/mainboard/facebook/monolith/vboot-rw.fmd 2 files changed, 6 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/38130/1 diff --git a/src/mainboard/facebook/monolith/vboot-ro.fmd b/src/mainboard/facebook/monolith/vboot-ro.fmd index 989afcb..4abd883 100644 --- a/src/mainboard/facebook/monolith/vboot-ro.fmd +++ b/src/mainboard/facebook/monolith/vboot-ro.fmd @@ -6,7 +6,9 @@ } SI_BIOS@0x700000 0x900000 { MISC_RW@0x0 0x20000 { - RW_MRC_CACHE@0x0 0x10000 + UNIFIED_MRC_CACHE@0x0 0x10000 { + RW_MRC_CACHE@0x00000 0x10000 + } RW_VPD(PRESERVE)@0x010000 0x2000 RW_NVRAM(PRESERVE)@0x012000 0x6000 } diff --git a/src/mainboard/facebook/monolith/vboot-rw.fmd b/src/mainboard/facebook/monolith/vboot-rw.fmd index fd7811b..df2674b 100644 --- a/src/mainboard/facebook/monolith/vboot-rw.fmd +++ b/src/mainboard/facebook/monolith/vboot-rw.fmd @@ -6,7 +6,9 @@ } SI_BIOS@0x700000 0x900000 { MISC_RW@0x0 0x20000 { - RW_MRC_CACHE@0x0 0x10000 + UNIFIED_MRC_CACHE@0x0 0x10000 { + RW_MRC_CACHE@0x00000 0x10000 + } RW_VPD(PRESERVE)@0x010000 0x2000 RW_NVRAM(PRESERVE)@0x012000 0x6000 } -- To view, visit https://review.coreboot.org/c/coreboot/+/38130 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1654ca210dc2a8e976d698fd8330641da23e8380 Gerrit-Change-Number: 38130 Gerrit-PatchSet: 1 Gerrit-Owner: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-MessageType: newchange

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